Alinco DR-140E, DR-140TE1, DR-140TE2, DR-140T Service Manual

DR-140T/E/TE1/TE 2

Serv ic e M a n u al

C O N T E N T S

• SP ECIFICATIONS

1) General................................................................................2

2) Tran smitter................*

3) R eceiver...............................................................................3

• CIRC UIT DESCRIPTION

1) R eceiver S yte m

2) Transmitter System ....................................................5-6

3) PLL C ircuit.........................................................................6

4) Terminal Function of C PU ...........................................7

• SEM ICONDUCTO R DATA

1) AK2341 ............................................................................10

2) AN78L05M ...................................................................11

3) LA4425A ..........................................................................11

4) M 5 218FP.........................................................................11

5) M 56760FP...................................................................... 12

6) M 6774 6............................................................................13

7) M68702H..........................................................................13

6) M 68702L..........................................................................13

9) M C7808CT...................................................................... 14

10) RH5VL32AA-T1 ............................................................14

11) RH5VL45AA-T1 ............................................................14

12) TK10930VTL...................................................................15

13) jczPC2710T......................................................................16

14 )24LC16B 16

15).Transistor,D iode and LED Outline D raw ing s

16) L C D ....................................................................................18

• EXPLO DED VIEW

1) Bottom V ie w

2) LCD A ssem bly...............................................................20

3) Top, and Front V ie w .....................................................21

........................................................

.........................................................4 -5

...................................................................19

.......

• PARTS LIST

Main U nit...................................................................... 21 -2 2

Packing.................................................................................23

CPU Unit...............................................................................23

SP Unit ..............................................................................

VCO U nit.............................................................................23

Mechanical Parts ..............................................................23

EJ-20U .................................................................................24

• AD JU STMENT

1) Required Test Equipment

2) PLL Adjustm ent.............................................................26

3) TX Adjustme nt

4) RX Adjustment..............................................................27

5) Adjustment Points

• PC BOAD VIEW

1) Main Unit Side A ...........................................................29

2) Main Unit Side B...........................................................30

3) CPU Unit Side A ..........................................................31

4) CPU Unit Side B............................................................31

5) VCO Unit Side A ...........................................................32

6) VCO Unit Side B ...........................................................32

7) EJ-20U (CTCSS Unit: O ptio n)..................................33

• BLO CK D IAG RA M ...................................................................34

• SCHEMATIC DIAGRAM

1) Main Unit T/E....................................................

2) Main Unit TE 1/T E2 ...............................................37 -3 8

3) CPU U n it

4) VCO U nit

5) EJ-20U (CTCSS Unit: O ption)

.............................................................26

........................................................................

........................................................................40

..........................................

........................................................28

...............................

.....

35-3 6

ALINCO, inc

SPECIFICATIONS

1) General

TX Frequency Range:

RX Frequency Range:

CTCSS Encode: CTCSS Decode: Microphone: Frequency Resolution Antenna Impedance: Power Input: Current Drain @13.8V DC:

Dimensions: Weight:

Memory Channels:

Display:

Tone Bursts:

Time Out Timer: Busy Channel Lock Out: Penalty Timer: Scan Function:

T 144.000- 147.995MHz

E 144.000- 145.995MHz

TE1 136.000- 155.000MHz TE2 150.000- 173.995MHz T 118.000 - 135.995MHz (AM), 136.000 - 173.995MHz (FM)

E 144.000 - 145.995MHz (FM) TE1 136.000 - 173.995MHz (FM) TE2 136.000 - 173.995MHz (FM)

Standard 50 Tones

Optional 50 Tones

Electret Cond* with DTMF

5, 10, 12.5, 15, 20, 30, 50kHz steps, user adjustable

50Q unbalanced

13.8 V DC ± 10%

RX - Squelched: less than 800mA

TX - High: approx. 10.5A, Low: approx. 3.5A

141mm(W) x 41mm(H) x 154mm(D) (without projections)

approx. 0.86kg

50 Channels plus CALL channel; each stores RX; TX offset,

CTCSS encode, optional CTCSS decode and alphanumeric display

information

Alphanumeric, English and Cyrillic alphabets, numbers 0-9, figures,

up to 7 characters; backlit LCD

1000, 1450, 1750, 2100 Hz

30 to 450 seconds; selectable in 30 second increments

Available - Requires Optional EJ20U CTCSS Tone Decode Unit

0-15 seconds Busy or Timed; Up or Down, memory or VFO

2) Transmitter

Output Power (approx.):

Emission: Modulation System: Max. Frequency Deviation:

Spurious Emission: Operations: TX/RX Offset Range:

High 50W / Low 5W (T/E), High 35W / Low 5W (TE1/TE2) F3E FM Variable Reactance Frequency Modulation

± 5kHz

-60dB or under below carrier Simplex or Semi-Duplex Modes

From 0 up to ± 99.995MHz (full tuning range of radio)

Offset may be saved as part of information stored in any memory channel

3) Receiver

Receiving System: IF Frequencies: Sensitivity: Selectivity: Audio Output: Speaker Impedance:

Specifications are subject to change without notice or obligation. Performance specifications apply only to

transmit bands. Names of certain products mentioned in this catalog are used for identification purposes only

and may be trademarks or registered trademarks of their respective company.

Dual Conversion Superheterodyne First: 30.85MHz; Second: 455kHz 12dB SINAD -15dB|i More than ± 6kHz at -6dB; Less than ± 15kHz at -60dB More than 2.5 Watts @10% distortion 8£2

CIRCUIT DESCRIPTION

1) Receiver System

1. Antenna Switching Circuit

(Main unit)

The signal from the anlenna is input to RF amplifier circuit passing through the 5 stages low-pass filter (L15 ~ L18, C76 ~ C80, C148), the anlenna switching circuit (D9, D11, L14, C63), T type high-pass filter (L11, LI 2, C57, C64, C58, C59) and band switch circuit (D20 T, E version only). The antenna switching circuit uses XI4 diode switch circuit.

2. RF Amplifier Circuit

(Main unit)

RF signal is amplified approximately 2GdB by RF amplifier, RF amplifier circuit uses dual gate FET to get good inter-modulation characteristics. The RF amplifier

consists of vollage tuned band-pass filter (L1, L2, L4, L5, D2, D3, D5, D6) and RF

AMP (Q6). The signal is amplified after eliminating unwanted signals so that image interference characteristics are improved.

3. 1st Mixer Circuit

(Main unit)

The amplified signal is converted into the first IF signal of 30.85MHz by mixer

circuit (Q5). Mixer circuit uses dual gate FET to improve multifrequency character istics such as inter-modulation. The output signal from mixer circuit is led fo 1st IF circuit.

4. Air Band Circuit

(Main unit I T, E version)

The output signal from band switch circuit is led to low-pass filter circuit (L7, L8, C55, C56) and input to RF amplifier circuit (Q11). There the signal is amplified approximately 20dB and input to the mixer circuit.

5.1st IF Circuit

(Main unit)

The output 1 st IF signal from mixer circuit is led to crystal filter XF1.

Unwanted frequency band of IF signal is eliminated by a crystal filler. The result ing signal is led to the 2nd IF amplifier, and the signal is output to 2nd IF circuit.

6. 2nd IF Circuit and Detector Circuit

(Main unit)

The 1st IF signal is led to 2nd mixer circuit of IC1, then it is converted into the 2nd IF signal (455kHz) by 2nd local signal. IC1 has the 2nd mixer, 2nd local oscillator circuit, quadrature detector circuit and AM detector circuit. The 2nd local oscillator oscillates 2nd local signal (30.395MHz). The 2nd IF output signal from mixer (pin 3 of IC1) circuit is led to ceramic filler {FL1). Unwanted frequency band of 2nd IF signal is eliminated by a ceramic filter. The resulting FM signal is led to the limiter amplifier (pin 7 of IC1) circuit and quadrature deteclor circuit (pin 11 of IC 1 and ceramic discriminator Xt), and the 2nd IF signal is converted to AF signal. The FM AF signal is output from pin 12 of 1C1 to AF circuit. The AM signal is input to AM detector circuit (pin 5 of IC1), and the AM AF signal is output from pin 13 of IC1.

7. AF and Mute Circuit

(Main unit)

8. Squelch Circuit

(CPU unit)

2) Transmitter System

1. Microphone Amplifier Circuit

(CPU unit)

The AF signal from IC1 is filtered by the low-pass filter amplifier (Q2) and led to the high-pass filter amplifier (Q1), and output to the AF gain volume. Q3 and Q4 are switched ON/OFF by AFC signal from CPU, then AF signal is muted when the squelch is ON.

IC1 has the noise amplifier, rectifier circuit and comparator circuit. The noise signal from pin 12 of IC1 is input to the noise amplifier (pin19 of IC1) and passed through buffer amplifier (Q28), rectified by D8, then it is input to comparator circuit (pin 21

of IC1). When the noise signal is decreased by the receiving signal, the compara tor output SD becomes low.

The voice from external microphone is amplified by the microphone amplifier (Q303), and passed through the microphone mute circuit (Q304), the signal is input to the microphone gain potentiometer (VR3) in the main unit.

2. Limiter Amplifier Circuit

(Main unit)

3. Modulation Circuit

(VCO unit)

4. Drive Amplifier Circuit

(Main unit)

5. RF Younger Amplifier Circuit

(Main unit)

The signal from microphone gain potentiometer (VR3) is amplified by limiter amplifier and low-pass (IC4). The resulting signal is passed through the modula tion adjustment potentiometer (VR4), then input to VCO unit. IC4A is limiter amplifier with pre-emphasis characteristics. IC4B is low-pass filter.

The adjusted AF signal in VR4 is led to the VCO unit. The frequency modulation is

executed when the audio signal is supplied to the D207.

The signal from VCO unit is input to the drive amplifier (IC3). IC3 has high gain of approximately 30dB and high level of approximately 10dBm wide band amplifier.

The signal from IC3 is passed through diode switch D12, and input to younger amplifier Q13. Q13 has approximately 15dB gain and output level is 400mW. The output signal of younger amplifier is led to the PA amplifier (IC2).

6. RF Power Amplifier Circuit

(Main unit)

7. Antenna Switch Circuit

(RF unit)

8. A PC Circuit

(RF unit)

IC2 is the power module, which obtains stable output power (50W T/E, 35W TE1/

TE2) within the band. The signal of younger amplifier is amplified by the PA amplifier (IC2), and then led to the antenna switch circuit.

When transmitting, D11 and D9 are ON in the antenna switch circuit, L14 becomes

parallel components. This causes the output signal of IC2 not to go to the RX

circuit. The signal is led to the antenna connector passing through the low-pass

filter (L15 ~ L18, C76 ~ C80, C148).

When the TX signal is passed through the low-pass filter, matching voltage and

mismatching voltage are detected by the D14 and D15. When the antenna

impedance is 50£2, the detected voltage of D14 and D15 are minimum. But when the antenna impedance is not 50ft, the detected voltage becomes higher. The detected voltage is passed through the power setting potentiometer (VR1), and the signal is amplified by Q17, Q16 and Q14. The transmitting power is controlled by the voltage of V1 (IC2) and collector voltage of Q13. When the temperature of the

unit goes high, the powerdown circuit (R104, TH2) prevents the device from being damaged.

3) PLL Circuit

1. Summary

2. Reference Oscillator Circuit

(Main unit)

3. Loop Filter Circuit

(VCO unit)

4. VCO Circuit

(VCO unit)

The PLL circuit uses PLL IC (IC201) equipped with built-in dual modulus prescaler.

The PLL IC serial data is sent from CPU.

The VCO output frequency divided by N is compared with reference frequency in the phase comparator.

The reference frequency is obtained by X3 (12.8MHz), and its output is led to the

VCO unit.

The phase error of phase comparator is integrated to DC voltage by loop filter

circuit, and supplied to D201, D202 of varicap diode jn VCO unit. The time

constant of the active loop filter (consisting of Q202 and Q210) is determined by

C211, C212, R228, R210. The output is passed through the lag filte r (R213,

C208), and input to VCO unit.

The circuit is the Hartley oscillator circuit (Q201), and the signal is output passing

through the buffer amplifier (Q204). C247 is switched by D205 to vary the capaci

tance, and the oscillating frequency range is shifted.

4) Terminal function of CPU

No.

1 AN7 SD

2 AN6 SMT 3 AN5

5 P63

6 P62 7

8 P60

12 13

Nam e

P64

P61

P57 AM 0 AM/FM selection AM FM

TOUT

P55

CNTR TBST

P53 T8 0

P52

Pin Name I/O Description

TON1 0 Tone output 1 Pulse

TON2

TON3

TON4 O

BEEP 0

- HL

STB2

TICD

H L H iZ

SD signal input

I S meter signal input Analog

BP1 I Band plan Analog

Unlock input Unlock

0 Tone output 2

0 Tone output 3 Pulse

Tone output 4

Beep sound output, SCR ON-OFF Pulse

TX, Squelch level H/L Power

0 Tone burst output / microphone mute

TX power supply control TX

0ITone unit strobe

Tone unit detection input

Squelch

Signal

Pulse

Low Low

Pulse None

Pull UP

No signal

Lock

High High

TX. Pulse

OFF

Normal

Equipped

15 P51

16 17

19 TXD

20 RXD

22 INTO

25 RST

26 27

29 30 VSS

31 P27

33 P25 DOWN

34 P24 KEY 1

INT2 RE2

P47

P46 DATA 0

INT1

P41 SQL 0

P40 TSQD I

P71

P70

XIN

XOUT

P26

P23

STB1

CLK 0

CTX CRX

RE1

RST

SCL

SDA

XIN

XOUT

GND I

PTT

KEY 2

0 PLL strobe permitted

I Rotary encoder down input OFF

Clock signal output

Data signal output

0 Data output for the cloning mode Pulse

Data input for the cloning mode

Rotary encoder up input OFF

Backup signal input

AF mute Mute

Tone signal detection input No Tone

Reset signal input

0 Clock input for E2PROM

10 Data input for E2PROM Pulse

Internal clock input

0 Internal clock output

GND

PTT key

UP key

Down key OFF

I Key 1 H/L

Key 2 SET OFF ON

Pulse

Normal

at work

Pulse

OFF ON

OFF

OFF ON

Inhibited

Backup

Tone

ON ON

Normal

o o

No.

Name Pin Name I/O

Descriptio n H

L H iZ

Pull UP

39 S31

40 S30 S30

47 S23 48

49 S21 S21

51 52 S18

P22

P21 KEY 4

P20 KEY 5 I

S29 S29 0 Segment 29 output

S28

S27

S26 S26 S25 S25

S24

S22 S22

S20

S19

KEY 3

S31

S28

S27 0

S24 0 Segment 24 output

S23 0 Segment 23 output Pulse

S20 S19 o S18 o

Key 3 CALL OFF

Key 4 V/M

Key 5 FUN

Segment 31 output

0 Segment 30 output

Segment 28 output

Segment 27 output

Segment 26 output Segment 25 output

0 Segment 22 output

0 Segment 21 output Pulse

Segment 20 output Pulse

Segment 19 output Pulse Segment 18 output Pulse

OFF

Pulse

Pulse Pulse

Pulse

ON ON

53 S17

54 55 S15 S15

57 S13 58

59 S11 S11

60 S10 S10

65 S5

66 67 S3 S3 o Segment 3 output Pulse 68

69 S1

S16 S16

S14

S12 S12

S9 S9 S8 S8

S4 S4

S17

S14 S13 0

S7 S6 o

S2 S1 0 Segment 1 output

Segment 17 output

o 0 Segment 16 output Pulse

Segment 15 output

Segment 14 output

Segment 13 output Pulse

Segment 12 output Pulse

0 0 Segment 11 output 0 Segment 10 output Pulse

Segment 9 output

0 0 Segment 8 output Pulse

o Segment 7 output Pulse

Segment 6 output Pulse

Segment 5 output

Segment 4 output

o Segment 2 output

Pulse

SO SO

Segment 0 output Pulse

No.

Name

Pin Name

I/O Description H L HiZ

Pull UP

71 72 VREF VREF I

78 VL3

79 80 VL1 VL1 I LCD power supply input

vcc

AVSS

COM3 COM3

COM2

COM1 COMO

VL2 VL2

VDD I

GND I

COM2 0 LCD common 2 output

COM1 COMO 0

VL3

Power supply

Reference voltage input GND

O LCD common 3 output

0 LCD common 1 output

LCD common 0 output

LCD power supply input

I I

LCD power supply input

Pulse

Pulse Pulse

SEMICONDUCTOR DATA

1) AK2341 (XA0239)

CTCSS Encoder/Decoder

No.

RXINO 0 AMP2 Output

3 TXINO 4

RXOUT 0

TXOUT

7 8

11 SDATA 12 SCLK 13

DETOUT

14 15 VSS 16 17 18

19 TLINO 20 RXTONE 21 TXTONE

AGNDIN

22 23

24 BIAS

I/O

Name

RXIN I

TXIN I

VDD

XOUT

STB

- I

XIN

Crystal Terminal (3.6864MHz)

o Crystal Terminal (3.6864MHz)

DCS

0 Tone Detection Output (Detect: Low)

DREF I Tone Detection Level Adjust Input TLINP TLINN I

RX Tone Signal Reference Input

o o o

I Analog Ground Input

AGND

Function

RX Signal Input

AMP1 Output

TX Audio Input RX Audio Output TX Audio Output

Power Supply (1.8 ~ 5.5V)

Strobe for Serial Data

Serial Data

Serial Clock

DCS Input

Ground

RX Tone Signal Input

AMP3 Output RX Tone Signal Output TX Tone Signal Output

Analog Ground Output

Bias Input

RXIN

RXINO

TXINO

TXIN

RXOUT

TXOUT

VDD

XIN

XOUT n z

STB

SDATA

SCLK

d =

n z

[Z Z

n z

Z U

= ]

Z Z 2

= □

zzn

BIAS

AGND

AGNDIN

TXTONE

RXTONE

Z D

TLINO

13 =Z1

Z □

Z Z 3

=□ =□

= l

TLINN

TLINP

DREF

VSS

DETOUT

DCS

Block Diagram

2 ) AN78L05M (XA0238)

5V Voltage Regulator

3) LA4425A (XA0410)

5W Audio Power Amplifiers

u u u

Output Common Input

AN78L05M

4) M5218FP (XA0068)

Dual Low Noise

Operational Amplifiers

Output 1 1

Inverting Input 1 2

Non Inverting Input 1 3

Power Supply Minus 4

1 2 3 4 5

8 Power Supply Plus

7 Output 2

6 Inverting Input 2

5 Non Inverting Input 2

5) M56760FP (XA0235)

540MHz Frequency Synthesizer

Serial data input terminal

Clock input terminal

Reset input terminal

Reference Bias input terminal

Local Oscillator input terminal fmax =540MHz

Output p ortl terminal

Output port2-terminal

Ground terminal

Function Table

P/N input

High or Low

High

Phase

Locked Hi-Z

Lead

S l t =

ere n z

RST C Z

REF tZ Z

FIN n z

swi n z

SW 2 I—

GND I

----

PD output

High

=]v c c

XIN

ZZÏ XOUT

2 CJ1

o o>

H D LOCK

ZZÏPD

T I

=□ LFI

ZZ] LFO

= D P /N

Power supply terminal 3 -5.5 V 14mA

Reference oscillator input terminal

Reference oscillator output terminal

Phase detector output terminal when locked Low

Phase detector output terminal

Low pass filter input terminal

Low pass filter output terminal

Phase switch input terminal of phase comparator

XIN

XOUT

FIN

REF

CPS RST

High

Low Low

Lag Lead Lag

Low Low

High

LFI LFO

6) M67746 (XA0412)

144 - 148MHz 60W

RF Power Module

I ?

Z E

3 O

CLO C CO

M67746

12 3 4

cvi

□

R-e

Q. ^

4-*

7) M68702H (XA0444)

1 50 - 175MHz 60W

RF Power Module

— *>

9-in

Q ^

s !

il £

D C

f i o .£

(TE2)

Supply voltage Vcc 17

Total current Input power Output power Operation case temperature Storage temperature Tstg

Zg=ZI=50Q

Supply voltage Total current

Input power Output power Operation case temperature Tc(op) Storage temperature

Zg=Z I=50ii

Ratings

Symbol

Icc 20 Pin (max) Po(max) Tc(op)

Symbol Ratings

Vcc

Icc Pin (max) Po(max)

Tstg -40 t o +110

Ratings

600

-30 to +110

-40 t o +110

20 A

600

-30 t o +110

Unit

V A

W °C °0

Unit

W °C °C

8) M68702L (XA0445)

135 - 160MHz 60W

RF Power Module

(TE1)

Ratings

Supply voltage

Total current Icc 20

Input power Output power Po(max) 75 Operation case temperature Storage temperature Tstg

Zg=ZI=50i2

Symbol

Vcc

Pin (max) 600

Tc(op) -30 t o +110

Ratings

-40 to +110

Unit

V A

W °C °C

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