Alinco DR135 User Guide

DR-135

Service Manual

CONTENTS

SPECIFICATIONS

1) GENERAL ................................................................ 2

2) TRANSMITTER ........................................................ 2

3) RECEIVER ............................................................... 2

CIRCUIT DESCRIPTION DR-135

1) Receiver System .................................................. 3, 4

2) Transmitter System............................................... 4, 5

3) PLL Synthesizer Circuit ........................................ 5, 6

4) CPU and Peripheral Circuits ................................. 6, 7

5) P ower Supply Circuit................................................. 7

6) M3826M8L

SEMICONDUCTOR DATA

1) M5218FP (XA0068)................................................11

2) NJM7808FA (XA0102)............................................ 11

3) TC4S66F (XA0115) ................................................ 11

4) TK10930VTL (XA0223) .......................................... 12

5) BU4052BF (XA0236).............................................. 13

6) TC4W53FU (XA0348) ............................................ 13

7) M64076GP (XA0352) ............................................. 1 4

8) LA4425A (XA0410)................................................. 15

9) M67746 (XA0412) .................................................. 15

10) µPC2710T (XA0449) .............................................. 16

11) NJM2902 (XA0596)................................................ 16

12) 24LC32A (XA0604) ................................................ 17

13) S-80845ALMP-EA9-T2 (XA0620)........................... 17

14) L88MS05TLL (XA0675).......................................... 17

15) Transistor, Diode, and LED Ontline Drawings ......... 18

16) LCD Connection (TTR3626UPFDHN) ................... 18

EXPLODED VIEW

1) Top and Front View ................................................. 19

2) Bottom View ........................................................... 20

3) LCD Assembly........................................................21

GP (XA0795)............................... 8~10

***

PARTS LIST

CPU.................................................................. 22, 23

DSUB ..................................................................... 23

Main Unit .......................................................... 23~26

Mechanical Parts.................................................... 26

Packing Parts ......................................................... 26

Speaker.................................................................. 27

TNC.................................................................. 27, 28

TNC (EJ-41U) Mechanical Parts ............................ 28

TNC (EJ-41U) Packing Parts .................................. 28

ADJUSTMENT

1) Adjustment Spot .................................................... 29

2) VCO and RX Adjustment Specification................... 30

3) Tx Adjustment Specification ................................... 30

4) Rx Test Specification............................................... 31

5) Tx Test Specification ............................................... 32

PC BOARD VIEW

1) CPU Unit Side A (UP 0400).................................... 33

2) CPU Unit Side B (UP 0400).................................... 33

3) Main Unit Side A (UP 0400).................................... 34

4) Main Unit Side B (UP 0400).................................... 34

Tnc Unit Side A (UP 0402) (DR-135TP only).................

Tnc Unit Side B (UP 0402) (DR-135TP only).................

SCHEMATIC DIAGRAM

1) CPU Unit ................................................................ 36

2) Main Unit ................................................................ 37

3) TNC Unit (DR-135TP only) ..................................... 38

BLOCK DIAGRAM ..................................................... 39

35 35

ALINCO,INC.

SPECIFICATIONS

1) GENERAL

Frequency coverage DR-135T, TG (U .S amature) 118.000 ~ 135.995MHz (AM RX)

136.000 ~ 173.995MHz (RX)

144.000 ~ 147.995MHz (TX) DR-135E, EG (European amature) 144.000 ~ 145.995MHz (RX, TX) DR-135TA, TAG (Commercial) 118.000 ~ 135.995MHz (AM RX)

136.000 ~ 173.995MHz (RX, TX) Operating mode 16K0F3E (Wide mode) 8K50F3E (Narrow mode) Frequency resolution 5, 8.33, 10, 12.5, 15, 20, 25, 30, 50 Number of memory channels 100 Antenna impedance 50Ω unbalanced Power requirement 13.8V DC ±15% (11.7 to 15.8V) Ground Method Negative ground Current drain Recieve 0.6A (Max.) 0.4A (Squelched) Transmit 11.0A Operating temperature -10 to 60°C Frequency stability ±1.0k Hz Dimensions 142 (w) × 40 (h) × 174 (d) mm

(142 × 40 × 188mm for projection included)

Weight Approx. 1.0kg

2) TRANSMITTER

Output power High: 50W (T, TG/E, EG) more than 33W(TA, TAG)

Mid:10W Low:5W Modulation system Variable reactance frequency modulation Maximum frequency deviation ±5kHz (Wide mode) ±2.5kHz (Narrow mode) Spurious emission -60dB Adjacent channel power -60dB Noise and hum ratio -40dB (Wide mode) -34dB (Narrow mode) Microphone impedance 2kΩ

3) RECEIVER

Sensitivity -12dBu for 12dB SINAD Receiver circuitry Double conversion superheterodyne Intermediate frequency 1st 21.7MHz 2nd 450kHz Squelch sensitivity -16dBu Adjacent channel selectivity -65dB (Wide mode) -55dB (Narrow mode) Intermoduration rejection ratio 60dB Spurious and image rejection ratio 70dB Audio output po wer 2.0W (8Ω, 10% THD)

! Note: All spesifications are subject to change without notice or obligation.

CIRCUIT DESCRIPTION DR-135

1) Receiver System

The receiver system is a double superheterodyne system with a 21.7MHz first IF and a 450kHz second IF.

1. Front End

The received signal at any frequency in the 136.000MHz to 173.995MHz r ange is passed through the low-pass filter (L116, L115, L114, L113, C204, C203, C202, C216 and C215) and tuning circuit (L105, L104 and D105, D104), and amplified by the RF amplifier (Q107). The signal from Q107 is then passed through the tuning circuit (L103, L102, and varicaps D103 and D102) and converted into 21.7MHz by the mixer (Q106). The tuning circuit, which consists of L105, L104, varicaps D105 and D104, L103, L102, varicaps D103 and D102, is controlled by the tracking voltage form the VCO. The local signal from the VCO is passed through the buffer (IC112), and supplied to the source of the mixer (Q106). The radio uses the lower side of the superheterodyne system.

2. IF Circuit

The mixer mixes the received signal with the local signal to obtain the sum of and difference between them. The crystal filter (XF102, XF101) selects 21.7MHz frequency from the results and eliminates the signals of the unwanted frequencies. The first IF amplifier (Q105) then amplifies the signal of the selected frequency.

3. Demodulator Circuit

4. Audio Circuit

After the signal is amplified by the first IF amplifier (Q105), it is input to pin 24 of the demodulator IC (IC108). The second local signal of 21.25MHz (shared with PLL IC reference oscillation), which is oscillated by the internal oscillation circuit in IC116 and crystal (X103), is input through pin 1 of IC108. Then, these two signals are mixed b y the internal mixer in IC108 and the result is conv erted into the second IF signal with a frequency of 450kHz. The second IF signal is output from pin 3 of IC108 to the ceramic filter (FL101 or FL102), where the unwanted frequency band of that signal is eliminated, and the resulting signal is sent back to the IC108 through pins 5. The second IF signal input via pin 5 is demodulated by the internal limiter amplifier and quadrature detection circuit in IC108, and output as an audio signal through pin 12.

The audio signal from pin 12 of IC108 is amplified by the audio amplifier (IC104:A),and switched by the signal s witch IC (IC111) and then input it to the de-emphasis circuit. and is compensated to the audio frequency characteristics in the de-emphasis circuit (R203, R207, R213, R209, C191, C218, C217) and amplified by the AF amplifier (IC104:D). The signal is then input to volume (VR1) . The adjusted signal is sent to the audio power amplifier (IC117) through pin 1 to drive the speaker.

5. Squelch Circuit

The detected output which is outputted from the pin 12 of IC108 is inputted to pin 19 of IC108 after it was been amplified by IC104:A and it is outputted from pin 20 after the noise component was been eliminated from the composed band pass filter in the built in amplifier of the IC, then the signal is rectified b y D106 to convert into DC component. The adjusted voltage level at VR101 is delivered to the comparator of the CPU . The voltage is led to pin 2 of CPU and compared with the setting voltage . The squelch will open if the input voltage is low er than the setting v oltage. During open squelch, pin 30 (SQC) of the CPU becomes “L” le vel, AF control signal is being controlled and sounds is outputted from the speaker .)

6. AIR Band Reception (T only)

When the frequency is within 118 ~ 135.995MHz, Q110 automatically turns ON, pin 14 of IC108 becomes “L” le v el and the condition becomes in AM detection mode. The receiver signal passed through the duplexer is let to the antenna switch (D107, D101). After passing through the band-pass filter, the signal is amplified by RF amplifier Q112. Secondly the signal is mix ed with the signal from the first local oscillator in the first-mixer Q106, then conver ted into the first IF. Its unwanted signal is let to IC106, pin24. Then converted into the second IF. and is demodulated by AM decoder of IC106,and is output from pin13 as the AF signal.

7. WIDE/NARRO W switching circuit

The 2nd IF 450 kHz signal which passes through filter FL101 (wide) and FL102 (narrow) during narrow, changes its width using the width control switching IC103 and IC102.

2) Transmitter System

1. Modulator Circuit

The audio signal is converted to an electric signal by the microphone, and input it to the microphone amplifier (Q6). Amplified signal which passes through mic-mute control IC109 is adjusted to an appropriate mic-volume b y means of mic-gain adjust VR106. IC114:A and B consists of two operational amplifiers; one amplifier (pins 1, 2, and 3) is composed of pre-emphasis and IDC circuits and the other (pins 5, 6, and 7) is composed of a splatter filter. The maximum frequency deviation is obtained by VR107. and input to the signal switch (IC113) (9600 bps packet signal input switch) and input to the cathode of the varicap of the VCO, to change the electric capacity in the oscillation circuit. This produces the frequency modulation.

2. Po wer Amplifier Cir cuit

The transmitted signal is oscillated by the VCO , amplified by the drive amplifier (IC112) and younger amplifier (Q115), and input to the final power module (IC110). The signal is then amplified by the final po wer module (IC110) and led to the antenna switch (D110) and low-pass filter (L113, L114, L115, L116, C215, C216, C202, C203 and C204), where unwanted high harmonic wav es are reduced as needed, and the resulting signal is supplied to the antenna.

3. APC Circuit

Part of the transmission power from the lo w-pass filter is detected by D111 and D112, converted to DC. The detection voltage is passed through the APC circuit (Q118, Q117, Q116), then it controls the APC voltage supplied to the younger amplifier Q115 and the final power module IC110 to fix the transmission pow er.

3) PLL Synthesizer Circuit

1. PLL

The dividing ratio is obtained by sending data from the CPU (IC1) to pin 2 and sending clock pulses to pin 3 of the PLL IC (IC116). The oscillated signal from the VCO is amplified by the buffer (Q134 and Q135) and input to pin 15 of IC116. Each programmab le divider in IC116 divides the frequency of the input signal by N according to the frequency data, to generate a comparison frequency of 5 or 6.25kHz.

2. Reference Frequency Circuit

The reference frequency appropriate for the channel steps is obtained by dividing the 21.25MHz reference oscillation (X103) by 4250 or 3400, according to the data from the CPU (IC1). When the resulting frequency is 5kHz, channel steps of 5, 10, 15, 20, 25, 30, and 50kHz are used. When it is 6.25kHz, the

12.5kHz channel step is used.

3. Phase Comparator Circuit

The PLL (IC116) uses the reference frequency, 5 or 6.25kHz. The phase comparator in the IC116 compares the phase of the frequency from the VCO with that of the comparison frequency , 5 or 6.25kHz, which is obtained b y the internal divider in IC116.

4. PLL Loop Filter Circuit

If a phase difference is f ound in the phase comparison between the ref erence frequency and VCO output frequency , the charge pump output (pin 13) of IC116 generates a pulse signal, which is converted to DC voltage by the PLL loop filter and input to the varicap of the VCO unit for oscillation frequency control.

5. VCO Circuit

A Colpitts oscillation circuit driven by Q131 directly oscillates the desired frequency. The frequency control voltage determined in the CPU (IC1) and PLL circuit is input to the varicaps (D122 and D123). This change the oscillation frequency, which is amplified by the VCO buffer (Q134) and output from the VCO area.

6. VCO Shift Circuit

During transmission or the AIR band Reception (118 ~ 136 MHz), the VCO shift circuit turns ON Q138, change control the capacitance of L123 and safely oscillates the VCO by means of H signal from pin 16 of IC116.)

4) CPU and Peripheral Circuits

1. LCD Display Circuit

The CPU turns ON the LCD via segment and common terminals with 1/4 the duty and 1/3 the bias, at the frame frequency is 64Hz.

2. Dimmer Circuit

The dimmer circuit makes the output of pin 13 of CPU (IC1) into “H” le v el at set mode, so that Q9 and Q3 will turn ON to make the lamp control resistor R84 short and make its illumination bright. But on the other hand, if the dimmer circuit makes pin 13 into “L” level, Q9 and Q3 will turn OFF, R84’s illumination will become dimmer as its hang on voltage f alls down in the working LED (D11, D2, D5, D3 and D6).

3. Reset and Backup

When the power f orm the DC cable increases from Circuits 0 V to 2.5 or more, “H” level reset signal is output form the reset IC (IC4) to pin 33 of the CPU (IC1), causing the CPU to reset. The reset signal, however, waits at 100, and does not enter the CPU until the CPU clock (X1) has stabilized.

4. S(Signal) Meter Circuit

5. DTMF Encoder

6. Tone Encoder

7. DCS Encoder

The DC potential of pin 16 of IC106 is input to pin 1 of the CPU (IC1), converted from an analog to a digital signal, and displayed as the S-meter signal on the LCD.

The CPU (IC1) is equipped with an internal DTMF encoder. The DTMF signal is output from pin 10, through R35, R34 and R261 (for level adjustment), and then through the microphone amplifier (IC114:A), and is sent to the varicap of the VCO f or modulation. At the same time, the monitoring tone passes through the AF circuit and is output form the speaker .

The CPU (IC1) is equipped with an internal tone encoder.The tone signal (67.0 to 250.3Hz) is output from pin 9 of the CPU to the varicap (D122 and D123) of the VCO for modulation.

The CPU (IC1) is equipped with an internal DCS code encoder. The code (023 to 754) is output from pin 9 of the CPU to the varicap (D124) of the PLL reference oscillator. When DCS is ON, DCS MUTE circuit (Q126-ON, Q133-ON, Q132-OFF) works. The modulation activates in X103 side only.

8. CTCSS, DCS Decoder

The voice band of the AF output signal from pin 1 of IC104:A is cut by sharp active filter IC104:B and C (VCVS) and amplified, then led to pin 4 of CPU . The input signal is compared with the programmed tone frequency code in the CPU. The squelch will open when they match. During DCS, Q108 is ON, C156 is working and cut off frequency is lowered.

5) Power Supply Circuit

When power supply is ON, there is a “L” signal being inputted to pin 39 (PSW) of CPU which enables the CPU to work. Then, “H” signal is outputted from the pin 41 (C5C) of CPU and drives ON the power supply switch control Q8 and Q7 which turns the 5VS ON. 5VS turns ON the PLL IC116, main power supply switch Q127 and Q122, AF PO WER IC117 and the 8 V of AVR (IC115). During reception, pin 29 (R5) of CPU outputs “H” level, Q124 is ON, and the reception circuits supplied by 8 V. While during transmission, pin 28 (T5) of CPU outputs “L” level which is re verse by Q11 so that the output in Q128 will be “H” level, Q123 is ON, and the transmission circuit is supplied by 8 V. Or, in the case when the condition of PLL is UNLOCK, “H” level is outputted from pin 14 of IC106, UNLOCK switch Q129

is ON, transmission switch Q128 is OFF which makes the transmission to stop.

1. ACC External Power Supply Terminal

When optional power supply cord DEC-37 etc. is connected to the external power supply terminal JK101, with ACC power supply ON, switch Q101 will turn ON, 5 V of AVR IC101 pin 2 (STB) becomes “L” which mak es C5V to turn ON. With this, it can turn the power supply of the radio ON.

6) M3826M8L***GP (XA0795)

CPU Terminal Connection

(TOP VIEW)

No. Pin Name Function I/O PU Logic Descript ion

1 P67/AN7 SMT I - A/D S-meter input 2 P66/AN6 SQL I - A/D Noise level input f or squelch 3 P65/AN5 BAT I - A/D Battery voltage input 4 P64/AN4 TIN I - A/D CTCSS tone input/DSC code input 5 P63/SCLK22/AN3 BP1 I - A/D Band plan 1 6 P62/SCLK21/AN2 BP2 I - A/D Band plan 2 7 P61/SOUT2/AN1 DCSW O - Activ high DCS signal mute 8 P60/SIN2/AN0 RE2 I - Activ low Rotary encoder input 9 P57/ADT/DA2 T OUT O - D/A CTCSS tone output/DCS tone output

10 P56/DA1 DOUT O - D/A DTMF output

11 P55/CNTR1 SCL O - Pulse Serial clock for EEPROM 12 P54/CNTR0 TBST O - Pulse Tone burst output 13 P53/RTP1 BP4 I - - Band plan 4 14 P52/RTP0 MUTE I/O - Activ low Microphone mute/Security alarm SW 15 P51/PWM3 CLK O - Pulse Serial clock output for PLL,scr amble 16 P50/PWM DATA I/O - Pulse 17 P47/SR OY1 TSTB I/O - Activ low/Pulse

Serial data output for PLL scramble/PLL unlock signal input Trunking board detection / Strobe signal to trunking board

18 P46/SCLK1 STB O - Pulse Strobe for PLL IC 19 P45/TXD UTX O - Pulse UART data transmission output 20 P44/RXD RTX I - Pulse UART data reception output 21 P43/

/TOUT BEEP I/O - Pulse/Activ low Beep tone/Band plan 3 22 P42I/NT2 SEC I - Activ high Security voltage input 23 P41/INT1 RE1 I - Activ low Rotary encoder input 24 P40 DSQ I - Activ high Digital squelch input 25 P77 PTT I - Activ low PTT input 26 P7 SSTB O - Pulse/Activ low Strobe signal to scramble IC/Security mode 27 P75 W/N O - Activ low Wide Narrow SW 28 P74 T5 O - Activ low TX power ON/OFF output 29 P73 R5 O - Activ high RX power ON/OFF output 30 P72 SQC O - Activ low SQL ON/OFF 31 P71 C/S O - Activ low Digital scramble ON/OFF 32 P70/INTO BU I - Activ low Backup signal detection input 33 RESET RESET I - Activ low Reset input 34 Xcin Xcin - - - 35 Xcout Xcout - - - 36 Xin Xin - - - Main clock input 37 Xout Xout - - - Main clock output 38 Vss GND - - - CPU GND 39 P27 PSW I - Avtiv low Power switch input 40 P26 SDA O - Pulse Serial data for EEPROM 41 P25 C5C O - Activ high C5V power ON/OFF output 42 P24 AIR O - Activ high Air band SW / Tx middle power 43 P23 LOW O - Activ high Tx low power 44 P22 EXP O - Activ high Trunking data SW 45 P21 SW6 I Activ lo w Key sw6 (SQL) 46 P20 SW5 I Activ lo w Key sw5 (CALL) 47 P17 SW4 I Activ low Key sw4 (TSQ) 48 P16 SW3 I Activ low Key sw3 (MHz) 49 P15/SEG39 SW2 I Activ low Key sw2 (V/M) 50 P14/SEG38 SW1 I Activ low Key sw1 (FUNC) 51 P13/SEG37 DOWN I Activ low Mic down input 52 P12/SEG36 DUD I - - Digital unit detect 53 P11/SEG35 SCR I Active low Scramble IC ready signal/Packet PTT 54 P10/SEG34 UP I Active low Mic down input 55 P07/SEG33 S33 O - - LCD segment signal

No. Pin Name Function I / O PU Logic Descripti on

56 P06/SEG32 S32 O - 57 P05/SEG31 S31 O - 58 P04/SEG30 S30 O - 59 P03/SEG29 S29 O - 60 P02/SEG28 S28 O - 61 P01/SEG27 S27 O - 62 P00/SEG26 S26 O - 63 P37/SEG25 S25 O - 64 P36/SEG24 S24 O - 65 P35/SEG23 S23 O - 66 P34/SEG22 S22 O - 67 P33/SEG21 S21 O - 68 P32/SEG20 S20 O - 69 P31/SEG19 S19 O - 70 P30/SEG18 S18 O - 71 SEG17 S17 O - 72 SEG16 S16 O - 73 SEG15 S15 O - -

LCD segment signal

74 SEG14 S14 O - 75 SEG13 S13 O - 76 SEG12 S12 O - 77 SEG11 S11 O - 78 SEG10 S10 O - 79 SEG9 S9 O - 80 SEG8 S8 O - 81 SEG7 S7 O - 82 SEG6 S6 O - 83 SEG5 S5 O - 84 SEG4 S4 O - 85 SEG3 S3 O - 86 SEG2 S2 O - 87 SEG1 S1 O - 88 SEG0 S0 O - 89 Vcc VDD - - - CPU power terminal 90 Vref Vref - - - AD converter power supply 91 A vss Avss - - - AD converter GND 92 COM3 COM3 O - - LCD COM3 output 93 COM2 COM2 O - - LCD COM2 output 94 COM1 COM1 O - - LCD COM1 output 95 COM0 COM0 O - - LCD COM0 output 96 VL3 VL3 - - 97 VL2 VL2 - - -

LCD power supply

98 C2 I - - - 99 C1 C1 - - - -

100 VL1 VL1 I - A/D LCD power supply

SEMICONDUCTOR DATA

1) M5218FP (XA0068)

Dual Low Noise Operational Amplifiers

Output 1

Inverting Input 1

Non Inverting Input 1

Power supply Minus

2) NJM7808FA (XA0102)

Pin Assignment

1. OUTPUT

2. COMMON

3. INPUT

Power Supply Plus

Output 2

Inverting Input 2

Non Inverting Input 2

123

3) TC4S66F (XA0115)

Bilateral Switch

4) TK10930VTL (XA0223)

Narrow Band FM IF IC

IF IN

10.7MHz

Vcc

0.01

RF INPUT

24 23 22 21 20 19 18 17 16 15 14 13

30K 270K

GND

COMP OUT

COMP IN

NOISE AMP OUTPUT

1 F

AM AGC

NOISE AMP INPUT

AM LOW CUT

0.033

RSSI OUT

0.1

68K

IF GND

AM SW

4.7K

AM AF OUT

AF OUTPUT (AM)

0.022

OSC

MIX

123456789101112

33p

OSC(E)

120p

10.245MHz OSC(B)

Vcc

MIX OUT

CFU455D

AMP

AM IF INPUT

AM DET

AGC

0.1

DECOUPLING

IF AMP

0.1

FM IF INPUT

S DET

0.1

DECOUPLING

0.1

2.2K

FM DET

30K

LIM OUT

10 F

QUAD IN

7BRE-7437Z

0.1 F

FM AF OUT

Vcc 3V

Parameter Symbol Ratings Unit Supply voltage Vcc max 10.0 V Power dissipation Pd 400 mV Storage temperature Tstg -55~+150 Operating temperature Top -30~+75 Operating voltage Vop 2.5~8.5 V Operating frequency fop ~60 MHz

Parameter Symbol

Ratings

Min Typical Max

Unit Condition

Ta=25 Vcc=3V

Supply Current 1 lcc1 6.8 8.9 mA No signal, AM ON Supply Current 2 lcc2 3.9 5.3 mA No signal, AM OFF Mixer Coversion Gain Mg 20 dB Mixer Input Impedance Mz 3.6 K

DC Test

FM Limiting Sensitivity Limit 2.0 8.0

V -3.0dB Output Voltage Vo1 85 150 230 mVrms 10mVin +/-3kHz DEV Distortion THD1 1.0 2.0 % 10mVin +/-3kHz DEV Output Impedance Zo 800

10mVin Filter Gain Gf 30 38 dB Fin=30kHz, Vo=100mV Scan Control Hi Voltage SH 2.3 V Squelch input=2.5V Scan Control Low Voltage SL 0.3 V Squelch input=0V Squelch Hysteresis Hys 30 mV S meter Output Voltage S0 0.05 0.5 V Vin=0mV, RS=68k

S meter Output Voltage S1 0.05 0.5 0.9 V Vin=0.01mV, RS=68k S meter Output Voltage S2 0.7 1.2 1.7 V Vin=0.1mV, RS=68k S meter Output Voltage S3 1.2 1.8 2.5 V Vin=1mV, RS=68k

S meter Output Voltage S4 1.6 2.3 2.9 V Vin=10mV, RS=68k S meter Output Voltage S5 1.8 2.4 2.9 V Vin=100mV, RS=68k AM

Sensitivity US 20 15

required input level to get

20mV rms output

Output Voltage Vo2 60 120 160 mVrms 1kHz, 30%, Vin=1mV Distortion-1 THD2 1.0 2.0 % 1kHz, 30%, Vin=1mV Distortion-2 THD3 2.0 4.0 % 1kHz, 30%, Vin=1mV S/N S/N 40 48 dB 1kHz, 30%, Vin=1mV AM OFF Vo -0.3 0.3 %

AF OUTPUT (FM)

8.2K

0.01

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