Aiwa 4ZG1 Diagram
WIRING-2 (VOS1RMDSM, VOS1RMDS)
14
13 12 11 10 9 8
7
6
5
432
1
A
B
C
D
E
F
G
H
I
J
1413
1
234567
8
9
10
11 12 13
14
A
B
C
D
E
F
G
H
I
J
1615
SCHEMATIC DIAGRAM-1
VOS1NDSHM,
VOS1RNDSHM,
VOS1RNDSC
MODEL
VOS1RMDSM,
VOS1RMDS
MODEL
VOS1RMDSM,
VOS1RMDS MODEL
TO
MAIN UNIT
Q203
DTC114YKA
DIGITAL
OUT
SWITCH
VOS1RMDSM,
VOS1RMDS
MODEL
VOS1NDSHM, VOS1RNDSM, VOS1RMDSM : 3ZG-2 E3
VOS1RMDS,VOS1RNDSC : KSM-2131FAM
DRIVE C.B
(VOS1NDSHM, VOS1RNDSM,
VOS1RMDSM)
MOTOR C.B
(VOS1RMDS, VOS1RNDSC)
SLP6130C-81H-S
VOS1RMDSM,
VOS1RMDS
MODEL
1817
SCHEMATIC DIAGRAM-2
C560
0.01
BK
MSM54V16258 B/BS D RAM
2019
WIRING-3 (MECHA)
1
A
234567
WAVE FORM
1 IC101 Pin ‹ (RF-O) VOLT/DIV: 200mV
TIME/DIV: 0.5µS
MAX
1.2±0.1Vp-p
0V
6
IC504 Pin º UCAS VOLT/DIV: 1V
(Pin ⁄ LCAS) TIME/DIV: 2µS
___________
___________
B
2 IC501 Pin DA XCK VOLT/DIV: 1V
16.93MHz TIME/DIV: 20nS
C
D
3 IC501 Pin GCK OUT VOLT/DIV: 1V
42.3MHz TIME/DIV: 10nS
E
EYE PATTERN
must be CLEAR and MAX
86
107
____________
7
IC501 Pin VSync VOLT/DIV: 1V
NTSC TIME/DIV: 5mS
IC501 Pin VSync VOLT/DIV: 1V
PAL TIME/DIV: 5mS
93
____________
93
F
4 IC503 Pin 8 VCK VOLT/DIV: 1V
G
H
I
J
27MHz±1.35kHz TIME/DIV: 10nS
5 IC506 Pin ! OSD CLK VOLT/DIV: 1V
13.5MHz±675Hz TIME/DIV: 20nS
8
IC501 Pin HSync VOLT/DIV: 1V
PAL TIME/DIV: 20µS
IC501 Pin HSync VOLT/DIV: 1V
NTSC TIME/DIV: 20µS
101
101
____________
____________
K
21
22
IC DESCRIPTION
IC, CXA1992AR
Pin No. Pin Name I/O Description
1
2
3
FEO
FEI
FDFCT
Output terminal for focus error amplifier. Internally connected to window comparator
O
input for bias condition.
Input terminal for focus error.
I
Capacitor connection terminal for time constant used when there is defect.
I
10
11
12
13
14
15
16
4
5
6
7
8
9
FGD
FLB
FE_O
FEM
SRCH
TGU
TG2
FSET
TA_M
TA_O
SL_P
SL_M
SL_O
This pin is connected to GND via capacitor when high frequency gain of the focus
I
servo is attenuated.
This is a pin where the time constant is externally connected to raise the low frequency
I
gain of the focus servo.
Focus drive output.
O
Focus amplifier inverted input pin.
I
This is a pin where the time constant is externally connected to generate the focus
I
search waveform.
This is a pin where the selection time constant is externally connected to set the
I
tracking servo the high frequency gain.
This is a pin where the selection time constant is externally connected to set the
I
tracking high frequency gain.
Pin for setting peak of the phase compensator of the focus tracking.
I
Tracking amplifier inverted input pin.
I
Tracking drive output.
O
Sled amplifier non-inverted input pin.
I
Sled amplifier inverted input pin.
I
Sled drive output.
O
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
ISET
Vcc
LOCK
CLK
XLT
DATA
XRST
C_OUT
SENS1
SENS2
FOK
CC2
CC1
CB
CP
The current which determines height of the focus search, track jump and sled kick is
I
input with external resistance connected.
Power supply.
I
“L” setting starts sled disorder-prevention circuit. (Not pull-up resistance)
I
Clock input for serial data transfer from CPU. (No pull-up resistance)
I
Latch input from CPU. (No pull-up resistance)
I
Serial data input from CPU. (No pull-up resistance)
I
Reset system at “L” setting. (No pull-up resistance)
I
Signal output for track number counting.
O
FZC, DFCT1, TZC, BALH, TGH, FOH, or ATSC is output depending on the
O
command from CPU.
DFCT2, MIRR, BALL, TGL or FOL is output depending on the command from CPU.
O
Output terminal for focus OK comparator.
O
Input pin where the DEFECT bottom hold output is capacitance coupled.
I
DEFECT bottom-hold output terminal. Internally connected to interruption comparator
O
input.
Connection terminal for DEFECT bottom-hold capacitor.
I
Connection terminal for MIRR hold-capacitor.
I
Anti-reverse input terminal for MIRR comparator.
23
Pin No. Pin Name I/O Description
32
33
34
RF_I
RF_O
RF_M
I
Input terminal by capacity combination of RF summing amplifier.
O
Output terminal of RF summing amplifier. Checkpoint of Eye pattern.
Anti-reverse input terminal for RF summing amplifier.
The gain of RF amplifier is decided by the connection resistance between RF_M and
I
RFO terminals.
35
36
37
38, 39
40
41, 42
43
44
45
46
47
48
49
50
RFTC
LD
PD
PD1, PD2
FEBIAS
F, E
EI
VEE
TEO
LPFI
TEI
ATSC
TZC
TDFCT
O
I/O
—
—
O
This is a pin where the selection time constant is externally connected to control the
I
RF level.
APC amplifier output terminal.
I
APC amplifier input terminal.
RFI-V amplifier inverted input pin.
I
These pins are connected to the A+C and B+C pins of the optical pickup, receiving by
currents input.
Bias adjustment pin of the focus error amplifier.
F and EIV amplifier inverted input pins.
I
These pins are connected to the F and E of the optical pickup, receiving by current
input.
Gain adjustment pin of the I-V amplifier E. (When not in use of BAL automatic
adjustment)
GND connection pin.
Output terminal for tacking-error amplifier. Output E-F signal.
I
BAL adjustment comparator input pin. (Input through LPF from TEO)
I
Input terminal for tracking error.
I
Window-comparator input terminal for detecting ATSC.
I
Input terminal for tracking-zero cross comparator.
I
Capacitor connection pin for the time constant used when there is defect.
51
52
VC
FZC
O
Output terminal for DC voltage reduced to half of VCC+VEE.
I
Input terminal for focus-zero cross comparator.
24
IC, CXD2540Q
Pin No. Pin Name I/O Description
1
2
3
FOK
FSW
MON
I
Focus OK input. Used for SENS output and the servo auto sequencer.
O
Spindle motor output filter switching output.
O
Spindle motor on/off control output.
10
11
12
13
14
15
16
17
18
19
20
21
22
4
5
6
7
8
9
MDP
MDS
LOCK
NC
VCOO
VCOI
TEST
PDO
VSS
PWMI
V16M
VCTL
VPCO
VCKI
FILO
FILI
PCO
AVSS
CLTV
O
Spindle motor servo control.
O
High, when sampled value of GFS at 460Hz is high.
O
Low, when sampled value of GFS at 460Hz is low by 8 times successively.
—
Not used.
O
Analog EFM PLL oscillation circuit output.
I
Analog EFM PLL oscillation circuit input. fLOCK=8.6436MHz.
I
TEST pin.
O
Analog EFM PLL charge pump output.
—
GND.
I
Spindle motor external control input.
O
VCO2 oscillation output for the wide-band EFM PLL.
I
VCO2 control voltage input for the wide-band EFM PLL.
O
Wide-band EFM PLL charge pump output.
I
VCO2 oscillation input for the wide-band EFM PLL.
O
Multiplier PLL (slave=digital PLL) filter output.
I
Multiplier PLL filter input.
O
Multiplier PLL charge pump output.
—
Analog GND.
I
Multiplier VCO1 control voltage input.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
AVDD
RF
BIAS
ASYI
ASYO
ASYE
NC
PSSL
WDCK
LRCK
VDD
DA16
DA15
DA14
DA13
DA12
—
Analog power supply (5V).
I
EFM signal input.
I
Constant current input of the asymmetry circuit.
I
Asymmetry comparator voltage input.
O
EFM full-swing output.
I
Low: asymmetry circuit off; high: asymmetry circuit on.
—
Not used.
I
Audio data output mode switching input. Low: serial output; high: parallel output.
O
D/A interface for 48-bit slot. Word clock f=2Fs.
O
D/A interface for 48-bit slot. LR clock f=Fs.
—
Power supply (5V).
DA16 (MSB) output when PSSL=1.
O
48-bit slot serial data (two’s complement, MSB first) when PSSL=0.
O
DA15 output when PSSL=1. 48-bit slot bit clock when PSSL=0.
DA14 output when PSSL=1.
O
64-bit slot serial data (two’s complement, LSB first) when PSSL=0.
O
DA13 output when PSSL=1. 64-bit slot bit clock when PSSL=0.
O
DA12 output when PSSL=1. 64-bit slot LR clock when PSSL=0.
25
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