Acer ASPIRE VX5-591G Schematic

A

1 1

2 2

B

C

D

E

Compal Confidential

C5PM2 MB Schematic Document

LA-E361P

3 3

Rev:1.0

2016.10.27

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Cover Sheet

Cover Sheet

Cover Sheet

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

C5PM2_LA-E361P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

1 61Friday, October 28, 2016

1 61Friday, October 28, 2016

1 61Friday, October 28, 2016

E

1.0

1.0

1.0

A

HDMI Conn.

B

C

D

E

Fan Control*2

page 42

1

HDMI
PS8407A

page 31

NGFF

WLAN

USB port 7

2

3

RTC CKT.

Power On/Off CKT.

DC/DC Interface CKT.

4

Power Circuit DC/DC

HDMI x 4 lanes

page 37

PCIE 2.0
5GT/s

port 3

Realtek 8111H

RJ45 conn.

page 21

page 41

page 43

page 44~61

A

page 34

PCIE 3.0 x4
8GT/s

Port 9-12

page 32

PCIE 2.0
5GT/s

port 4

LAN(GbE)

page 32.

Sub Board

LS-E361P
FUN/B

LS-E362P
LED/B

eDP

SATA Re-Driver

PARADE PS8527

SATA HDD Conn.

page 38

page 33

page 33

Kabylake H PROCESSOR

page 30

eDP

DDI

Flexible IO

page 38

SATA3.0

6.0 Gb/s

port 3

Touch Pad Int.KBD

PS2 / I2C

page 41

B

BGA1440
(42X28) (SKL-H_4+2)

Processor

Skylake PCH - H
FCBGA(23X23)

837pin FCBGA

LPC/eSPI BUS

CLK=24MHz

ENE
KB9022/9032

page 39

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

X4 DMI

page 41

Memory BUS

Dual Channel

1.2V DDR4 1333/1600

PEG x16

page 06~13

8GT/s

USB 3.0
conn x2

USB (port 1,2)

USBx8

page 36 page 30

3.3V 24MHz

page 16~22

TPM

page 41

48MHz

HD Audio

SPI

SPI ROM x1

page 17

www.schematic-x.blogspot.com

Compal Secret Data

Compal Secret Data

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

C

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Interleaved Memory

Nvidia N17P-GX
with gDDR5 x4

USB 3.0
Type-C x1

(port 3)

USB/B

page 35

Int. Speaker

D

260 pin DDR4-SO-DIMM X1

BANK 0, 1, 2, 3

page 14

260pin DDR4-SO-DIMM X1

BANK 4, 5, 6, 7

page 15

Card Reader

page 23~29

CMOS
Camera

USB (port 9)

POA

USB (port 11)

page 31

Card Reader
RTS5170

on SUB/B

USB2.0
USB (port 10)

page 33

HDA Codec

ALC255

page 40

Int. DMIC

page 40

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet

Date: Sheet

Date: Sheet

on Sub/B

page 33 page 33

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Block Diagrams

Block Diagrams

Block Diagrams

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

UAJ

on Sub/B

E

of

2 61Friday, October 28, 2016

of

2 61Friday, October 28, 2016

of

2 61Friday, October 28, 2016

1

2

3

4

1.0

1.0

1.0

A

B

C

D

E

Board ID Table for AD channel

Vcc 3.3V +/- 5%

Board ID

1 1

2 2

100K +/- 5%Ra

0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19

0
12K +/- 1% 0.347 V 0.345 V 0.360 V
15K +/- 1%
20K +/- 1%
27K +/- 1%
33K +/- 1%
43K +/- 1%
56K +/- 1%
75K +/- 1%
100K +/- 1%
130K +/- 1%
160K +/- 1%
200K +/- 1%
240K +/- 1%
270K +/- 1%
330K +/- 1%
430K +/- 1%
560K +/- 1%
750K +/- 1%

NC

Rb V min

BID

0.423 V 0.430 V 0.438 V

1.398 V

1.634 V

1.849 V

2.015 V

2.185 V

2.316 V

2.395 V

2.521 V

2.667 V

2.791 V

2.905 V

3.000 V

V typ

BID

0.000 V

1.414 V

1.650 V

1.865 V

2.031 V

2.200 V

2.329 V

2.408 V

2.533 V

2.677 V

2.800 V

2.912 V

3.000 V

V

BID

0.300 V

1.430 V

1.667 V

1.881 V

2.046 V

2.215 V

2.343 V

2.421 V

2.544 V

2.687 V

2.808 V

2.919 V

max

EC AD

0x00 - 0x13
0x14 - 0x1E
0x1F - 0x25
0x26 - 0x300.541 V 0.550 V 0.559 V
0x31 - 0x3A0.691 V 0.702 V 0.713 V
0x3B - 0x450.807 V 0.819 V 0.831 V
0x46 - 0x540.978 V 0.992 V 1.006 V
0x55 - 0x641.169 V 1.185 V 1.200 V
0x65 - 0x76
0x77 - 0x87
0x88 - 0x96
0x97 - 0xA4
0xA5 - 0xAF
0xB0 - 0xB7
0xB8 - 0xBF
0xC0 - 0xC9
0xCA - 0xD4
0xD5 - 0xDD
0xDE - 0xF0
0xF1 - 0xFF

I2C Address Table

BUS

Device

I2C_0 (+3VS) Touch Panel

Address(7 bit)

reserved

TM-P2969-001 (Touch Pad)I2C_1 (+3VS)

SB8787-1200 (Touch Pad)

PCH_SMBCLK

(+3VS)

PCH_SML1CLK

(+3VS)

EC_SMB_CK1
(+3VLP)

3 3

DIMM1
DIMM2

LIS3DHTR(G-sensor)

N17P-GX (VGA)

EC

BQ24780 (Charger IC)

BATTERY PACK

0x30

0x9E

0x12
0x16

Write

Address(8bit)

Read

Power State

STATE

S0 (Full ON) ON ON ON ONHIGH HIGH HIGH

S3 (Suspend to RAM)

S4 (Suspend to Disk)

S5 (Soft OFF)

SIGNAL

SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

LOW HIGH

BOM Structure Table

BOM Option Table

Item BOM Structure

Unpop

Connector
EMC requirement
EMC requirement depop
UMA only
TPM

LPC MODE for EC LPC@
BA Serial

dGPU

N17P-G0
N17P-G1 G1@
VRAM BOM Select
DMIC*1
For Acer IOAC
No Acer IOAC
POA

@

CONN@
EMC@
XEMC@

UMA@

TPM@

CMC@CMC

BA@
VGA@
G0@

X76@

DMIC@
IOAC@
NIOAC@

FP@

ONONON

HIGH

LOWLOW

HIGH

OFF

ON

OFFLOW LOW LOW

OFF

OFF

OFF

OFF

OFF

OFF

Voltage Rails

Power Plane

+RTCVCC

+19V_VIN
+12.6V_BATT
+19VB
+3VLP +19VB to +3VLP power rail for suspend power
+5VALW
+3VALW System +3VALW always on power rail
+3VALW_DSW +3VALW power for PCH DSW rails
+3VALW_PCH_PRIM
+3VALW_SPI
+1.0VALW +1.0V Always power rail

+1.0V_VCCST

+5VS System +5V power rail
+3VS

+1.0VS_VCCSTG +1.0VALW_PRIM Gated version of VCCST

+0.6VS_VTT

+VCC_CORE
+VCC_GT
+VCCIO

+VCC_SA

+VGA_CORE

+1.35VSDGPU +1.35VS power rail for GPU
+1.0VSDGPU +1.0VS power rail for GPU

+VGA_CORE_S

Description
RTC Battery Power
Adapter power supply
Battery power supply
AC or battery power rail for power circuit.

+5V Always power rail

+3VALW power for PCH power rails

+3VALW_PRIM supply for the SPI IO

DDR4 +1.2V power rail+1.2V_VDDQ
Sustain voltage for processor in Standby modes

System +3V power rail

DDR +0.6VS power rail for DDR terminator .
Core voltage for CPU

Sliced graphics power rail

CPU IO power rail

System Agent power rail

+1.8VS power rail for GPU(AON rails)+1.8VSDGPU_AON
+1.8VS power rail for GPU GC6+1.8VSDGPU_MAIN
Core voltage for VGA

Core voltage for VGA

BOARD ID Table

Board ID

0
1
2
3
4
5
6
7

PCB Revision

0.1

0.2

0.3

1.0

S0

ON
N/A N/A N/A

N/A

ON
ON
ON
ON
ON

ON
ON
ON ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON
ON

ON

S4

S3

ON ON

ON

N/A
N/A

N/A N/A

N/A

ON ON

ON

ON ON

ON

ON

ON

ON ON

ON
ON
ON ON ONON

ON

ON

ON

OFF
OFF
OFF

OFF
OFF OFF
OFF OFF OFF

OFF

OFF

OFF

OFF

OFF

OFF
OFF OFF OFF

OFF

OFF

OFF OFF

OFF

OFF OFF
OFF OFF
OFF OFF OFF
OFF OFF OFF

S5

N/AN/AN/A

ON*

ON*ON

ON

OFF
OFF
OFF
OFF

OFF
OFF
OFF

OFFOFF

OFF

Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.

43 level BOM table

431A5HBOL14
431A5HBOL15 I573@/NIOAC@/VGA@/G0@/4G@
431A5HBOL16
431A5HBOL17
431A5HBOL18
431A5HBOL19
431A5HBOL20
431A5HBOL21

4 4

SMT MB AE361 C5PM2 I57300 G0 2G HDMI
SMT MB AE361 C5PM2 I57300 G0 4G HDMI
SMT MB AE361 C5PM2 I77700 G0 2G HDMI
SMT MB AE361 C5PM2 I77700 G0 4G HDMI
SMT MB AE361 C5PM2 I57300 G1 2G HDMI
SMT MB AE361 C5PM2 I57300 G1 4G HDMI
SMT MB AE361 C5PM2 I77700 G1 2G HDMI
SMT MB AE361 C5PM2 I77700 G1 4G HDMI

A

I573@/NIOAC@/VGA@/G0@/2G@

I777@/NIOAC@/VGA@/G0@/2G@
I777@/NIOAC@/VGA@/G0@/4G@
I573@/NIOAC@/VGA@/G1@/2G@
I573@/NIOAC@/VGA@/G1@/4G@
I777@/NIOAC@/VGA@/G1@/2G@
I777@/NIOAC@/VGA@/G1@/4G@

B

BOM Structure43 Level Description

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

C

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Notes List

Notes List

Notes List

Size Document Number Re v

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

E

3 61Friday, October 28, 2016

3 61Friday, October 28, 2016

3 61Friday, October 28, 2016

1.0

1.0

1.0

5

4

3

2

1

DC_IN

PJP101

D D

C C

AC CONN.

PU301

CHARGER

PL101

+19V_VI N

+12.6V_B ATT

+19VB

+19VB

+19VB

+19VB

+19VB

+19VB

PL201,PL202

+12.6V_BATT+

IMVP8

PL803,PL804,PL 805

PU801

EN:VR_O N

PL806,PL807

PU808

EN:DRON

PU401

EN:3V_E N

PU501

EN:SYSO N

PU601

EN:+3VA LW

PU7201 PJ7201

EN:SUSP

PJP201

PL809

PJ401

PJ501

PJ502

PJ601

BATTERY

+VCCCOR E

+VCCGT

+VCCSA

+3VALW

+3VLP

+1.2V_V DDQ

+0.6VS_ VTT

+1.0VAL W

+1.0VS_V CCIO

CPU

CPU

EC,LID
FP

CPU

+1.8VSDGP U_AO N

UG12

UA1

PU702

PU7102

CPU

CPU

PU7103

UQ1

R4

UM1

RL1

RH97

RH99

RH100

UK1

RS10

UK4

RH96

RH98

UC3

UC4

CPU

+3V_FP

UK3

RC41

RC42

FP

+VCCSFR_ OC_1

+VCCSFR_ OC_2

PJ7103

PJ7104

J11

+3VALW_ TPM

+3VS_WL AN

+3V_LAN

+3VALW_ DSW

+3VALW_PC H_PRI M

+3VALW_ HDA

+3V_PTP

+3VALW_ CC

+3VALW

+1.0VALW_ PRIM

+1.0VALW _PCH

RH101
RH103
LH1
RH104
LH2
LH3
RH106
RH107

JC1

RC45

+2.5V

+1.5VS

+3VS

PCH

PCH

PCH

PCH

+1.0VALW_ DCPDS W
+1.0VALW_V CCCL K
+1.0VALW_ VCCCL K5
+1.0VALW_ MPHY
+1.0VALW_A MPHYP LL
+1.0VALW_AU SB_AZ PLL
+1.0VALW_P RIMAL 22
+1.0VALW_P RIMAD 15

+1.0V_VC CST

+1.0VS_VC CSTG

JNGFF1

UL2

RH102

JTP1

US1

US1

+1.8VS

PJ7107

DIMM1

DIMM2

UY2

U2

TPM

WLAN CARD (IOAC)

LAN

+3VALW_ SPI

TP

USB_CC

POA

CODEC

DDR4

HDMI REDRIVER

CPU

CPU

PCH

UH3

SPI

+1.8VSDGPU _MAI N

UG12

UA1

JHDD1

UO1

LGAU3

RM8

RM1

R5

RX8

JUSB1

JLED1

RY1 UY2

UX1

RH105

JFAN1

JFAN2

+3VS_SSD_ NGFF

+TP_PWR

J1

+3VS_AL S

+LCDVDD

+3VS_VCC ATS

+3VS_WL AN

+3VS_TP M

+3VS_CA RD

GPU

CODEC

HDD

SATA Re-driver

G-SENSOR

JNGFF1

WLAN

JSSD1

SSD

TPM

U2

JEDP1

TP

MIC1

DMIC SUB

Card Reader SUB

UY2

HDMI REDRIVER

JEDP1

PANEL

PCH

FAN1

FAN2

B B

+19VB

+19VB

EN:VGA_CO RE_E N

+19VB

EN:VGA_CO RE_S_ EN

+19VB

EN:1.35VSDG PU_PW R_EN

+19VB

PU402

PU1501

PU1601

PJ402

PL1501,PL15 02

PL1601

PU1301 PJ1301

PU1401 PJ1401

+5VALW

+VGA_CO RE

+VGA_COR E_S

+1.35VSD GPU

+1.0VSD GPU

GPU

GPU

GPU

GPU

US2

US3

JSUB1

UQ1

+5VALW_ CC

RS9

US1

J12

US1

+USB3_V CCA

+USB3_V CCB

+USB_VC CA

+5VS

+USB3_V CCC

JUSB1

JUSB2

SUB/B USB

USB3.0

USB3.0

JUSB3

USB_CC

UF1

UF2

J18

U1

RO3

UY1

+VDDA

+5VS_BL

+5VS_HD D

+HDMI_5V _OUT

FAN1

FAN2

UA1

JBL1

JHDD1

JHDMI1

CODEC

KB BackLight

HDD

HDMI

EN:VGA_CO RE_S_ EN

A A

+INVPWR _B+

+19VB

5

LX1

4

PANEL

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

3

2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

Compal Secret Data

Compal Secret Data

Compal Secret Data

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Map

Power Map

Power Map

Size

Size

Size

Document Number Rev

Document Number Rev

Document Number Rev

E

E

E

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

Date: Sheet of

Date: Sheet of

Date: Sheet of

1

4 61Friday, October 28, 2016

4 61Friday, October 28, 2016

4 61Friday, October 28, 2016

1.0

1.0

1.0

A

BIOS ver: V0.01
EC: ver: V0.01

AC modeC5PM2_DIS_EVT Power Sequence

B

C

D

E

Plug in

1 1

2 2

3 3

+3VLP

EC_ON

+5VALW

ON/OFFBTN#

+3VALW

+1.0VALW

EC_RSMRST#

PBTN_OUT#

PM_SLP_S4#

PM_SLP_S3#

SYSON

+1.0V_VCCST

+1.2V_VDDQ

+2.5VS

SUSP#

+1.0VS_VCCSTG

+5VS

+3VS

+1.8VS

EC_VCCST_PG

SM_PG_CTRL

+0.6VS_VTT

VR_ON

+VCC_SA

+VCC_CORE

+VCC_GT

PCH_PWROK

SYS_PWROK

PLT_RST#

→

222.8us

→

5.64ms

3.031ms

→

159ms

→

158.7ms

→

→

174.6ms

26.24ms

20.3ms

← →

→

→

→

Power On

3.07ms

3.03ms

69.64us

→

691.5us

→

669us

→

1.26ms

→

13.12ms

→

13.76ms

→

14.13ms

→

734.9us

→

2.185ms

→

20.18ms

→

19.87ms

→

19.88ms

→

19.88ms

→

2.213ms

→

133.7ms

→

9.806ms

→

→

121ms

131ms

→

1.268S

→

→

→

→

→

→

→

→

S3 S3 Resume

Power Off

100.5us

99.75us

175.9us

485.8us

307.8us

→

5.105ms

→

99.51us

21.26us

20.12us 20.52us

→

1.452ms

← →

360.2ns

→

350us

→

350us

→

948ms

20.01us

6.806us

524.8us

→

26.09ms

→

→

→

→

28.27ms

27.11ms

759.9us

2.205ms

→

→

20.19ms

→

→

→

20.27ms

20.27ms

20.27ms

2.204ms

→

→

9.901ms

→

121.4ms

→

126ms

726.4ms

123.6ms

→

→

171.8us

22.24us

→

→

20.01us

7.205us

524.8us

293.7us

481.7us

→

→

8.193us

153.8us

153.8us

→

109.5us

579.5us

1.84ms

→

42.26us

384.9us

7.982s

4.92ms

8.952S

8.952S

3.920ms

+3VLP

EC_ON

+5VALW

ON/OFFBTN#

+3VALW

+1.0VALW

EC_RSMRST#

PBTN_OUT#

PM_SLP_S4#

PM_SLP_S3#

SYSON

+1.0V_VCCST

+1.2V_VDDQ

+2.5VS

SUSP#

+1.0VS_VCCSTG

+5VS

+3VS

+1.8VS

EC_VCCST_PG

SM_PG_CTRL

+0.6VS_VTT

VR_ON

+VCC_SA

+VCC_CORE

+VCC_GT

PCH_PWROK

SYS_PWROK

PLT_RST#

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY W ITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Power Sequence

Power Sequence

Power Sequence

Size

Size

Size

Document Number Re v

Document Number Re v

Document Number Re v

C

C

C

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

5 61Friday, October 28, 2016

5 61Friday, October 28, 2016

5 61Friday, October 28, 2016

1.0

1.0

1.0

A

UC1

SR32S 2.5G

I573@

SA0000AD850

ZZZ

1 1

LA-E361P

DAZ1TY00100

2 2

UC1

SR32Q 2.8G

I777@

SA0000AD750

UV1

N17P-G0-A1

G0@

SA0000A0510

UH1

HM175 SR30W-PCH

SA0000ADB30

UV1

N17P-G1-A1

G1@

SA0000A0610

<HDMI>

CPU_DP2_P0<31>
CPU_DP2_N0<31>
CPU_DP2_P1<31>
CPU_DP2_N1<31>
CPU_DP2_P2<31>
CPU_DP2_N2<31>
CPU_DP2_P3<31>
CPU_DP2_N3<31>

B

K36
K37
J35

J34
H37
H36

J37

J38
D27

E27
H34

H33

F37
G38

F34

F35

E37

E36

F26

E26
C34

D34

B36

B34

F33

E33
C33

B33

A27

B27

UC1D

DDI1_TXP[0]
DDI1_TXN[0]
DDI1_TXP[1]
DDI1_TXN[1]
DDI1_TXP[2]
DDI1_TXN[2]
DDI1_TXP[3]
DDI1_TXN[3]

DDI1_AUXP
DDI1_AUXN

DDI2_TXP[0]
DDI2_TXN[0]
DDI2_TXP[1]
DDI2_TXN[1]
DDI2_TXP[2]
DDI2_TXN[2]
DDI2_TXP[3]
DDI2_TXN[3]

DDI2_AUXP
DDI2_AUXN

DDI3_TXP[0]
DDI3_TXN[0]
DDI3_TXP[1]
DDI3_TXN[1]
DDI3_TXP[2]
DDI3_TXN[2]
DDI3_TXP[3]
DDI3_TXN[3]

DDI3_AUXP
DDI3_AUXN

SKL-H_BGA1440

@

SKYLAKE_HALO

BGA1440

4 OF 14

EDP_TXP[0]
EDP_TXN[0]
EDP_TXP[1]
EDP_TXN[1]
EDP_TXN[2]
EDP_TXP[2]
EDP_TXN[3]
EDP_TXP[3]

EDP_AUXP
EDP_AUXN

EDP_DISP_UTIL

EDP_RCOMP

PROC_AUDIO_CLK

PROC_AUDIO_SDI

PROC_AUDIO_SDO

C

D29
E29
F28
E28
B29
A29
B28
C28

C26
B26

A33

EDP_COMP

D37

G27
G25

CPU_DISPA_SDI

G29

?REV = 1

EDP_TXP0 <30>
EDP_TXN0 <30>
EDP_TXP1 <30>
EDP_TXN1 <30>
EDP_TXN2 <30>
EDP_TXP2 <30>
EDP_TXN3 <30>
EDP_TXP3 <30>

EDP_AUXP <30>

EDP_AUXN <30>

CAD note:
Trace width=20 mils,Spacing=25mil,Max length=100mils

12

RC2

20_0402_1%

Close to CPU

<eDP>

+1.0VS_VCCIO

12

RC124.9_0402_1%

CPU_DISPA_BCLK <18>
CPU_DISPA_SDO <18>

CPU_DISPA_SDI_R <18>

D

E

CPU_XDP_TMS<9,18>
CPU_XDP_TDI<9,18>

CPU_XDP_TDO<9,18>
CPU_XDP_TCK0<9,18>
PCH_JTAG_TCK1<18>

3 3

+1.0VS_VCCSTG

TMS/TDI pin CPU on-die termination

Place to PCH side

CPU_XDP_TMS
CPU_XDP_TDI

CPU_XDP_TDO
CPU_XDP_TCK0
PCH_JTAG_TCK1

RC5 51_0402_5%CMC@
RC6 51_0402_5%CMC@

1 2

RC7 100_0402_1%CMC@
RC14 51_0402_5%@

12
12

12

CPU_XDP_TMS
CPU_XDP_TDI

CPU_XDP_TDO

PCH_JTAG_TCK1

If need debug from usb port. this cmc@ need pop

+1.0VS_VCCSTG

RC8 100_0402_1%CMC@

Place to CPU side

4 4

A

1 2

RC13 51_0402_1%CMC@

12

CPU_XDP_TDO

CPU_XDP_TCK0

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

C

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

SKL-H(1/9)DDI,EDP

SKL-H(1/9)DDI,EDP

SKL-H(1/9)DDI,EDP

Custom

Custom

Custom

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

1.0

1.0

6 61Friday, October 28, 2016

6 61Friday, October 28, 2016

E

6 61Friday, October 28, 2016

1.0

A

Interleaved Memory

B

C

D

E

DDR_A_D[0..15]<14>

1 1

DDR_A_D[16..31]<14>

DDR_A_D[32..47]<14>

2 2

DDR_A_D[48..63]<14>

3 3

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63

UC1A

BR6

DDR0_DQ[0]

BT6

DDR0_DQ[1]

BP3

DDR0_DQ[2]

BR3

DDR0_DQ[3]

BN5

DDR0_DQ[4]

BP6

DDR0_DQ[5]

BP2

DDR0_DQ[6]

BN3

DDR0_DQ[7]

BL4

DDR0_DQ[8]

BL5

DDR0_DQ[9]

BL2

DDR0_DQ[10]

BM1

DDR0_DQ[11]

BK4

DDR0_DQ[12]

BK5

DDR0_DQ[13]

BK1

DDR0_DQ[14]

BK2

DDR0_DQ[15]

BG4

DDR0_DQ[16]/DDR0_DQ[32]

BG5

DDR0_DQ[17]/DDR0_DQ[33]

BF4

DDR0_DQ[18]/DDR0_DQ[34]

BF5

DDR0_DQ[19]/DDR0_DQ[35]

BG2

DDR0_DQ[20]/DDR0_DQ[36]

BG1

DDR0_DQ[21]/DDR0_DQ[37]

BF1

DDR0_DQ[22]/DDR0_DQ[38]

BF2

DDR0_DQ[23]/DDR0_DQ[39]

BD2

DDR0_DQ[24]/DDR0_DQ[40]

BD1

DDR0_DQ[25]/DDR0_DQ[41]

BC4

DDR0_DQ[26]/DDR0_DQ[42]

BC5

DDR0_DQ[27]/DDR0_DQ[43]

BD5

DDR0_DQ[28]/DDR0_DQ[44]

BD4

DDR0_DQ[29]/DDR0_DQ[45]

BC1

DDR0_DQ[30]/DDR0_DQ[46]

BC2

DDR0_DQ[31]/DDR0_DQ[47]

AB1

DDR0_DQ[32]/DDR1_DQ[0]

AB2

DDR0_DQ[33]/DDR1_DQ[1]

AA4

DDR0_DQ[34]/DDR1_DQ[2]

AA5

DDR0_DQ[35]/DDR1_DQ[3]

AB5

DDR0_DQ[36]/DDR1_DQ[4]

AB4

DDR0_DQ[37]/DDR1_DQ[5]

AA2

DDR0_DQ[38]/DDR1_DQ[6]

AA1

DDR0_DQ[39]/DDR1_DQ[7]

V5

DDR0_DQ[40]/DDR1_DQ[8]

V2

DDR0_DQ[41]/DDR1_DQ[9]

U1

DDR0_DQ[42]/DDR1_DQ[10]

U2

DDR0_DQ[43]/DDR1_DQ[11]

V1

DDR0_DQ[44]/DDR1_DQ[12]

V4

DDR0_DQ[45]/DDR1_DQ[13]

U5

DDR0_DQ[46]/DDR1_DQ[14]

U4

DDR0_DQ[47]/DDR1_DQ[15]

R2

DDR0_DQ[48]/DDR1_DQ[32]

P5

DDR0_DQ[49]/DDR1_DQ[33]

R4

DDR0_DQ[50]/DDR1_DQ[34]

P4

DDR0_DQ[51]/DDR1_DQ[35]

R5

DDR0_DQ[52]/DDR1_DQ[36]

P2

DDR0_DQ[53]/DDR1_DQ[37]

R1

DDR0_DQ[54]/DDR1_DQ[38]

P1

DDR0_DQ[55]/DDR1_DQ[39]

M4

DDR0_DQ[56]/DDR1_DQ[40]

M1

DDR0_DQ[57]/DDR1_DQ[41]

L4

DDR0_DQ[58]/DDR1_DQ[42]

L2

DDR0_DQ[59]/DDR1_DQ[43]

M5

DDR0_DQ[60]/DDR1_DQ[44]

M2

DDR0_DQ[61]/DDR1_DQ[45]

L5

DDR0_DQ[62]/DDR1_DQ[46]

L1

DDR0_DQ[63]/DDR1_DQ[47]

BA2

DDR0_ECC[0]

BA1

DDR0_ECC[1]

AY4

DDR0_ECC[2]

AY5

DDR0_ECC[3]

BA5

DDR0_ECC[4]

BA4

DDR0_ECC[5]

AY1

DDR0_ECC[6]

AY2

DDR0_ECC[7]

DDR CHANNEL A

SKL-H_BGA1440

REV = 1

@

SKYLAKE_HALO

BGA1440

DDR0_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
DDR0_BA[2]/DDR0_CAA[5]/DDR0_BG[0]

DDR0_RAS#/DDR0_CAB[3]/DDR0_MA[16]

DDR0_WE#/DDR0_CAB[2]/DDR0_MA[14]

DDR0_CAS#/DDR0_CAB[1]/DDR0_MA[15]

DDR0_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
DDR0_MA[2]/DDR0_CAB[5]/DDR0_MA[2]

DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0_MA[8]/DDR0_CAA[3]/DDR0_MA[8]

DDR0_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
DDR0_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
DDR0_MA[13]/DDR0_CAB[0]/DDR0_MA[13]

DDR0_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0_MA[15]/DDR0_CAA[8]/DDR0_ACT#

DDR0_DQSN[2]/DDR0_DQSN[4]
DDR0_DQSN[3]/DDR0_DQSN[5]

DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0_DQSP[5]/DDR1_DQSP[1]
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0_DQSP[7]/DDR1_DQSP[5]

DDR0_DQSP[2]/DDR0_DQSP[4]

DDR0_DQSP[3]/DDR0_DQSP[5]
DDR0_DQSN[4]/DDR1_DQSN[0]
DDR0_DQSN[5]/DDR1_DQSN[1]
DDR0_DQSN[6]/DDR1_DQSN[4]
DDR0_DQSN[7]/DDR1_DQSN[5]

1 OF 14

DDR0_CKP[0]
DDR0_CKN[0]
DDR0_CKN[1]

DDR0_CKP[1]
DDR0_CLKP[2]
DDR0_CLKN[2]
DDR0_CLKP[3]
DDR0_CLKN[3]

DDR0_CKE[0]

DDR0_CKE[1]

DDR0_CKE[2]

DDR0_CKE[3]

DDR0_CS#[0]

DDR0_CS#[1]

DDR0_CS#[2]

DDR0_CS#[3]

DDR0_ODT[0]

DDR0_ODT[1]

DDR0_ODT[2]

DDR0_ODT[3]

DDR0_MA[3]
DDR0_MA[4]

DDR0_PAR

DDR0_ALERT#

DDR0_DQSN[0]
DDR0_DQSN[1]

DDR0_DQSP[0]
DDR0_DQSP[1]

DDR0_DQSP[8]
DDR0_DQSN[8]

?

AG1
AG2
AK1
AK2
AL3
AK3
AL2
AL1

AT1
AT2
AT3
AT5

AD5
AE2
AD2
AE5

AD3
AE4
AE1
AD4

AH5
AH1
AU1

AH4
AG4
AD1

AH3
AP4
AN4
AP5
AP2
AP1
AP3
AN1
AN3
AT4
AH2
AN2
AU4
AE3
AU2
AU3

AG3
AU5

BR5
BL3
BG3
BD3
AB3
V3
R3
M3

BP5
BK3
BF3
BC3
AA3
U3
P3
L3

AY3
BA3

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK#1
DDR_A_CLK1

DDR_A_CKE0
DDR_A_CKE1

DDR_A_CS#0
DDR_A_CS#1

DDR_A_ODT0
DDR_A_ODT1

DDR_A_BA0
DDR_A_BA1
DDR_A_BG0

DDR_A_MA16
DDR_A_MA14
DDR_A_MA15

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_BG1
DDR_A_ACT#

DDR_A_PARITY
DDR_A_ALERT#

DDR_A_DQS#0
DDR_A_DQS#1
DDR_A_DQS#2
DDR_A_DQS#3
DDR_A_DQS4
DDR_A_DQS5
DDR_A_DQS6
DDR_A_DQS7

DDR_A_DQS0
DDR_A_DQS1
DDR_A_DQS2
DDR_A_DQS3
DDR_A_DQS#4
DDR_A_DQS#5
DDR_A_DQS#6
DDR_A_DQS#7

DDR_A_CLK0 <14>
DDR_A_CLK#0 <14>
DDR_A_CLK#1 <14>
DDR_A_CLK1 <14>

DDR_A_CKE0 <14>
DDR_A_CKE1 <14>

DDR_A_CS#0 <14>
DDR_A_CS#1 <14>

DDR_A_ODT0 <14>
DDR_A_ODT1 <14>

DDR_A_BA0 <14>
DDR_A_BA1 <14>
DDR_A_BG0 <14>

DDR_A_MA16 <14>
DDR_A_MA14 <14>
DDR_A_MA15 <14>

DDR_A_MA0 <14>
DDR_A_MA1 <14>
DDR_A_MA2 <14>
DDR_A_MA3 <14>
DDR_A_MA4 <14>
DDR_A_MA5 <14>
DDR_A_MA6 <14>
DDR_A_MA7 <14>
DDR_A_MA8 <14>
DDR_A_MA9 <14>
DDR_A_MA10 <14>
DDR_A_MA11 <14>
DDR_A_MA12 <14>
DDR_A_MA13 <14>
DDR_A_BG1 <14>
DDR_A_ACT# <14>

DDR_A_PARITY <14>
DDR_A_ALERT# <14>

DDR_A_DQS#0 <14>
DDR_A_DQS#1 <14>
DDR_A_DQS#2 <14>
DDR_A_DQS#3 <14>
DDR_A_DQS4 <14>
DDR_A_DQS5 <14>
DDR_A_DQS6 <14>
DDR_A_DQS7 <14>

DDR_A_DQS0 <14>
DDR_A_DQS1 <14>
DDR_A_DQS2 <14>
DDR_A_DQS3 <14>
DDR_A_DQS#4 <14>
DDR_A_DQS#5 <14>
DDR_A_DQS#6 <14>
DDR_A_DQS#7 <14>

DDR_B_D[0..15]<15>

DDR_B_D[16..31]<15>

DDR_B_D[32..47]<15>

DDR_B_D[48..63]<15>

close to CPU

DDR CHANNEL B

SKYLAKE_HALO

BGA1440

DDR1_RAS#/DDR1_CAB[3]/DDR1_MA[16]

DDR1_WE#/DDR1_CAB[2]/DDR1_MA[14]

DDR1_CAS#/DDR1_CAB[1]/DDR1_MA[15]

DDR1_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1_BA[1]/DDR1_CAB[6]/DDR1_BA[1]

DDR1_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1_MA[0]/DDR1_CAB[9]/DDR1_MA[0]

DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
DDR1_MA[2]/DDR1_CAB[5]/DDR1_MA[2]

DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1_MA[8]/DDR1_CAA[3]/DDR1_MA[8]

DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
DDR1_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
DDR1_MA[13]/DDR1_CAB[0]/DDR1_MA[13]

DDR1_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
DDR1_MA[15]/DDR1_CAA[8]/DDR1_ACT#

DDR1_DQSN[0]/DDR0_DQSN[2]
DDR1_DQSN[1]/DDR0_DQSN[3]
DDR1_DQSN[2]/DDR0_DQSN[6]
DDR1_DQSN[3]/DDR0_DQSN[7]
DDR1_DQSN[4]/DDR1_DQSN[2]
DDR1_DQSN[5]/DDR1_DQSN[3]

DDR1_DQSP[0]/DDR0_DQSP[2]
DDR1_DQSP[1]/DDR0_DQSP[3]
DDR1_DQSP[2]/DDR0_DQSP[6]
DDR1_DQSP[3]/DDR0_DQSP[7]
DDR1_DQSP[4]/DDR1_DQSP[2]
DDR1_DQSP[5]/DDR1_DQSP[3]

2 OF 14

DDR1_CKP[0]
DDR1_CKN[0]
DDR1_CKN[1]
DDR1_CKP[1]

DDR1_CLKP[2]

DDR1_CLKN[2]

DDR1_CLKP[3]

DDR1_CLKN[3]

DDR1_CKE[0]
DDR1_CKE[1]
DDR1_CKE[2]
DDR1_CKE[3]

DDR1_CS#[0]
DDR1_CS#[1]
DDR1_CS#[2]
DDR1_CS#[3]

DDR1_ODT[0]
DDR1_ODT[1]
DDR1_ODT[2]
DDR1_ODT[3]

DDR1_MA[3]
DDR1_MA[4]

DDR1_PAR

DDR1_ALERT#

DDR1_DQSN[6]
DDR1_DQSN[7]

DDR1_DQSP[6]
DDR1_DQSP[7]

DDR1_DQSP[8]
DDR1_DQSN[8]

DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ

AM9
AN9
AM8
AM7
AM11
AM10
AJ10
AJ11

AT8
AT10
AT7
AT11

AF11
AE7
AF10
AE10

AF7
AE8
AE9
AE11

AH10
AH11
AF8

AH8
AH9
AR9

AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10
AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9

AJ7
AR8

BP9
BL9
BG9
BC9
AC9
W9
R9
M9

BR9
BJ9
BF9
BB9
AA9
V9
P9
L9

AW9
AY9

BN13
BP13
BR13

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK#1
DDR_B_CLK1

DDR_B_CKE0
DDR_B_CKE1

DDR_B_CS#0
DDR_B_CS#1

DDR_B_ODT0
DDR_B_ODT1

DDR_B_MA16
DDR_B_MA14
DDR_B_MA15

DDR_B_BA0
DDR_B_BA1
DDR_B_BG0

DDR_B_MA0
DDR_B_MA1
DDR_B_MA2
DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_BG1
DDR_B_ACT#

DDR_B_PARITY
DDR_B_ALERT#

DDR_B_DQS#0
DDR_B_DQS#1
DDR_B_DQS#2
DDR_B_DQS#3
DDR_B_DQS#4
DDR_B_DQS#5
DDR_B_DQS#6
DDR_B_DQS#7

DDR_B_DQS0
DDR_B_DQS1
DDR_B_DQS2
DDR_B_DQS3
DDR_B_DQS4
DDR_B_DQS5
DDR_B_DQS6
DDR_B_DQS7

+0.6V_VREFCA
+0.6V_B_VREFDQ

DDR_B_CLK0 <15>
DDR_B_CLK#0 <15>
DDR_B_CLK#1 <15>
DDR_B_CLK1 <15>

DDR_B_CKE0 <15>
DDR_B_CKE1 <15>

DDR_B_CS#0 <15>
DDR_B_CS#1 <15>

DDR_B_ODT0 <15>
DDR_B_ODT1 <15>

DDR_B_MA16 <15>
DDR_B_MA14 <15>
DDR_B_MA15 <15>

DDR_B_BA0 <15>
DDR_B_BA1 <15>
DDR_B_BG0 <15>

DDR_B_MA0 <15>
DDR_B_MA1 <15>
DDR_B_MA2 <15>
DDR_B_MA3 <15>
DDR_B_MA4 <15>
DDR_B_MA5 <15>
DDR_B_MA6 <15>
DDR_B_MA7 <15>
DDR_B_MA8 <15>
DDR_B_MA9 <15>
DDR_B_MA10 <15>
DDR_B_MA11 <15>
DDR_B_MA12 <15>
DDR_B_MA13 <15>
DDR_B_BG1 <15>
DDR_B_ACT# <15>

DDR_B_PARITY <15>
DDR_B_ALERT# <15>

DDR_B_DQS#0 <15>
DDR_B_DQS#1 <15>
DDR_B_DQS#2 <15>
DDR_B_DQS#3 <15>
DDR_B_DQS#4 <15>
DDR_B_DQS#5 <15>
DDR_B_DQS#6 <15>
DDR_B_DQS#7 <15>

DDR_B_DQS0 <15>
DDR_B_DQS1 <15>
DDR_B_DQS2 <15>
DDR_B_DQS3 <15>
DDR_B_DQS4 <15>
DDR_B_DQS5 <15>
DDR_B_DQS6 <15>
DDR_B_DQS7 <15>

+0.6V_VREFCA
+0.6V_B_VREFDQ

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_D8
DDR_B_D9
DDR_B_D10
DDR_B_D11
DDR_B_D12
DDR_B_D13
DDR_B_D14
DDR_B_D15
DDR_B_D16
DDR_B_D17
DDR_B_D18
DDR_B_D19
DDR_B_D20
DDR_B_D21
DDR_B_D22
DDR_B_D23
DDR_B_D24
DDR_B_D25
DDR_B_D26
DDR_B_D27
DDR_B_D28
DDR_B_D29
DDR_B_D30
DDR_B_D31
DDR_B_D32
DDR_B_D33
DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D37
DDR_B_D38
DDR_B_D39
DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_D48
DDR_B_D49
DDR_B_D50
DDR_B_D51
DDR_B_D52
DDR_B_D53
DDR_B_D54
DDR_B_D55
DDR_B_D56
DDR_B_D57
DDR_B_D58
DDR_B_D59
DDR_B_D60
DDR_B_D61
DDR_B_D62
DDR_B_D63

SM_RCOMP0

RC17121_0402_1%

12

SM_RCOMP1

12

RC1875_0402_1%

SM_RCOMP2

RC19100_0402_1%

12

UC1B

BT11

DDR1_DQ[0]/DDR0_DQ[16]

BR11

DDR1_DQ[1]/DDR0_DQ[17]

BT8

DDR1_DQ[2]/DDR0_DQ[18]

BR8

DDR1_DQ[3]/DDR0_DQ[19]

BP11

DDR1_DQ[4]/DDR0_DQ[20]

BN11

DDR1_DQ[5]/DDR0_DQ[21]

BP8

DDR1_DQ[6]/DDR0_DQ[22]

BN8

DDR1_DQ[7]/DDR0_DQ[23]

BL12

DDR1_DQ[8]/DDR0_DQ[24]

BL11

DDR1_DQ[9]/DDR0_DQ[25]

BL8

DDR1_DQ[10]/DDR0_DQ[26]

BJ8

DDR1_DQ[11]/DDR0_DQ[27]

BJ11

DDR1_DQ[12]/DDR0_DQ[28]

BJ10

DDR1_DQ[13]/DDR0_DQ[29]

BL7

DDR1_DQ[14]/DDR0_DQ[30]

BJ7

DDR1_DQ[15]/DDR0_DQ[31]

BG11

DDR1_DQ[16]/DDR0_DQ[48]

BG10

DDR1_DQ[17]/DDR0_DQ[49]

BG8

DDR1_DQ[18]/DDR0_DQ[50]

BF8

DDR1_DQ[19]/DDR0_DQ[51]

BF11

DDR1_DQ[20]/DDR0_DQ[52]

BF10

DDR1_DQ[21]/DDR0_DQ[53]

BG7

DDR1_DQ[22]/DDR0_DQ[54]

BF7

DDR1_DQ[23]/DDR0_DQ[55]

BB11

DDR1_DQ[24]/DDR0_DQ[56]

BC11

DDR1_DQ[25]/DDR0_DQ[57]

BB8

DDR1_DQ[26]/DDR0_DQ[58]

BC8

DDR1_DQ[27]/DDR0_DQ[59]

BC10

DDR1_DQ[28]/DDR0_DQ[60]

BB10

DDR1_DQ[29]/DDR0_DQ[61]

BC7

DDR1_DQ[30]/DDR0_DQ[62]

BB7

DDR1_DQ[31]/DDR0_DQ[63]

AA11

DDR1_DQ[32]/DDR1_DQ[16]

AA10

DDR1_DQ[33]/DDR1_DQ[17]

AC11

DDR1_DQ[34]/DDR1_DQ[18]

AC10

DDR1_DQ[35]/DDR1_DQ[19]

AA7

DDR1_DQ[36]/DDR1_DQ[20]

AA8

DDR1_DQ[37]/DDR1_DQ[21]

AC8

DDR1_DQ[38]/DDR1_DQ[22]

AC7

DDR1_DQ[39]/DDR1_DQ[23]

W8

DDR1_DQ[40]/DDR1_DQ[24]

W7

DDR1_DQ[41]/DDR1_DQ[25]

V10

DDR1_DQ[42]/DDR1_DQ[26]

V11

DDR1_DQ[43]/DDR1_DQ[27]

W11

DDR1_DQ[44]/DDR1_DQ[28]

W10

DDR1_DQ[45]/DDR1_DQ[29]

V7

DDR1_DQ[46]/DDR1_DQ[30]

V8

DDR1_DQ[47]/DDR1_DQ[31]

R11

DDR1_DQ[48]

P11

DDR1_DQ[49]

P7

DDR1_DQ[50]

R8

DDR1_DQ[51]

R10

DDR1_DQ[52]

P10

DDR1_DQ[53]

R7

DDR1_DQ[54]

P8

DDR1_DQ[55]

L11

DDR1_DQ[56]

M11

DDR1_DQ[57]

L7

DDR1_DQ[58]

M8

DDR1_DQ[59]

L10

DDR1_DQ[60]

M10

DDR1_DQ[61]

M7

DDR1_DQ[62]

L8

DDR1_DQ[63]

AW11

DDR1_ECC[0]

AY11

DDR1_ECC[1]

AY8

DDR1_ECC[2]

AW8

DDR1_ECC[3]

AY10

DDR1_ECC[4]

AW10

DDR1_ECC[5]

AY7

DDR1_ECC[6]

AW7

DDR1_ECC[7]

G1

DDR_RCOMP[0]

H1

DDR_RCOMP[1]

J2

DDR_RCOMP[2]

SKL-H_BGA1440

@

REV = 1 ?

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

C

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

SKL-H(2/9)DDRIII

SKL-H(2/9)DDRIII

SKL-H(2/9)DDRIII

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

Friday, October 28, 2016

Friday, October 28, 2016

Friday, October 28, 2016

E

1.0

1.0

1.0

61

61

61

7

7

7

A

B

C

D

E

1 1

1 2

PEG_GTX_HRX_P15<23>
PEG_GTX_HRX_N15<23>

PEG_GTX_HRX_P14<23>
PEG_GTX_HRX_N14<23>

PEG_GTX_HRX_P13<23>
PEG_GTX_HRX_N13<23>

PEG_GTX_HRX_P12<23>
PEG_GTX_HRX_N12<23>

PEG_GTX_HRX_P11<23>
PEG_GTX_HRX_N11<23>

PEG_GTX_HRX_P10<23>
PEG_GTX_HRX_N10<23>

PEG_GTX_HRX_P9<23>
PEG_GTX_HRX_N9<23>

PEG_GTX_HRX_P8<23>

2 2

3 3

PEG_GTX_HRX_N8<23>
PEG_GTX_HRX_P7<23>

PEG_GTX_HRX_N7<23>
PEG_GTX_HRX_P6<23>

PEG_GTX_HRX_N6<23>
PEG_GTX_HRX_P5<23>

PEG_GTX_HRX_N5<23>
PEG_GTX_HRX_P4<23>

PEG_GTX_HRX_N4<23>
PEG_GTX_HRX_P3<23>

PEG_GTX_HRX_N3<23>
PEG_GTX_HRX_P2<23>

PEG_GTX_HRX_N2<23>
PEG_GTX_HRX_P1<23>

PEG_GTX_HRX_N1<23>
PEG_GTX_HRX_P0<23>

PEG_GTX_HRX_N0<23>

CC6 0.22U_0201_6.3V6KVGA@

1 2

CC8 0.22U_0201_6.3V6KVGA@

1 2

CC10 0.22U_0201_6.3V6KVGA@

1 2

CC12 0.22U_0201_6.3V6KVGA@

1 2

CC14 0.22U_0201_6.3V6KVGA@

1 2

CC15 0.22U_0201_6.3V6KVGA@

1 2

CC3 0.22U_0201_6.3V6KVGA@

1 2

CC17 0.22U_0201_6.3V6KVGA@

1 2

CC19 0.22U_0201_6.3V6KVGA@

1 2

CC21 0.22U_0201_6.3V6KVGA@

1 2

CC5 0.22U_0201_6.3V6KVGA@

1 2

CC23 0.22U_0201_6.3V6KVGA@

1 2

CC25 0.22U_0201_6.3V6KVGA@

1 2

CC27 0.22U_0201_6.3V6KVGA@

1 2

CC29 0.22U_0201_6.3V6KVGA@

1 2

CC31 0.22U_0201_6.3V6KVGA@

1 2

CC33 0.22U_0201_6.3V6KVGA@

1 2

CC35 0.22U_0201_6.3V6KVGA@

1 2

CC37 0.22U_0201_6.3V6KVGA@

1 2

CC39 0.22U_0201_6.3V6KVGA@

1 2

CC41 0.22U_0201_6.3V6KVGA@

1 2

CC43 0.22U_0201_6.3V6KVGA@

1 2

CC45 0.22U_0201_6.3V6KVGA@

1 2

CC47 0.22U_0201_6.3V6KVGA@

1 2

CC49 0.22U_0201_6.3V6KVGA@

1 2

CC51 0.22U_0201_6.3V6KVGA@

1 2

CC53 0.22U_0201_6.3V6KVGA@

1 2

CC55 0.22U_0201_6.3V6KVGA@

1 2

CC57 0.22U_0201_6.3V6KVGA@

1 2

CC59 0.22U_0201_6.3V6KVGA@

1 2

CC61 0.22U_0201_6.3V6KVGA@

1 2

CC63 0.22U_0201_6.3V6KVGA@

+1.0VS_VCCIO

CAD note:
Trace width=12 mils,Spacing=15mil,Max length=400mils

DMI_CRX_PTX_P0<16>
DMI_CRX_PTX_N0<16>

DMI_CRX_PTX_P1<16>
DMI_CRX_PTX_N1<16>

DMI_CRX_PTX_P2<16>
DMI_CRX_PTX_N2<16>

DMI_CRX_PTX_P3<16>
DMI_CRX_PTX_N3<16>

1 2

RC20 24.9_0402_1%

PEG_GTX_C_HRX_P15
PEG_GTX_C_HRX_N15

PEG_GTX_C_HRX_P14
PEG_GTX_C_HRX_N14

PEG_GTX_C_HRX_P13
PEG_GTX_C_HRX_N13

PEG_GTX_C_HRX_P12
PEG_GTX_C_HRX_N12

PEG_GTX_C_HRX_P11
PEG_GTX_C_HRX_N11

PEG_GTX_C_HRX_P10
PEG_GTX_C_HRX_N10

PEG_GTX_C_HRX_P9
PEG_GTX_C_HRX_N9

PEG_GTX_C_HRX_P8
PEG_GTX_C_HRX_N8

PEG_GTX_C_HRX_P7
PEG_GTX_C_HRX_N7

PEG_GTX_C_HRX_P6
PEG_GTX_C_HRX_N6

PEG_GTX_C_HRX_P5
PEG_GTX_C_HRX_N5

PEG_GTX_C_HRX_P4
PEG_GTX_C_HRX_N4

PEG_GTX_C_HRX_P3
PEG_GTX_C_HRX_N3

PEG_GTX_C_HRX_P2
PEG_GTX_C_HRX_N2

PEG_GTX_C_HRX_P1
PEG_GTX_C_HRX_N1

PEG_GTX_C_HRX_P0
PEG_GTX_C_HRX_N0

PEG_RCOMP

DMI_CRX_PTX_P0
DMI_CRX_PTX_N0

DMI_CRX_PTX_P1
DMI_CRX_PTX_N1

DMI_CRX_PTX_P2
DMI_CRX_PTX_N2

DMI_CRX_PTX_P3
DMI_CRX_PTX_N3

E25
D25

E24
F24

E23
D23

E22
F22

E21
D21

E20
F20

E19
D19

E18
F18

D17
E17

F16
E16

D15
E15

F14
E14

D13
E13

F12
E12

D11
E11

F10
E10

G2

D8
E8

E6
F6

D5
E5

J8
J9

SKL-H_BGA1440

@

UC1C

PEG_RXP[0]
PEG_RXN[0]

PEG_RXP[1]
PEG_RXN[1]

PEG_RXP[2]
PEG_RXN[2]

PEG_RXP[3]
PEG_RXN[3]

PEG_RXP[4]
PEG_RXN[4]

PEG_RXP[5]
PEG_RXN[5]

PEG_RXP[6]
PEG_RXN[6]

PEG_RXP[7]
PEG_RXN[7]

PEG_RXP[8]
PEG_RXN[8]

PEG_RXP[9]
PEG_RXN[9]

PEG_RXP[10]
PEG_RXN[10]

PEG_RXP[11]
PEG_RXN[11]

PEG_RXP[12]
PEG_RXN[12]

PEG_RXP[13]
PEG_RXN[13]

PEG_RXP[14]
PEG_RXN[14]

PEG_RXP[15]
PEG_RXN[15]

PEG_RCOMP

DMI_RXP[0]
DMI_RXN[0]

DMI_RXP[1]
DMI_RXN[1]

DMI_RXP[2]
DMI_RXN[2]

DMI_RXP[3]
DMI_RXN[3]

REV = 1

SKYLAKE_HALO

BGA1440

3 OF 14

PEG_TXP[0]

PEG_TXN[0]
PEG_TXP[1]

PEG_TXN[1]
PEG_TXP[2]

PEG_TXN[2]
PEG_TXP[3]

PEG_TXN[3]
PEG_TXP[4]

PEG_TXN[4]
PEG_TXP[5]

PEG_TXN[5]
PEG_TXP[6]

PEG_TXN[6]
PEG_TXP[7]

PEG_TXN[7]
PEG_TXP[8]

PEG_TXN[8]
PEG_TXP[9]

PEG_TXN[9]

PEG_TXP[10]
PEG_TXN[10]

PEG_TXP[11]
PEG_TXN[11]

PEG_TXP[12]
PEG_TXN[12]

PEG_TXP[13]
PEG_TXN[13]

PEG_TXP[14]
PEG_TXN[14]

PEG_TXP[15]
PEG_TXN[15]

DMI_TXP[0]

DMI_TXN[0]

DMI_TXP[1]

DMI_TXN[1]

DMI_TXP[2]

DMI_TXN[2]

DMI_TXP[3]

DMI_TXN[3]

B25
A25

B24
C24

B23
A23

B22
C22

B21
A21

B20
C20

B19
A19

B18
C18

A17
B17

C16
B16

A15
B15

C14
B14

A13
B13

C12
B12

A11
B11

C10
B10

B8
A8

C6
B6

B5
A5

D4
B4

?

PEG_HTX_GRX_P15
PEG_HTX_GRX_N15

PEG_HTX_GRX_P14
PEG_HTX_GRX_N14

PEG_HTX_GRX_P13
PEG_HTX_GRX_N13

PEG_HTX_GRX_P12
PEG_HTX_GRX_N12

PEG_HTX_GRX_P11
PEG_HTX_GRX_N11

PEG_HTX_GRX_P10
PEG_HTX_GRX_N10

PEG_HTX_GRX_P9
PEG_HTX_GRX_N9

PEG_HTX_GRX_P8
PEG_HTX_GRX_N8

PEG_HTX_GRX_P7
PEG_HTX_GRX_N7

PEG_HTX_GRX_P6
PEG_HTX_GRX_N6

PEG_HTX_GRX_P5
PEG_HTX_GRX_N5

PEG_HTX_GRX_P4
PEG_HTX_GRX_N4

PEG_HTX_GRX_P3
PEG_HTX_GRX_N3

PEG_HTX_GRX_P2
PEG_HTX_GRX_N2

PEG_HTX_GRX_P1
PEG_HTX_GRX_N1

PEG_HTX_GRX_P0
PEG_HTX_GRX_N0

DMI_CTX_PRX_P0
DMI_CTX_PRX_N0

DMI_CTX_PRX_P1
DMI_CTX_PRX_N1

DMI_CTX_PRX_P2
DMI_CTX_PRX_N2

DMI_CTX_PRX_P3
DMI_CTX_PRX_N3

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

12
12

DMI_CTX_PRX_P0 <16>
DMI_CTX_PRX_N0 <16>

DMI_CTX_PRX_P1 <16>
DMI_CTX_PRX_N1 <16>

DMI_CTX_PRX_P2 <16>
DMI_CTX_PRX_N2 <16>

DMI_CTX_PRX_P3 <16>
DMI_CTX_PRX_N3 <16>

CC70.22U_0201_6.3V6K VGA@
CC90.22U_0201_6.3V6K VGA@

CC110.22U_0201_6.3V6K VGA@
CC130.22U_0201_6.3V6K VGA@

CC10.22U_0201_6.3V6K VGA@
CC20.22U_0201_6.3V6K VGA@

CC160.22U_0201_6.3V6K VGA@
CC180.22U_0201_6.3V6K VGA@

CC200.22U_0201_6.3V6K VGA@
CC40.22U_0201_6.3V6K VGA@

CC220.22U_0201_6.3V6K VGA@
CC240.22U_0201_6.3V6K VGA@

CC260.22U_0201_6.3V6K VGA@
CC280.22U_0201_6.3V6K VGA@

CC300.22U_0201_6.3V6K VGA@
CC320.22U_0201_6.3V6K VGA@

CC340.22U_0201_6.3V6K VGA@
CC360.22U_0201_6.3V6K VGA@

CC380.22U_0201_6.3V6K VGA@
CC400.22U_0201_6.3V6K VGA@

CC420.22U_0201_6.3V6K VGA@
CC440.22U_0201_6.3V6K VGA@

CC460.22U_0201_6.3V6K VGA@
CC480.22U_0201_6.3V6K VGA@

CC500.22U_0201_6.3V6K VGA@
CC520.22U_0201_6.3V6K VGA@

CC540.22U_0201_6.3V6K VGA@
CC560.22U_0201_6.3V6K VGA@

CC580.22U_0201_6.3V6K VGA@
CC600.22U_0201_6.3V6K VGA@

CC620.22U_0201_6.3V6K VGA@
CC640.22U_0201_6.3V6K VGA@

PEG_HTX_C_GRX_P15 <23>
PEG_HTX_C_GRX_N15 <23>

PEG_HTX_C_GRX_P14 <23>
PEG_HTX_C_GRX_N14 <23>

PEG_HTX_C_GRX_P13 <23>
PEG_HTX_C_GRX_N13 <23>

PEG_HTX_C_GRX_P12 <23>
PEG_HTX_C_GRX_N12 <23>

PEG_HTX_C_GRX_P11 <23>
PEG_HTX_C_GRX_N11 <23>

PEG_HTX_C_GRX_P10 <23>
PEG_HTX_C_GRX_N10 <23>

PEG_HTX_C_GRX_P9 <23>
PEG_HTX_C_GRX_N9 <23>

PEG_HTX_C_GRX_P8 <23>
PEG_HTX_C_GRX_N8 <23>

PEG_HTX_C_GRX_P7 <23>
PEG_HTX_C_GRX_N7 <23>

PEG_HTX_C_GRX_P6 <23>
PEG_HTX_C_GRX_N6 <23>

PEG_HTX_C_GRX_P5 <23>
PEG_HTX_C_GRX_N5 <23>

PEG_HTX_C_GRX_P4 <23>
PEG_HTX_C_GRX_N4 <23>

PEG_HTX_C_GRX_P3 <23>
PEG_HTX_C_GRX_N3 <23>

PEG_HTX_C_GRX_P2 <23>
PEG_HTX_C_GRX_N2 <23>

PEG_HTX_C_GRX_P1 <23>
PEG_HTX_C_GRX_N1 <23>

PEG_HTX_C_GRX_P0 <23>
PEG_HTX_C_GRX_N0 <23>

4 4

Security Classification

Security Classification

Security Classification

2016/01/29 2017/01/10

2016/01/29 2017/01/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/01/29 2017/01/10

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

SKL-H(3/9) PEG,DMI

SKL-H(3/9) PEG,DMI

SKL-H(3/9) PEG,DMI

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v
Custom

Custom

Custom

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

8 61Friday, October 28, 2016

8 61Friday, October 28, 2016

8 61Friday, October 28, 2016

E

1.0

1.0

1.0

A

B

C

D

E

SKYLAKE_HALO

BGA1440

5 OF 14

REV = 1 ?

+1.0V_VCCST

RC28 1K_0402_5%

PROC_TDO

PROC_TDI
PROC_TMS
PROC_TCK

PROC_TRST#
PROC_PREQ#
PROC_PRDY#

CFG_RCOMP

1 2

CFG[0]
CFG[1]
CFG[2]
CFG[3]
CFG[4]
CFG[5]
CFG[6]
CFG[7]
CFG[8]

CFG[9]
CFG[10]
CFG[11]
CFG[12]
CFG[13]
CFG[14]
CFG[15]

CFG[17]
CFG[16]
CFG[19]
CFG[18]

BPM#[0]
BPM#[1]
BPM#[2]
BPM#[3]

+1.0VS_VCCSTG

From EC(open-drain)

H_PROCHOT#<39,46>

BN25

CFG0

BN27
BN26

CFG2

BN28
BR20

CFG4

BM20

CFG5

BT20
BP20

CFG7

BR23
BR22
BT23
BT22
BM19
BR19
BP19
BT19

BN23
BP23
BP22
BN22

BR27
BT27
BM31
BT30

CPU_XDP_TDO

BT28

CPU_XDP_TDI

BL32

CPU_XDP_TMS

BP28

CPU_XDP_TCK0

BR28
BP30

BL30
BP27

CFG_RCOMP

BT25

THERMTRIP#

12

RC31
1K_0402_5%

1 2

RC33 499_0402_1%

RC24 49.9_0402_1%

@

T36PAD

@

T37PAD

1 2

H_PROCHOT#_R

CPU_XDP_TDO <6,18>
CPU_XDP_TDI <6,18>
CPU_XDP_TMS <6,18>
CPU_XDP_TCK0 <6,18>

CFG4

CFG5

CFG2

1 2

RC23 1K_0402_1%

1 2

RC25 1K_0402_1%@

1 2

RC26 1K_0402_1%

ESD Reserve ,pleace close to cpu

H_CPUPW RGD

H_PROCHOT#_R

THERMTRIP#

1 2

1 2

1 2

XEMC@

XEMC@

XEMC@

CH1 .1U_0402_16V7K

CH2 .1U_0402_16V7K

CH3 .1U_0402_16V7K

CPU_SVID_ALERT#
CPU_SVID_CLK
CPU_SVID_DAT

H_PROCHOT#_R

DDR_PG_CTRL

EC_VCCST_PG

H_CPUPW RGD
PLTRST_CPU#
H_PM_SYNC
PM_DOW N
H_PECI

THERMTRIP#

SKL_CNL_N

@

T3 PAD

EC_VCCST_PG

CPU_BCLK
CPU_BCLK#

CPU_PCIBCLK
CPU_PCIBCLK#

CPU_24M
CPU_24M#

H_CATERR#

PM_DOW N

CPU_BCLK<19>
CPU_BCLK#<19>

CPU_PCIBCLK<19>
CPU_PCIBCLK#<19>

CPU_24M<19>

1 1

H_PECI

2

CH65
.1U_0402_16V7K

1

XEMC@

H_SKTOCC#<18>

2 2

From EC OD output

EC_VCCST_PG_R<39,43>

3 3

PM_DOW N_R<17>

H_SKTOCC# H_SKTOCC#_R

1 2

@

RC32 1K_0402_5%

CPU_24M#<19>

CPU_SVID_CLK<52>

H_CPUPW RGD<18>
PLTRST_CPU#<17>
H_PM_SYNC<17>

H_PECI<17,39>

THERMTRIP#<17>

1 2

RC21 0_0402_5%@

1 2

RC22 0_0402_5%@

FLOAT FOR SKL
GND FOR CNL

+1.0V_VCCST

12

RC27
1K_0402_5%

RC29 60.4_0402_1%

RC30 20_0402_1%

1 2

12

BH31
BH32
BH29
BR30

BT13

BT31
BP35
BM34
BP31

BT34

BR33

BN1

BM30

B31
A32

D35
C36

E31
D31

H13

J31

UC1E

BCLKP
BCLKN

PCI_BCLKP
PCI_BCLKN

CLK24P
CLK24N

VIDALERT#
VIDSCK
VIDSOUT
PROCHOT#

DDR_VTT_CNTL

VCCST_PWRGD
PROCPWRGD

RESET#
PM_SYNC
PM_DOWN
PECI
THERMTRIP#

SKTOCC#
PROC_SELECT#

CATERR#

SKL-H_BGA1440

@

Reference SKL EDS 0.85 Table 6-8
CFG signals internal PH default value = 1

Description

Stall reset sequence after PCU PLL

CFG[0]

CFG[4]

CFG[7]

CFG[1]
CFG[3]

CFG[8:19]

lock until de-asserted
— 1 = (Default) Normal Operation;

*

No stall.
— 0 = Stall.

Enable eDP
— 1 = Disabled.
— 0 = Enabled.

*

PEG Training:
— 1 = (default) PEG Train immediately

*

following RESET# de assertion.
— 0 = PEG Wait for BIOS for training

Reserved configuration lane.

PCIE
pore
assign

1 x 16
1 x 16

reverse
2 x 8

2 x 8
reverse
1 x 8
+ 2 x 4
1x8+2x4
reverse

Config. Signals

1 1 1

*

1 1
1 1
1

0 0 0

CFG[2]CFG[5]CFG[6]

0
0 0
00

0

1

DDR_VTT_CNTL to DDR
VTT supplied ramped

SVID ALERT

+1.0V_VCCST

CPU_SVID_ALERT#

4 4

SVID DATA

+1.0V_VCCST

CPU_SVID_DAT

A

1 2

RC34 56_0402_5%

1 2

RC36 220_0402_5%

1 2

RC38 100_0402_1%

Place the PU
resistors close to CPU

CPU_SVID_ALERT#_R <52>

Place the PU
resistors close to CPU

CPU_SVID_DAT <52>

B

Follow PDG1.0
Table 12-16

(To VR)

(To VR)

<35uS
(tCPU18)

DDR_PG_CTRL

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

NC1VCC

2

A

3

GND

74AUP1G07GW_TSSOP5

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

+1.2V_VDDQ

+3VS

12

CC65.1U_0402_16V7K

UC2

5

4

Y

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

12

RC35
220K_0402_5%

RC37
2M_0402_5%@

1 2

CRB 330K

SM_PG_CTRL <48>

D

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

SKL-H(4/9)CLK,GPIO

SKL-H(4/9)CLK,GPIO

SKL-H(4/9)CLK,GPIO

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

Date: Sheet of

Date: Sheet of

Date: Sheet of

9 61Friday, October 28, 2016

9 61Friday, October 28, 2016

9 61Friday, October 28, 2016

E

1.0

1.0

1.0

A

B

C

D

E

1 1

+VCC_CORE +VCC_CORE

H-4+2/68A

2 2

3 3

4 4

AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38

AF35
AF36
AF37
AF38

K13
K14
L13
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13

SKYLAKE_HALO

UC1G

BGA1440

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

7 OF 14

SKL-H_BGA1440

REV = 1 ?

@

A

VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC

VCC_SENSE

VSS_SENSE

V32
V33
V34
V35
V36
V37
V38
W13
W14
W29
W30
W31
W32
W35
W36
W37
W38
Y29
Y30
Y31
Y32
Y33
Y34
Y35
Y36
L14
P29
P30
P31
P32
P33
P34
P35
P36
R13
R31
R32
R33
R34
R35
R36
R37
R38
T29
T30
T31
T32
T35
T36
T37
T38
U29
U30
U31
U32
U33
U34
U35
U36
V13
V14
V31
P14

Trace Length < 25 mils

AG37
AG38

VCCSENSE <52>

PH/PL on pwr side
10/07 Dan

VSSSENSE <52>

H-4+2/55A

B

+VCC_GT +VCC_GT

SKYLAKE_HALO

UC1H

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

SKL-H_BGA1440

@

BGA1440

8 OF 14

REV = 1

BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38

BJ37
BJ38
BL36

BL37
BM36
BM37
BN36
BN37
BN38
BP37
BP38
BR37

BT37
BE38

BF13

BF14

BF29

BF30

BF31

BF32

BF35

BF36

BF37

BF38
BG29
BG30
BG31
BG32
BG33
BC36
BC37
BC38
BD13
BD14
BD29
BD30
BD31
BD32
BD33
BD34
BD35
BD36
BE31
BE32
BE37

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

Rev_0 .53

AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BE33
BE34
BE35
BE36

?

Change to 14/14
Loss 13 of 14

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

+VCC_GT

AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38

AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP14
AP29
AP30
AP31
AP32
AP35
AP36
AP37
AP38
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36

AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36

AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38

AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38

UC1N

VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT
VCCGT

SKL-H_BGA1440

REV = 1

SKYLAKE_HALO

BGA1440

@

D

EDS:Rail is unconnected for Processors without GT3/4.

AF29

VCCGTX

AF30

VCCGTX

AF31

VCCGTX

AF32

VCCGTX

AF33

VCCGTX

AF34

VCCGTX

AG13

VCCGTX

AG14

VCCGTX

AG31

VCCGTX

AG32

VCCGTX

AG33

VCCGTX

AG34

VCCGTX

AG35

VCCGTX

AG36

VCCGTX

AH13

VCCGTX

AH14

VCCGTX

AH29

VCCGTX

AH30

VCCGTX

AH31

VCCGTX

AH32

VCCGTX

AJ13

VCCGTX

AJ14

VCCGTX

VCCGT_SENSE

VSSGTX_SENSE

VSSGT_SENSE

VCCGTX_SENSE

AH38
AH35
AH37
AH36

VCCGT_SENSE

VSSGT_SENSE

Trace Length < 25 mils

14 OF 14

?

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

SKL-H(5/9)Power,SVID

SKL-H(5/9)Power,SVID

SKL-H(5/9)Power,SVID

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

E

VCCGT_SENSE <52>

VSSGT_SENSE <52>

10 61Friday, October 28, 2016

10 61Friday, October 28, 2016

10 61Friday, October 28, 2016

1.0

1.0

1.0

A

B

C

D

E

DDR4/2.8A

VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ

?

+1.2V_VDDQ_CPU

AA6
AE12
AF5
AF6
AG5
AG9
AJ12
AL11
AP6
AP7
AR12
AR6
AT12
AW6
AY6
J5
J6
K12
K6
L12
L6
R6
T6
W6

Y12
BH13

G11

H30
H29

20mA

G30
H28

150mA

J28

VCCSA_SENSE

M38

VSSSA_SENSE

M37

VCCIO_SENSE

H14

VSSIO_SENSE

J14

For Power consumption
Measurement

JPC1

12

JUMP_43X118

JUMP_43X118

+VDDQ_CLK

+VCCSFR_OC_1
+VCCSFR_OC_2

+1.0V_VCCST
+1.0VS_VCCSTG

+1.0V_VCCSFR

@

JPC2

12

@

130mA

VCCSA_SENSE <52>
VSSSA_SENSE <52>

VCCIO_SENSE <51>
VSSIO_SENSE <51>

+1.2V_VDDQ

+1.0V_VCCST

1 2

RC39 0_0402_5%@

1 1

+1.0VS_VCCSTG

2 2

+1.2V_VDDQ_CPU

(1.0VS)

1U_0402_6.3V6K

CC68

1U_0402_6.3V6K

1

CC69

2

PVT modify

RC40

1 2

@

0_0603_5%

1

2

Place at Back Side

+1.2V_VDDQ

1 2

@

RC41 0_0402_5%

1 2

@

RC42 0_0402_5%

NOTE:
VCCPLL_OC is allowed to be turned off
during S3 & DS3 if it is not powered

3 3

directly from VDDQ

(1.35V)

+1.0V_VCCSFR

CC66 1U_0402_6.3V6K

+1.0V_VCCST

1

CC67
1U_0402_6.3V6K

2

Place at Back Side

+VDDQ_CLK

BSC Side

10U_0603_6.3V6M

1

CC70

2

+VCCSFR_OC_1

1U_0402_6.3V6K

1

CC71

2

1 2

+VCCSFR_OC_2

1

2

SKYLAKE_HALO

K29
K30
K31
K32
K33
K34
K35

M29
M30
M31
M32
M33
M34
M35
M36

AG12

G15
G17
G19
G21

J30

L31
L32
L35
L36
L37
L38

H15
H16
H17
H19
H20
H21
H26
H27
J15
J16
J17
J19
J20
J21
J26
J27

UC1I

VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA
VCCSA

VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO
VCCIO

SKL-H_BGA1440

REV = 1

@

BGA1440

9 OF 14

VDDQC

VCCPLL_OC
VCCPLL_OC

VCCST
VCCSTG
VCCSTG

VCCPLL
VCCPLL

VCCSA_SENSE
VSSSA_SENSE

VCCIO_SENSE

VSSIO_SENSE

RVP11 47u*1,10u*7,1u*3
CAP place on PWR side.

+VCC_SA

H-4+2/11.1A

RVP11
PWR NEED PROVIDE

0.95V FOR VCCIO

+1.0VS_VCCIO

H /5.5A

1U_0402_6.3V6K

CC72

Place at Back Side

+1.2V_VDDQ_CPU

10U_0603_6.3V6M

1

2

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC73

CC74

2

1

1

CC75

2

2

10U_0603_6.3V6M

1

CC76

1

CC77

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC79

CC78

2

2

10U_0603_6.3V6M

10U_0603_6.3V6M

1

CC80

2

10U_0603_6.3V6M

1

CC81

CC82

2

22U_0603_6.3V6M

CC83

1

1

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

CC84

1

2

22U_0603_6.3V6M

CC85

CC86

1

2

+1.0VS_VCCIO

10U_0603_6.3V6M

1

CC91

2

22U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

1

1

CC92

2

2

1

CC89

2

22U_0603_6.3V6M

CC90

CC87

1

1

2

2

22U_0603_6.3V6M

22U_0603_6.3V6M

CC88

CC93

1

2

Place at Back SidePlace at Back Side Follow ORB 3/20

+1.2V_VDDQ_CPU : 10UF/6.3V/0603 *10
22UF/6.3V/0603 * 4

4 4

update CRB cap QTY

CPU_CORE/VCCGT/VCCSA decoupling capacitor place to PWR side

Security Classification

Security Classification

Security Classification

2016/01/29 2017/01/10

2016/01/29 2017/01/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/01/29 2017/01/10

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

Compal Electronics, Inc.

SKL-H(6/9)POWER

SKL-H(6/9)POWER

SKL-H(6/9)POWER

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

11 61Friday, October 28, 2016

11 61Friday, October 28, 2016

11 61Friday, October 28, 2016

E

1.0

1.0

1.0

A

B

C

D

E

C17
C13

BT9
BT5

BR7

BP7

BN9
BN7
BN4
BN2

BM9
BM6
BM2

BH9
BH8
BH5
BH4
BH1

BE6
BD9

C9

SKYLAKE_HALO

UC1L

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-H_BGA1440

REV = 1

@

BGA1440

12 OF 14

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS

SKYLAKE_HALO

UC1J

REV = 1

BGA1440

10 OF 14

?

C25
C23
C21
C19
C15
C11
C8
C5
BM29
BM25
BM18
BM11
BM8
BM7
BM5
BM3
BL38
BL35
BL13
BL6
BK25
BK22
BK13
BK6
BJ30
BJ29
BJ15
BJ12
BH11
BH10
BH7
BH6
BH3
BH2
BG37
BG14
BG6
BF34
BF6
BE30
BE5
BE4
BE3
BE2
BE1
BD38
BD37
BD12
BD11
BD10
BD8
BD7
BD6
BC33
BC14
BC13
BC6
BB30
BB29
BB6
BB5

C2
BT36
BT35
BT4
BT3
BR38

?

T4 @
T5 @
T6 @

EDRAM

CRB EDRAM

OPC_RCOMP
OPCE_RCOMP
OPCE_RCOMP2

BJ17
BJ19

BJ20
BK17
BK19
BK20

BL16

BL17

BL18

BL19

BL20

BL21
BM17
BN17

BJ23

BJ26

BJ27
BK23
BK26
BK27

BL23

BL24

BL25

BL26

BL27

BL28
BM24

BL15
BM16

BL22
BM22

BP15
BR15

BT15
BP16

BR16

BT16

BN15
BM15

BP17
BN16

BM14

BL14

BJ35

BJ36

AT13

AW13

AU13
AY13

BT29
BR25
BP25

VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC
VCCOPC

RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD
RSVD

VCCOPC_SENSE
VSSOPC_SENSE

RSVD
RSVD

VCCEOPIO
VCCEOPIO
VCCEOPIO

RSVD
RSVD
RSVD

VCCEOPIO_SENSE
VSSEOPIO_SENSE

RSVD
RSVD

VCC_OPC_1P8
VCC_OPC_1P8

RSVD
RSVD

ZVM#
MSM#

ZVM2#
MSM2#

OPC_RCOMP
OPCE_RCOMP
OPCE_RCOMP2

SKL-H_BGA1440

@

SKYLAKE_HALO

UC1F

Y9
Y8
Y7

V6

U6

T9
T8
T7
T5
T4
T3
T2
T1

P6

N9
N8
N7
N6
N5
N4
N3
N2
N1

K9
K8
K7
K5
K4
K3
K2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-H_BGA1440

@

BGA1440

6 OF 14

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS

K1
J36
J33
J32
J25
J22
J18
J10
J7
J4
H35
H32
H25
H22
H18
H12
H11
G28
G26
G24
G23
G22
G20
G18
G16
G14
G12
G10
G9
G8
G6
G5
G4
F36
F31
F29
F27
F25
F23
F21
F19
F17
F15
F13
F11
F9
F8
F5
F4
F3
F2
E38
E35
E34
E9
E4
D33
D30
D28
D26
D24
D22
D20
D18
D16
D14
D12
D10
D9
D6
D3
C37
C31
C29
C27

D38

?REV = 1

BA38
BA37
BA12
BA11
BA10

AY34
AY33
AY14

AY12
AW30
AW29
AW12

AW5
AW4
AW3
AW2

AW1
AV38
AV37
AU34
AU33
AU12
AU11
AU10

AT30

AT29
AR38

AR37
AR14
AR13

AP34
AP33
AP12
AP11
AP10

AN30
AN29
AN12

AM38
AM37
AM12

AL34

AL33

AL14

AL12

AL10

Y38
Y37
Y14

1 1

2 2

3 3

4 4

Y13
Y11
Y10

W34
W33
W12

V30
V29
V12

U38
U37

T34
T33
T14
T13
T12
T11
T10

R30
R29
R12
P38
P37
P12

N34
N33
N12
N11
N10

M14
M13
M12

L34
L33
L30
L29
K38
K11
K10

W5
W4
W3
W2
W1

M6

BB4
BB3
BB2
BB1

BA9
BA8
BA7
BA6

AU9
AU8
AU7
AU6

AT6

AR5
AR4
AR3
AR2
AR1

AP9
AP8

AN6
AN5

AM5
AM4
AM3
AM2
AM1

AL9
AL8
AL7
AL4

B9

SKYLAKE_HALO

UC1M

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

SKL-H_BGA1440

REV = 1

@

BGA1440

13 OF 14

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS
NCTFVSS

AK30
AK29
AK4
AJ38
AJ37
AJ6
AJ5
AJ4
AJ3
AJ2
AJ1
AH34
AH33
AH12
AH6
AG30
AG29
AG11
AG10
AG8
AG7
AG6
AF14
AF13
AF12
AF4
AF3
AF2
AF1
AE34
AE33
AE6
AD30
AD29
AD12
AD11
AD10
AD9
AD8
AD7
AD6
AC38
AC37
AC12
AC6
AC5
AC4
AC3
AC2
AC1
AB34
AB33
AB6
AA30
AA29
AA12
A30
A28
A26
A24
A22
A20
A18
A16
A14
A12
A10
A9
A6

B37
B3
A34
A4
A3

?

BT32
BT26
BT24
BT21
BT18
BT14
BT12

BR36
BR34
BR29
BR26
BR24
BR21
BR18
BR14
BR12

BP34
BP33
BP29
BP26
BP24
BP21
BP18
BP14
BP12

BN34
BN31
BN30
BN29
BN24
BN21
BN20
BN19
BN18
BN14
BN12

BM38
BM35
BM28
BM27
BM26
BM23
BM21
BM13
BM12

BL29
BK29
BK15
BK14

BJ32

BJ31

BJ25

BJ22
BH14
BH12

BG38
BG13
BG12

BF33

BF12
BE29

BC34
BC12
BB12

Security Classification

Security Classification

Security Classification

2016/01/29 2017/01/10

2016/01/29 2017/01/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/01/29 2017/01/10

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

SKL-H(8/9)GND

SKL-H(8/9)GND

SKL-H(8/9)GND

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

E

1.0

1.0

1.0

12 61Friday, October 28, 2016

12 61Friday, October 28, 2016

12 61Friday, October 28, 2016

A

1 1

B

C

D

E

UC1K

D1

RSVD_TP

E1

RSVD_TP

E3

RSVD_TP

E2

RSVD_TP

BR1

RSVD_TP

BT2

RSVD_TP

BN35

RSVD

J24

RSVD

H24

RSVD

BN33

RSVD

BL34

RSVD

N29

RSVD

R14

RSVD

AE29

RSVD

2 2

PROC_TRIGIN_R<22>

PROC_TRIGOUT_R<22>

3 3

1 2

RC44 30_0402_1%

PROC_TRIGIN_R
PROC_TRIGOUT

AA14

H23

C30

BR35
BR31
BH30

A36
A37

J23
F30

E30
B30

G3

J3

RSVD
RSVD

RSVD
PROC_TRIGIN

PROC_TRIGOUT
RSVD

RSVD
RSVD

RSVD
RSVD

RSVD

RSVD
RSVD
RSVD

SKL-H_BGA1440

@

SKYLAKE_HALO

BGA1440

11 OF 14

Rev_0 .53

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD
RSVD

VSS

RSVD_TP
RSVD_TP

RSVD_TP
RSVD_TP

RSVD
RSVD

RSVD
RSVD

VSS

RSVD_TP
RSVD_TP

RSVD
RSVD
RSVD

NCTF
NCTF
NCTF
NCTF
NCTF
NCTF

1

2

1U_0402_6.3V6K

CC98

+1.0VALW

+1.0VALW

CC94

1

2

EN_1.0V_VCCSTU

1U_0402_6.3V6K

CC100

1

2

CC102

1

@

2

1U_0402_6.3V6K

+1.0VALW TO +1.0V_VCCST

UC3

1

IN

2
3
4

OUT
IN
VBIAS

VCC_PAD

ON

GND

AOZ1334DI-01_DFN8-7_3X3

6
7

5

+1.0V_VCCST_L

+1.0VALW

+1.0VALW TO +1.0VS_VCCSTG

VCCSTG and VCCIO SLEW RATE <=65us

UC4

1

IN

2

IN

3

VBIAS

VCC_PAD

4

ON

1U_0402_6.3V6K

AOZ1334DI-01_DFN8-7_3X3

OUT

GND

6

7

5

+1.0VALW

+1.0VS_VCCSTG_IO

UNPOP
Default use POWER side

JC1

112

JUMP_43X79

@

+1.0VS_VCCSTG

1 2

@

RC45 0_0402_5%

JC2

1 2

JUMP_43X118

@

+1.0V_VCCST

2

1

CC96
.1U_0402_16V7K

2

1 2

CC101 .1U_0402_16V7K

+1.0VS_VCCIO

BM33
BL33

BJ14
BJ13

BK28
BJ28

BJ18
BJ16

BK16

BK24
BJ24

BK21
BJ21

BT17
BR17

BK18
BJ34

BJ33

G13
AJ8
BL31

NCTF_0

B2

NCTF_1

B38

NCTF_2

BP1

NCTF_3

BR2

NCTF_4

C1

NCTF_5

C38

?REV = 1

SYSON<39,43,48,50>

T7 PAD@
T8 PAD@
T9 PAD@
T10 PAD@
T11 PAD@
T12 PAD@

SUSP#<39,43,48,50,51>

+5VALW

CC95 1U_0402_6.3V6K

RC43 0_0402_5%@

PVT modify

12

@

1 2

+1.0V_VCCST: 60mA
R ON = 4.5mΩ
VDROP= 1.32mV
Delay time: 270us

+5VALW

1

CC99

.1U_0402_16V7K

SUSP#

2

1 2

RC46 0_0402_5%@

PVT modify

+1.0VS_VCCSTG: 60mA
R ON = 4.4mΩ
VDROP= 11mV
Delay time: 9.3us

4 4

Security Classification

Security Classification

Security Classification

2016/01/29 2017/01/10

2016/01/29 2017/01/10

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

A

B

2016/01/29 2017/01/10

C

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

SKL-H(9/9)RSVD

SKL-H(9/9)RSVD

SKL-H(9/9)RSVD

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

E

1.0

1.0

1.0

13 61Friday, October 28, 2016

13 61Friday, October 28, 2016

13 61Friday, October 28, 2016

A

B

C

D

E

DDR_A_DQS#[0..7]<7>

DDR_A_D[0..63]<7>

DDR_A_DQS[0..7]<7>

DDR_A_MA[0..16]<7>

DDR_A_BA0<7>

DDR_A_BA1<7>

DDR_A_BG0<7>

1 1

Layout Note:
Place near JDIMM1

2 2

+1.2V_VDDQ

1U_0402_6.3V6K

1

2

+1.2V_VDDQ

10U_0603_6.3V6M

C

1

D18

3 3

4 4

2

Layout Note:
Place near JDIMM1.258

Layout Note:
Place near JDIMM1.255

DDR_A_BG1<7>

DDR_A_CLK0<7>
DDR_A_CLK#0<7>
DDR_A_CLK1<7>

DDR_A_CLK#1<7>

DDR_A_CKE0<7>
DDR_A_CKE1<7>
DDR_A_CS#0<7>

DDR_A_CS#1<7>

D_CK_SDATA<15,18,38>
D_CK_SCLK<15,18,38>

DDR_A_ODT0<7>

DDR_A_ODT1<7>

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

C
D4

2

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

C
D28

2

C
D19

C
D5

2

10U_0603_6.3V6M

1

2

+0.6VS_VTT

1U_0402_6.3V6K

1

C
D29

2

C
D6

10U_0603_6.3V6M

C
D20

1U_0402_6.3V6K

1

2

+3VS

DDR_A_BA0
DDR_A_BA1
DDR_A_BG0
DDR_A_BG1

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

DDR_A_CKE0
DDR_A_CKE1
DDR_A_CS#0
DDR_A_CS#1

D_CK_SDATA
D_CK_SCLK

DDR_A_ODT0
DDR_A_ODT1

Note:
place caps close to DIMM
4 on each side of DIMM

1U_0402_6.3V6K

1

2

C

1

D21

2

C
D30

0_0402_5%

A

1U_0402_6.3V6K

1

C

CD8

D7

2

10U_0603_6.3V6M

10U_0603_6.3V6M

CD22

1

2

1U_0402_6.3V6K

1

CD31

2

@

RD8

12

1U_0402_6.3V6K

1

1

CD9

2

2

10U_0603_6.3V6M

CD23

1

1

2

2

10U_0603_6.3V6M

CD32

1

1

2

2

Place Holder

@

1

CD35

2

.1U_0402_16V7K

1U_0402_6.3V6K

1

CD10

2

10U_0603_6.3V6M

CD24

1

2

10U_0603_6.3V6M

CD33

+3VS_DIMMA

1

CD36

2

2.2U_0402_6.3V6M

1U_0402_6.3V6K

CD25

+1.2V_VDDQ

CD11

CD12

Follow MA51

1

+

CD26
330U_D2_2V_Y

2

SGA00009S00
330U 2V H1.9
9mohm POLY

+0.6V_DDRA_VREFCA

1

2

CPU Side

+0.6V_VREFCA

1

CD2

0.022U_0402_16V7K

RD4

24.9_0402_1%

2

12

Place near to SO-DIMM connector.

Layout Note:
Place near JDIMM1.257/259

1

CD13

2

.1U_0402_16V7K

.1U_0402_16V7K

1

1

CD38

CD37

2

2

.1U_0402_16V7K

Layout Note:
Place near JDIMM1.164

2.2U_0402_6.3V6M

within 200mils

B

RD2
2_0402_1%

1

2

1U_0402_6.3V6K

+1.2V_VDDQ

RD1

1 2

12

RD3

1 2

+2.5V

1

1

CD15

CD14

2

2

1U_0402_6.3V6K

DDR_DRAMRST#<18>

*2015MOW02, Can't install Cap on DRAMRST

Layout Note:
Place near JDIMM1.164

1

CD1

2

1K_0402_1%

.1U_0402_16V7K

1

CD3

2

1K_0402_1%

.1U_0402_16V7K

1

CD16

CD17

2

10U_0603_6.3V6M

10U_0603_6.3V6M

XEMC@

CD34

100P_0402_50V8J

Dimm1 Side

+0.6V_DDRA_VREFCA

+0.6V_DDRA_VREFCA

+1.2V_VDDQ

RD7

0_0402_5%

1

@

2

Layout NOTE
PLACE THE CAP within 200mil from Pin108

#543016 PDG 1.0164
20mils wide & spacing

DDR_A_ACT#<7>

DDR_A_PARITY<7>
DDR_A_ALERT#<7>

1 2

RD5 240_0402_1%

SPD Address for CHANNEL0
Write Adress 0xA0
Read Address 0xA1
SA0=0;SA1=0;SA2=0

+1.2V_VDDQ

RD6
470_0402_5%

1 2

12

1

CD27
.1U_0402_16V7K

2

@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

DDR_A_CLK0
DDR_A_CLK#0
DDR_A_CLK1
DDR_A_CLK#1

DDR_A_CKE0
DDR_A_CKE1

DDR_A_CS#0
DDR_A_CS#1

DDR_A_ODT0
DDR_A_ODT1

DDR_A_BG0
DDR_A_BG1
DDR_A_BA0
DDR_A_BA1

DDR_A_MA0
DDR_A_MA1
DDR_A_MA2
DDR_A_MA3
DDR_A_MA4
DDR_A_MA5
DDR_A_MA6
DDR_A_MA7
DDR_A_MA8
DDR_A_MA9
DDR_A_MA10
DDR_A_MA11
DDR_A_MA12
DDR_A_MA13
DDR_A_MA14
DDR_A_MA15

DDR_A_MA16
DDR_A_ACT#
DDR_A_PARITY

DDR_A_ALERT#
DDR_A_EVENT#
DDR_DRAMRST#_R

D_CK_SDATA
D_CK_SCLK

DDR_A_SA2

DDR_A_SA1

DDR_A_SA0

+1.2V_VDDQ

DDR_DRAMRST#_R <15>

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

JDIMM1A

REVERSE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR0206-P001A

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQS0(T)

DQS0#(C)

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQS6#(C)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

8
7
20
21
4
3
16
17
13
11

28
29
41
42
24
25
38
37
34
32

50
49
62
63
46
45
58
59
55
53

70
71
83
84
66
67
79
80
76
74

174
173
187
186
170
169
183
182
179
177

195
194
207
208
191
190
203
204
200
198

216
215
228
229
211
212
224
225
221
219

237
236
249
250
232
233
245
246
242
240

D

DDR_A_D0
DDR_A_D1
DDR_A_D2
DDR_A_D3
DDR_A_D4
DDR_A_D5
DDR_A_D6
DDR_A_D7
DDR_A_DQS0
DDR_A_DQS#0

DDR_A_D8
DDR_A_D9
DDR_A_D10
DDR_A_D11
DDR_A_D12
DDR_A_D13
DDR_A_D14
DDR_A_D15
DDR_A_DQS1
DDR_A_DQS#1

DDR_A_D16
DDR_A_D17
DDR_A_D18
DDR_A_D19
DDR_A_D20
DDR_A_D21
DDR_A_D22
DDR_A_D23
DDR_A_DQS2
DDR_A_DQS#2

DDR_A_D24
DDR_A_D25
DDR_A_D26
DDR_A_D27
DDR_A_D28
DDR_A_D29
DDR_A_D30
DDR_A_D31
DDR_A_DQS3
DDR_A_DQS#3

DDR_A_D32
DDR_A_D33
DDR_A_D34
DDR_A_D35
DDR_A_D36
DDR_A_D37
DDR_A_D38
DDR_A_D39
DDR_A_DQS4
DDR_A_DQS#4

DDR_A_D40
DDR_A_D41
DDR_A_D42
DDR_A_D43
DDR_A_D44
DDR_A_D45
DDR_A_D46
DDR_A_D47
DDR_A_DQS5
DDR_A_DQS#5

DDR_A_D48
DDR_A_D49
DDR_A_D50
DDR_A_D51
DDR_A_D52
DDR_A_D53
DDR_A_D54
DDR_A_D55
DDR_A_DQS6
DDR_A_DQS#6

DDR_A_D56
DDR_A_D57
DDR_A_D58
DDR_A_D59
DDR_A_D60
DDR_A_D61
DDR_A_D62
DDR_A_D63
DDR_A_DQS7
DDR_A_DQS#7

+1.2V_VDDQ +1.2V_VDDQ

+0.6V_DDRA_VREFCA

+3VS_DIMMA

Interleaved Memory

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

Reverse Type-4H

2-3A to 1 DIMMs/channel

JDIMM1B

REVERSE

111

VDD1

112

VDD2

117

VDD3

118

VDD4

123

VDD5

124

VDD6

129

VDD7

130

VDD8

135

VDD9

136

VDD10

255

VDDSPD

164

VREFCA

1

VSS

2

VSS

5

VSS

6

VSS

9

VSS

10

VSS

14

VSS

15

VSS

18

VSS

19

VSS

22

VSS

23

VSS

26

VSS

27

VSS

30

VSS

31

VSS

35

VSS

36

VSS

39

VSS

40

VSS

43

VSS

44

VSS

47

VSS

48

VSS

51

VSS

52

VSS

56

VSS

57

VSS

60

VSS

61

VSS

64

VSS

65

VSS

68

VSS

69

VSS

72

VSS

73

VSS

77

VSS

78

VSS

81

VSS

82

VSS

85

VSS

86

VSS

89

VSS

90

VSS

93

VSS

94

VSS

98

VSS

262

GND

LOTES_ADDR0206-P001A

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

DDR4_DIMMA

DDR4_DIMMA

DDR4_DIMMA

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VTT

VPP1
VPP2

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

E

141
142
147
148
153
154
159
160
163

+0.6VS_VTT

258
257

259
99

102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252

261

+2.5V

14 61Friday, October 28, 2016

14 61Friday, October 28, 2016

14 61Friday, October 28, 2016

1.0

1.0

1.0

A

DDR_B_DQS#[0..7]<7>
DDR_B_D[0..63]<7>
DDR_B_DQS[0..7]<7>

DDR_B_MA[0..16]<7>

DDR_B_BA0<7>
DDR_B_BA1<7>

1 1

Layout Note:
Place near JDIMM2

2 2

+1.2V_VDDQ

+1.2V_VDDQ

10U_0603_6.3V6M

3 3

Layout Note:
Place near JDIMM2.258

4 4

Layout Note:
Place near JDIMM1.255

DDR_B_BG0<7>
DDR_B_BG1<7>

DDR_B_CLK0<7>
DDR_B_CLK#0<7>
DDR_B_CLK1<7>
DDR_B_CLK#1<7>

DDR_B_CKE0<7>
DDR_B_CKE1<7>
DDR_B_CS#0<7>
DDR_B_CS#1<7>

D_CK_SDATA<14,18,38>
D_CK_SCLK<14,18,38>

DDR_B_ODT0<7>
DDR_B_ODT1<7>

1U_0402_6.3V6K

1

C
D42

2

10U_0603_6.3V6M

C

1

D56

2

1

2

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

1U_0402_6.3V6K

2

1

2

C
D66

C
D57

C
D43

2

10U_0603_6.3V6M

1

2

+0.6VS_VTT

1U_0402_6.3V6K

1

C
D67

2

C
D44

10U_0603_6.3V6M

C
D58

1

2

A

DDR_B_BA0
DDR_B_BA1
DDR_B_BG0
DDR_B_BG1

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_CKE0
DDR_B_CKE1

DDR_B_CS#0

DDR_B_CS#1

D_CK_SDATA DDR_B_MA2
D_CK_SCLK

DDR_B_ODT0
DDR_B_ODT1

Note:
place caps close to DIMM
4 on each side of DIMM

+1.2V_VDDQ

1U_0402_6.3V6K

1U_0402_6.3V6K

1

1

@

CD72

2

1

2

1

2

CD48

10U_0603_6.3V6M

CD62

10U_0603_6.3V6M

CD71

+3VS_DIMMB

1

2

CD49

2

CD63

1

@

2

CD73

2.2U_0402_6.3V6M

+3VS

1U_0402_6.3V6K

1U_0402_6.3V6K

1

2

CD59

1

2

CD68

1

CD45

2

10U_0603_6.3V6M

1

2

1U_0402_6.3V6K

1

2

@

RD15

0_0402_5%

1U_0402_6.3V6K

1

CD46

2

10U_0603_6.3V6M

CD60

1

2

1

CD69

2

Place Holder

12

1

2

1U_0402_6.3V6K

CD47

10U_0603_6.3V6M

CD61

10U_0603_6.3V6M

CD70

.1U_0402_16V7K

CPU Side

+0.6V_B_VREFDQ +0.6V_DDRB_VREFCA

CD40

0.022U_0402_16V7K

RD12

24.9_0402_1%

Place near to SO-DIMM connector.

1

CD50

CD51

2

.1U_0402_16V7K

Follow MA51

1

+

CD64
330U_D2_2V_Y

2

SGA00009S00
330U 2V H1.9
9mohm POLY

+0.6V_DDRB_VREFCA

1

CD74

2

B

+1.2V_VDDQ

1

CD39

RD9

RD11
2_0402_1%

12

1

2

12

Layout Note:
Place near JDIMM2.257/259

1

2

.1U_0402_16V7K

1

2

2

1 2

1K_0402_1%

RD10

1 2

1K_0402_1%

1

CD53

CD52

2

1U_0402_6.3V6K

1U_0402_6.3V6K

+2.5V

.1U_0402_16V7K

1

2

Dimm2 Side

Layout Note:
Place near JDIMM2.164

20mils wide & spacing

1

CD41
.1U_0402_16V7K

2

1

CD54

CD55

2

10U_0603_6.3V6M

10U_0603_6.3V6M

Layout NOTE
PLACE THE CAP within 200mil from Pin108

+1.2V_VDDQ

C

DDR_B_CLK0
DDR_B_CLK#0
DDR_B_CLK1
DDR_B_CLK#1

DDR_B_CKE0
DDR_B_CKE1

DDR_B_CS#0
DDR_B_CS#1

DDR_B_ODT0
DDR_B_ODT1

DDR_B_ACT#<7>

DDR_B_PARITY<7>
DDR_B_ALERT#<7>

1 2

RD13 240_0402_1%

+3VS

1 2

PVT modify

SPD Address for CHANNELB
Write Adress 0xA4
Read Address 0xA3
SA0=0;SA1=1;SA2=0

From CPU to CHB

1

CD65
.1U_0402_16V7K

2

@

DDR_B_ACT#
DDR_B_PARITY

DDR_B_ALERT#
DDR_B_EVENT#
DDR_DRAMRST#_R

D_CK_SDATA
D_CK_SCLK

RD14

@

0_0402_5%

+1.2V_VDDQ

DDR_DRAMRST#_R <14>

DDR_B_BG0
DDR_B_BG1
DDR_B_BA0
DDR_B_BA1

DDR_B_MA0
DDR_B_MA1

DDR_B_MA3
DDR_B_MA4
DDR_B_MA5
DDR_B_MA6
DDR_B_MA7
DDR_B_MA8
DDR_B_MA9
DDR_B_MA10
DDR_B_MA11
DDR_B_MA12
DDR_B_MA13
DDR_B_MA14
DDR_B_MA15
DDR_B_MA16

DDR_B_SA2
DDR_B_SA1
DDR_B_SA0

JDIMM2A

RESERVE

137

CK0(T)

139

CK0#(C)

138

CK1(T)

140

CK1#(C)

109

CKE0

110

CKE1

149

S0#

157

S1#

162

S2#/C0

165

S3#/C1

155

ODT0

161

ODT1

115

BG0

113

BG1

150

BA0

145

BA1

144

A0

133

A1

132

A2

131

A3

128

A4

126

A5

127

A6

122

A7

125

A8

121

A9

146

A10_AP

120

A11

119

A12

158

A13

151

A14_WE#

156

A15_CAS#

152

A16_RAS#

114

ACT#

143

PARITY

116

ALERT#

134

EVENT#

108

RESET#

254

SDA

253

SCL

166

SA2

260

SA1

256

SA0

92

CB0_NC

91

CB1_NC

101

CB2_NC

105

CB3_NC

88

CB4_NC

87

CB5_NC

100

CB6_NC

104

CB7_NC

97

DQS8(T)

95

DQS8#(C)

12

DM0#/DBI0#

33

DM1#/DBI1#

54

DM2#/DBI2#

75

DM3#/DBI3#

178

DM4#/DBI4#

199

DM5#/DBI5#

220

DM6#/DBI6#

241

DM7#/DBI7#

96

DM8#/DBI8#

LOTES_ADDR0070-P009A

DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7

DQS0(T)

DQS0#(C)

DQ8

DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15

DQS1(T)

DQS1#(C)

DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23

DQS2(T)

DQS2#(C)

DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31

DQS3(T)

DQS3#(C)

DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39

DQS4(T)

DQS4#(C)

DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47

DQS5(T)

DQS5#(C)

DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55

DQS6(T)

DQS6#(C)

DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63

DQS7(T)

DQS7#(C)

D

8
7
20
21
4
3
16
17
13
11

28
29
41
42
24
25
38
37
34
32

50
49
62
63
46
45
58
59
55
53

70
71
83
84
66
67
79
80
76
74

174
173
187
186
170
169
183
182
179
177

195
194
207
208
191
190
203
204
200
198

216
215
228
229
211
212
224
225
221
219

237
236
249
250
232
233
245
246
242
240

DDR_B_D0
DDR_B_D1
DDR_B_D2
DDR_B_D3
DDR_B_D4
DDR_B_D5
DDR_B_D6
DDR_B_D7
DDR_B_DQS0
DDR_B_DQS#0

DDR_B_D8
DDR_B_D9
DDR_B_D11
DDR_B_D15
DDR_B_D14
DDR_B_D10
DDR_B_D12
DDR_B_D13
DDR_B_DQS1
DDR_B_DQS#1

DDR_B_D16
DDR_B_D17
DDR_B_D19
DDR_B_D20
DDR_B_D22
DDR_B_D18
DDR_B_D23
DDR_B_D21
DDR_B_DQS2
DDR_B_DQS#2

DDR_B_D30
DDR_B_D25
DDR_B_D26
DDR_B_D24
DDR_B_D28
DDR_B_D27
DDR_B_D29
DDR_B_D31
DDR_B_DQS3
DDR_B_DQS#3

DDR_B_D34
DDR_B_D35
DDR_B_D36
DDR_B_D32
DDR_B_D39
DDR_B_D38
DDR_B_D37
DDR_B_D33
DDR_B_DQS4
DDR_B_DQS#4

DDR_B_D40
DDR_B_D41
DDR_B_D42
DDR_B_D43
DDR_B_D44
DDR_B_D45
DDR_B_D46
DDR_B_D47
DDR_B_DQS5
DDR_B_DQS#5

DDR_B_D48
DDR_B_D52
DDR_B_D50
DDR_B_D55
DDR_B_D51
DDR_B_D54
DDR_B_D49
DDR_B_D53
DDR_B_DQS6
DDR_B_DQS#6

DDR_B_D61
DDR_B_D57
DDR_B_D60
DDR_B_D56
DDR_B_D62
DDR_B_D59
DDR_B_D63
DDR_B_D58
DDR_B_DQS7
DDR_B_DQS#7

+1.2V_VDDQ

+0.6V_DDRB_VREFCA

E

Reverse Type-8H

2-3A to 1 DIMMs/channel

JDIMM2B

RESERVE

111

VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10

VDDSPD
VREFCA

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

GND

VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
VDD18
VDD19

VPP1
VPP2

GND

+3VS_DIMMB

112
117
118
123
124
129
130
135
136

255
164

1
2
5
6

9
10
14
15
18
19
22
23
26
27
30
31
35
36
39
40
43
44
47
48
51
52
56
57
60
61
64
65
68
69
72
73
77
78
81
82
85
86
89
90
93
94
98

262

LOTES_ADDR0070-P009A

VTT

VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS

+1.2V_VDDQ

141
142
147
148
153
154
159
160
163

+0.6VS_VTT

258
257

259
99

102
103
106
107
167
168
171
172
175
176
180
181
184
185
188
189
192
193
196
197
201
202
205
206
209
210
213
214
217
218
222
223
226
227
230
231
234
235
238
239
243
244
247
248
251
252

261

+2.5V

*2015MOW02, Can't install Cap on DRAMRST

1

CD75

2

.1U_0402_16V7K

Layout Note:
Place near JDIMM1.164

2.2U_0402_6.3V6M

within 200mils

B

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

C

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

D

Interleaved Memory

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

Size Document Number Re v

Size Document Number Re v

Size Document Number Re v

Custom

Custom

Custom

Date: Sheet of

Date: Sheet of

Date: Sheet of

DDR4_DIMMB

DDR4_DIMMB

DDR4_DIMMB

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

E

15 61Friday, October 28, 2016

15 61Friday, October 28, 2016

15 61Friday, October 28, 2016

1.0

1.0

1.0

A

B

C

D

E

REV = 1.3

REV = 1.3

USB

SPT-H_PCH

LPC/eSPI

GPP_A14/SUS_STAT#/ESPI_RESET#

SATA

6 OF 12

SPT-H_PCH

DMI

PCIe/USB 3

GPP_A1/LAD0/ESPI_IO0
GPP_A2/LAD1/ESPI_IO1
GPP_A3/LAD2/ESPI_IO2
GPP_A4/LAD3/ESPI_IO3

GPP_A5/LFRAME#/ESPI_CS0#

GPP_A6/SERIRQ/ESPI_CS1#

GPP_A7/PIRQA#/ESPI_ALERT0#

GPP_A0/RCIN#/ESPI_ALERT1#

GPP_A9/CLKOUT_LPC0/ESPI_CLK

GPP_A10/CLKOUT_LPC1

GPP_G19/SMI#

GPP_G18/NMI#

GPP_E6/DEVSLP2
GPP_E5/DEVSLP1
GPP_E4/DEVSLP0
GPP_F9/DEVSLP7
GPP_F8/DEVSLP6
GPP_F7/DEVSLP5
GPP_F6/DEVSLP4
GPP_F5/DEVSLP3

USB2N_1

USB2P_1

USB2N_2

USB2P_2

USB2N_3

USB2P_3

USB2N_4

USB2P_4

USB2N_5

USB2P_5

USB2N_6

USB2P_6

USB 2.0

2 OF 12

USB2N_7

USB2P_7

USB2N_8

USB2P_8

USB2N_9

USB2P_9
USB2N_10
USB2P_10
USB2N_11
USB2P_11
USB2N_12
USB2P_12
USB2N_13
USB2P_13
USB2N_14
USB2P_14

GPP_E9/USB2_OC0#
GPP_E10/USB2_OC1#
GPP_E11/USB2_OC2#
GPP_E12/USB2_OC3#

GPP_F15/USB2_OCB_4
GPP_F16/USB2_OCB_5
GPP_F17/USB2_OCB_6
GPP_F18/USB2_OCB_7

USB2_COMP

USB2_VBUSSENSE

RSVD_AB13

USB2_ID

GPD7/RSVD

?

?

LPC_AD0

AT22

LPC_AD1

AV22

LPC_AD2

AT19

LPC_AD3

BD16

LPC_FRAME#

BE16

TPM_SERIRQ

BA17

LPC_PIRQA#

AW17

EC_KBRST#_R

AT17

ESPI_RST#

BC18

CLK_LPC

BC17

CLK_LPC_TPM

AV19
M45

N43

AE45
AG43

SSD_DEVSLP0

AG42
AB39
AB36
AB43
AB42
AB41

USB20_N1

AF5

USB20_P1

AG7

USB20_N2

AD5

USB20_P2

AD7

USB20_N3

AG8

USB20_P3

AG10

USB20_N4

AE1

USB20_P4

AE2

USB20_N5

AC2

USB20_P5

AC3
AF2
AF3

USB20_N7

AB3

USB20_P7

AB2

USB20_N8

AL8

USB20_P8

AL7

USB20_N9

AA1

USB20_P9

AA2

USB20_N10

AJ8

USB20_P10

AJ7

USB20_N11

W2

USB20_P11

W3
AD3
AD2
V2
V1
AJ11
AJ13

AD43
AD42
AD39
AC44
Y43
Y41
W44
W43

AG3
AD10
AB13
AG2

BD14

CHECK ACER DVR for port use
12/08 Change Port, follow DVR1044_R1.03

USB_OC0#
USB_OC1#

USB_OC3#
USB_OC4
USB_OC5
USB_OC6
USB_OC7

USB2_COMP
USB2_VBUSSENSE

USB2_ID

546765_2015WW10_Skylake_MOW_Rev_1_0
05/19 RH150

LPC_AD0 <39,41>
LPC_AD1 <39,41>
LPC_AD2 <39,41>
LPC_AD3 <39,41>

LPC_FRAME# <39,41>
TPM_SERIRQ <39,41>

EC_KBRST#_R <20,39>

T203PAD@

RH3 22_0402_5%
RH4 22_0402_5%TPM@

12
12

SSD_DEVSLP0 <34>

USB20_N1 <36>
USB20_P1 <36>
USB20_N2 <36>
USB20_P2 <36>
USB20_N3 <35>
USB20_P3 <35>
USB20_N4 <35>
USB20_P4 <35>
USB20_N5 <33>
USB20_P5 <33>

USB20_N7 <37>
USB20_P7 <37>
USB20_N8 <30>
USB20_P8 <30>
USB20_N9 <30>
USB20_P9 <30>
USB20_N10 <33>
USB20_P10 <33>
USB20_N11 <42>
USB20_P11 <42>

USB_OC0# <36>
USB_OC1# <36>

1 2

RH7 113_0402_1%
RH8 0_0402_5%@

1 2
1 2

RH9 0_0402_5%@

LPC Bus

LPC : +3.3V

To TPM

CLK_LPC_R <39>
CLK_LPC_TPM_R <41>

USB3 MB
USB3 MB

TYPE C

USB2 (SUB/B)

BT

TS
Camera
Card Reader (SUB/B)
FingerPrint

PVT modify

To EC

TPM_SERIRQ

DG requierment 8.2k PH +3VS
CRB 10K PH +3vs

EC_KBRST#_R

check EC design needed
pop RH2 or not

LPC_PIRQA#

1 2

RH1 10K_0402_5%

1 2

RH2 10K_0402_5%

RH5 10K_0402_5%

reference PDG1.0 50-30

USB_OC0#
USB_OC1#
USB_OC3#
USB_OC2#USB_OC2#

USB_OC5
USB_OC4
USB_OC6
USB_OC7

RPH1

18
27
36
45

10K_0804_8P4R_5%

RPH2

18
27
36
45

10K_0804_8P4R_5%

@

+3VS

@

+3VALW_PCH_PRIM

12

+3VALW_PCH_PRIM

UH1F

1 1

USB3 MB

USB3 MB

USB3 Type C

2 2

#546884 P.231 PCIE_RCOMPN/PCIE_RCOMPP
BO=4 W=12~15 S=12 R=100ohm

3 3

NGFF WL+BT(KEY E)

GLAN

PCIE_PRX_DTX_N3<37>

PCIE_PRX_DTX_P3<37>
PCIE_PTX_C_DRX_N3<37>
PCIE_PTX_C_DRX_P3<37>

PCIE_PRX_DTX_N4<32>

PCIE_PRX_DTX_P4<32>

PCIE_PTX_C_DRX_N4<32>
PCIE_PTX_C_DRX_P4<32>

CHECK ACER DVR for port use
12/08 Change Port, follow DVR1044_R1.03

USB3_PTX_DRX_N1<36>
USB3_PTX_DRX_P1<36>
USB3_PRX_DTX_N1<36>
USB3_PRX_DTX_P1<36>
USB3_PTX_DRX_N2<36>
USB3_PTX_DRX_P2<36>
USB3_PRX_DTX_N2<36>
USB3_PRX_DTX_P2<36>

USB3_PTX_DRX_N3<35>
USB3_PTX_DRX_P3<35>
USB3_PRX_DTX_N3<35>
USB3_PRX_DTX_P3<35>

USB3_PTX_DRX_N4<35>
USB3_PTX_DRX_P4<35>
USB3_PRX_DTX_N4<35>
USB3_PRX_DTX_P4<35>

DMI_CTX_PRX_N0<8>
DMI_CTX_PRX_P0<8>
DMI_CRX_PTX_N0<8>
DMI_CRX_PTX_P0<8>
DMI_CTX_PRX_N1<8>
DMI_CTX_PRX_P1<8>
DMI_CRX_PTX_N1<8>
DMI_CRX_PTX_P1<8>
DMI_CTX_PRX_N2<8>
DMI_CTX_PRX_P2<8>
DMI_CRX_PTX_N2<8>
DMI_CRX_PTX_P2<8>
DMI_CTX_PRX_N3<8>
DMI_CTX_PRX_P3<8>
DMI_CRX_PTX_N3<8>
DMI_CRX_PTX_P3<8>

RH6 100_0402_1%

1 2

12

CH4 .1U_0402_16V7K
CH5 .1U_0402_16V7K

12

CH6 .1U_0402_16V7K

12
12

CH7 .1U_0402_16V7K

DMI_CTX_PRX_N0
DMI_CTX_PRX_P0
DMI_CRX_PTX_N0
DMI_CRX_PTX_P0
DMI_CTX_PRX_N1
DMI_CTX_PRX_P1
DMI_CRX_PTX_N1
DMI_CRX_PTX_P1
DMI_CTX_PRX_N2
DMI_CTX_PRX_P2
DMI_CRX_PTX_N2
DMI_CRX_PTX_P2
DMI_CTX_PRX_N3
DMI_CTX_PRX_P3
DMI_CRX_PTX_N3
DMI_CRX_PTX_P3

PCIE_RCOMPN
PCIE_RCOMPP

PCIE_PRX_DTX_N3
PCIE_PRX_DTX_P3
PCIE_PTX_DRX_N3
PCIE_PTX_DRX_P3
PCIE_PRX_DTX_N4

PCIE_PRX_DTX_P4
PCIE_PTX_DRX_N4
PCIE_PTX_DRX_P4

C11

USB3_1_TXN

B11

USB3_1_TXP

B7

USB3_1_RXN

A7

USB3_1_RXP

B12

USB3_2_TXN/SSIC_1_TXN

A12

USB3_2_TXP/SSIC_1_TXP

C8

USB3_2_RXN/SSIC_1_RXN

B8

USB3_2_RXP/SSIC_1_RXP

B15

USB3_6_TXN

C15

USB3_6_TXP

K15

USB3_6_RXN

K13

USB3_6_RXP

B14

USB3_5_TXN

C14

USB3_5_TXP

G13

USB3_5_RXN

H13

USB3_5_RXP

D13

USB3_3_TXP/SSIC_2_TXP

C13

USB3_3_TXN/SSIC_2_TXN

A9

USB3_3_RXP/SSIC_2_RXP

B10

USB3_3_RXN/SSIC_2_RXN

B13

USB3_4_TXP

A14

USB3_4_TXN

G11

USB3_4_RXP

E11

USB3_4_RXN

SKL-H-PCH_BGA837

@

UH1B

L27

DMI_RXN0

N27

DMI_RXP0

C27

DMI_TXN0

B27

DMI_TXP0

E24

DMI_RXN1

G24

DMI_RXP1

B28

DMI_TXN1

A28

DMI_TXP1

G27

DMI_RXN2

E26

DMI_RXP2

B29

DMI_TXN2

C29

DMI_TXP2

L29

DMI_RXN3

K29

DMI_RXP3

B30

DMI_TXN3

A30

DMI_TXP3

B18

PCIE_RCOMPN

C17

PCIE_RCOMPP

H15

PCIE1_RXN/USB3_7_RXN

G15

PCIE1_RXP/USB3_7_RXP

A16

PCIE1_TXN/USB3_7_TXN

B16

PCIE1_TXP/USB3_7_TXP

B19

PCIE2_TXN/USB3_8_TXN

C19

PCIE2_TXP/USB3_8_TXP

E17

PCIE2_RXN/USB3_8_RXN

G17

PCIE2_RXP/USB3_8_RXP

L17

PCIE3_RXN/USB3_9_RXN

K17

PCIE3_RXP/USB3_9_RXP

B20

PCIE3_TXN/USB3_9_TXN

C20

PCIE3_TXP/USB3_9_TXP

E20

PCIE4_RXN/USB3_10_RXN

G19

PCIE4_RXP/USB3_10_RXP

B21

PCIE4_TXN/USB3_10_TXN

A21

PCIE4_TXP/USB3_10_TXP

K19

PCIE5_RXN

L19

PCIE5_RXP

D22

PCIE5_TXN

C22

PCIE5_TXP

G22

PCIE6_RXN

E22

PCIE6_RXP

B22

PCIE6_TXN

A23

PCIE6_TXP

L22

PCIE7_RXN

K22

PCIE7_RXP

C23

PCIE7_TXN

B23

PCIE7_TXP

K24

PCIE8_RXN

L24

PCIE8_RXP

C24

PCIE8_TXN

B24

PCIE8_TXP

SKL-H-PCH_BGA837

@

4 4

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

C

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(1/7)DMI,PCIE,USB

PCH(1/7)DMI,PCIE,USB

PCH(1/7)DMI,PCIE,USB

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

E

16 61Friday, October 28, 2016

16 61Friday, October 28, 2016

16 61Friday, October 28, 2016

1.0

1.0

1.0

A

B

C

D

E

REV = 1.3

RH28
100K_0402_5%

@

RPH3

PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_IO3
PCH_SPI_CLK

15_0804_8P4R_5%

PCH_SPI_IO2PCH_SPI_IO2_0_R

+3VALW_SPI

8

PCH_SPI_IO3_0_RPCH_SPI_SO_0_R

7

PCH_SPI_CLK_0_R

6

PCH_SPI_SI_0_R

5

@

1 2

CH19
68P_0402_50V8J

+3VALW_SPI

8

PCH_SPI_CLK_0_R

6

PCH_SPI_SI_0_R

5

PCH_SPI_SO_0_R

2

SPT-H_PCH

GPP_B13/PLTRST#

GPP_G16/GSXCLK

GPP_G12/GSXDOUT

GPP_G13/GSXSLOAD

GPP_G14/GSXDIN

GPP_G15/GSXSRESET#

GPP_E3/CPU_GP0
GPP_E7/CPU_GP1
GPP_B3/CPU_GP2
GPP_B4/CPU_GP3

GPP_H18/SML4ALERT#

GPP_H17/SML4DATA

GPP_H16/SML4CLK

GPP_H15/SML3ALERT#

GPP_H14/SML3DATA

GPP_H13/SML3CLK

GPP_H12/SML2ALERT#

GPP_H11/SML2DATA

GPP_H10/SML2CLK

1 OF 12

PLT_RST_BUF# <32,34,37>

+3VALW_SPI

CH17 .1U_0402_16V7K

1 2

INTRUDER#

BB27
P43

R39
R36
R42
R41

AF41
AE44
BC23
BD24

BC36
BE34
BD39
BB36
BA35
BC35
BD35
AW35
BD34

BE11

?

PLT_RST#

I2C_TS_INT#
TP_INT#

DH1
RB751V-40_SOD323-2

for server and WS use

@

PAD

SM_INTRUDER#

M.2 SSD PCIE L2

M.2 SSD PCIE L3

PLT_RST# <23,39,41>

I2C_TS_INT# <30>

12

T13

RH12 1M_0402_5%

1 2

EC_TP_INT# <39,41>

+RTCVCC

PCIE_PTX_DRX_P11<34>
PCIE_PTX_DRX_N11<34>

PCIE_PRX_DTX_P11<34>
PCIE_PRX_DTX_N11<34>

PCIE_PTX_DRX_P12<34>
PCIE_PTX_DRX_N12<34>
PCIE_PRX_DTX_P12<34>
PCIE_PRX_DTX_N12<34>

DVT modify

Follow MOW 2015WW09

PCH_SPI_IO2

PCH_SPI_IO3

Follow MOW WW36
pull down with pre-ES1/ES1 samples

DVT modify

PCIE_PTX_DRX_P11
PCIE_PTX_DRX_N11
PCIE_PRX_DTX_P11
PCIE_PRX_DTX_N11

DGPU_PRSNT#

PCIE_PTX_DRX_P12
PCIE_PTX_DRX_N12
PCIE_PRX_DTX_P12
PCIE_PRX_DTX_N12

RH36 1K_0402_1%@

1 2

RH40 1K_0402_1%@

1 2

UH1C

AV2

CL_CLK

AV3

CL_DATA

AW2

CL_RST#

R44

GPP_G8/FAN_PWM_0

R43

GPP_G9/FAN_PWM_1

U39

GPP_G10/FAN_PWM_2

N42

GPP_G11/FAN_PWM_3

U43

GPP_G0/FAN_TACH_0

U42

GPP_G1/FAN_TACH_1

U41

GPP_G2/FAN_TACH_2

M44

GPP_G3/FAN_TACH_3

U36

GPP_G4/FAN_TACH_4

P44

GPP_G5/FAN_TACH_5

T45

GPP_G6/FAN_TACH_6

T44

GPP_G7/FAN_TACH_7

B33

PCIE11_TXP

C33

PCIE11_TXN

K31

PCIE11_RXP

L31

PCIE11_RXN

AB33

GPP_F10/SCLOCK

AB35

GPP_F11/SLOAD

AA44

GPP_F13/SDATAOUT0

AA45

GPP_F12/SDATAOUT1

B38

PCIE14_TXN/SATA1B_TXN

C38

PCIE14_TXP/SATA1B_TXP

D39

PCIE14_RXN/SATA1B_RXN

E37

PCIE14_RXP/SATA1B_RXP

C36

PCIE13_TXN/SATA0B_TXN

B36

PCIE13_TXP/SATA0B_TXP

G35

PCIE13_RXN/SATA0B_RXN

E35

PCIE13_RXP/SATA0B_RXP

A35

PCIE12_TXP

B35

PCIE12_TXN

H33

PCIE12_RXP

G33

PCIE12_RXN

J45

PCIE20_TXP/SATA7_TXP

K44

PCIE20_TXN/SATA7_TXN

N38

PCIE20_RXP/SATA7_RXP

N39

PCIE20_RXN/SATA7_RXN

H44

PCIE19_TXP/SATA6_TXP

H43

PCIE19_TXN/SATA6_TXN

L39

PCIE19_RXP/SATA6_RXP

L37

PCIE19_RXN/SATA6_RXN

SKL-H-PCH_BGA837

@

+3VALW_SPI

REV = 1.3

SPT-H_PCH

CLINK

FAN

HOST

3 OF 12

?

DGPU_PRSNT#

DIS,Optimus10

UMA

PCIE9_RXN/SATA0A_RXN
PCIE9_RXP/SATA0A_RXP
PCIE9_TXN/SATA0A_TXN

PCIE9_TXP/SATA0A_TXP

PCIE10_RXN/SATA1A_RXN
PCIE10_RXP/SATA1A_RXP

PCIE10_TXN/SATA1A_TXN
PCIE10_TXP/SATA1A_TXP

PCIE15_RXN/SATA2_RXN
PCIE15_RXP/SATA2_RXP

PCIE15_TXN/SATA2_TXN
PCIE15_TXP/SATA2_TXP

PCIe/SATA

PCIE16_RXN/SATA3_RXN
PCIE16_RXP/SATA3_RXP

PCIE16_TXN/SATA3_TXN
PCIE16_TXP/SATA3_TXP

PCIE17_RXN/SATA4_RXN
PCIE17_RXP/SATA4_RXP

PCIE17_TXN/SATA4_TXN
PCIE17_TXP/SATA4_TXP

PCIE18_RXN/SATA5_RXN
PCIE18_RXP/SATA5_RXP

PCIE18_TXN/SATA5_TXN
PCIE18_TXP/SATA5_TXP

GPP_E8/SATALED#
GPP_E0/SATAXPCIE0/SATAGP0
GPP_E1/SATAXPCIE1/SATAGP1
GPP_E2/SATAXPCIE2/SATAGP2
GPP_F0/SATAXPCIE3/SATAGP3
GPP_F1/SATAXPCIE4/SATAGP4
GPP_F2/SATAXPCIE5/SATAGP5
GPP_F3/SATAXPCIE6/SATAGP6
GPP_F4/SATAXPCIE7/SATAGP7

GPP_F21/EDP_BKLTCTL

GPP_F20/EDP_BKLTEN

GPP_F19/EDP_VDDEN

THERMTRIP#

PLTRST_PROC#

+3VALW_PCH_PRIM

12

RH42

UMA@

10K_0402_5%

12

RH43

VGA@

10K_0402_5%

GPP_F13

DGPU_PRSNT#

PECI

PM_SYNC

PM_DOWN

PCIE_PRX_DTX_N9

G31

PCIE_PRX_DTX_P9

H31

PCIE_PTX_DRX_N9

C31

PCIE_PTX_DRX_P9

B31

PCIE_PRX_DTX_N10

G29

PCIE_PRX_DTX_P10

E29

PCIE_PTX_DRX_N10

C32

PCIE_PTX_DRX_P10

B32

SATA_PRX_DTX_N2

F41

SATA_PRX_DTX_P2

E41

SATA_PTX_DRX_N2

B39

SATA_PTX_DRX_P2

A39
D43

E42
A41
A40

H42
H40
E45
F45

K37
G37
G45

RH109

G44

10K_0402_5%

SATA_LED#

AD44
AG36
AG35
AG39
AD35
AD31
AD38
AC43
AB44

FOR SERVER & WS ONLY

PCH_BKL_PWM

W36
W35

ENBKL
PCH_ENVDD

W42

PCH_THERMTRIP#

AJ3

PCH_PECI

AL3

H_PM_SYNC_R

AJ4

PLTRST_CPU#

AK2
AH2

PCH_BKL_PWM
ENBKL

PCH_PECI

M.2 SSD PCIE L0

M.2 SSD PCIE L1

SATA_PRX_DTX_N2 <38>
SATA_PRX_DTX_P2 <38>

SATA_PTX_DRX_N2 <38>
SATA_PTX_DRX_P2 <38>

+3VS

1 2

1 2

@

1 2
1 2

@

RH19 10K_0402_5%
RH20 10K_0402_5%

@

1 2
1 2

RH21 10K_0402_5%

@

1 2

@

RH22 10K_0402_5%
RH24 10K_0402_5%

RH25 620_0402_5%
RH26 12.1_0402_1%@
RH27 30_0402_1%

RH31 100K_0402_5%
RH32 100K_0402_5%
RH33 10K_0402_5%@

RH34 10K_0402_5%

RH16
10K_0402_5%

SATA_GP0

PCH_BKL_PWM <30>
ENBKL <39>
PCH_ENVDD <30>

1 2
1 2

PLTRST_CPU# <9>

PM_DOWN_R <9>

1 2
1 2
1 2

@

1 2

SATA_LED#

12

PCIE_PRX_DTX_N9 <34>
PCIE_PRX_DTX_P9 <34>

PCIE_PTX_DRX_N9 <34>
PCIE_PTX_DRX_P9 <34>

PCIE_PRX_DTX_N10 <34>
PCIE_PRX_DTX_P10 <34>

PCIE_PTX_DRX_N10 <34>
PCIE_PTX_DRX_P10 <34>

SATA_LED# <33>

M.2 SSD PCIE/SATA select pin

SATA_GP0 <34>

THERMTRIP# <9>
H_PECI <9,39>
H_PM_SYNC <9>

+1.0VALW_PRIM

Functional Strap Definitions

SPI0_MOSI
int. PH
This strap should sample HIGH. There should NOT be any
on-board device driving it to opposite direction during
strap sampling.

SPI0_MISO
int. PH
This strap should sample HIGH. There should NOT be any
on-board device driving it to opposite direction during
strap sampling.

SPI0_IO2
int. PH
This strap should sample HIGH. There should NOT be any
on-board device driving it to opposite direction during
strap sampling.

SPI0_IO3
int. PH
This strap should sample HIGH. There should NOT be any
on-board device driving it to opposite direction during
strap sampling.

GPP_H12
int. PD
This strap should sample LOW.

HDD

UH1A

@

PCH_SPI_SI
PCH_SPI_SO
PCH_SPI_CS#0
PCH_SPI_CLK

PCH_SPI_IO2
PCH_SPI_IO3

TP_INT#

I2C_TS_INT#

EC_PME#_R

BD17
AG15

AG14
AF17
AE17

AR19
AN17

BB29
BE30
BD31
BC31

AW31

BC29
BD30
AT31

AN36

AL39
AN41
AN38
AH43
AG44

GPP_A11/PME#
RSVD

RSVD
RSVD
RSVD

TP2
TP1

SPI0_MOSI
SPI0_MISO
SPI0_CS0#
SPI0_CLK
SPI0_CS1#
SPI0_IO2
SPI0_IO3
SPI0_CS2#

GPP_D1/SPI1_CLK
GPP_D0/SPI1_CS#
GPP_D3/SPI1_MOSI
GPP_D2/SPI1_MISO
GPP_D22/SPI1_IO3
GPP_D21/SPI1_IO2

SKL-H-PCH_BGA837

@

EC_PME#<32,39>

1 1

1 2

RH10 0_0402_5%

SPI ROM

+3VS

1 2

RH13 100K_0402_5%

1 2

RH15 100K_0402_5%

2 2

PCH PLTRST Buf f er

+3VS

CH16

.1U_0402_16V7K

1 2

5

PLT_RST#

MC74VHC1G08DFT2G_SC70-5

Single SPI ROM_CS0#

3 3

4 4

To SPI ROM

UH2

1

P

IN1

4

O

2

IN2

G

3

PCH_SPI_CS#0

PCH_SPI_SI_0_R
PCH_SPI_SO_0_R
PCH_SPI_IO3_0_R
PCH_SPI_CLK_0_R

SPI ROM ( 8MByte )

PCH_SPI_CS#0

PCH_SPI_IO2_0_R

ROM Socket

PCH_SPI_CLK_0_R

PCH_SPI_CS#0
PCH_SPI_IO2_0_R
PCH_SPI_IO3_0_R

1
2
3
4

PLT_RST_BUF#

12

1 2

RH35 4.7K_0402_5%

RPH3 and close UH6

1 8
2 7
3 6
4 5

1 2

RH38 15_0402_5%

UH3

/CS
DO(IO1)
/WP(IO2)
GND

W25Q64FVSSIQ_SO8

1
3
7
4

VCC

/HOLD(IO3)

CLK

DI(IO0)

@

1 2

RH44
0_0402_5%

JH1

CS#

VCC

WP#

SCLK

HOLD#

SI/SIO0

SO/SIO1

GND

ACES_91960-0084N_MX25L3206EM2I

CONN@

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

A

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

C

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(2/7)SPI,SATA,XDP

PCH(2/7)SPI,SATA,XDP

PCH(2/7)SPI,SATA,XDP

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

E

17 61Friday, October 28, 2016

17 61Friday, October 28, 2016

17 61Friday, October 28, 2016

1.0

1.0

1.0

A

B

C

D

E

HDA for AUDIO

ME_EN<39>

HDA_SDOUT_R<40>
HDA_RST_AUDIO#<40>
HDA_SYNC_R<40>
HDA_BIT_CLK_R<40>

+3VALW_PCH_PRIM

+3VALW_DSW

HDA_SDIN0<40>

RPH7

10K_0804_8P4R_5%

1 1

Follow 543016_SKL_U_Y_PDG_0_9

+3VALW_DSW

EC_RSMRST#

2 2

+RTCVCC

CRB 8.2K

1 2

RH49 10K_0402_5%

@

1 2

RH50 10K_0402_5%

1 2

RH51 1K_0402_5%

PCH_DPWROK

@

12

RH54 0_0402_5%

RH57 0_0402_5%

JCMOS1 0_0603_5%@
JCMOS2 0_0603_5%@

PCH_PWROKSYS_PWROK

12

@

1 2

RH60 20K_0402_5%

1 2

CH21 1U_0402_6.3V6K

1 2

RH63 20K_0402_5%

1 2

CH23 1U_0402_6.3V6K

1 2
1 2

Place at RAM DOOR

3 3

Functional Strap Definitions

SMBALERT# / GPP_C2
int. PD
0 = Disable Intel ME (TLS) (Default)
1 = Enable Intel ME (TLS)

SML0ALERT# / GPP_C5
int. PD
0 = LPC Is selected for EC. (Default)
1 = eSPI Is selected for EC.

SML1ALERT# / PCHHOT# / GPP_B23
int. PD

SPKR / GPP_B14
int. PD
0 = Disable “ Top Swap” mode. ( Def ault )
1 = Enable “ Top S wap” mode.

HDA_SDO

4 4

int. PD
0 = Enable security measures defined in the Flash
Descriptor. (Default)
1 = Disable Flash Descriptor Security (override).

DDPB_CTRLDATA / GPP_I6
int. PD
0 = Port B is not detected.
1 = Port B is detected. (Default)

A

1 2

RH47 0_0402_5%

RPH6

1 8
2 7
3 6
4 5

33_0804_8P4R_5%

SYS_RESET#

18

PCH_PWROK

27

EC_RSMRST#

36

LAN_WAKE#

45

PM_BATLOW#
AC_PRESENT_R

WAKE#

@

HDA_SDIN0

PCH_SRTCRST#

Remove CLR ME

PCH_RTCRST#

CLR CMOS

HDA_SDOUT
HDA_RST#
HDA_SYNC
HDA_BIT_CLK

HDM I

.1U_0402_16V7K

0.047U_0402_16V7K

1

2

CH62

CH64

2

1

XEMC@

XEMC@

WAKE# (DSX wake event)
10 KΩ pull- up t o Vcc DS W3_3
The pull-up is required even if PCIe* interface
is not used on the plat f or m.

CPU_DISPA_SDO<6>

CPU_DISPA_SDI_R<6>

CPU_DISPA_BCLK<6>

PCH_DMIC_DATA0<40>
PCH_DMIC_CLK0<40>

(SO-DIMM,G-sensor)

+3VALW_PCH_PRIM

+3VALW_PCH_PRIM

DDPC_CTRLDATA / GPP_I8
int. PD
0 = Port C is not detected.
1 = Port C is detected. (Default)

DDPD_CTRLDATA / GPP_I10
int. PD
0 = Port D is not detected. (Default)
1 = Port D is detected.

1 2

RH64 4.7K_0402_5%

1 2

RH65 499_0402_1%

1 2

RH66 499_0402_1%

T14

T23

T24

T25

PAD@

close to PCH

1 2

30_0402_1%

1 2

30_0402_1%

PCH_DMIC_DATA0
PCH_DMIC_CLK0

@

PAD

@

PAD

@

PAD

PCH_DP2_HPD
EC_SCI#_I3

PCH_EDP_HPD

CPU_DISPA_SDO_R
CPU_DISPA_SDI_R
CPU_DISPA_BCLK_R

PCH_DP2_HPD<31>

PCH_EDP_HPD<30>

RH56
RH58

PCH_PWROK<39,43>
EC_RSMRST#<39>

(VGA, EC, RTD2168)

PCH_SMBALERT#

PCH_SML0CLK
PCH_SML0DATA

B

HDA_BIT_CLK
HDA_RST#
HDA_SDIN0

HDA_SDOUT
HDA_SYNC

PCH_RTCRST#
PCH_SRTCRST#

PCH_PWROK
EC_RSMRST#

PCH_DPWROK
PCH_SMBALERT#
PCH_SMBCLK
PCH_SMBDATA
PCH_SML0ALERT#
PCH_SML0CLK
PCH_SML0DATA
PCH_SML1ALERT#
PCH_SML1CLK
PCH_SML1DATA

UH1E

AW4

GPP_I0/DDPB_HPD0

AY2

GPP_I1/DDPC_HPD1

AV4

GPP_I2/DDPD_HPD2

BA4

GPP_I3/DDPE_HPD3

BD7

GPP_I4/EDP_HPD

SKL-H-PCH_BGA837

REV = 1.3

@

UH1D

BA9

HDA_BCLK

BD8

HDA_RST#

BE7

HDA_SDI0

BC8

HDA_SDI1

BB7

HDA_SDO

BD9

HDA_SYNC

BD1

RSVD_BD1

BE2

RSVD_BE2

AM1

DISPA_SDO

AN2

DISPA_SDI

AM2

DISPA_BCLK

AL42

GPP_D8/I2S0_SCLK

AN42

GPP_D7/I2S0_RXD

AM43

GPP_D6/I2S0_TXD

AJ33

GPP_D5/I2S0_SFRM

AH44

GPP_D20/DMIC_DATA0

AJ35

GPP_D19/DMIC_CLK0

AJ38

GPP_D18/DMIC_DATA1

AJ42

GPP_D17/DMIC_CLK1

BC10

RTCRST#

BB10

SRTCRST#

AW11

PCH_PWROK

BA11

RSMRST#

AV11

DSW_PWROK

BB41

GPP_C2/SMBALERT#

AW44

GPP_C0/SMBCLK

BB43

GPP_C1/SMBDATA

BA40

GPP_C5/SML0ALERT#

AY44

GPP_C3/SML0CLK

BB39

GPP_C4/SML0DATA

AT27

GPP_B23/SML1ALERT#/PCHHOT#

AW42

GPP_C6/SML1CLK

AW45

GPP_C7/SML1DATA

SKL-H-PCH_BGA837

REV = 1.3

@

+3VALW_PCH_PRIM

+3VALW_PCH_PRIM

+3VS

SPT-H_PCH

AUDIO

+3VS

2.2K_0804_8P4R_5%

2.2K_0804_8P4R_5%

PDG_0_71 requirement PH to +3V_PCH
10/14 Dan

GPP_I7/DDPC_CTRLCLK

GPP_I8/DDPC_CTRLDATA

GPP_I5/DDPB_CTRLCLK

GPP_I6/DDPB_CTRLDATA

GPP_I9/DDPD_CTRLCLK

GPP_I10/DDPD_CTRLDATA

5 OF 12

SPT-H_PCH

SMBUS

RPH8

18
27
36
45

RPH9

18
27
36
45

GPP_F14
GPP_F23

GPP_F22
GPP_G23
GPP_G22
GPP_G21
GPP_G20
GPP_H23

GPP_A12/BMBUSY#/ISH_GP6/SX_EXIT_HOLDOFF#

GPP_A13/SUSWARN#/SUSPWRDNACK

JTAG

4 OF 12

EC_SMB_DA2
EC_SMB_CK2
PCH_SML1CLK
PCH_SML1DATA

PCH_SMBDATA
PCH_SMBCLK
D_CK_SCLK
D_CK_SDATA

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

C

PCH_DP2_CTRL_CLK

BB3

PCH_DP2_CTRL_DATA

BD6
BA5
BC4
BE5
BE6

Y44
V44
W39
L43
L44
U35
R35
BD36

?

GPP_A8/CLKRUN#
GPD11/LANPHYPC
GPD9/SLP_WLAN#

DRAM_RESET#

GPP_B2/VRALERT#

GPP_G17/ADR_COMPLETE

GPP_B11

SYS_PWROK

GPD6/SLP_A#

SLP_LAN#

GPP_B12/SLP_S0#

GPD4/SLP_S3#
GPD5/SLP_S4#

GPD10/SLP_S5#

GPD8/SUSCLK

GPD0/BATLOW#

GPP_A15/SUSACK#

GPD2/LAN_WAKE#
GPD1/ACPRESENT

SLP_SUS#

GPD3/PWRBTN#

SYS_RESET#

GPP_B14/SPKR

PROCPWRGD

ITP_PMODE

JTAG_TMS
JTAG_TDO

JTAG_TDI

JTAG_TCK

PCH_DP2_CTRL_CLK <31>
PCH_DP2_CTRL_DATA <31>

H_SKTOCC# <9>

BB17

PM_CLKRUN#

AW22
AR15

SLP_WLAN#

AV13

DDR_DRAMRST#

BC14

PCH_VRALERT#

BD23

CC_CHG_HI#

AL27

GPP_B1
GPP_B0

WAKE#

JTAGX

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

LAN_GPO

AR27
N44
AN24

SYS_PWROK

AY1
BC13

WAKE#
PM_SLP_A#

BC15

SLP_LAN#

AV15
BC26

PM_SLP_S3#

AW15

PM_SLP_S4#

BD15

PM_SLP_S5#

BA13
AN15

SUSCLK
PM_BATLOW#

BD13
BB19
BD19

BD11
BB15
BB13
AT13
AW1
BD26
AM3

AT2
AR3
AR2
AP1
AP2
AN3

?

1 2

RH62 0_0402_5%

LAN_WAKE#
AC_PRESENT_R
PM_SLP_SUS#
PBTN_OUT#_R
SYS_RESET#
PCH_SPKR

H_CPUPWRGD

XDP_ITP_PMODE
CPU_XDP_TCK0
CPU_XDP_TMS
CPU_XDP_TDO
CPU_XDP_TDI
PCH_JTAG_TCK1

DMN66D0LDW-7_SOT363-6

PCH_SMBCLK

DMN66D0LDW-7_SOT363-6

PCH_SMBDATA

DMN66D0LDW-7_SOT363-6

PCH_SML1CLK

PCH_SML1DATA

Compal Secret Data

Compal Secret Data

Compal Secret Data

@

DMN66D0LDW-7_SOT363-6

Deciphered Date

Deciphered Date

Deciphered Date

HDM I

PM_CLKRUN# <41>

T15

@

PAD

DDR_DRAMRST# <14>
CC_CHG_HI# <35>

LAN_GPO <32>

SYS_PWROK <39,43>

T16

@

PAD

T17

@

PAD

PM_SLP_S3# <39,43>
PM_SLP_S4# <39,43>

T19

@

PAD

SUSCLK <34,37>

PAD

T22

@

PAD

PCH_SPKR <40>

H_CPUPWRGD <9>

T204

@

PAD

CPU_XDP_TCK0 <6,9>
CPU_XDP_TMS <6,9>
CPU_XDP_TDO <6,9>
CPU_XDP_TDI <6,9>
PCH_JTAG_TCK1 <6>

+3VS

QH1A

2

6 1

QH1B

3 4

QH2A

6 1

QH2B

3 4

D

T21

@

SUSPWRDNACK <39>

5

+3VS

2

5

D_CK_SCLK

D_CK_SDATA

EC_SMB_CK2

EC_SMB_DA2

+3VS

PM_CLKRUN#

PCH_VRALERT#

PBTN_OUT#_R

PBTN_OUT#_R

AC_PRESENT_R

PM_SLP_S3#

PM_SLP_S4#

SYS_PWROK

SYS_RESET#

D_CK_SCLK <14,15,38>

RH48 10K_0402_5%

RH52 10K_0402_5%

RH53 100K_0402_5%

RH55 0_0402_5%

RH59 0_0402_5%

RH61 10K_0402_5%

CH61 .1U_0402_16V7K

CH22
.1U_0402_16V7K

XEMC@

1 2

@

1 2

@

@

1 2

1 2

1 2

XEMC@

1 2

12

12

PAD

PAD

CRB 8.2K

+3VALW_PCH_PRIM

T18

@

T20

@

+3VALW_DSW

PBTN_OUT# <39>

AC_PRESENT <39>

(DDR,G-Sensor)

D_CK_SDATA <14,15,38>

EC_SMB_CK2 <23,39>

(EC, VGA)

EC_SMB_DA2 <23,39>

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(3/7)GPIO,SMBUS

PCH(3/7)GPIO,SMBUS

PCH(3/7)GPIO,SMBUS

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

Date: Sheet of

Date: Sheet of

Date: Sheet of

E

18 61Friday, October 28, 2016

18 61Friday, October 28, 2016

18 61Friday, October 28, 2016

1.0

1.0

1.0

A

B

C

D

E

1 1

2 2

+3VS

RPH10

18
27
36
45

10K_0804_8P4R_5%

RPH11

18
27
36
45

10K_0804_8P4R_5%

RPH12

18
27
36
45

10K_0804_8P4R_5%

RPH13

18
27
36
45

10K_0804_8P4R_5%

Follow PDG 0.71Table 52-17
10/13 Dan
CHECK NEEDED IF UNUSE?

VGA_CLKREQ#<23>

LAN_CLKREQ#
CLKREQ_PCIE#3
CLKREQ_PCIE#5
NGFF_CLKREQ#

CLKREQ_PCIE#12
CLKREQ_PCIE#7
CLKREQ_PCIE#10
WLAN_CLKREQ#

CLKREQ_PCIE#9
CLKREQ_PCIE#8
CLKREQ_PCIE#6
CLKREQ_PCIE#13

CLKREQ_PCIE#14
CLKREQ_PCIE#11
CLKREQ_PCIE#15

+3VS

12

RH68
10K_0402_5%

VGA_CLKREQ#

+1.0VALW_VCCCLK5

CPU_24M<9>
CPU_24M#<9>

CPU_BCLK<9>
CPU_BCLK#<9>

FOLLOW RVP11

PH at DGPU side

XTAL24_OUT
XTAL24_IN

LAN_CLKREQ#<32>
WLAN_CLKREQ#<37>

NGFF_CLKREQ#<34>

RH67

2.7K_0402_1%

12

XCLK_BIASREF

RTCX1
RTCX2

VGA_CLKREQ#
LAN_CLKREQ#
WLAN_CLKREQ#
CLKREQ_PCIE#3
NGFF_CLKREQ#
CLKREQ_PCIE#5
CLKREQ_PCIE#6
CLKREQ_PCIE#7
CLKREQ_PCIE#8
CLKREQ_PCIE#9
CLKREQ_PCIE#10
CLKREQ_PCIE#11
CLKREQ_PCIE#12
CLKREQ_PCIE#13
CLKREQ_PCIE#14
CLKREQ_PCIE#15

UH1G

AR17

GPP_A16/CLKOUT_48

G1

CLKOUT_CPUNSSC_P

F1

CLKOUT_CPUNSSC_N

G2

CLKOUT_CPUBCLK_P

H2

CLKOUT_CPUBCLK_N

A5

XTAL24_OUT

A6

XTAL24_IN

E1

XCLK_BIASREF

BC9

RTCX1

BD10

RTCX2

BC24

GPP_B5/SRCCLKREQ0#

AW24

GPP_B6/SRCCLKREQ1#

AT24

GPP_B7/SRCCLKREQ2#

BD25

GPP_B8/SRCCLKREQ3#

BB24

GPP_B9/SRCCLKREQ4#

BE25

GPP_B10/SRCCLKREQ5#

AT33

GPP_H0/SRCCLKREQ6#

AR31

GPP_H1/SRCCLKREQ7#

BD32

GPP_H2/SRCCLKREQ8#

BC32

GPP_H3/SRCCLKREQ9#

BB31

GPP_H4/SRCCLKREQ10#

BC33

GPP_H5/SRCCLKREQ11#

BA33

GPP_H6/SRCCLKREQ12#

AW33

GPP_H7/SRCCLKREQ13#

BB33

GPP_H8/SRCCLKREQ14#

BD33

GPP_H9/SRCCLKREQ15#

R13

CLKOUT_PCIE_N15

R11

CLKOUT_PCIE_P15

P1

CLKOUT_PCIE_N14

R2

CLKOUT_PCIE_P14

W7

CLKOUT_PCIE_N13

Y5

CLKOUT_PCIE_P13

U2

CLKOUT_PCIE_N12

U3

CLKOUT_PCIE_P12

SKL-H-PCH_BGA837

@

REV = 1.3

SPT-H_PCH

CLKOUT_CPUPCIBCLK_N
CLKOUT_CPUPCIBCLK_P

7 OF 12

CLKOUT_ITPXDP_N
CLKOUT_ITPXDP_P

CLKOUT_PCIE_N0
CLKOUT_PCIE_P0

CLKOUT_PCIE_N1
CLKOUT_PCIE_P1

CLKOUT_PCIE_N2
CLKOUT_PCIE_P2

CLKOUT_PCIE_N3
CLKOUT_PCIE_P3

CLKOUT_PCIE_N4
CLKOUT_PCIE_P4

CLKOUT_PCIE_N5
CLKOUT_PCIE_P5

CLKOUT_PCIE_N6
CLKOUT_PCIE_P6

CLKOUT_PCIE_N7
CLKOUT_PCIE_P7

CLKOUT_PCIE_N8
CLKOUT_PCIE_P8

CLKOUT_PCIE_N9
CLKOUT_PCIE_P9

CLKOUT_PCIE_N10
CLKOUT_PCIE_P10

CLKOUT_PCIE_N11
CLKOUT_PCIE_P11

CLK_CPU_ITP#

L1

CLK_CPU_ITP

L2

CPU_PCIBCLK#

J1

CPU_PCIBCLK

J2

CLK_PEG_VGA#

N7

CLK_PEG_VGA

N8

CLK_PCIE_LAN#

L7

CLK_PCIE_LAN

L5

CLK_PCIE_WLAN#

D3

CLK_PCIE_WLAN

F2
E5

G4

CLK_PCIE_NGFF#

D5

CLK_PCIE_NGFF

E6
D8

D7
R8

R7
U5

U7
W10

W11
N3

N2
P3

P2
R3

R4

?

PAD

T26

@

PAD

T27

@

CPU_PCIBCLK# <9>
CPU_PCIBCLK <9>

CLK_PEG_VGA# <23>

CLK_PEG_VGA <23>

CLK_PCIE_LAN# <32>
CLK_PCIE_LAN <32>

CLK_PCIE_WLAN# <37>
CLK_PCIE_WLAN <37>

CLK_PCIE_NGFF# <34>
CLK_PCIE_NGFF <34>

DGPU

GLAN

NGFF WL+BT(KEY E)

M2 SSD

3 3

RTCX1

1 2

RH71 10M_0402_5%

1 2

32.768KHZ_9PF_CM7V-T1A9.0PF20PPM
8

.2P_0402_50V8D

1

C
H26

2

DVT modify

4 4

RTCX2

YH1

8.2P_0402_50V8D

1

CH27

2

A

XTAL24_OUT

1 2

RH72 1M_0402_5%

YH2
24MHZ_12PF_7V24000020

3

15P_0402_50V8J

3

GND

CH24

4

GND

XTAL24_IN

1

15P_0402_50V8J

1

2

CH25

Security Classification

Security Classification

Security Classification

Issued Date

Issued Date

Issued Date

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL

THIS SHEET OF ENGINEERING DRAWING I S THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D

AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED F ROM THE CUSTODY OF THE COMPETENT DI VISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

B

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN C ONSENT OF COMPAL ELECTRONICS, INC.

C

2016/01/29 2017/01/10

2016/01/29 2017/01/10

2016/01/29 2017/01/10

Compal Secret Data

Compal Secret Data

Compal Secret Data

Deciphered Date

Deciphered Date

Deciphered Date

Compal Electronics, Inc.

Compal Electronics, Inc.

Compal Electronics, Inc.

Title

Title

Title

PCH(4/7)CLK

PCH(4/7)CLK

PCH(4/7)CLK

Size Document Number R ev

Size Document Number R ev

Size Document Number R ev

Custom

Custom

Custom

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

C5PM2 M/B LA-E361P

Date: Sheet of

Date: Sheet of

D

Date: Sheet of

E

19 61Friday, October 28, 2016

19 61Friday, October 28, 2016

19 61Friday, October 28, 2016

1.0

1.0

1.0