Page 1
1
V/+5V S5
+3
PG.39
+1
A A
.05V/+1.5V
PG.40/45
CP
U Core
PG.42~
43
DDR4
PG.41
Cha
rge
PG.38
VGA POWER
47
PG.46~
B B
VC
CGT/VCCSA
PG.44
2
IN
SOD
IMM1
Max. 16GB
STD
SOD
STD
HDD
PG.17
IMM2
Max. 16GB
PG.18
PG.33
3
4
TEL SYSTEM DIAGRAM
PEG
2400MT/s
L
DDR4
Channel A
2400MT/s
DDR4
L
Channel B
SATA2 6GB/s
INTEL
Sky
Lake-H
Processor : Daul / Quad Core
Power : 45 (Watt)
Package : BGA1400
Size : 42 x 28 (mm)
PG.2~8
I
DM
eDP (5.4Gb/s)
DDI
DDI
eD
2
1
5
U
GP
6P-GT
N1
P1
9~P23
P
eD
P Conn.
IT
E6515
PS8
407
P28
P30
TAL 27MHz
X'
P29
6
VR
AM
DDR3
A Conn.
VG
DMI Conn.
H
P24~P27
P29
P3
7
8
01
0
INTEL PCH
US
nx Point
Ly
PCI-E x 1
Port4
LA
N
RTL8111GSH
10/
100/1000
Port3
WLA
COMBO
BT
N
B 2.0
US
PORT7
PG.34PG.31
PCI-E x 4
C C
PG.34
PG.37
FA
SATA0~1 6GB/s
LPC
NROM
G- Sensor
FF SSD
NG
KBC
E IT8987E/BX
IT
LPC Interface
TPM
PAGE 33 NPCT650
SLG3NB3454
L
D D
GreenCLK
25MHz
TPKB
PG.35PG.35 PG.35PG.12
PAGE 33
Power : Watt
Package : FCBGA837
Size : 23 x 23 (mm)
PG.9~
DIO
AU
CO
DEC
AL
P3
5
C255
Speaker
15
PAGE 32
Az
alia
US
PG.32
Dual Digital MIC
B 3.0
PORT1,2
US
PAGE 32
B3-1 & USB3-2
B 2.0
US
B3.0 Ports
Un
X2
PG.36
PORT1,2
iversal HP
We
bcam
PG.29
PORT9
PORT5
DB IO Port
PG.36
P3
2
Ca
rd Reader
To
uch Screen
PG.36
PORT10
PORT8
PG.29
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
1
2
3
4
5
6
7
OCK DIAGRAM
OCK DIAGRAM
OCK DIAGRAM
BL
BL
BL
Date: Sheet of
Date: Sheet of
Date: Sheet of
8
1A
1A
1A
149Monday, September 07, 2015
149Monday, September 07, 2015
149Monday, September 07, 2015
Page 2
5
4
3
2
1
Host CLK:
Trace length < 11000 MILS
Trace spacing = 15 ,20 MILS, Impendence 90 ohm
K_CPU_BCLKP11
CL
K_CPU_BCLKN11
CL
U_PCI_BCLKP11
D D
H_
PECI (50ohm)
Route on micro strip only
Spacing > 18 mils
Trace Length: 15 inch
CP
U RESET#
C C
HPECI Ra,Ca n eed placement close to EC.
H_PECI11
PC
_PECI37
EC
U_PLTRST#R11
CP
TRST#12,16,19,31,33,34,37
PL
CP
U_PLTRST# (50o hm)
Trace Length: 10~17 inches
R563 13/F_4
02 *47P/50V_4
C8
PROCHOT# (50ohm)
Trace Length <11 inches
THERMTRIP# (50ohm)
Trace Length: 1.1~12 inches
Ra
Ca
PROCHOT#37,38,42
H_
Ch
ange net name_20141203
PM
_SYNC (50ohm)
Trace Length: 1~11.25 inches
R5
41 *1.5K/F_4
R5
42 *750/F_4
_THRMTRIP#5,11,17,18
PM
+V
CCSTPLL
R6
26 1K_4
Rb need placment near PCH
_PECI
EC
07
C8
Cb
47P/50V_4
_THRMTRIP#
PM
Rb
+V
CP
U_PCI_BCLKN11
CP
CL
K_DPLL_NSCCLKP11
K_DPLL_NSCCLKN11
CL
R5
67 499/F_4
Cb need placment near VR
DDR_VTT_CNTL17
PROCPWRGD (50ohm)
Trace Length: 1~11.25 inches
CST_PWRGD16
VC
OCPWRGD10
PR
R553 *SHORT_4
CCSTPLL
+V
SKT
SKT
CCSTPLL
OCC_N_R13
H_
R5
PM
_SYNC11
OCC_N_R
R5
71 49.9/F_4
New CN to PCH pin Y44_20141203
R5
PM_DOWN11
H_
59 20_4
R14 need change to 20ohm
PD
HW
CPU CORE SVID
Layout note: need routing together and ALERT need between CLK and DATA.
B B
A A
OSE TO CPU
CL
PLACE THE PU RESISTORS
H_
CPU_SVIDALRT#
ACE THE PU RESISTORS
PL
CLOSE TO V R
PULL UP IS IN THE VR MODULE
_SVID_CLK_R
VR
OSE TO CPU
CL
PLACE THE PU RESISTORS
CPU_SVIDDAT
H_
R5
45 220/F_4
R540 *SHORT_4
5
CCSTPLL
+V
38
R5
56.2/F_4
55
C7
*0.1U/16V_4
CCSTPLL
+V
5
C8
R5
39
*54.9/F_4
*1000p/50V_4
CCSTPLL
+V
44
R5
100/F_4
SVI
SVI
43 *SHORT_4
R5
D ALERT
VR
_SVID_ALERT# 42
D CLK
SVI
_SVID_CLK 42
VR
D DATA
_SVID_DATA 42
VR
4
VC
CST_PWRGD
R1
17
C4
*0.1u/16V_4
CPU thermal trip
VP_PWR GD42
IM
SKYLAKE Processor (CLK,MISC,JTAG)
AKE_HALO
SKYL
U41E
BCLKP
LKN
BC
I_BCLKP
PC
PCI_BCLKN
CLK24P
CL
K24N
DALERT#
VI
DSCK
VI
DSOUT
VI
OCHOT#
PR
DDR_
VTT_CNTL
VC
CST_PWRGD
PR
OCPWRGD
RE
SET#
PM
_SYNC
_DOWN
PM
PEC
I
ERMTRIP#
TH
OCC#
SKT
PROC_SELECT#
CATERR#
SKL_H_BGA_BGA
CRB is via +1.05V PGVCCST PWRGD
5
20
4
+VCCSTPLL
12
41
3
BGA1440
5
OF 14
U2
1
VC
C
GN
Y
74AUP1G07GW
V
+3
R2
00
*10K_4
PR
PR
PR
PR
PR
OC_TRST#
OC_PREQ#
PR
PROC_PRDY#
G_RCOMP
CF
1
NC
2
A
3
D
VP_PWR GD_3V 10
IM
CFG[0]
G[1]
CF
CFG[2]
G[3]
CF
CFG[4]
CF
G[5]
CFG[6]
CF
G[7]
CFG[8]
CF
G[9]
G[10]
CF
CF
G[11]
G[12]
CF
CF
G[13]
G[14]
CF
G[15]
CF
G[17]
CF
G[16]
CF
G[19]
CF
CF
G[18]
BPM
BPM
BPM
BPM
OC_TDO
OC_TDI
OC_TMS
OC_TCK
#[0]
#[1]
#[2]
#[3]
H_
VR
_SVID_CLK_R
H_CPU_SVIDDAT
PROCHOT#_R
60 *10K_4
R5
80 *100K/F_4
R1
H_
PM_DOWN_R
CCSTPLL
+V
79 60.4/F_4
K_CPU_BCLKP
CL
K_CPU_BCLKN
CL
CP
U_PCI_BCLKP
U_PCI_BCLKN
CP
K_DPLL_NSCCLKP
CL
CL
K_DPLL_NSCCLKN
CPU_SVIDALRT#
VTT_CNTL
DDR_
CST_PWRGD
VC
OCPWRGD
PR
PM_DOWN_R
H_
EC
_PECI
56 *SHORT_4
81 *0_4
R1
CA
R1
78
*1K_4
Shortpad change
to 60.4 ohm. 11/6
U2
NC1VCC
2
A
GND3Y
*74AUP1G07GW
BH31
BH32
BH29
BR30
BT13
BT31
BP35
BM34
BP31
BT34
BR33
SKT
OCC_N
BM30
TERR#
.0V
+1
R2
03
1K_4
VC
2
82 *SHORT_4
R1
B31
A32
D35
C36
E31
D31
H13
J31
BN1
+3
V_S5
C4
0.1u/16V_4
CST_PWRGD_R
5
C4
*0.1u/16V_4
4
BN25
G0
CF
BN27
G1
CF
BN26
CF
G2
BN28
CF
G3
BR20
G4
CF
BM20
G5
CF
BT20
G6
CF
BP20
CF
G7
BR23
CF
G8
BR22
CF
G9
BT23
G10
CF
BT22
G11
CF
BM19
CF
G12
BR19
CFG13
BP19
CF
G14
BT19
G15
CF
BN23
CFG17
BP23
G16
CF
BP22
CF
G18
BN22
G19
CF
BR27
P_BPM0
XD
BT27
P_BPM1
XD
BM31
XD
P_BPM2
BT30
P_BPM3
XD
BT28
P_TDO_CPU
XD
BL32
XD
P_TDI_CPU
BP28
P_TMS_CPU
XD
BR28
P_TRST#_CPU
XD
BP30
P_TRST#
XD
BL30
XD
P_PREQ#
BP27
XD
P_PRDY#
BT25
G_RCOMP
CF
VC
CST_PWRGD_EN_L
IM
VP_PWR GD_3V
+V
PM
_THRMTRIP#
CCSTPLL
R1
*1K_4
+V
2
86
CF
G0 16
CF
G1 16
G2 8,16
CF
G3 8,16
CF
G4 8,16
CF
CF
G5 8,16
CF
G6 8,16
G7 16
CF
G8 16
CF
G9 16
CF
CF
G10 8,16
CF
G11 16
CF
G12 8,16
G13 8,16
CF
G14 16
CF
CF
G15 16
CF
G17 16
G16 16
CF
G18 16
CF
CFG19 16
TP
TP
XD
XD
XD
R300 *0_4
XD
XD
XD
R1
4
3
U5
TC7SH08FU
R9
69 *0_4
CCSTPLL
3
Q2
FDV301N
1
R191
1K_4
2
1 3
Q2
3 MMBT3904 -7-F
2
XD
P_BPM0 16
P_BPM1 16
XD
17
18
CP
U XDP
P_TDO_CPU 16
P_TDI_CPU 16
P_TMS_CPU 16
P_TRST# 15,16
P_PREQ# 15,16
P_PRDY# 15,16
2949.9/F_4
V_S5
+3
C8
12 0.1u/16V_4
2
1
3 5
0
R1
84
1 2
*100K_4
JT
AGX_PCH 10,16
SB#
SU
CST_PWRGD_EN
VC
No
SYS_SHDN# 39,45
02
ocessor pull-up (CPU)
Pr
PROCHOT#
H_
XD
P_TDO_CPU
P_TMS_CPU
XD
P_TDI_CPU
XD
P_PREQ#
XD
P_TRST#_CPU
XD
XD
P_TRST#
SB# 10,16,37,39
SU
CPU VDDQ
Del R2574_20141217
te: please keep plane is enough for VDDQ 2. 8A
66 1K_4
R5
R5
78 51_4
77 *51_4
R5
R5
58 *51_4
R5
72 *51_4
R5
79 *51_4
R5
64 51_4
A
B2
S0->S5 & S0->S3
Power of sequence 1us
SUSB# -> VCCST_PWRGD
R204 *0_4
R2
02 *SHORT_4
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Cu
Cu
Cu
stom
stom
stom
Date: Sheet
Date: Sheet
Date: Sheet
02 -- SKYPAKE 1/20(eDP/DDI)
02 -- SKYPAKE 1/20(eDP/DDI)
02 -- SKYPAKE 1/20(eDP/DDI)
PC
H_PWROK
HW
R2
10K_4
+1
.0V
+1
65 *SHORT_4
R5
R5
70 *0_4
PG
05
.2VSUS
03 0.1U/16V_4
C4
C4
02 *0.1U/16V_4
1
Pl
PC
HW
acement close to CPU.
+1
.0V
CCSTPLL
+V
H_PWROK 10,37
PG 10,37
1A
1A
1A
of
of
of
249Monday, September 07, 2015
249Monday, September 07, 2015
249Monday, September 07, 2015
Page 3
5
PEG_RX1519
_RX#1519
PEG
_RX1419
PEG
_RX#1419
PEG
PEG
_RX1319
_RX#1319
D D
Lane Reversed
C C
dGPU PEG*16
PEG
_RCOMP
Trace length < 400 MILS
Trace width = 12 MILS
Trace spacing = 15 MILS
DM
I
PEG
PEG
_RX1219
PEG
_RX#1219
PEG
_RX1119
PEG_RX#1119
_RX1019
PEG
_RX#1019
PEG
_RX919
PEG
PEG
_RX#919
PEG
_RX819
PEG
_RX#819
PEG_RX719
_RX#719
PEG
_RX619
PEG
_RX#619
PEG
PEG
_RX519
PEG
_RX#519
PEG
_RX419
PEG
_RX#419
_RX319
PEG
PEG_RX#319
_RX219
PEG
_RX#219
PEG
_RX119
PEG
PEG
_RX#119
PEG
_RX019
PEG_RX#019
CCIO
+V
DM
I_RXP09
DM
I_RXN09
DM
I_RXP19
DMI_RXN19
I_RXP29
DM
I_RXN29
DM
I_RXP39
DM
DM
I_RXN39
4
SKYLAKE Processor (DMI,PEG,FDI)
E25
D25
E24
F24
E23
D23
E22
F22
E21
D21
E20
F20
E19
D19
E18
F18
D17
E17
F16
E16
D15
E15
F14
E14
D13
E13
F12
E12
D11
E11
F10
E10
PEG
R1
94 24.9/F_4
_COMP
G2
D8
E8
E6
F6
D5
E5
J8
J9
PEG
PEG
PEG
PEG
PEG
PEG_RXN[2]
PEG_RXP[3]
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG_RXN[10]
PEG_RXP[11]
PEG
PEG
PEG
PEG
PEG
PEG_RXP[14]
PEG
PEG
PEG
PEG
DM
DMI_RXN[0]
DM
DM
DM
DM
DM
DM
SKYL
U41C
_RXP[0]
_RXN[0]
_RXP[1]
_RXN[1]
_RXP[2]
_RXN[3]
_RXP[4]
_RXN[4]
_RXP[5]
_RXN[5]
_RXP[6]
_RXN[6]
_RXP[7]
_RXN[7]
_RXP[8]
_RXN[8]
_RXP[9]
_RXN[9]
_RXP[10]
_RXN[11]
_RXP[12]
_RXN[12]
_RXP[13]
_RXN[13]
_RXN[14]
_RXP[15]
_RXN[15]
_RCOMP
I_RXP[0]
I_RXP[1]
I_RXN[1]
I_RXP[2]
I_RXN[2]
I_RXP[3]
I_RXN[3]
SKL_H_BGA_BGA
BGA1440
AKE_HALO
3
OF 14
_TXP[0]
PEG
_TXN[0]
PEG
_TXP[1]
PEG
PEG
_TXN[1]
PEG
_TXP[2]
PEG_TXN[2]
PEG_TXP[3]
_TXN[3]
PEG
_TXP[4]
PEG
_TXN[4]
PEG
PEG
_TXP[5]
PEG
_TXN[5]
PEG
_TXP[6]
PEG
_TXN[6]
_TXP[7]
PEG
_TXN[7]
PEG
_TXP[8]
PEG
_TXN[8]
PEG
PEG
_TXP[9]
PEG
_TXN[9]
PEG
_TXP[10]
PEG_TXN[10]
PEG_TXP[11]
_TXN[11]
PEG
_TXP[12]
PEG
PEG
_TXN[12]
PEG
_TXP[13]
PEG
_TXN[13]
PEG_TXP[14]
PEG
_TXN[14]
_TXP[15]
PEG
_TXN[15]
PEG
DM
I_TXP[0]
DMI_TXN[0]
I_TXP[1]
DM
I_TXN[1]
DM
I_TXP[2]
DM
DM
I_TXN[2]
DM
I_TXP[3]
DM
I_TXN[3]
B25
A25
B24
C24
B23
A23
B22
C22
B21
A21
B20
C20
B19
A19
B18
C18
A17
B17
C16
B16
A15
B15
C14
B14
A13
B13
C12
B12
A11
B11
C10
B10
B8
A8
C6
B6
B5
A5
D4
B4
C_
PEG_TX15
C_
PEG_TX#15
C_
PEG_TX14
C_PEG_TX#14
PEG_TX13
C_
PEG_TX#13
C_
PEG_TX12
C_
C_
PEG_TX#12
C_
PEG_TX11
C_
PEG_TX#11
C_PEG_TX10
PEG_TX#10
C_
PEG_TX9
C_
PEG_TX#9
C_
C_
PEG_TX8
C_
PEG_TX#8
C_
PEG_TX7
C_
PEG_TX#7
PEG_TX6
C_
C_PEG_TX#6
PEG_TX5
C_
PEG_TX#5
C_
PEG_TX4
C_
C_
PEG_TX#4
C_
PEG_TX3
C_PEG_TX#3
C_PEG_TX2
PEG_TX#2
C_
PEG_TX1
C_
PEG_TX#1
C_
C_
PEG_TX0
C_
PEG_TX#0
3
194 [email protected]/10V_4
C1
C1
195 [email protected]/10V_4
C1
200 [email protected]/10V_4
C1
198 [email protected]/10V_4
C1197 [email protected]/10V_4
196 [email protected]/10V_4
C1
201 [email protected]/10V_4
C1
199 [email protected]/10V_4
C1
C1
202 [email protected]/10V_4
C1
203 [email protected]/10V_4
C1
208 [email protected]/10V_4
C1
206 [email protected]/10V_4
205 [email protected]/10V_4
C1
C1204 [email protected]/10V_4
209 [email protected]/10V_4
C1
207 [email protected]/10V_4
C1
13 [email protected]/10V_ 4
C8
C8
11 [email protected]/10V_ 4
C8
14 [email protected]/10V_ 4
C815 [email protected]/10V _4
C817 [email protected]/10V _4
16 [email protected]/10V_ 4
C8
19 [email protected]/10V_ 4
C8
18 [email protected]/10V_ 4
C8
C8
22 [email protected]/10V_ 4
C8
20 [email protected]/10V_ 4
C8
23 [email protected]/10V_ 4
C8
25 [email protected]/10V_ 4
27 [email protected]/10V_ 4
C8
26 [email protected]/10V_ 4
C8
28 [email protected]/10V_ 4
C8
30 [email protected]/10V_ 4
C8
DM
I_TXP0 9
DM
I_TXN0 9
DM
I_TXP1 9
DMI_TXN1 9
I_TXP2 9
DM
I_TXN2 9
DM
I_TXP3 9
DM
DM
I_TXN3 9
PEG_TX15 19
_TX#15 19
PEG
_TX14 19
PEG
_TX#14 19
PEG
PEG
_TX13 19
_TX#13 19
PEG
PEG
_TX12 19
PEG_TX#12 19
PEG
_TX11 19
PEG_TX#11 19
_TX10 19
PEG
_TX#10 19
PEG
_TX9 19
PEG
PEG
_TX#9 19
PEG
_TX8 19
PEG
_TX#8 19
PEG_TX7 19
_TX#7 19
PEG
_TX6 19
PEG
_TX#6 19
PEG
PEG
_TX5 19
PEG
_TX#5 19
PEG
_TX4 19
PEG_TX#4 19
_TX3 19
PEG
PEG_TX#3 19
_TX2 19
PEG
_TX#2 19
PEG
_TX1 19
PEG
PEG
_TX#1 19
PEG
_TX0 19
PEG
_TX#0 19
Lane
Reversed
2
1
03
SKYL
AKE_HALO
U41D
B B
A A
5
HDM
I
CRT
CRT
CRT
CRT
CRT
4
_AUX_C
_AUX#_C
K36
K37
J35
J34
H37
H36
J37
J38
D27
E27
H34
H33
F37
G38
F34
F35
E37
E36
F26
E26
C34
D34
B36
B34
F33
E33
C33
B33
A27
B27
DDI1_TXP[0]
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI2_AUXN
DDI3_TXP[0]
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI3_AUXP
DDI
_D2
IN
_D230
IN
IN
_D2#30
IN
IN_D130
_D1#30
IN
IN_D030
IN
_D0#30
IN
_CLK30
_CLK#30
IN
_AUXP28
_AUXN28
_D2#
_D1
IN
_D1#
IN
_D0
IN
_D0#
IN
IN_CLK
IN
_CLK#
_TXP028
CRT
_TXN028
CRT
_TXP128
CRT
CRT_TXN128
R998*short_4
R9
99*short_4
1_TXN[0]
1_TXP[1]
1_TXN[1]
1_TXP[2]
1_TXN[2]
1_TXP[3]
1_TXN[3]
1_AUXP
1_AUXN
2_TXP[0]
2_TXN[0]
2_TXP[1]
2_TXN[1]
2_TXP[2]
2_TXN[2]
2_TXP[3]
2_TXN[3]
2_AUXP
3_TXN[0]
3_TXP[1]
3_TXN[1]
3_TXP[2]
3_TXN[2]
3_TXP[3]
3_TXN[3]
3_AUXN
SKL_H_BGA_BGA
BGA1440
4 OF 14
PR
EDP_TXP[0]
ED
P_TXN[0]
ED
P_TXP[1]
P_TXN[1]
ED
ED
P_TXN[2]
P_TXP[2]
ED
ED
P_TXN[3]
P_TXP[3]
ED
P_AUXP
ED
P_AUXN
ED
ED
P_DISP_UTIL
ED
P_RCOMP
OC_AUDIO_CLK
PR
PROC_AUDIO_SDI
OC_AUDIO_SDO
D29
E29
F28
E28
B29
A29
B28
C28
C26
B26
A33
D37
G27
G25
G29
eDP
P_TXP0 29
ED
P_TXN0 29
ED
EDP_TXP1 29
P_TXN1 29
ED
EDP_TXN2 29
ED
P_TXP2 29
ED
P_TXN3 29
P_TXP3 29
ED
P_AUXP 29
ED
ED
P_AUXN 29
ED
P_DISP_UTIL
EDP_RCOMP
DP
P_RCOMP
eD
Trace length < 100 Mils
Trace Width 20 Mils Trace Spacing 25 Mils
D_AZACPU_SO
AU
TP87
1624.9/F_4
R1
+V
& PEG Compensation
R1
27 *SHORT_4
R1
26 20_4
CCIO 6 ,16,38,40,42, 45
+V
.0V 2,5,6,10,1 6,40,45
+1
3
CCIO
D_AZACPU_SCLK 10
AU
AU
D_AZACPU_SDO 10
D_AZACPU_SDI 10
AU
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
2
B 1/5 (PCIE&DMI&FDI)
B 1/5 (PCIE&DMI&FDI)
B 1/5 (PCIE&DMI&FDI)
SN
SN
SN
Date: Sheet
Date: Sheet
Date: Sheet
1
1A
1A
1A
349Tuesday, Augu st 25, 2015
349Tuesday, Augu st 25, 2015
349Tuesday, Augu st 25, 2015
of
of
of
Page 4
5
4
3
2
1
SK
YLAKE Processor (DDR3)
CHANNEL B
SKYLAKE_HALO
BGA1440
DDR1
_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1
_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1
_CAS#/DDR1_CAB[1]/DDR1_MA[15]
_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1
DDR1
_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1
_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1
_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1
_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1
_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1
DDR1
_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1
DDR1
_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
OF 14
2
DDR1_CKP[0]
_CKN[0]
DDR1
DDR1_CKN[1]
DDR1
_CKP[1]
DDR1_CLKP[2]
DDR1
_CLKN[2]
DDR1_CLKP[3]
DDR1
_CLKN[3]
DDR1
_CKE[0]
_CKE[1]
DDR1
DDR1
_CKE[2]
_CKE[3]
DDR1
_CS#[0]
DDR1
_CS#[1]
DDR1
_CS#[2]
DDR1
_CS#[3]
DDR1
_ODT[0]
DDR1
DDR1
_ODT[1]
_ODT[2]
DDR1
DDR1
_ODT[3]
DDR1_MA[3]
_MA[4]
DDR1
_PAR
DDR1
_ALERT#
DDR1
_DQSN[0]/DDR0_DQSN[2]
_DQSN[1]/DDR0_DQSN[3]
_DQSN[2]/DDR0_DQSN[6]
_DQSN[3]/DDR0_DQSN[7]
_DQSN[4]/DDR1_DQSN[2]
_DQSN[5]/DDR1_DQSN[3]
DDR1
_DQSN[6]
DDR1
_DQSP[0]/DDR0_DQSP[2]
_DQSP[1]/DDR0_DQSP[3]
_DQSP[2]/DDR0_DQSP[6]
_DQSP[3]/DDR0_DQSP[7]
_DQSP[4]/DDR1_DQSP[2]
_DQSP[5]/DDR1_DQSP[3]
_DQSN[7]
DDR1_DQSP[6]
_DQSP[7]
DDR1
_DQSP[8]
DDR1
DDR1_DQSN[8]
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
AM9
AN9
AM8
AM7
AM11
AM10
AJ10
AJ11
AT8
AT10
AT7
AT11
AF11
AE7
AF10
AE10
AF7
AE8
AE9
AE11
AH10
AH11
AF8
AH8
AH9
AR9
AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10
AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9
AJ7
AR8
BP9
BL9
BG9
BC9
AC9
W9
R9
M9
BR9
BJ9
BF9
BB9
AA9
V9
P9
L9
AW9
AY9
BN13
BP13
BR13
B_BA#0
M_
M_
B_BA#1
B_BG#0
M_
M_
B_A0
M_
B_A1
M_
B_A2
B_A3
M_
B_A4
M_
M_
B_A5
M_
B_A6
M_
B_A7
B_A8
M_
B_A9
M_
M_B_A10
M_
B_A11
M_
B_A12
B_A13
M_
B_BG#1
M_
B_ACT#
M_
M_
B_PARITY
B_ALERT#
M_
M_
B_DQSN0
M_
B_DQSN1
M_
B_DQSN2
B_DQSN3
M_
B_DQSN4
M_
M_
B_DQSN5
M_
B_DQSN6
B_DQSN7
M_
B_DQSP0
M_
M_
B_DQSP1
M_
B_DQSP2
M_
B_DQSP3
M_
B_DQSP4
B_DQSP5
M_
M_
B_DQSP6
M_B_DQSP7
_VREF
SM
SM
DDR_VREF_DQ0_M3
DDR_VREF_DQ1_M3
SM
M_
M_
M_
M_
M_
M_
B_RAS# 18
M_
B_WE# 18
M_
B_CAS# 18
M_
M_
M_
R1
46*1K _4
R154*1K _4
M_
M_B_CS#1 18
M_
M_
M_
B_CLKP0 18
B_CLKN0 18
B_CLKN1 18
B_CLKP1 18
B_CKE0 18
B_CKE1 18
B_CS#0 18
B_ODT0_CPU 18
B_ODT1_CPU 18
B_BA#0 18
M_
B_BA#1 18
M_
M_
B_BG#0 18
B_A[13:0] 18
M_
B_BG#1 18
M_
B_ACT# 18
B_PARITY 18
M_
B_ALERT# 18
M_
B_DQSN[7:0] 18
B_DQSP[7:0] 18
M_
AKE_HALO
A_DQ[63:0]17
D D
C C
B B
M_
VD_V10 must be grounded
RS
A_DQ0
M_
A_DQ1
M_
A_DQ2
M_
M_
A_DQ3
M_
A_DQ4
M_
A_DQ5
A_DQ6
M_
A_DQ7
M_
M_
A_DQ8
M_A_DQ9
M_
A_DQ10
A_DQ11
M_
A_DQ12
M_
M_A_DQ13
A_DQ14
M_
M_
A_DQ15
A_DQ16
M_
A_DQ17
M_
A_DQ18
M_
A_DQ19
M_
M_
A_DQ20
A_DQ21
M_
A_DQ22
M_
A_DQ23
M_
A_DQ24
M_
M_
A_DQ25
A_DQ26
M_
M_
A_DQ27
A_DQ28
M_
A_DQ29
M_
M_
A_DQ30
M_
A_DQ31
M_
A_DQ32
A_DQ33
M_
A_DQ34
M_
M_
A_DQ35
M_
A_DQ36
M_
A_DQ37
A_DQ38
M_
A_DQ39
M_
M_A_DQ40
M_
A_DQ41
M_
A_DQ42
A_DQ43
M_
A_DQ44
M_
A_DQ45
M_
M_
A_DQ46
M_
A_DQ47
A_DQ48
M_
M_
A_DQ49
A_DQ50
M_
M_
A_DQ51
M_
A_DQ52
M_
A_DQ53
A_DQ54
M_
A_DQ55
M_
M_
A_DQ56
M_
A_DQ57
A_DQ58
M_
M_
A_DQ59
A_DQ60
M_
M_
A_DQ61
M_
A_DQ62
M_
A_DQ63
U41A
BR6
DDR0_DQ[0]
BT6
DDR0
_DQ[1]
BP3
DDR0_DQ[2]
BR3
DDR0
_DQ[3]
BN5
DDR0_DQ[4]
BP6
DDR0
_DQ[5]
BP2
_DQ[6]
DDR0
BN3
DDR0
_DQ[7]
BL4
_DQ[8]
DDR0
BL5
DDR0
_DQ[9]
BL2
_DQ[10]
DDR0
BM1
_DQ[11]
DDR0
BK4
_DQ[12]
DDR0
BK5
_DQ[13]
DDR0
BK1
_DQ[14]
DDR0
BK2
_DQ[15]
DDR0
BG4
DDR0
_DQ[16]/DDR0_DQ[32]
BG5
_DQ[17]/DDR0_DQ[33]
DDR0
BF4
DDR0
_DQ[18]/DDR0_DQ[34]
BF5
_DQ[19]/DDR0_DQ[35]
DDR0
BG2
DDR0
_DQ[20]/DDR0_DQ[36]
BG1
DDR0
_DQ[21]/DDR0_DQ[37]
BF1
DDR0
_DQ[22]/DDR0_DQ[38]
BF2
DDR0
_DQ[23]/DDR0_DQ[39]
BD2
DDR0
_DQ[24]/DDR0_DQ[40]
BD1
DDR0
_DQ[25]/DDR0_DQ[41]
BC4
_DQ[26]/DDR0_DQ[42]
DDR0
BC5
DDR0
_DQ[27]/DDR0_DQ[43]
BD5
_DQ[28]/DDR0_DQ[44]
DDR0
BD4
DDR0
_DQ[29]/DDR0_DQ[45]
BC1
_DQ[30]/DDR0_DQ[46]
DDR0
BC2
DDR0_DQ[31]/DDR0_DQ[47]
AB1
_DQ[32]/DDR1_DQ[0]
DDR0
AB2
DDR0_DQ[33]/DDR1_DQ[1]
AA4
_DQ[34]/DDR1_DQ[2]
DDR0
AA5
DDR0_DQ[35]/DDR1_DQ[3]
AB5
DDR0
_DQ[36]/DDR1_DQ[4]
AB4
DDR0_DQ[37]/DDR1_DQ[5]
AA2
DDR0
_DQ[38]/DDR1_DQ[6]
AA1
DDR0_DQ[39]/DDR1_DQ[7]
V5
DDR0
_DQ[40]/DDR1_DQ[8]
V2
_DQ[41]/DDR1_DQ[9]
DDR0
U1
DDR0
_DQ[42]/DDR1_DQ[10]
U2
_DQ[43]/DDR1_DQ[11]
DDR0
V1
DDR0
_DQ[44]/DDR1_DQ[12]
V4
_DQ[45]/DDR1_DQ[13]
DDR0
U5
_DQ[46]/DDR1_DQ[14]
DDR0
U4
_DQ[47]/DDR1_DQ[15]
DDR0
R2
_DQ[48]/DDR1_DQ[32]
DDR0
P5
_DQ[49]/DDR1_DQ[33]
DDR0
R4
_DQ[50]/DDR1_DQ[34]
DDR0
P4
DDR0
_DQ[51]/DDR1_DQ[35]
R5
_DQ[52]/DDR1_DQ[36]
DDR0
P2
DDR0
_DQ[53]/DDR1_DQ[37]
R1
_DQ[54]/DDR1_DQ[38]
DDR0
P1
DDR0
_DQ[55]/DDR1_DQ[39]
M4
DDR0
_DQ[56]/DDR1_DQ[40]
M1
DDR0
_DQ[57]/DDR1_DQ[41]
L4
DDR0
_DQ[58]/DDR1_DQ[42]
L2
DDR0
_DQ[59]/DDR1_DQ[43]
M5
DDR0
_DQ[60]/DDR1_DQ[44]
M2
_DQ[61]/DDR1_DQ[45]
DDR0
L5
DDR0
_DQ[62]/DDR1_DQ[46]
L1
_DQ[63]/DDR1_DQ[47]
DDR0
BA2
_ECC[0]
DDR0
BA1
DDR0_ECC[1]
AY4
_ECC[2]
DDR0
AY5
DDR0_ECC[3]
BA5
_ECC[4]
DDR0
BA4
DDR0_ECC[5]
AY1
DDR0
_ECC[6]
AY2
DDR0_ECC[7]
DDR CHANNEL A
SKL_H_BGA_BGA
SKYL
BGA1440
DDR0
_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0
_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0
_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0
DDR0
_WE#/DDR0_CAB[2]/DDR0_MA[14]
_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0
_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0
_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0
_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0
DDR0
_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0
DDR0
_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0
_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0
_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0
OF 14
1
DDR0_CKP[0]
DDR0
_CKN[0]
DDR0_CKP[1]
DDR0
_CKN[1]
DDR0_CLKP[2]
DDR0
_CLKN[2]
_CLKP[3]
DDR0
DDR0
_CLKN[3]
DDR0
_CKE[0]
_CKE[1]
DDR0
_CKE[2]
DDR0
_CKE[3]
DDR0
_CS#[0]
DDR0
_CS#[1]
DDR0
DDR0
_CS#[2]
_CS#[3]
DDR0
_ODT[0]
DDR0
DDR0
_ODT[1]
DDR0
_ODT[2]
DDR0
_ODT[3]
DDR0_MA[3]
DDR0
_MA[4]
_PAR
DDR0
_ALERT#
DDR0
DDR0
_DQSN[0]
_DQSN[1]
DDR0
_DQSN[2]/DDR0_DQSN[4]
_DQSN[3]/DDR0_DQSN[5]
_DQSN[4]/DDR1_DQSN[0]
_DQSN[5]/DDR1_DQSN[1]
_DQSN[6]/DDR1_DQSN[4]
_DQSN[7]/DDR1_DQSN[5]
DDR0
_DQSP[0]
_DQSP[1]
DDR0
_DQSP[2]/DDR0_DQSP[4]
_DQSP[3]/DDR0_DQSP[5]
_DQSP[5]/DDR1_DQSP[1]
_DQSP[7]/DDR1_DQSP[5]
DDR0
_DQSP[8]
DDR0_DQSN[8]
AG1
AG2
AK2
AK1
AL3
AK3
AL2
AL1
AT1
AT2
AT3
AT5
AD5
AE2
AD2
AE5
AD3
AE4
AE1
AD4
AH5
AH1
AU1
AH4
AG4
AD1
AH3
AP4
AN4
AP5
AP2
AP1
AP3
AN1
AN3
AT4
AH2
AN2
AU4
AE3
AU2
AU3
AG3
AU5
BR5
BL3
BG3
BD3
AA3
U3
P3
L3
BP5
BK3
BF3
BC3
AB3
V3
R3
M3
AY3
BA3
A_BA#0
M_
M_
A_BA#1
A_BG#0
M_
M_
A_A0
A_A1
M_
A_A2
M_
M_
A_A3
M_
A_A4
M_
A_A5
A_A6
M_
A_A7
M_
M_A_A8
M_
A_A9
M_
A_A10
A_A11
M_
A_A12
M_
A_A13
M_
M_
A_BG#1
M_
A_ACT#
M_
A_PARITY
A_ALERT#
M_
M_
A_DQSN0
A_DQSN1
M_
A_DQSN2
M_
M_
A_DQSN3
M_
A_DQSN4
A_DQSN5
M_
M_
A_DQSN6
A_DQSN7
M_
M_
A_DQSP0
M_
A_DQSP1
M_
A_DQSP2
A_DQSP3
M_
M_
A_DQSP4
M_A_DQSP5
M_
A_DQSP6
M_
A_DQSP7
B_DQ[63:0]18
A_CLKP0 17
M_
A_CLKN0 17
M_
A_CLKP1 17
M_
M_
A_CLKN1 17
M_A_CKE0 17
M_
A_CKE1 17
A_CS#0 17
M_
M_
A_CS#1 17
A_ODT0_CPU 17
M_
M_
A_ODT1_CPU 17
A_BA#0 17
M_
A_BA#1 17
M_
A_BG#0 17
M_
A_RAS# 17
M_
A_WE# 17
M_
M_
A_CAS# 17
M_
A_A[13:0] 17
A_BG#1 17
M_
A_ACT# 17
M_
M_
A_PARITY 17
M_
A_ALERT# 17
M_
A_DQSN[7:0] 17
A_DQSP[7:0] 17
M_
R1
R1
R1
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_B_DQ11
M_
M_
M_
M_B_DQ15
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_B_DQ42
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
SM
95121/F_4
SM
9375/F_4
SM
92100/F_4
B_DQ0
B_DQ1
B_DQ2
B_DQ3
B_DQ4
B_DQ5
B_DQ6
B_DQ7
B_DQ8
B_DQ9
B_DQ10
B_DQ12
B_DQ13
B_DQ14
B_DQ16
B_DQ17
B_DQ18
B_DQ19
B_DQ20
B_DQ21
B_DQ22
B_DQ23
B_DQ24
B_DQ25
B_DQ26
B_DQ27
B_DQ28
B_DQ29
B_DQ30
B_DQ31
B_DQ32
B_DQ33
B_DQ34
B_DQ35
B_DQ36
B_DQ37
B_DQ38
B_DQ39
B_DQ40
B_DQ41
B_DQ43
B_DQ44
B_DQ45
B_DQ46
B_DQ47
B_DQ48
B_DQ49
B_DQ50
B_DQ51
B_DQ52
B_DQ53
B_DQ54
B_DQ55
B_DQ56
B_DQ57
B_DQ58
B_DQ59
B_DQ60
B_DQ61
B_DQ62
B_DQ63
_RCOMP_0
_RCOMP_1
_RCOMP_2
U41B
BT11
DDR1_DQ[0]/DDR0_DQ[16]
BR11
_DQ[1]/DDR0_DQ[17]
DDR1
BT8
DDR1_DQ[2]/DDR0_DQ[18]
BR8
DDR1
_DQ[3]/DDR0_DQ[19]
BP11
DDR1_DQ[4]/DDR0_DQ[20]
BN11
DDR1
_DQ[5]/DDR0_DQ[21]
BP8
DDR1_DQ[6]/DDR0_DQ[22]
BN8
DDR1
_DQ[7]/DDR0_DQ[23]
BL12
_DQ[8]/DDR0_DQ[24]
DDR1
BL11
DDR1
_DQ[9]/DDR0_DQ[25]
BL8
_DQ[10]/DDR0_DQ[26]
DDR1
BJ8
DDR1
_DQ[11]/DDR0_DQ[27]
BJ11
_DQ[12]/DDR0_DQ[28]
DDR1
BJ10
_DQ[13]/DDR0_DQ[29]
DDR1
BL7
_DQ[14]/DDR0_DQ[30]
DDR1
BJ7
_DQ[15]/DDR0_DQ[31]
DDR1
BG11
_DQ[16]/DDR0_DQ[48]
DDR1
BG10
_DQ[17]/DDR0_DQ[49]
DDR1
BG8
DDR1
_DQ[18]/DDR0_DQ[50]
BF8
_DQ[19]/DDR0_DQ[51]
DDR1
BF11
DDR1
_DQ[20]/DDR0_DQ[52]
BF10
_DQ[21]/DDR0_DQ[53]
DDR1
BG7
DDR1
_DQ[22]/DDR0_DQ[54]
BF7
DDR1
_DQ[23]/DDR0_DQ[55]
BB11
DDR1
_DQ[24]/DDR0_DQ[56]
BC11
DDR1
_DQ[25]/DDR0_DQ[57]
BB8
DDR1
_DQ[26]/DDR0_DQ[58]
BC8
DDR1
_DQ[27]/DDR0_DQ[59]
BC10
_DQ[28]/DDR0_DQ[60]
DDR1
BB10
DDR1
_DQ[29]/DDR0_DQ[61]
BC7
_DQ[30]/DDR0_DQ[62]
DDR1
BB7
DDR1
_DQ[31]/DDR0_DQ[63]
AA11
_DQ[32]/DDR1_DQ[16]
DDR1
AA10
DDR1_DQ[33]/DDR1_DQ[17]
AC11
_DQ[34]/DDR1_DQ[18]
DDR1
AC10
DDR1_DQ[35]/DDR1_DQ[19]
AA7
_DQ[36]/DDR1_DQ[20]
DDR1
AA8
DDR1_DQ[37]/DDR1_DQ[21]
AC8
DDR1
_DQ[38]/DDR1_DQ[22]
AC7
DDR1_DQ[39]/DDR1_DQ[23]
W8
DDR1
_DQ[40]/DDR1_DQ[24]
W7
DDR1_DQ[41]/DDR1_DQ[25]
V10
DDR1
_DQ[42]/DDR1_DQ[26]
V11
_DQ[43]/DDR1_DQ[27]
DDR1
W11
DDR1
_DQ[44]/DDR1_DQ[28]
W10
_DQ[45]/DDR1_DQ[29]
DDR1
V7
DDR1
_DQ[46]/DDR1_DQ[30]
V8
_DQ[47]/DDR1_DQ[31]
DDR1
R11
_DQ[48]
DDR1
P11
_DQ[49]
DDR1
P7
_DQ[50]
DDR1
R8
_DQ[51]
DDR1
R10
_DQ[52]
DDR1
P10
DDR1
_DQ[53]
R7
_DQ[54]
DDR1
P8
DDR1
_DQ[55]
L11
_DQ[56]
DDR1
M11
DDR1
_DQ[57]
L7
DDR1
_DQ[58]
M8
DDR1
_DQ[59]
L10
DDR1
_DQ[60]
M10
DDR1
_DQ[61]
M7
DDR1
_DQ[62]
L8
_DQ[63]
DDR1
AW11
_ECC[0]
DDR1
AY11
DDR1
_ECC[1]
AY8
_ECC[2]
DDR1
AW8
DDR1_ECC[3]
AY10
_ECC[4]
DDR1
AW10
DDR1_ECC[5]
AY7
_ECC[6]
DDR1
AW7
DDR1_ECC[7]
G1
DDR_RCOMP[0]
H1
DDR_RCOMP[1]
J2
DDR_RCOMP[2]
SKL_H_BGA_BGA
DDR
04
_VREF 17
SM
TP
74
DDR_VREF_DQ1_M3 18
SM
A A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Cu
Cu
Cu
stom
stom
stom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
B 2/5 (DDR3 I/F)
B 2/5 (DDR3 I/F)
B 2/5 (DDR3 I/F)
SN
SN
SN
1
1A
1A
1A
of
of
of
449Tuesday, August 25, 2015
449Tuesday, August 25, 2015
449Tuesday, August 25, 2015
Page 5
5
4
3
2
1
SKYLAKE Processor (POWER)
.5V 14,30,32,34,45
+1
low SKL H EDS page 133 to 45W(GT4+OPC): +VCCGT=104A/12A (GTx)
Fol
Follow SKL H EDS page 133 to 45W(GT2): +VCCGT=55A
Follow SKL H DG page 574 to place Cap
D D
+
C C
B B
22uF x 14, 10uF x 35, 1uF x 68
C3
C2
00
197
PC
330u/2V_7343
22U/6.3V_6
C7
52
22U/6.3V_6
C7
62
22U/6.3V_6
94
C1
10U/6.3V_6
26
C3
10U/6.3V_6
27
C3
10U/6.3V_6
C3
61
1U/6.3V_4
C3
83
1U/6.3V_4
C2
02
1U/6.3V_4
22U/6.3V_6
C7
22U/6.3V_6
C7
22U/6.3V_6
C7
10U/6.3V_6
C2
10U/6.3V_6
C3
10U/6.3V_6
C2
1U/6.3V_4
C2
1U/6.3V_4
C2
1U/6.3V_4
C3
C1
10
22U/6.3V_6
C7
53
22U/6.3V_6
C2
63
22U/6.3V_6
65
C2
10U/6.3V_6
09
C2
10U/6.3V_6
28
C7
10U/6.3V_6
C2
18
1U/6.3V_4
C1
89
1U/6.3V_4
C7
51
1U/6.3V_4
C3
29
91
22U/6.3V_6
C7
75
50
22U/6.3V_6
C3
24
55
22U/6.3V_6
13
21
C2
10U/6.3V_6
42
07
C3
10U/6.3V_6
64
88
C1
10U/6.3V_6
C3
27
64
1U/6.3V_4
C3
94
93
1U/6.3V_4
C2
91
52
1U/6.3V_4
07
22U/6.3V_6
C7
51
22U/6.3V_6
C3
52
22U/6.3V_6
76
C7
10U/6.3V_6
39
C3
10U/6.3V_6
74
C7
10U/6.3V_6
C2
16
1U/6.3V_4
C3
63
1U/6.3V_4
C3
51
1U/6.3V_4
C1
95
22U/6.3V_6
C3
08
22U/6.3V_6
C3
53
22U/6.3V_6
73
C7
10U/6.3V_6
40
C3
10U/6.3V_6
60
C7
10U/6.3V_6
41
C7
47U/6.3VS_8
C3
17
1U/6.3VS_4
C3
81
1U/6.3VS_4
C7
82
1U/6.3VS_4
+V
CCGT7,42,44
47U/6.3VS_8
C7
49
22U/6.3V_6
C3
09
22U/6.3V_6
C3
54
22U/6.3V_6
25
C2
10U/6.3V_6
41
C3
10U/6.3V_6
72
C7
10U/6.3V_6
42
C7
C2
29
1U/6.3V_4
C7
83
1U/6.3V_4
C2
79
1U/6.3V_4
+V
CCGT
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38
AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP14
AP29
AP30
AP31
AP32
AP35
AP36
AP37
AP38
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
U41N
CGT
VC
CGT
VC
VCCGT
VCCGT
VC
CGT
VC
CGT
CGT
VC
CGT
VC
CGT
VC
VCCGT
VCCGT
VC
CGT
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VCCGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
VCCGT
VCCGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VCCGT
VCCGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VCCGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
VCCGT
VCCGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VCCGT
VCCGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VCCGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
VCCGT
VCCGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VCCGT
VCCGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
VC
CGT
VCCGT
CGT
VC
CGT
VC
VC
CGT
VC
CGT
SKL_H_BGA_BGA
SKY
LAKE_HALO
BGA1440
14
OF 14
VCCGTX
VCCGTX
VC
CGTX
VC
CGTX
CGTX
VC
CGTX
VC
CGTX
VC
VCCGTX
VCCGTX
VC
CGTX
CGTX
VC
CGTX
VC
CGTX
VC
CGTX
VC
VCCGTX
VC
CGTX
VC
CGTX
VC
CGTX
VC
CGTX
CGTX
VC
VCCGTX
VCCGTX
VC
CGT_SENSE
VSSG
TX_SENSE
T_SENSE
VSSG
VCCGTX_SENSE
AF29
AF30
AF31
AF32
AF33
AF34
AG13
AG14
AG31
AG32
AG33
AG34
AG35
AG36
AH13
AH14
AH29
AH30
AH31
AH32
AJ13
AJ14
AH38
AH35
AH37
AH36
R5
*100/F_4
R5
*100/F_4
4+4e, Support eDRAM Only, GTX 12A
ed c aps.. .
Ne
CCGT
+V
50
VC
CGT_SENSE 42
86
TP
VCCGTSS_SENSE 42
85
TP
49
VPCU
+3
CCGT
+V
C785
C287
1U/6.3V_4
92
C2
1U/6.3V_4
28
C2
1U/6.3V_4
76
C2
1U/6.3V_4
99
C3
1U/6.3V_4
C7
94
1U/6.3V_4
C385
1U/6.3V_4
46
C3
1U/6.3V_4
66
C2
1U/6.3V_4
95
C3
1U/6.3V_4
03
C2
1U/6.3V_4
C3
60
1U/6.3V_4
1U/6.3V_4
32
C3
1U/6.3V_4
74
C2
1U/6.3V_4
93
C7
1U/6.3V_4
26
C2
1U/6.3V_4
C3
62
1U/6.3V_4
+1
.2VSUS 2,6,10,17,18,41
Thrm Protect
IO
R2
15
*16.5K/F_4
RM_MOINTOR
TH
R2
31
*3.3K/F_4
For
75 degree, 1.2 v limit, (HW)
41
R2
1 2
00K_4 NTC
*1
C325
1U/6.3VS_4
54
C2
1U/6.3VS_4
17
C2
1U/6.3VS_4
96
C3
1U/6.3VS_4
78
C2
1U/6.3VS_4
C3
97
1U/6.3VS_4
68
C4
*0.1U/16V_4
C275
1U/6.3V_4
84
C7
1U/6.3V_4
77
C2
1U/6.3V_4
50
C2
1U/6.3V_4
15
C2
1U/6.3V_4
C7
92
1U/6.3V_4
1 2
05
C4
53
*0.1U/16V_4
TH
RM_MOINTOR1 37
C288
1U/6.3VS_4
53
C2
1U/6.3VS_4
92
C1
1U/6.3VS_4
04
C2
1U/6.3VS_4
80
C3
1U/6.3VS_4
C3
82
1U/6.3VS_4
C290
1U/6.3V_4
91
C2
1U/6.3V_4
49
C2
1U/6.3V_4
84
C3
1U/6.3V_4
65
C3
1U/6.3V_4
C3
98
1U/6.3V_4
Local CPU Thermal Sensor
U4
0
B_RUN_CLK10, 16,17,18,35
VC
C Output Decoupli ng Recommendations
A A
5
4
3
SM
SM
B_RUN_DAT10,16,17, 18,35
CPU_THRMTRIP#
R5
55 10K/F_4
+3
V
+1
.0V
PM_THRMTRIP#2,11,17,18
R562*4.7K_4
1 3
*METR3904-G
8
VC
SC
LK
7
DX
SD
A
6
ERT#
DX
AL
4
GN
OV
ERT#
*TMP431ADGKR
2
8
Q3
U_THRMTRIP#
CP
2
C8
06 0.01U/50 V_4
1
C
2
CP
P
3
N
5
D
U_THERMDA
09
C8
2200P/50V_4
CP
U_THERMDC
AL000431014
V
+3
CP
U Thermal Sensor
9
Q3
2
*METR3904-G
1 3
TMP431ADGKR(98h)
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
SNB 3/5 (POWER)
SNB 3/5 (POWER)
SNB 3/5 (POWER)
Date: Sheet
Date: Sheet
Date: Sheet
1
549Monday, S eptember 07, 2015
549Monday, S eptember 07, 2015
549Monday, S eptember 07, 2015
1A
1A
1A
of
of
of
Page 6
5
4
3
2
1
06
Fol
low SKL H EDS page 135 to 45W(GT2): VCCSA=11.1A (GTx)
D D
+VCCSA42,
44
C1
22U/6.3V_6
C7
10U/6.3V_6
C C
C2
87
10U/6.3V_6
C3
22u/6.3V_6
C7
90
22U/6.3V_6
05
C7
1U/6.3V_4
57
C3
22u/6.3V_6
C3
1U/6.3V_4
88
C7
86
10U/6.3V_6
66
50
73
C2
19
22U/6.3VS_6
C7
78
10U/6.3V_6
C2
08
1U/6.3V_4
18
C3
22U/6.3VS_6
C3
93
1U/6.3V_4
+VCCI
Follow SKL H EDS P136 to 45W: VCCIO
+VCCIO = 0.95V
B B
+VDDQC+VCCSTG+VCCPLL_O
86
73
C3
C2
10U/6.3V_6
+VCCI
O
A A
5
C3
56
*1U/6.3V_ 4
C4
1U/6.3V_4
C3
59
*22U/6.3V _6
01
1U/6.3V_4
C7
89
22U/6.3VS_6
C1
81
10U/6.3V_6
C2
96
1U/6.3V_4
O
31
C3
22U/6.3VS_6
C3
44
10U/6.3V_6
C
00
C4
+VCCSA
J30
K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37
L38
M29
M30
M31
M32
M33
M34
M35
M36
AG12
G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27
J15
J16
J17
J19
J20
J21
J26
J27
SKYLAKE_HALO
U41I
VC
CSA
11.1 A
CSA
VC
CSA
VC
VC
CSA
VC
CSA
CSA
VC
CSA
VC
VC
CSA
VCCSA
CSA
VC
VC
CSA
VC
CSA
CSA
VC
CSA
VC
VC
CSA
VC
CSA
CSA
VC
CSA
VC
VC
CSA
VC
CSA
CSA
VC
CSA
VC
CIO
VC
5.5 A
CIO
VC
VC
CIO
VCCIO
CIO
VC
VC
CIO
VC
CIO
CIO
VC
CIO
VC
VC
CIO
VC
CIO
CIO
VC
CIO
VC
VC
CIO
VC
CIO
CIO
VC
CIO
VC
VC
CIO
VC
CIO
CIO
VC
VC
CIO
SKL_H_BGA_BGA
C2
98
1U/6.3V_4
Close CPUUnder CPU
4
BG
A1440
O
1U/6.3V_4
0.26 A
9
C2
97
2.8 A
0.12 A
0.145 A
VC
VSSSA_
VC
VSSI
OF 14
+VCCPLL+VCCI
VD
VD
VD
VD
VD
VD
VD
VD
VDDQ
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
DQC
VD
VCCPLL_OC
CPLL_OC
VC
CST
VC
VC
CSTG
CSTG
VC
VC
CPLL
VC
CPLL
CSA_SENSE
SENSE
CIO_SENSE
O_SENSE
Follow SKL H EDS page 135 45W: VDDQ=2.8A
+1.
2VSUS
+1.
AA6
DQ
AE12
DQ
AF5
DQ
AF6
DQ
AG5
DQ
AG9
DQ
AJ12
DQ
AL11
DQ
AP6
AP7
DQ
AR12
DQ
AR6
DQ
AT12
DQ
AW6
DQ
AY6
DQ
J5
DQ
J6
DQ
K12
DQ
K6
DQ
L12
DQ
L6
DQ
R6
DQ
T6
DQ
W6
DQ
Y12
BH13
G11
H30
H29
G30
H28
J28
M38
M37
H14
J14
2VSUS 2,10,17,18,41
47
59
40
PLL
C2
1U/6.3V_4
ohm near CPU
100
VSA_
SENSE 42
VSASS_
SENSE 42
R151*SHORT_6
56*SH ORT_6
R1
R1
15*SHORT_6
R1
18*0_ 6
23*SH ORT_6
R1
3
C4
22U/6.3VS_6
C4
10U/6.3V_6
C4
10U/6.3V_6
60
+1.
+1.
52
49
51
2VSUS
2VSUS
+VCCST
+1.0V
C4
22U/6.3VS_6
C4
10U/6.3V_6
C4
10U/6.3V_6
+VDDQ
+VCCPLL_O
+VCCST
+VCCPLL
51 *100/F_4
R5
R5
46 *100/F_4
VCCI
O_VCCSENSE
O_VSSSENSE
VSSI
C
+VDDQ
C
+VCCPLL_O
+VCCSTG
+VCCPLL +VCCST
C4
21
22U/6.3VS_6
C4
60
10U/6.3V_6
C4
50
10U/6.3V_6
C
+VCCST
C
G
+VCCSA
R1
44 *SHORT_4
42 *SHORT_4
R1
+VCCI
C4
44
22U/6.3VS_6
C4
22
10U/6.3V_6
C4
34
10U/6.3V_6
O
45
R1
100_4
43
R1
100_4
PLL
PLL
+1.
+VCCST
+
C5
02
*330U/2V _7343
C4
32
10U/6.3V_6
C4
16
10U/6.3V_6
0V 2,5,10,16,40,45
PLL 2,10,40,42
EDRAM Only, PLACE CAPS IN ACK SIDE
BJ17
BJ19
BJ20
BK17
BK19
BK20
BL16
BL17
BL18
BL19
BL20
BL21
BM17
BN17
BJ23
BJ26
BJ27
BK23
BK26
BK27
BL23
BL24
BL25
BL26
BL27
BL28
BM24
BL15
BM16
BL22
BM22
BP15
BR15
BT15
BP16
BR16
BT16
BN15
BM15
BP17
BN16
91
TP
TP
24
29
TP
28
TP
TP
30
TP
27
OPC_COMP
76*49.9/F_4
CPU_
R5
CPU_
R1
R1
2
OPCE_COMP
33*49.9/F_4
CPU_
OPCE_COMP2
32*49.9/F_4
BM14
BL14
BJ35
BJ36
AT13
AW13
AU13
AY13
BT29
BR25
BP25
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Si
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
SNB 4/5 (POWER & GND)
SNB 4/5 (POWER & GND)
SNB 4/5 (POWER & GND)
Date: Sheet
Date: Sheet
Date: Sheet
SKYLAKE_HALO
U41J
BG
VC
COPC
3.8 A
COPC
VC
COPC
VC
VC
COPC
VC
COPC
COPC
VC
COPC
VC
VC
COPC
VCCOPC
COPC
VC
VC
COPC
VC
COPC
COPC
VC
COPC
VC
RS
VD
VD
RS
VD
RS
RS
VD
RS
VD
VD
RS
VD
RS
RS
VD
RS
VD
VD
RS
VD
RS
RS
VD
RSVD
VC
COPC_SENSE
PC_SENSE
VSSO
RS
VD
RS
VD
VC
CEOPIO
2.8 A
VC
CEOPIO
CEOPIO
VC
RS
VD
RS
VD
VD
RS
VCCEOPIO_SENSE
PIO_SENSE
VSSEO
RS
VD
VD
RS
VC
C_OPC_1P8
C_OPC_1P8
VC
RS
VD
RS
VD
ZV
M#
MS
M#
ZV
M2#
MS
M2#
C_RCOMP
OP
CE_RCOMP
OP
OP
CE_RCOMP2
SKL_H_BGA_BGA
A1440
0.05 A
10
1
OF 14
1A
1A
1A
of
of
of
9Monday, September 07, 2015
9Monday, September 07, 2015
64
64
64
9Monday, September 07, 2015
Page 7
5
4
3
2
1
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BE33
BE34
BE35
BE36
+V
CCGT
07
n
et name
C_SENSE
SENSE
CCCORE
+V
CCCORE 42,43
+V
Follow SKL H DG page 573 to place Cap
V32
VCC
V33
C
VC
V34
C
VC
V35
C
VC
V36
C
VC
V37
C
VC
V38
VC
C
W13
VC
C
W14
VC
C
W29
VC
C
W30
VC
C
W31
VCC
W32
C
VC
W35
C
VC
W36
C
VC
W37
C
VC
W38
C
VC
Y29
VC
C
Y30
VC
C
Y31
VC
C
Y32
VC
C
Y33
VC
C
Y34
VCC
Y35
C
VC
Y36
VCC
L14
C
VC
P29
C
VC
P30
C
VC
P31
VC
C
P32
C
VC
P33
VC
C
P34
VC
C
P35
VC
C
P36
VCC
R13
VC
C
R31
VCC
R32
C
VC
R33
C
VC
R34
C
VC
R35
C
VC
R36
C
VC
R37
VC
C
R38
VC
C
T29
VC
C
T30
VC
C
T31
VC
C
T32
VCC
T35
C
VC
T36
C
VC
T37
C
VC
T38
C
VC
U29
C
VC
U30
VC
C
U31
VC
C
U32
VC
C
U33
VC
C
U34
VC
C
U35
VCC
U36
C
VC
V13
VCC
V14
C
VC
V31
C
VC
P14
C
VC
AG37
AG38
22uF x 12, 10uF x 28, 1uF x 63
C3
C3
0.1U/10V_4
1 2
C2
0.1U/10V_4
1 2
C180
0.1U/10V_4
1 2
C2
0.1U/10V_4
1 2
C2
0.1U/10V_4
1 2
69
82
44
45
88
0.1U/10V_4
1 2
81
C2
0.1U/10V_4
1 2
C739
0.1U/10V_4
1 2
76
C3
0.1U/10V_4
1 2
91
C3
0.1U/10V_4
1 2
R5
48 *100_4
R5
47 *100_4
C3
87
0.1U/10V_4
1 2
71
C3
0.1U/10V_4
1 2
C283
0.1U/10V_4
1 2
79
C3
0.1U/10V_4
1 2
48
C2
0.1U/10V_4
1 2
CCCORE
+V
ORE_SENSE 42
VC
ORESS_SENSE 42
VC
C2
C2
0.1U/10V_4
1 2
C2
0.1U/10V_4
1 2
C370
0.1U/10V_4
1 2
C7
0.1U/10V_4
1 2
C3
0.1U/10V_4
1 2
47
70
0.1U/10V_4
1 2
1 2
84
82
C1
0.1U/10V_4
1 2
1 2
C745
0.1U/10V_4
1 2
1 2
40
69
C2
0.1U/10V_4
1 2
1 2
92
90
C3
0.1U/10V_4
1 2
1 2
Se
nse resistor should be placed within 2
inches (50.8 mm) o f the processor soc ket
Trace Impendence 50 ohm
C3
78
0.1U/10V_4
67
C2
0.1U/10V_4
C375
0.1U/10V_4
95
C7
0.1U/10V_4
06
C2
0.1U/10V_4
1 2
1 2
1 2
1 2
1 2
C2
71
0.1U/10V_4
77
C3
0.1U/10V_4
C286
0.1U/10V_4
75
C1
0.1U/16V_4
67
C3
0.1U/10V_4
C3
0.1U/10V_4
1 2
C3
0.1U/10V_4
1 2
C214
0.1U/10V_4
1 2
C2
0.1U/10V_4
1 2
C3
0.1U/10V_4
1 2
C3
89
74
0.1U/10V_4
1 2
72
66
C2
0.1U/10V_4
1 2
C246
0.1U/10V_4
1 2
68
87
C1
0.1U/10V_4
1 2
68
85
C2
0.1U/10V_4
1 2
CCCORE
+V
U41G
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF35
AF36
AF37
AF38
K13
K14
L13
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
SKYLAKE_HALO
BG
VCC
C
VC
C
VC
C
VC
C
VC
C
VC
VC
C
VC
C
VC
C
VC
C
VC
C
VCC
C
VC
C
VC
C
VC
C
VC
C
VC
VC
C
VC
C
VC
C
VC
C
VC
C
VCC
C
VC
VCC
C
VC
C
VC
C
VC
VC
C
C
VC
VC
C
VC
C
VC
C
VCC
VC
C
VCC
C
VC
C
VC
C
VC
C
VC
C
VC
VC
C
VC
C
VC
C
VC
C
VC
C
VCC
C
VC
C
VC
C
VC
C
VC
C
VC
VC
C
VC
C
VC
C
VC
C
VC
C
VCC
C
VC
VCC
C
VC
C
VC
C
VC
SKL_H_BGA_BGA
A1440
VC
VSS_
7 OF 14
D D
C757
C211
22U/6.3V_6
22U/6.3V_6
C C
B B
C1
85
22U/6.3V_6
48
C3
10U/6.3V_6
83
C1
1U/6.3V_4
43
C3
1U/6.3V_4
C7
70
22U/6.3V_6
37
C3
10U/6.3V_6
89
C1
1U/6.3V_4
69
C7
1U/6.3V_4
Follow SKL H EDS page 131 to 45W(GT2): VCC_CORE=68A
C3
23
22U/6.3V_6
86
C1
22U/6.3V_6
C324
22U/6.3V_6
C3
47
22U/6.3V_6
58
C7
10U/6.3V_6
43
C7
1U/6.3V_4
01
C2
1U/6.3V_4
C7
48
22U/6.3V_6
97
C1
22U/6.3V_6
C759
22U/6.3V_6
C7
77
22U/6.3V_6
61
C7
10U/6.3V_6
99
C1
1U/6.3V_4
90
C7
1U/6.3V_4
C3
22
22U/6.3V_6
84
C1
22U/6.3V_6
C223
22U/6.3V_6
C7
47
22U/6.3V_6
12
C3
10U/6.3V_6
C7
67
10U/6.3V_6
79
C1
1U/6.3V_4
81
C7
1U/6.3V_4
C3
13
22U/6.3V_6
76
C1
22U/6.3V_6
C212
22U/6.3V_6
C3
36
22U/6.3V_6
10
C2
10U/6.3V_6
C3
49
10U/6.3V_6
80
C7
1U/6.3V_4
30
C3
1U/6.3V_4
C7
44
22U/6.3V_6
98
C1
22U/6.3V_6
C314
22U/6.3V_6
C2
22
22U/6.3V_6
71
C7
10U/6.3V_6
C3
38
10U/6.3V_6
15
C3
1U/6.3VS_4
21
C3
1U/6.3VS_4
C1
78
47U/6.3VS_8
C1
96
22U/6.3V_6
46
C7
22U/6.3V_6
C220
22U/6.3V_6
C7
56
22U/6.3V_6
68
C7
10U/6.3V_6
C7
54
10U/6.3V_6
74
C1
1U/6.3V_4
79
C7
1U/6.3V_4
C1
77
47U/6.3VS_8
CCGT
+V
CCGT 5,42,44
+V
U41H
SKYLAKE_HALO
A1440
BJ37
BJ38
BL36
BL37
BT37
BG
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VCCGT
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VCCGT
CGT
VC
VCCGT
CGT
VC
CGT
VC
CGT
VC
VC
CGT
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VCCGT
VC
CGT
VCCGT
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VCCGT
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
SKL_H_BGA_BGA
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VCCGT
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VCCGT
CGT
VC
VCCGT
CGT
VC
CGT
VC
CGT
VC
VC
CGT
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VCCGT
VC
CGT
VCCGT
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VCCGT
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
8
OF 14
BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38
BM36
BM37
BN36
BN37
BN38
BP37
BP38
BR37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BC36
BC37
BC38
BD13
BD14
BD29
BD30
BD31
BD32
BD33
BD34
BD35
BD36
BE31
BE32
BE37
Ch
ange R2053 to NI_20141203
VC
ORE_SENSE
A A
5
4
VC
R5
ORESS_SENSE
52*49.9/F_4
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Si
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
SN
SN
SN
B 4/5 (POWER & GND)
B 4/5 (POWER & GND)
B 4/5 (POWER & GND)
Date: Sheet
Date: Sheet
3
2
Date: Sheet
1
1A
1A
1A
749Tuesday, Augu st 25, 2015
749Tuesday, Augu st 25, 2015
749Tuesday, Augu st 25, 2015
of
of
of
Page 8
5
4
3
2
1
Haswell Processor (GND)
AW
AW
AW
BA38
BA3
BA12
BA1
BA10
AY3
AY3
AY1
AY1
AW
AW
AW
AW
AW
AV3
AV3
AU
AU
AU
AU
AU
AT30
AT
AR
AR37
AR
AR13
AP3
AP3
AP1
AP1
AP1
AN
AN
AN
AM
AM
AM
AM
AM
AM
AM
AM
AL
AL
AL
AL12
AL
BB4
BB3
BB2
BB1
BA9
BA8
BA7
BA6
AU
AU
AU
AU
AT6
AR
AR4
AR
AR
AR
AP9
AP8
AN
AN
AL9
AL
AL7
AL
U41M
VSS
VSS
VSS
VSS
VSS
7
VSS
VSS
1
VSS
VSS
VSS
VSS
VSS
VSS
B9
VSS
4
VSS
3
VSS
4
VSS
2
VSS
30
VSS
29
VSS
12
VSS
5
VSS
4
VSS
3
VSS
2
VSS
1
VSS
8
VSS
7
VSS
34
VSS
33
VSS
12
VSS
11
VSS
10
VSS
9
VSS
8
VSS
7
VSS
6
VSS
VSS
29
VSS
VSS
38
VSS
VSS
14
VSS
VSS
5
VSS
VSS
3
VSS
2
VSS
1
VSS
4
VSS
3
VSS
2
VSS
1
VSS
0
VSS
VSS
VSS
30
VSS
29
VSS
12
VSS
6
VSS
5
VSS
38
VSS
37
VSS
12
VSS
5
VSS
4
VSS
3
VSS
2
VSS
1
VSS
34
VSS
33
VSS
14
VSS
VSS
10
VSS
VSS
8
VSS
VSS
4
VSS
SKL_H_BGA_BGA
SKYL
AKE_HALO
BGA1440
13 OF 14
0
AK3
VSS
9
AK2
VSS
AK4
VSS
38
AJ
VSS
AJ37
VSS
6
AJ
VSS
AJ5
VSS
4
AJ
VSS
AJ3
VSS
2
AJ
VSS
AJ1
VSS
34
AH
VSS
33
AH
VSS
12
AH
VSS
6
AH
VSS
30
AG
VSS
29
AG
VSS
11
AG
VSS
10
AG
VSS
8
AG
VSS
7
AG
VSS
6
AG
VSS
AF
14
VSS
13
AF
VSS
AF
12
VSS
4
AF
VSS
AF
3
VSS
2
AF
VSS
AF
1
VSS
4
AE3
VSS
AE3
3
VSS
AE6
VSS
30
AD
VSS
29
AD
VSS
12
AD
VSS
11
AD
VSS
10
AD
VSS
AD9
VSS
8
AD
VSS
AD7
VSS
6
AD
VSS
AC38
VSS
37
AC
VSS
AC12
VSS
6
AC
VSS
AC5
VSS
4
AC
VSS
3
AC
VSS
2
AC
VSS
1
AC
VSS
4
AB3
VSS
3
AB3
VSS
AB6
VSS
0
AA3
VSS
9
AA2
VSS
2
AA1
VSS
0
A3
VSS
A2
8
VSS
6
A2
VSS
A2
4
VSS
2
A2
VSS
A2
0
VSS
8
A1
VSS
A1
6
VSS
4
A1
VSS
A1
2
VSS
0
A1
VSS
A9
VSS
A6
VSS
B37
FVSS
NCT
B3
NCTFVSS
A34
FVSS
NCT
A4
NCTFVSS
A3
FVSS
NCT
CF
G[3] (PHYSICAL_DEBUG_ENABLED (DFX PRIVACY))
Enable; SET DFX ENABLED BIT IN DEBUG
0
1 , Disable;
3
H_2_CPU_TRIG15
PC
CF
CF
G32,16
G22,16
CF
CFG42,16
CFG52,16
CFG62,16
CFG102,16
CFG122,16
CF
G132,16
G3
G2
CF
CFG4
CFG5
CFG6
CFG10
CFG12
CF
G13
U41F
AKE_HALO
SKYL
BGA1440
8
Y3
VSS
7
Y3
VSS
Y14
VSS
3
Y1
VSS
Y11
VSS
0
Y1
VSS
Y9
D D
C C
B B
W3
W33
W1
V3
V2
V1
U3
U3
T3
T3
T1
T1
T1
T1
T1
R30
R2
R12
P3
P37
P1
N3
N3
N1
N1
N1
M1
M1
M1
L34
L33
L30
L29
K3
K1
K1
Y8
Y7
4
2
W5
W4
W3
W2
W1
0
9
2
V6
8
7
U6
4
3
4
3
2
1
0
T9
T8
T7
T5
T4
T3
T2
T1
9
8
2
P6
4
3
2
1
0
N9
N8
N7
N6
N5
N4
N3
N2
N1
4
3
2
M6
8
1
0
K9
K8
K7
K5
K4
K3
K2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL_H_BGA_BGA
OF 14
6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NCTFVSS
K1
6
J3
J33
2
J3
J25
2
J2
J18
0
J1
J7
J4
H35
2
H3
5
H2
2
H2
8
H1
2
H1
1
H1
8
G2
6
G2
4
G2
3
G2
2
G2
G2
0
8
G1
G1
6
4
G1
G1
2
0
G1
G9
G8
G6
G5
G4
6
F3
1
F3
9
F2
7
F2
F25
3
F2
F21
9
F1
F17
5
F1
F13
1
F1
F9
F8
F5
F4
F3
F2
8
E3
5
E3
4
E3
E9
E4
3
D3
D3
0
8
D2
D2
6
4
D2
D2
2
0
D2
D1
8
6
D1
D1
4
2
D1
0
D1
D9
D6
D3
7
C3
C31
9
C2
C27
D38
Processor Strapping
U41L
SKYL
AKE_HALO
BGA1440
7
C1
VSS
3
C1
VSS
C9
VSS
32
BT
VSS
BT26
VSS
24
BT
VSS
BT21
VSS
18
BT
VSS
BT14
VSS
12
BT
VSS
BT9
VSS
5
BT
VSS
36
BR
VSS
34
BR
VSS
29
BR
VSS
26
BR
VSS
24
BR
VSS
21
BR
VSS
18
BR
VSS
14
BR
VSS
12
BR
VSS
7
BR
VSS
BP3
4
VSS
3
BP3
VSS
BP2
9
VSS
6
BP2
VSS
BP2
4
VSS
1
BP2
VSS
BP1
8
VSS
4
BP1
VSS
BP1
2
VSS
BP7
VSS
34
BN
VSS
31
BN
VSS
30
BN
VSS
29
BN
VSS
24
BN
VSS
BN21
VSS
20
BN
VSS
BN19
VSS
18
BN
VSS
BN14
VSS
12
BN
VSS
BN9
VSS
7
BN
VSS
BN4
VSS
2
BN
VSS
38
BM
VSS
35
BM
VSS
28
BM
VSS
27
BM
VSS
26
BM
VSS
23
BM
VSS
21
BM
VSS
13
BM
VSS
12
BM
VSS
9
BM
VSS
BM
6
VSS
2
BM
VSS
BL
29
VSS
9
BK2
VSS
BK1
5
VSS
4
BK1
VSS
BJ
32
VSS
31
BJ
VSS
BJ
25
VSS
22
BJ
VSS
14
BH
VSS
12
BH
VSS
9
BH
VSS
8
BH
VSS
5
BH
VSS
BH4
VSS
1
BH
VSS
BG38
VSS
13
BG
VSS
BG12
VSS
33
BF
VSS
BF12
VSS
9
BE2
VSS
BE6
VSS
BD9
VSS
BC34
VSS
BC12
VSS
BB12
VSS
SKL_H_BGA_BGA
e CFG signals have a default value of '1' if not terminated on the board.
Th
NCT
NCT
NCT
NCT
NCTFVSS
NCT
12
OF 14
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FVSS
FVSS
FVSS
FVSS
FVSS
C2
C2
C21
C1
C15
C1
C8
C5
BM29
BM
BM18
BM
BM
BM
BM
BM
BL
BL
BL
BL
BK2
BK2
BK1
BK6
BJ
BJ
BJ
BJ
BH
BH
BH
BH
BH
BH
BG
BG
BG
BF34
BF
BE30
BE5
BE4
BE3
BE2
BE1
BD38
BD
BD
BD
BD
BD
BD
BD
BC
BC
BC
BC
BB3
BB2
BB6
BB5
C2
BT36
BT35
BT4
BT3
BR38
5
3
9
1
25
11
8
7
5
3
38
35
13
6
5
2
3
30
29
15
12
11
10
7
6
3
2
37
14
6
6
37
12
11
10
8
7
6
33
14
13
6
0
9
1 0
FG2
A A
C
(PEG Static Lane Reversal)
FG4
C
(DP Presence Strap)
C
FG7
(PEG Defer Training)
5
Normal Operation Lane Reversed
Disable; No physical DP attached to eDP
PEG
train immediately following
xxRESETB de assertion
4
Enable; An ext DP device is connected to eDP
PEG
wait for BIOS training
Haswell Processor (RESERVED, CFG)
SKYLAKE_HALO
A1440
BG
11
OF 14
CP
U_2_PCH_TRIG
CP
U_2_PCH_TRIG 15
G[6:5] (PCIE Port Bifurcation S traps)
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Cu
Cu
Cu
stom
stom
stom
Date: Sheet
Date: Sheet
Date: Sheet
TP
95
TP
98
96
TP
94
TP
TP
97
TP
93
CP
CP
U_2_PCH_TRIG_R
R1
24 *1K_4
R1
28 1K_4
R580 1K_4
R5
82 *1K_4
R5
83 *1K_4
R5
81 *1K_4
R5
84 *1K_4
R5
85 *1K_4
U_2_PCH_TRIG_R
U41K
D1
RSVD_TP
E1
VD_TP
RS
E3
RSVD_TP
E2
VD_TP
RS
BR1
RS
VD_TP
BT2
RSVD_TP
BN35
RSVD
J24
VD
RS
H24
RS
VD
BN33
VD
RS
BL34
RS
VD
N29
VD
RS
R14
VD
RS
AE29
VD
RS
AA14
VD
RS
A36
RS
VD
A37
VD
RS
H23
OC_TRIGIN
PR
J23
PR
OC_TRIGOUT
F30
RS
VD
E30
RS
VD
B30
RS
VD
C30
VD
RS
G3
VD
RS
J3
RS
VD
BR35
VD
RS
BR31
RSVD
BH30
RS
VD
SKL_H_BGA_BGA
9130_4
R5
CF
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
2
08
BM33
RSVD_TP
BL33
VD_TP
RS
BJ14
VD_TP
RS
BJ13
RSVD_TP
BK28
RSVD
BJ28
RS
VD
18
BJ
VSS
BJ16
RS
VD_TP
BK16
VD_TP
RS
BK24
VD_TP
RS
BJ24
VD_TP
RS
BK21
VD
RS
BJ21
VD
RS
BT17
VD
RS
BR17
RS
VD
BK1
8
VSS
BJ34
RS
VD_TP
BJ33
RS
VD_TP
G13
RS
VD
AJ8
VD
RS
BL31
RS
VD
B2
NCTF
B38
F
NCT
BP1
NCTF
BR2
F
NCT
C1
NCTF
C38
NCT
F
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
B 5/5 (GND)
B 5/5 (GND)
B 5/5 (GND)
SN
SN
SN
1
TP
TP
TP
TP21
TP
TP
TP
TP
TP
TP
89
90
22
14
15
16
13
25
92
1A
1A
1A
of
of
of
849Tuesday, September 08, 2015
849Tuesday, September 08, 2015
849Tuesday, September 08, 2015
Page 9
5
4
3
2
1
U45B
IECOMP_P
L27
DM
I_RXN0
N27
I_RXP0
DM
C27
DM
I_TXN0
B27
I_TXP0
DM
E24
DMI_RXN1
G24
I_RXP1
DM
B28
DMI_TXN1
A28
I_TXP1
DM
G27
DMI_RXN2
E26
DM
I_RXP2
B29
DMI_TXN2
C29
DM
I_TXP2
L29
DMI_RXN3
K29
DM
I_RXP3
B30
I_TXN3
DM
A30
DM
I_TXP3
B18
PC
IE_RCOMPN
C17
IE_RCOMPP
PC
H15
IE1_RXN/USB3_7_RXN
PC
G15
IE1_RXP/USB3_7_RXP
PC
A16
IE1_TXN/USB3_7_TXN
PC
B16
IE1_TXP/USB3_7_TXP
PC
B19
PC
IE2_TXN/USB3_8_TXN
C19
IE2_TXP/USB3_8_TXP
PC
E17
PC
IE2_RXN/USB3_8_RXN
G17
IE2_RXP/USB3_8_RXP
PC
L17
PC
IE3_RXN/USB3_9_RXN
K17
PC
IE3_RXP/USB3_9_RXP
B20
PC
IE3_TXN/USB3_9_TXN
C20
PC
IE3_TXP/USB3_9_TXP
E20
PC
IE4_RXN/USB3_10_RXN
G19
PC
IE4_RXP/USB3_10_RXP
B21
IE4_TXN/USB3_10_TXN
PC
A21
PC
IE4_TXP/USB3_10_TXP
K19
IE5_RXN
PC
L19
PC
IE5_RXP
D22
IE5_TXN
PC
C22
PCIE5_TXP
G22
IE6_RXN
PC
E22
PCIE6_RXP
B22
IE6_TXN
PC
A23
PCIE6_TXP
L22
PC
IE7_RXN
K22
PCIE7_RXP
C23
PC
IE7_TXN
B23
PCIE7_TXP
K24
PC
IE8_RXN
L24
IE8_RXP
PC
C24
PC
IE8_TXN
B24
IE8_TXP
PC
SPT_PCH_H
I_TXN03
DM
DM
I_TXP03
DM
I_RXN03
DM
I_RXP03
I_TXN13
DM
I_TXP13
DM
DM
I_RXN13
DM
I_RXP13
I_TXN23
D D
PC
IE_RXN3_WLAN34
IE_RXP3_WLAN34
WL
AN
LAN
C C
PC
IE_TXN3_WLAN34
PC
PC
IE_TXP3_WLAN34
IE_RXN4_LAN31
PC
PC
IE_RXP4_LAN31
IE_TXN4_LAN31
PC
PC
IE_TXP4_LAN31
DM
I_TXP23
DM
I_RXN23
DM
DM
I_RXP23
DM
I_TXN33
DM
I_TXP33
I_RXN33
DM
I_RXP33
DM
90 100/F_4
R6
C8
70 0.1U/16V_4
C8
69 0.1U/16V_4
72 0.1U/16V_4
C8
C8
71 0.1U/16V_4
PCIECOMP_N
PC
IE_TXN3_WLAN_C
PC
IE_TXP3_WLAN_C
PC
IE_TXN4_LAN_C
PC
PC
IE_TXP4_LAN_C
SPT-H_PCH
I
DM
PC
Ie/USB 3
USB 2.0
OF 12
2
GP
P_E9/USB2_OC0#
GP
P_E10/USB2_OC1#
GP
P_E11/USB2_OC2#
P_E12/USB2_OC3#
GP
GP
P_F15/USB2_OCB_4
P_F16/USB2_OCB_5
GP
GP
P_F17/USB2_OCB_6
P_F18/USB2_OCB_7
GP
USB2_COMP
B2_VBUSSENSE
US
RSVD_AB13
GP
US
B2N_1
B2P_1
US
US
B2N_2
B2P_2
US
USB2N_3
B2P_3
US
USB2N_4
B2P_4
US
USB2N_5
US
B2P_5
USB2N_6
US
B2P_6
USB2N_7
US
B2P_7
B2N_8
US
US
B2P_8
B2N_9
US
US
B2P_9
B2N_10
US
B2P_10
US
B2N_11
US
B2P_11
US
B2N_12
US
B2P_12
US
US
B2N_13
B2P_13
US
US
B2N_14
B2P_14
US
US
D7/RSVD
B2_ID
AF5
AG7
AD5
AD7
AG8
AG10
AE1
AE2
AC2
AC3
AF2
AF3
AB3
AB2
AL8
AL7
AA1
AA2
AJ8
AJ7
W2
W3
AD3
AD2
V2
V1
Ch
ange DGPU_PRSNT# to GPU_EVENT#_20141203
AJ11
AJ13
AD43
B_OC0#
US
AD42
B_OC1#
US
AD39
US
B_OC2#
AC44
B_OC3#
US
Y43
US
B_OC4#
Y41
B_OC5#
US
W44
B_OC6#
US
W43
US
B_OC7#
AG3
B2_COMP
US
AD10
AB13
AG2
BD14
BP0- 36
US
US
BP0+ 36
US
BP1- 36
US
BP1+ 36
BP4- 36
US
US
BP4+ 36
US
BP6- 34
US
BP6+ 34
US
BP7- 29
BP7+ 29
US
US
BP8- 29
USBP8+ 29
US
BP9- 36
BP9+ 36
US
B_OC0# 36
US
B_OC1# 36
US
US
B_OC2# 36
41 113/F_4
R6
R4
85 1K_4
42 1K_4
R6
MB USB3.0
USB3.0
MB
DB USB2.0
BT
Touch Screen
CCD
Card reader
Port1
Port2
Port5
US
US
US
US
US
US
US
US
B_OC0#
B_OC1#
B_OC2#
B_OC3#
B_OC4#
B_OC5#
B_OC6#
B_OC7#
R7
6110K_4
R7
6010K_4
R7
5910K_4
8210K_4
R7
R7
5810K_4
R78110K_4
R7
8010K_4
R7
5710K_4
V_DEEP_SUS
+3
09
V
-H_PCH
B B
US
B3_TXN136
US
B3_TXP136
B3_RXN136
USB3.0 (M/B-2)
USB3.0 (M/B-1)
A A
5
US
US
B3_RXP136
US
B3_TXN036
US
B3_TXP036
B3_RXN036
US
USB3_RXP036
4
U45F
C11
B3_1_TXN
US
B11
US
B3_1_TXP
B7
B3_1_RXN
US
A7
US
B3_1_RXP
B12
USB3_2_TXN/SSIC_1_TXN
A12
B3_2_TXP/SSIC_1_TXP
US
C8
USB3_2_RXN/SSIC_1_RXN
B8
B3_2_RXP/SSIC_1_RXP
US
B15
US
B3_6_TXN
C15
USB3_6_TXP
K15
US
B3_6_RXN
K13
USB3_6_RXP
B14
USB3_5_TXN
C14
USB3_5_TXP
G13
USB3_5_RXN
H13
USB3_5_RXP
D13
USB3_3_TXP/SSIC_2_TXP
C13
USB3_3_TXN/SSIC_2_TXN
A9
USB3_3_RXP/SSIC_2_RXP
B10
USB3_3_RXN/SSIC_2_RXN
B13
USB3_4_TXP
A14
USB3_4_TXN
G11
USB3_4_RXP
E11
USB3_4_RXN
SPT_PCH_H
SPT
LPC/eSPI
US
B
SATA
OF 12
6
GP
P_A1/LAD0/ESPI_IO0
P_A2/LAD1/ESPI_IO1
GP
GP
P_A3/LAD2/ESPI_IO2
P_A4/LAD3/ESPI_IO3
GP
P_A5/LFRAME#/ESPI_CS0#
GP
GPP_A6/SERIRQ/ESPI_CS1#
P_A7/PIRQA#/ESPI_ALERT0#
GP
GPP_A0/RCIN#/ESPI_ALERT1#
GP
P_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_G19/SMI#
GPP_G18/NMI#
GPP_E6/DEVSLP2
GPP_E5/DEVSLP1
GPP_E4/DEVSLP0
GPP_F9/DEVSLP7
GPP_F8/DEVSLP6
GPP_F7/DEVSLP5
GPP_F6/DEVSLP4
GPP_F5/DEVSLP3
3
Add board ID_20141 20 3
AT22
AV22
AT19
BD16
BE16
BA17
IR
Q_SERIRQ
AW17
BO
ARD_ID8
AT17
BC18
BC17
K_PCI_EC_R
CL
AV19
CL
K_PCI_LPC_R
M45
N43
AE45
AG43
AG42
AB39
AB36
AB43
AB42
AB41
SI
DE
VSLP2
VSLP1
DE
DE
VSLP0
LP
C_LAD0 33,34,37
LP
C_LAD1 33,34,37
LP
C_LAD2 33,34,37
C_LAD3 33,34,37
LP
LPC_LFRAME# 33,34,37
O_EXT_SMI# 12,37
TP
105
DE
VSLP0 33,34
IR
Q_SERIRQ 33,37
O_RCIN# 37
SI
_RST# 37
ESPI
88 22/F_4
R6
R2
52 22/F_4
R2
53 22/F_4
EC
19 18P/50V_4
EC
5 18P/50V_4
2
EC6
18P/50V_4
K_PCI_EC 37
CL
CL
K_PCI_LPC 34
EMI(near PCH)
LK_TPM 33
PC
EM
I(near PCH)
IR
Q_SERIRQ
SI
O_RCIN#
SI
O_EXT_SMI#
VSLP0
DE
DE
VSLP1
VSLP2
DE
+3V_DEEP_SUS10,12,13,14,16,17
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Cu
Cu
Cu
stom
stom
stom
PC
PC
PC
Date: Sheet
Date: Sheet
Date: Sheet
54 10K_4
R2
R784 *10K_4
63 *10K_4
R7
R762 *10K_4
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
H 1/6 (DMI/FDI/VIDEO)
H 1/6 (DMI/FDI/VIDEO)
H 1/6 (DMI/FDI/VIDEO)
1
+3
+3
V
R2
5010K_4
R7
5610K_4
1A
1A
1A
of
of
of
949Tuesday, August 25, 2015
949Tuesday, August 25, 2015
949Tuesday, August 25, 2015
Page 10
76 2.2K_4
R7
R7
50 2.2K_4
R7
90 2.2K_4
R7
89 2.2K_4
79 2.2K_4
R7
77 2.2K_4
R7
R6
79 10K_4
92 *10K_4
R6
96 *10K_4
R6
V
+3
+3V
5
C8
R6
70 33_4
R659 33_4
R6
62 33_4
R6
B_ME0_CLK
SM
B_ME0_DAT
SM
SM
B_ME1_CLK
SM
B_ME1_DAT
SM
B_PCH_CLK
B_PCH_DAT
SM
PC
H_BATLOW#
SU
SWARN#
SACK#
SU
C6
08 *220P/50V_4
C884 *220P/50V_4
2N
2N
R3
46 4.7K_4
R355 4.7K_4
VPCU
+3
58 *33P/50V_4
Z_BCLK
AC
AC
Z_RST#
AC
Z_SDOUT
AC
Z_SYNC
66 33_4
R6
67
*1M_4
+3
V_S5
R8
28
8
Q2
*2.2K_4
5
43
2
6
1
*2N7002DW
D_MBCLK
R3
R3
D_MBDATA
Q2
4 3
1
2N7002KDW
On SKL voltage at VCCRTC does not exceed 3.2V
R6
58
*SHORT_4
40 *SHORT_4
51 *SHORT_4
9
1B-1
1 3
12
BT
1
B_ME1_CLK
SM
SM
B_ME1_DAT
V
+3
5
2
6
R671 1K_4
VC
CRTC_3
0
Q6
MMBT3904
2
+3
V_DEEP_SUS
R6
64
*4.7K_4
Z_SDOUT
AC
D_AZACPU_SDO3
AU
D_AZACPU_SDI3
AU
D_AZACPU_SCLK3
AU
DM
DM
MRST#37
RS
SM
BALERT#12
L0ALERT#12
SM
SM
B1ALERT#12,35
R8
31
*2.2K_4
B_ME1_CLK
SM
B_ME1_DAT
SM
SM
B_PCH_DAT
SM
B_PCH_CLK
D3
+3
V_RTC_2
+3V_RTC_1
BAT54C
V_RTC_[0:2]
+3
Trace width = 20 mils
20M
IL
R9
63 4.7K_4
IC_DATA032
IC_CLK032
To
XDP
DDR3-L
CPU heat pipe loca l thermal sensor
DDR thermal sensor
+3
V_RTC
0
VC
CRTC_4
HDA
Bus(CLG)
PC
H_AZ_CODEC_BITCLK32
PC
H_AZ_CODEC_RST#32
H_AZ_CODEC_SDOUT32
PC
H_AZ_CODEC_SYNC32
PC
V_DEEP_SUS
+3
D D
C C
B B
Add PU _20141212
RS
MRST#
EC
_PWROK
D_MBCLK22, 37
2N
2ND_MBDATA22, 37
SM
B_RUN_DAT5,16,17,18,35
B_RUN_CLK5,16,17,18,35
SM
RT
C Circuitry (RTC)
ME
_WR#12,37
H_AZ_CODEC_SDIN032
PC
SYS_
PWROK
R2
BALERT#
SM
SM
L0ALERT#
TP
49
VG
A
EC
uch Pa d
+3V_RTC
Trace width = 30 mils
R6
39
20K/F_4
57
R6
20K/F_4
C8
56
1u/6.3V_4
R9
65 4.7K_4
4
30 30_4
R6
R6
31 *SHORT_4
R6
46 30_4
R7
64 *33_4
06 *33_4
R3
R2
42 *0_4
33 *SHORT_4
54
C8
1u/6.3V_4
C8
55
1u/6.3V_4
V_S5
+5
R9
62
68.1K/F_4
R964
150K/F_4
= *Enable security in the Flash
0
AC
R6
Z_SDOUT
D_AZACPU_SDO_R
AU
D_AZACPU_SDI_R
AU
AU
D_AZACPU_SCLK_R
PC
DS
WROK_EC_R
SM
B_PCH_CLK
SM
B_PCH_DAT
SM
B_ME0_CLK
B_ME0_DAT
SM
SM
B1ALERT#
B_ME1_CLK
SM
SM
B_ME1_DAT
651K_4
AC
AC
AC
AC
DM
DM
RT
SRTC_RST#
EC
_PWROK_R
H_RSMRST#
Z_BCLK
Z_RST#
Z_SDOUT
Z_SYNC
IC_DATA0_R
IC_CLK0_R
C_RST#
Description (iPD 20K)
1 = Disable Flash Descriptor Security (Override)
U45D
BA9
HDA_BCLK
BD8
_RST#
HDA
BE7
_SDI0
HDA
BC8
HDA
_SDI1
BB7
HDA
_SDO
BD9
_SYNC
HDA
BD1
VD_BD1
RS
BE2
RS
VD_BE2
DIO
AM1
AN2
AM2
AL42
AN42
AM43
AJ33
AH44
AJ35
AJ38
AJ42
BC10
BB10
AW11
BA11
AV11
BB41
AW44
BB43
BA40
AY44
BB39
AT27
AW42
AW45
Sy
AU
SPA_SDO
DI
SPA_SDI
DI
SPA_BCLK
DI
GP
P_D8/I2S0_SCLK
P_D7/I2S0_RXD
GP
GPP_D6/I2S0_TXD
P_D5/I2S0_SFRM
GP
GP
P_D20/DMIC_DATA0
GP
P_D19/DMIC_CLK0
GPP_D18/DMIC_DATA1
GP
P_D17/DMIC_CLK1
RT
CRST#
SR
TCRST#
PC
H_PWROK
MRST#
RS
DS
W_PWROK
P_C2/SMBALERT#
GP
P_C0/SMBCLK
GP
P_C1/SMBDATA
GP
GP
P_C5/SML0ALERT#
GP
P_C3/SML0CLK
GPP_C4/SML0DATA
P_B23/SML1ALERT#/P CHHOT#
GP
P_C6/SML1CLK
GP
GP
P_C7/SML1DATA
SPT_PCH_H
stem PWR_OK(CLG)
SPWOK
SY
PWROK16
SYS_
SYS_
EC_PWROK_R
SYS_
PWROK_R
PWROK
SPT
-H_PCH
SM
BUS
For HWPG Sequence
For HWPG Sequence
.0V
+1
19
R8
4
4
U5
*TC7SH08FU
R9
+1
+3
V_S5
70 0_4
*15K/F_4
.0V_PWRGD_G1
95
C8
*0.1U/16V_4
C821 0.1u/16V_4
2
1
3 5
R8
*100K_4
SU
SU
C_RST#
RT
12
J1
*J
RE
->SLP_S4# assertion to
VDDQ(+1.35VSUS) ramp
down start(SUSON)
RTC_RST# 16
UMP
SR
TC_RST#
V:E tPLT15(max 200us)
SUSON
SUSON40,41 VRON42
3
GPP_A12/BMBUSY#/ISH_GP 6/SX_EXIT_HOLDOFF#
JT
AG
OF 12
4
+3
4
3
U4
*TC7SH08FU
R6
20 *0_4
19 *SHORT_4
R6
Non Deep Sx
R243 *SHORT_4
22 *0_4
R6
+5
2
20
SC#
SON_EC
P_A8/CLKRUN#
GP
GP
D11/LANPHYPC
GP
D9/SLP_WLAN#
DRA
P_B2/VRALERT#
GP
P_G17/ADR_COMPLETE
GP
SY
GP
P_B12/SLP_S0#
GP
GP
D4/SLP_S3#
GP
D5/SLP_S4#
GPD10/SLP_S5#
D8/SUSCLK
GP
GP
D0/BATLOW#
GP
P_A15/SUSACK#
GP
P_A13/SUSWARN#/SUSP WRDNACK
GP
D2/LAN_WAKE#
D1/ACPRESENT
GP
GP
D3/PWRBTN#
SY
P_B14/SPKR
GP
PR
IT
V_S5
C8
51 *0.1u/16V_4
2
_PWROK
EC
1
3 5
EC
R6
_PWROK
36*0_4
V_S5
08
R8
*100K_4
2
.0V_PWRGD_G2
+1
9
Q4
*METR3904-G
1 3
SU
SON_EC 37
M_RESET#
GP
GP
GP
S_PWROK
D6/SLP_A#
SLP_LAN#
SL
P_SUS#
S_RESET#
OCPWRGD
P_PMODE
AG_TMS
JT
AG_TDO
JT
JT
AG_TDI
JT
AG_TCK
+3V_S5
3
1
BB17
AW22
AR15
AV13
BC14
DRA
BD23
GP
AL27
P_B1
AR27
P_B0
N44
AN24
P_B11
AY1
SYS_
BC13
WA
KE#
BC15
AV15
BC26
AW15
BD15
BA13
AN15
SU
BD13
PC
BB19
SU
BD19
SU
BD11
PC
BB15
AC
BB13
SLP_SUS#_EC
AT13
DNB
AW1
SYS_
BD26
AC
AM3
PR
AT2
AR3
JTAGX
AR2
JT
AG_TMS_PCH
AP1
AG_TDO_PCH
JT
AP2
JT
AG_TDI_PCH
AN3
JT
AG_TCK_PCH
EC
_PWROK 37
IM
VP_PWRGD_3V 2
R6
25
*10K_4
PC
H_PWROK 2,37
R8
22
*10K_4
HW
PG_R
8
Q4
R806
*2N7002K
*100K_4
REV:E tPLT17(max
200us) ->SLP_S3#
assertion to IMVP
VR_ON(VRON) deassert ion
SYS_RESET#
P_B2
GP
CL
KRUN#
LA
N_DISABLE
M_RESET#
P_B2
PWROK_R
PC
IE_WAKE#
PC
H_SLP_S0_N
SCLK
H_BATLOW#
SACK#
SWARN#
IE_LAN_WAKE#
PRESENT
SWON#
RESET#
Z_SPKR
OCPWRGD
R8
09 *0_4
R6
511K_4
R6
R210 10K_4
R7
16 10K_4
TP
TP
35 *SHORT_4
TP
R645 *10K_4
+1
+3
4
6
U5
*TC7SH08FU
R9
72 0_4
+3
KRUN# 33,37
CL
43
37
SYS_
PWROK
PC
SL
PC
SU
SU
SL
SU
102
97*0_4
R6
93*0_4
R6
91*SHORT_4
SU
R6
AC
V_S5
AGX_PCH 2,16
JT
JTAG_TMS_PCH 16
AG_TDO_PCH 16
JT
JT
AG_TDI_PCH 16
JT
AG_TCK_PCH 16
PG 2,37
HW
V_S5
C831 0.1u/16V_4
2
1
VR
3 5
2
V
+1
IE_WAKE# 31,34
P_A# 16
H_SLP_S0_N 16,37
SB# 2,16,37,39
SC# 16,37
P_S5# 16
Ad
SCLK 34
SACK#_EC 37
SU
SU
SWARN#_EC 37
SWARN#
IE_LAN_WAKE# 31
PC
PRESENT 37
AC
SL
P_SUS#_EC 37
DNB
SWON# 37
SYS_
RESET# 16
Z_SPKR 12,32
OCPWRGD 2
PR
V_S5
+3
V_S5
+3
V
+3
SB#
SU
ON_EC
.2VSUS
12
R6
81
DRA
470_4
R6
82 *short_4
d SSD _20141 210
For DS3 Sequence
For DS3 -->Ra
Non-DS3 -->Rb
H_RSMRST#
PC
WROK_C37
DP
Add PU _20141212
78 1K_4
R6
R6
80 10K_4
89 10K_4
R6
62 *10K_4
R2
R2
67 10K_4
PC
H_RSMRST#
R2
32 10K_4
WROK_C
25 100K_4
DP
R2
SYS_
R2
PWROK_R
09 10K_4
VR
ON_EC 37
MRST
12
*0.1u/16V_4
+1
R6
23
*SHORT_4
34
R6
*210/F_4
R6
50
*100/F_4
Rb
R2
23 *SHORT_4
R2
24 *0_4
Ra
IE_LAN_WAKE#
PC
PC
IE_WAKE#
AC
PRESENT
KRUN#
CL
REV:E tPLT18(max 200 us)
->SLP_S3# assertion to
VCCIO VR(MAIND for +1 V_S5
to +VCCIO) disabled
MAINON41,45
1
10
_DRAMRST# 17,18
DDR3
68
C8
+V
.0V
CCSTPLL
R6
21
*0_4
33
32
R6
R6
*210/F_4
51_4
JT
AG_TMS_PCH
JTAG_TDI_PCH
JT
AG_TDO_PCH
AG_TCK_PCH
JT
R6
R6
R6
*100/F_4
49
48
*100/F_4
DS
WROK_EC_R
4
5
U5
*TC7SH08FU
R9
*51_4
V_S5
+3
3 5
71 0_4
47
C824 0.1u/16V_4
2
1
MA
SB#
SU
INON_EC
MA
INON_EC 37
A A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
PCH 2/6 (SATA/HDA/ SPI)
PCH 2/6 (SATA/HDA/ SPI)
PCH 2/6 (SATA/HDA/ SPI)
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
1A
1A
1A
10 49Monday, September 07, 2015
10 49Monday, September 07, 2015
10 49Monday, September 07, 2015
of
of
of
Page 11
5
D D
PEG_TXP11_L134
PEG
_TXN11_L134
PEG
_RXP11_L134
PEG
_RXN11_L134
_TXP12_L334
PEG
_TXN12_L334
PEG
PEG_RXP12_L334
PEG
C C
100
TP
C8
6512P/50V_4
1
2
R6
HZ +-30PPM
24M
TP
B B
73
1M_4
Y4
4
3
6212P/50V_4
C8
99
+1.0V_DEEP_SUS change to +1V_S5
Add XC LK_RNIAS# po rt_20 141205
C Clock 32.768KHz
RT
A A
61 18P/5 0V_4
C8
32.
C864 18P /50V_4
Y3
768KHz
C_X1
RT
12
75
R6
10M_4
RTC_X2
5
24M X'tral--->R2602 (Ra) Un-Install
XT
AL24_IN
Green CLK--->R2602 (Ra) Install
AL24_OUT
XT
K_PEGA_REQ#19
CL
IE_CLKREQ_WLAN#34
PC
CL
K_PCIE_LAN_REQ#31
PCIE_CLKREQ_NGFF1#34
_RXN12_L334
+1
V_S5
24 *SHORT_4
R3
76 *SHORT_4
R2
R724 *SHORT_4
58 *SHORT_4
R4
CL
K_DPLL_NSCCLKP2
CL
K_DPLL_NSCCLKN2
CL
CL
R6
68 2.7K/F_4
K_CPU_BCLKP2
K_CPU_BCLKN2
4
PEG
_TXP11_L1
_TXN11_L1
PEG
_RXP11_L1
PEG
_RXN11_L1
PEG
PEG
_TXP12_L3
PEG
_TXN12_L3
PEG
_RXP12_L3
_RXN12_L3
PEG
XTAL24_OUT
XT
XC
LK_RBIAS
RT
C_X1
C_X2
RT
IE_CLKREQ0#
PC
PCIE_CLKREQ1#
PC
IE_CLKREQ2#
PCIE_CLKREQ3#
IE_CLKREQ4#
PC
IE_CLKREQ5#
PC
PC
IE_CLKREQ6#
IE_CLKREQ7#
PC
PC
IE_CLKREQ8#
IE_CLKREQ9#
PC
PC
IE_CLKREQ10#
PC
IE_CLKREQ11#
PC
IE_CLKREQ12#
PC
IE_CLKREQ13#
PCIE_CLKREQ14#
IE_CLKREQ15#
PC
4
AL24_IN
U45C
AV2
_CLK
CL
AV3
CL
_DATA
AW2
CL
_RST#
R44
G
PP_G8/FAN_PWM_0
R43
PP_G9/FAN_PWM_1
G
U39
G
PP_G10/FAN_PWM_2
N42
G
PP_G11/FAN_PWM_3
U43
G
PP_G0/FAN_TACH_0
U42
G
PP_G1/FAN_TACH_1
U41
PP_G2/FAN_TACH_2
G
M44
PP_G3/FAN_TACH_3
G
U36
G
PP_G4/FAN_TACH_4
P44
PP_G5/FAN_TACH_5
G
T45
G
PP_G6/FAN_TACH_6
T44
PP_G7/FAN_TACH_7
G
B33
PC
IE11_TXP
C33
PCIE11_TXN
K31
IE11_RXP
PC
L31
PC
IE11_RXN
AB33
PP_F10/SCLOCK
G
AB35
G
PP_F11/SLOAD
AA44
PP_F13/SDATAOUT0
G
AA45
G
PP_F12/SDATAOUT1
B38
IE14_TXN/SATA1B_T XN
PC
C38
PC
IE14_TXP/SATA1B_T XP
D39
PC
IE14_RXN/SATA1B_RXN
E37
IE14_RXP/SATA1B_RXP
PC
C36
PC
IE13_TXN/SATA0B_T XN
B36
IE13_TXP/SATA0B_T XP
PC
G35
PC
IE13_RXN/SATA0B_RXN
E35
IE13_RXP/SATA0B_RXP
PC
A35
PC
IE12_TXP
B35
IE12_TXN
PC
H33
PC
IE12_RXP
G33
PC
IE12_RXN
J45
IE20_TXP/SATA7_T XP
PC
K44
PC
IE20_TXN/SATA7_T XN
N38
IE20_RXP/SATA7_RXP
PC
N39
PC
IE20_RXN/SATA7_RXN
H44
PC
IE19_TXP/SATA6_T XP
H43
IE19_TXN/SATA6_T XN
PC
L39
PC
IE19_RXP/SATA6_RXP
L37
PCIE19_RXN/SATA6_RXN
SPT_PCH_H
AR17
GP
G1
CL
F1
CL
G2
CL
H2
CL
A5
XT
A6
XT
E1
XC
BC9
RT
BD10
RT
BC24
GP
AW24
GPP_B6/SRCCLKREQ1#
AT24
GP
BD25
GP
BB24
GP
BE25
GP
AT33
GP
AR31
GP
BD32
GPP_H2/SRCCLKREQ8#
BC32
GP
BB31
GP
BC33
GP
BA33
GP
AW33
GP
BB33
GP
BD33
GPP_H9/SRCCLKREQ15#
R13
CL
R11
CL
P1
CL
R2
CL
W7
CL
Y5
CL
U2
CL
U3
CL
U45G
P_A16/CLKOUT_48
KOUT_CPUNSSC_P
KOUT_CPUNSSC
KOUT_CPUBCLK_P
KOUT_CPUBCLK
AL24_OUT
AL24_IN
LK_BIASREF
CX1
CX2
P_B5/SRCCLKREQ0#
P_B7/SRCCLKREQ2#
P_B8/SRCCLKREQ3#
P_B9/SRCCLKREQ4#
P_B10/SRCCLKREQ5#
P_H0/SRCCLKREQ6#
P_H1/SRCCLKREQ7#
P_H3/SRCCLKREQ9#
P_H4/SRCCLKREQ10#
P_H5/SRCCLKREQ11#
P_H6/SRCCLKREQ12#
P_H7/SRCCLKREQ13#
P_H8/SRCCLKREQ14#
KOUT_PCIE_N15
KOUT_PCIE_P15
KOUT_PCIE_N14
KOUT_PCIE_P14
KOUT_PCIE_N13
KOUT_PCIE_P13
KOUT_PCIE_N12
KOUT_PCIE_P12
SPT_PCH_H
3
SPT-H_PCH
G31
SAT
CL
INK
FAN
-H_PCH
SPT
7
PC
Ie/SATA
ST
HO
3 OF 12
CL
KOUT_CPUPCIBCLK_P
CL
OF 12
GP
GP
GP
G
G
G
G
G
CL
KOUT_CPUPCIBCLK
CL
CLKOUT_PCIE_P10
CL
CLKOUT_PCIE_P11
PC
IE9_RXN/SATA0A_RXN
PC
IE9_RXP/SATA0A_RXP
IE9_TXN/SATA0A_T XN
PC
PC
IE9_TXP/SATA0A_T XP
PC
IE10_RXN/SATA1A_RXN
PC
IE10_RXP/SATA1A_RXP
IE10_TXN/SATA1A_T XN
PC
PC
IE10_TXP/SATA1A_T XP
IE15_RXN/SATA2_RXN
PC
IE15_RXP/SATA2_RXP
PC
PC
IE15_TXN/SATA2_T XN
IE15_TXP/SATA2_T XP
PC
IE16_RXN/SATA3_RXN
PC
IE16_RXP/SATA3_RXP
PC
PC
IE16_TXN/SATA3_T XN
PCIE16_TXP/SATA3_T XP
PC
IE17_RXN/SATA4_RXN
PC
IE17_RXP/SATA4_RXP
IE17_TXN/SATA4_T XN
PC
PC
IE17_TXP/SATA4_T XP
PC
IE18_RXN/SATA5_RXN
PC
IE18_RXP/SATA5_RXP
IE18_TXN/SATA5_T XN
PC
PC
IE18_TXP/SATA5_T XP
P_E8/SATALED#
GP
P_E0/SATAXPCIE0/SATAGP0
P_E1/SATAXPCIE1/SATAGP1
P_E2/SATAXPCIE2/SATAGP2
PP_F0/SATAXPCIE3/SATAGP3
PP_F1/SATAXPCIE4/SATAGP4
PP_F2/SATAXPCIE5/SATAGP5
PP_F3/SATAXPCIE6/SATAGP6
PP_F4/SATAXPCIE7/SATAGP7
G
PP_F21/EDP_BKLTCTL
PP_F20/EDP_BKLTEN
G
G
PP_F19/EDP_VDDEN
TH
ERMTRIP#
_SYNC
PM
PL
TRST_PROC#
PM_DOWN
L1
KOUT_ITPXDP
CL
KOUT_ITPXDP_P
KOUT_PCIE_N0
CL
KOUT_PCIE_P0
CL
KOUT_PCIE_N1
CL
CL
KOUT_PCIE_P1
KOUT_PCIE_N2
CL
CL
KOUT_PCIE_P2
CL
KOUT_PCIE_N3
CLKOUT_PCIE_P3
KOUT_PCIE_N4
CL
KOUT_PCIE_P4
CL
CL
KOUT_PCIE_N5
KOUT_PCIE_P5
CL
CL
KOUT_PCIE_N6
KOUT_PCIE_P6
CL
CL
KOUT_PCIE_N7
CL
KOUT_PCIE_P7
CLKOUT_PCIE_N8
CL
KOUT_PCIE_P8
KOUT_PCIE_N9
CL
CL
KOUT_PCIE_P9
KOUT_PCIE_N10
KOUT_PCIE_N11
L2
J1
J2
N7
N8
L7
L5
D3
F2
E5
G4
D5
E6
D8
D7
R8
R7
U5
U7
W10
W11
N3
N2
P3
P2
R3
R4
H31
C31
B31
G29
E29
C32
B32
F41
E41
B39
A39
D43
E42
A41
A40
H42
H40
E45
F45
K37
G37
G45
G44
AD44
AG36
AG35
AG39
AD35
AD31
AD38
AC43
AB44
W36
W35
W42
AJ3
AL3
PEC
I
AJ4
AK2
AH2
_XDP_N_R
CK
_XDP_P_R
CK
A_RXN3/PEG_RXN9_L0
SATA_RXP3/PEG_RXP9_L0
SAT
A_TXN3/PEG_TXN9_L0
SAT
A_TXP3/PEG_TXP9_L0
A_RXN1/PEG_RXN10_L2
SAT
SAT
A_RXP1/PEG_RXP10_L2
A_TXN1/PEG_TXN10_L2
SAT
A_TXP1/PEG_TXP10_L2
SAT
SAT
A_LED#
83 10K_4
R7
IO37
GP
IO34
GP
GPIO35
GPIO36
PCH_THRMTRIP_R#
PM_SYNC_R
H_
PM_DOWN
61 *short_4
R6
56 *short_4
R6
CP
CP
TP
TP
CL
CL
CL
CL
TP
TP40
TP44
TP
TP
TP
CL
CL
R643 30_4
R6
28 *SHORT_4
U_PCI_BCLKN 2
U_PCI_BCLKP 2
K_PCIE_VGA# 19
CL
K_PCIE_VGA 19
CL
47
42
K_PCIE_WLA NN 34
K_PCIE_WLA NP 34
K_PCIE_LANN 31
K_PCIE_LANP 31
39
41
69
68
K_PCIE_NGFF1_N 34
K_PCIE_NGFF1_P 34
TP
110
52
TP
PC
H_BRIGHT 29
PC
H_BLON 29
ED
P_VDD_EN 29
R627 620_ 4
_XDP_N
CK
_XDP_P
CK
WL
LAN
SAT
SAT
SAT
SAT
+3
V
6 0_4
R8
5 *0_4
R8
R461 *0_4
R4
59 *0_4
_SYNC 2
PM
U_PLTRST#R 2
CP
PM_DOWN 2
H_
CK
CK
A
VG
AN
FF SSD
NG
A_RXN3/PEG_RXN9_L0 34
SAT
A_RXP3/PEG_RXP9_L0 34
SAT
A_TXN3/PEG_TXN9_L0 34
SAT
A_TXP3/PEG_TXP9_L0 34
SAT
SAT
A_RXN1/PEG_RXN10_L2 34
SAT
A_RXP1/PEG_RXP10_L2 34
SAT
A_TXN1/PEG_TXN10_L2 34
SAT
A_TXP1/PEG_TXP10_L2 34
A_RXN0 33
A_RXP0 33
A_TXN0 33
A_TXP0 33
_THRMTRIP# 2,5,17,18
PM
_XDP_N 1 6
_XDP_P 16
2
M.2.SSD
HDD (SATA0 6Gb/s)
FF3_DET 34
NG
H_PECI 2
PC
R6
44
*10K_4
PC
IE_CLKREQ4#
PCIE_CLKREQ1#
PCIE_CLKREQ0#
IE_CLKREQ2#
PC
IE_CLKREQ3#
PC
IE_CLKREQ5#
PC
PC
IE_CLKREQ6#
PC
IE_CLKREQ7#
IE_CLKREQ8#
PC
IE_CLKREQ9#
PC
PC
IE_CLKREQ10#
PC
IE_CLKREQ11#
PC
IE_CLKREQ12#
PCIE_CLKREQ13#
PCIE_CLKREQ14#
IE_CLKREQ15#
PC
GP
IO37
IO34
GP
IO35
GP
IO36
GP
0821*10K_4
R1
R7
R275 *10K_4
R718 10K_4
R2
R7
R7
R3
R3
R7
R7
R7
R7
R3
R316 *10K_4
R7
R7
0818*10K_4
0819*10K_4
0820*10K_4
R1
R1
R1
19 *10K_4
78 10K_4
23 10K_4
21 *10K_4
18 *10K_4
17 10K_4
36 *10K_4
35 *10K_4
31 *10K_4
39 *10K_4
15 *10K_4
38 *10K_4
34 *10K_4
R1
0814 10K _4
0816 10K _4
R1
0817 10K _4
R1
0815 10K _4
R1
+3
V
1
11
+3
V
Change from I to NI(For SCH List) _20141212
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Cu
Cu
Cu
stom
stom
stom
PC
PC
PC
H 3/6 (PCIE/USB/CLK)
H 3/6 (PCIE/USB/CLK)
H 3/6 (PCIE/USB/CLK)
Date: Sheet
Date: Sheet
3
2
Date: Sheet
1
1A
1A
1A
of
of
of
11 49Tuesday, Augu st 25, 2015
11 49Tuesday, Augu st 25, 2015
11 49Tuesday, Augu st 25, 2015
Page 12
5
TRST# Buffer
PL
TRST#(CLG)
PL
-H_PCH
D D
SI
O_EXT_SMI#9,37
C C
SP@
socket P/N: DFHS08FS023 only for A-TEST
SPI
ROM
ylake
Sk
3.3V
B B
Skylake
3.3V
A A
TP103
PCH_SPI_SI
PC
H_SPI_SO
H_SPI_CS0#
PC
H_SPI_CLK
PC
PCH_SPI_CS1#
PC
H_SPI_IO2
H_SPI_IO3
PC
O_EXT_SMI#
SI
Ve
nder Siz e Quanta P/N Vender P/N
EO
N
D
WN
PC
H_SPI_CLK_EC37
PCH_SPI_SI_EC37
H_SPI_SO_EC37
PC
SPI_CS0#_UR_ME37
V_PCH_ME
+3
16M
8M
8M
8M
AKE3
AKE2
AKE3EZN0Q01
AKE3DZN0N01
R6
94 10K_4
EFP0N07
EZN0Q00
R774 *4M@33_4
48 *4M@33_4
R7
R6
98 *4M@33_4
07 *SHORT_4
R7
R7
11 *4M@0_4
5
AG15
AG14
AF17
AE17
AR19
AN17
BB29
BE30
BD31
BC31
AW31
BC29
BD30
AT31
AN36
AL39
AN41
AN38
AH43
AG44
W2
GD
EN
25QH64-104HIP
W2
SPI_CS0#_UR_ME
GPP_A11/PM E#
RSVD
RSVD
RSVD
RSVD
TP2
TP1
SPI0_MOSI
SPI0_MISO
SPI0_CS0#
SPI0_CLK
SPI0_CS1#
SPI0_IO2
SPI0_IO3
SPI0_CS2#
GPP_D1/SPI1_C LK
GPP_D0/SPI1_C S#
GPP_D3/SPI1_M OSI
GPP_D2/SPI1_M ISO
GPP_D22/SPI1_ IO3
GPP_D21/SPI1_ IO2
SPT_PCH_H
5Q64FVSSIQWND
25B64CSIGRGGD
5Q128FVSIQ
H_SPI_CLK_R
PC
PC
H_SPI_SI_R
PC
H_SPI_SO_R
PC
H_SPI_CS0#
PC
H_SPI_CS1#
U45A
BD17
PCI_PME#
SPT
H_SPI_SO
PC
PCH_SPI_SO_EC
only 0ohm option
GPP_B13/PL TRST#
GPP_G16/GSXCL K
GPP_G12/GSXDOU T
GPP_G13/GSXS LOAD
GPP_G14/GSXDIN
GPP_G15/GSXS RESET#
GPP_E3/CPU_ GP0
GPP_E7/CPU_ GP1
GPP_B3/CPU_ GP2
GPP_B4/CPU_ GP3
GPP_H18/SML 4ALERT#
GPP_H17/SML 4DATA
GPP_H16/SML 4CLK
GPP_H15/SML 3ALERT#
GPP_H14/SML 3DATA
GPP_H13/SML 3CLK
GPP_H12/SML 2ALERT#
GPP_H11/SML 2DATA
GPP_H10/SML 2CLK
1
INTRUDER #
OF 12
H SPI ROM(8M+4M)
PC
15ohm CS01502JB12
33ohm CS03302JB29
PC
H_SPI_CS0#
1A-13
08 8M4M@15_4
R7
09 8M@0_4
R7
+3
V_PCH_ME
3.
3K is original and for no
support fast read function
PC
H_SPI_CS1#
PC
H_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO
76 *22p/50V_4
C8
+3
R710 1K_4
R7
47 *4M@33_4
R7
75 *4M@33_4
R712 *4M@33_4
PC
H_SPI_CLK_R
PCH_SPI_SI_R
PCH_SPI_SO_R
V_PCH_ME
1A-3 2013/10/16 Add U34 flash 4M ROM reserve for ZQ0D.
BB27
P43
R39
R36
R42
R41
AF41
AE44
BC23
BD24
BC36
BE34
BD39
BB36
BA35
BC35
BD35
AW35
BD34
BE11
PCI_PLTRST#
DG
SML4ALERT#
SM
B_ME4_DAT
B_ME4_CLK
SM
L3ALERT#
SM
SMB_ME3_DAT
SMB_ME3_CLK
SM
L2ALERT#
B_ME2_DAT
SM
B_ME2_CLK
SM
SM_INTRUDER#
_SO_8M
SPI
H_SPI_IO2
PC
PCH_SPI_IO3
R7
03 *1K_4
4
PU_PW_CTRL#
+3V_S5
1
2
3
4
SPI_WP_IO2_ME
4
2
1
R3
05 *0_4
DGPU_PW_CTRL# 13
TP107
R6771M_4
R7
54 *SHORT_6
U47
VCC
CS#
IO3/HOLD #
IO1/DO
CLK
IO2/W P#
IO0/DI
GND
W25Q64FW -- 8MB
H_SPI_CLK_EC
PC
PC
H_SPI_SI_EC
R713 *4M@33_4
R702 8M4M@15_4
R7
46 *4M@33_4
R7
73 8M4M@15_4
U46
1
CE#
VDD
6
SCK
5
SI
2
SO
HOLD#
3
WP#
VSS
*4M@ROM-4M_EC
SPI
_WP_IO2_EC
+3
V
C518 0.1u/16V_4
U2
4
3 5
TC7SH08FU
V_RTC
+3
8
7
SPI
6
SPI_CLK_8M
5
SPI
R7
44 8M@15_4
R7
45 8M@15_4
SPI_HOLD_IO3_ME
8
7
SPI_HOLD_IO3_EC
4
3
4
+3V_PCH_ME
_HOLD_IO3_ME
_SI_8M
SPI_WP_IO2_EC
_WP_IO2_ME
SPI
SPI
_HOLD_IO3_EC
PL
TRST# 2,16,19,31,33,34,37
07
R3
100K_4
C873 0.1u/16V_4
43 1K_4
R7
R770 8M4M@15_4
R7
71 8M4M@15_4
reserve for SPI fast read
+3V_PCH_ME
R772 *1K_4 R729
C8
74
*[email protected]/16V_4
V_PCH_ME
+3
PCH_SPI_CLK
H_SPI_SI
PC
C875
*22p/50V_4
SM
SMB_ME4_DAT
SM
SM
SMB_ME2_CLK
SM
R7
B_ME4_CLK
B_ME3_CLK
B_ME3_DAT
B_ME2_DAT
49 499/F_4
37 499/F_4
R7
R741 499/F_4
26 499/F_4
R3
R742 499/F_4
R3
25 499/F_4
TLS CONFIDENTIALITY ENABLED
HIGH:T Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). (CRB)
LOW: Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality). (Default)
BALERT#10
SM
3
+3V_DEEP_SUS
Ad
d PCH Strap Pin_20141203
TOP SWAP OVERRIDE STRAP
HIGH:TOP SWAP ENABLED (CRB)
LOW:TOP SWAP DISABLED(DEFAULT)
AC
Z_SPKR10,32
NO
REBOOT IF SAMPLED HIGH
HIGH:TOP SWAP ENABLED (CRB)
LOW: Disable "No Reboot" mode. (Default)
BBS_
V_DEEP_SUS
+3
R333
4.7K_4
32
R3
*20K/F_4
BIT1
BBS_
BIT113
SMBALERT#
Ch
ange R2725 from I to N_20141212
+3V
R7
*150K/F_4
+3
V
BOOT SELE CT STRAP
HIGH:LPC
LOW: SPI. (Default)
27
R722
*20K/F_4
ESPI
HIGH:eSPI Is selected for EC.
LOW: LPC Is selected for EC. (Default)
R337
4.7K_4
SML0ALERT#10
R336
*20K/F_4
RESERVED
This strap should sample HIGH.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
GPIO13
S_
/LPC SELECT STRAP
SM
L0ALERT#
+3
PCH_SPI_SI
S_GPIO
V_DEEP_SUS
*20K/F_4
28
R7
*4.7K_4
2
+3V_DEEP_SUS
R766
*4.7K_4
R767
*20K/F_4
+3
V_DEEP_SUS
R335
*4.7K_4
R334
4.7K/F_4
CONFIDENTIALITY ENABLED
TLS
HIGH: Flash Descriptor Security (override). This
strap should only be asserted high using external
pull-up in manufacturing/debug environments ONLY.(CRB)
LOW: security measures defined in the Flash
Descriptor. (Default)
2
RESERVED
This strap should sample HIGH.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
PC
H_SPI_SO
RESERVED
This strap should sample LOW.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
SM
SERVED
SERVED
ME
+3
_WR#
B1ALERT#
H_SPI_IO2
PC
PCH_SPI_IO3
V_DEEP_SUS
R6
40
*1K_4
B1ALERT#10,35
SM
RE
This strap should sample HIGH.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
RE
This strap should sample HIGH.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
ME
_WR#10,37
R653
*1K_4
+3
+3
V_DEEP_SUS
1
V_DEEP_SUS
R3
*20K/F_4
R2
*4.7K_4
R2
*4.7K_4
R2
*20K/F_4
+3V_DEEP_SUS
*20K/F_4
R726
*4.7K_4
+3
*20K/F_4
ESPI
01
98
92
94
30
R7
V_DEEP_SUS
R733
R7
32
*100_4
FLASH SHARING MODE
HIGH:SLAVE ATTACEHD FLASH SHARING
LOW: 0: MASTER ATTACHED FLASH SHARING
This strap should sample LOW.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
DFX TEST MODE QUALIFIER FOR OTHER DFX STRAP
WHEN SAMPLED LOW
PGDMON15
X TEST MODE
DF
XTAL INPUT IS SINGLE ENDED IF
SAMPLED LOW ELSE DIFFERENTIAL
PU_PWROK13,21
DG
RING OSCILLATOR BYPASS
PU_HOLD_RST#13,19
DG
DG
PU_PWR_EN13,47
XTAL INPUT FREQUENCY[1]
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Cu
Cu
Cu
stom
stom
stom
H 4/6 (GPIO/MISC)
H 4/6 (GPIO/MISC)
H 4/6 (GPIO/MISC)
PC
PC
PC
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
SML2ALERT#
DMON
PG
DG
PU_PWROK
DGPU_HOLD_RST#
DGPU_PWR_EN
+3V_DEEP_SUS
V_DEEP_SUS
+3
+3
V_DEEP_SUS
R2
*10K_4
12
R751
*4.7K_4
R740
*20K/F_4
66
R2
*1K_4
R264
*1K_4
R2
81
*10K_4
93
R2
*10K_4
R2
*10K_4
88
12 49Monday , S ept ember 07, 201 5
12 49Monday , S ept ember 07, 201 5
12 49Monday , S ept ember 07, 201 5
87
1A
1A
1A
Page 13
5
+3
V
I_SERR#
PC
R7
88*10K_4
V_S5
1
R7
GP
U Control PU/PD
96EV@10K_4
83*10K_4
DG
R3
09*10K_4
DG
PU_PW_CTRL#
DG
DG
PU_PWROK
CRT_HPD
ED
37100K_4
V
+3
2
2N7002K
78 *0_4
VG
PU_EN
PU_PWR_EN
6_FB_EN
GC
PU_HOLD_RST#
P_HPD
24 *10K/F_4
R6
+3
R7
Q4
69TPD@10K_4
3
6
R7
R2
TP
D_INT#_D
15 *IV@1K_4
86 *10K_4
+3
S5
R2
01*IV@10K_4
82*100K_4
R2
R3
13*10K_4
+3
V
V
+3V_DEEP_SUS
ED
P_HPD29
uchpad INT
To
D_INT#_D
TP
TP
D_INT#35,37
+3
V
V
+3
DG
PU_PW_CTRL#12
S5
20131015 For GC6 NV DG GC6_FB_EN PD.1A-1
R274 10K_4
high UMA Only
low
R7
14 EV@100K_4
R1
R2
GPU power is control by PCH
GPIO (Discrete, SG or Optimize)
D D
C C
DGPU_PWROK PD on GPU side
R652100K_4
R6
100k pull-down on PCH side
ylake-H Strapping Table
Sk
B B
A A
n Name Strap description
Pi
GP
P_B14 (SPKR)
GPP_B18
(GSPI0_MOSI)
GPP_C2
(SMBALERT#)
GPP_B22
(GSPI1_MOSI)
GPP_C5
(SML0ALERT#)
SPI0_MOSI
SPI0_MISO
GPP_B23
(SML1ALERT#
/PCHHOT#)
SPI0_IO2
SPI0_IO3
HDA_SDO /
I2S_TXD0
GPP_E19
(DDPB_CTRLDATA)
GPP_E21
(DDPC_CTRLDATA)
Top-Block Swap override PCH_PWROK
No reboot PCH_PWROK
TLS Confidentiality
Boot BIOS Strap Bit (BBS)
eSPI or LPC
Reserved
Reserved
Reserved
Reserved
Reserved
F
lash Descriptor Security
Override / Intel ME Debug Mode
splay Port B Detected
Di
Display Port C Detected
Sa
mpled
RSMRST#
PCH_PWROK
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
PCH_PWROK
PCH_PWROK
PCH_PWROK
0 = *Disable Top Swap (iPD 20K)
1 = Enable Top Swap Mode
0 = *Disable No Reboot (iPD 20K)
1 = Enable No Reboot Mode
0 = *Disable Intel ME Cryp to TLS(iPD 20K)
1 = Enable Intel ME Cryp to TLS
0 = *SPI (iPD 20K)
1 = LPC
0 = *LPC is selected for EC (iPD 20K)
1 = eSPI selected for EC
0 = *Enable security in the Flash
Description (iPD 20K)
1 = Disable Flash Descriptor Security (Override)
0 = *Port B is not detected (iPD 20K)
1 =Port B is detected
0 = *Port C is not detected (iPD 20K)
1 =Port C is detected
4
Ad
d G PU Pow er C on tro l Si gan ls
TP
BBS_
_EXTTS#017
PM
EXT
GPIO12
S_
I_SERR#
To
uch Screen
To
PC
uch PAD
waiting for define!
30 10K_4
P_HPD
ED
AW4
GP
AY2
CRT
_HPD
GP
AV4
GP
BA4
GPP_I3/DDPE_HPD3
BD7
GP
T_HDMI_HPD30
IN
CRT
_HPD28
38
TP
SI
O_EXT_SCI#37
R2
figuration note
Con
(iPU 15 ~ 40K)
(iPU 15 ~ 40K)
(iPD 20K)
(iPU 15 ~ 40K)
(iPU 15 ~ 40K)
DG
PU_HOLD_RST#12,19
DG
147
BIT112
_INT_PCH29
TP
CEL_INTA#35
AC
TS#117
87 *100_4
R7
I2
C1_SCL29
C1_SDA29
I2
C0_SCL35
I2
I2
C0_SDA35
U45E
P_I0/DDPB_HPD0
P_I1/DDPC_HPD1
P_I2/DDPD_HPD2
P_I4/EDP_HPD
SPT_PCH_H
V
+3
+3
V
3
2
V_DEEP_SUS9,10,12,14,16,17
+3
1
13
-H_PCH
U45K
AT29
GS
PI1_MOSI
GP
P_B22/GSPI1_MOSI
GS
PI0_MOSI
D_INT#_D
TP
RT2_CTS
UA
UA
RT2_RTS
UA
RT2_TXD
RT2_RXD
UA
GPP_I7/DDPC_CTRLCLK
P_I8/DDPC_CTRLDATA
GP
P_I5/DDPB_CTRLCLK
GP
GP
P_I6/DDPB_CTRLDAT A
GPP_I9/DDPD_CTRLCLK
GP
P_I10/DDPD_CTRLDATA
GS
GS
PI1_MOSI
AR29
GPP_B21/GSPI1_MISO
AV29
GP
BC27
GP
BD28
GP
BD27
GP
AW27
GP
AR24
GP
AV44
GP
BA41
GP
AU44
GP
AV43
GP
AU41
GP
AT44
GP
AT43
GP
AU43
GPP_C12/UART1_RXD/IS H_UART1_RXD
AN43
GP
AN44
GP
AR39
GP
AR45
GP
AR41
GP
AR44
GP
AR38
GP
AT42
GP
AM44
GP
AJ44
GP
BB3
BD6
BA5
BC4
BE5
BE6
Y44
P_F14
GP
V44
P_F23
GP
W39
GP
P_F22
L43
P_G23
GP
L44
P_G22
GP
U35
GP
P_G21
R35
GP
P_G20
BD36
GP
P_H23
PI0_MOSI
P_B20/GSPI1_CLK
P_B19/GSPI1_CS#
P_B18/GSPI0_MOSI
P_B17/GSPI0_MISO
P_B16/GSPI0_CLK
P_B15/GSPI0_CS#
P_C9/UART0_TXD
P_C8/UART0_RXD
P_C11/UART0_CTS#
P_C10/UART0_RTS#
P_C15/UART1_CTS#/IS H_UART1_CTS#
P_C14/UART1_RTS#/IS H_UART1_RTS#
P_C13/UART1_TXD/IS H_UART1_TXD
P_C23/UART2_CTS#
P_C22/UART2_RTS#
P_C21/UART2_TXD
P_C20/UART2_RXD
P_C19/I2C1_SCL
P_C18/I2C1_SDA
P_C17/I2C0_SCL
P_C16/I2C0_SDA
P_D4/ISH_I2C2_SDA/ISH_I 2C3_SDA
P_D23/ISH_I2C2_SCL/ISH_I2C 3_SCL
SPT_PCH_H
PU_EVENT#22
GC
6_FB_EN19,22
DGPU_PWROK12,21
DG
PU_PWR_EN12,47
VG
PU_EN46
OD
D_PRSNT#
BBS_BIT1
68 *0_4
R7
AC
CEL_INTA#
TP
112
C1_SCL
I2
I2
C1_SDA
I2
C0_SCL
I2C0_SDA
SPT
-H_PCH
OF 12
5
25 *1K_4
R7
17 *1K_4
R7
SPT
P_D14/ISH_UART0_TXD /SML0BCLK/I2C2_SCL
GP
P_D13/ISH_UART0_RXD/S ML0BDATA/I2C2_SDA
GP
11
_CLK
CRT
CRT
_DATA
OCC_N_R
SKT
Ne
w CN to CPU_201412 03
CRT
_CLK
R2
_DATA
CRT
R6
OF 12
I_DDCCLK_SW 30
HDM
HDM
I_DDCDATA_SW 30
TP
50
TP
36
SKT
OCC_N_R 2
11 2.2K_4
38 2.2K_4
GP
P_D16/ISH_UART0_CTS #
GP
P_D15/ISH_UART0_RTS #
P_H20/ISH_I2C0_SCL
GP
GP
P_H19/ISH_I2C0_SDA
GPP_H22/ISH_I2C1_SCL
GP
P_H21/ISH_I2C1_SDA
GP
P_A23/ISH_GP5
GP
P_A22/ISH_GP4
P_A21/ISH_GP3
GP
GP
P_A20/ISH_GP2
P_A19/ISH_GP1
GP
GP
P_A18/ISH_GP0
GP
P_A17/ISH_GP7
V
+3
GP
GP
GP
GPP_D9
P_D10
P_D11
P_D12
Bo
ard_ID4 29
Low
VRAM 2GB VRAM 4GB
Reserved
(Default)
TPM
No touch panel
ard ID
R7
94 10K_4
R3
20 10K_4
23 10K_4
R3
63 *10K_4
R2
04 10K_4
R7
R7
00 *10K_4
R6
99 *10K_4
91 *10K_4
R9
86 10K_4
R9
R7
65 *IV@10K_4
High
Reserve
G-sensor No G-sensor
No TPM
touch panel
RA
RA
RA
Board_ID0
Bo
Bo
Bo
Board_ID4
Bo
Bo
M_ID1
M_ID2
M_ID3
ard_ID1
ard_ID2
ard_ID3
ard_ID5
ard_ID6
SKU
_ID0
R7
86 EV@10K_4
UMA Only
dGPU Only
AL44
_ID0
SKU
AL36
M_ID3
RA
AL35
M_ID2
RA
AJ39
M_ID1
RA
AJ43
AL43
AK44
AK45
BC38
BB38
BD38
BE39
BC22
ARD_ID6
BO
BD18
BOARD_ID5
BE21
ARD_ID4
BO
BD22
BO
ARD_ID3
BD21
BO
ARD_ID2
BB22
BOARD_ID1
BC19
BO
ARD_ID0
Bo
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
R7
85 *10K_4
R3
22 *10K_4
27 *10K_4
R3
61 10K_4
R2
05 *10K_4
R7
R7
01 10K_4
R7
06 10K_4
R695 10K_4
90 10K_4
R9
87 *10K_4
R9
SKU_ID0
0
1
+3
V_DEEP_SUS
+3
V_DEEP_SUS
VGA H/W
Signal
UMA
GPU
Setup
Menu
Hidden
Hidden
UMA boot
GPU boot
HighLow
Reserved
BOARD_ID5
BOARD_ID6
Reserve UART FFC connect or for Win 7 debug
UA
RT2_RXD
UART2_TXD
UART2_RTS
RT2_CTS
UA
RT2_RXD
UA
RT2_TXD
UA
UART2_RTS
UA
RT2_CTS
(Before C1)
(Default)
R8
02 *49.9K/F_4
R799 *49.9K/F_4
R7
98 *49.9K/F_4
95 *49.9K/F_4
R7
+5V
4
CN1
1
2
3
7
4 8
5
6
*UART Function
Reserved
(After C2)
ReserveReserved
+3
V_S5
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
PCH 4/6 (GPIO/MISC )
PCH 4/6 (GPIO/MISC )
PCH 4/6 (GPIO/MISC )
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
1A
1A
1A
13 49Tuesday, September 08, 2015
13 49Tuesday, September 08, 2015
13 49Tuesday, September 08, 2015
of
of
of
Page 14
5
4
3
2
1
14
SPT
-H_PCH
CORE
MPHY
USB
8
VCCGPIO
OF 12
CPRIM_1P0
VC
VC
CDSW_3P3
VC
VC
CPGPPBCH
VC
CPGPPBCH
CPGPPEF
VC
CPGPPEF
VC
VC
CPGPPG
VCCPRIM_3P3
VC
CPRIM_1P0
CRTCPRIM_3P3
VC
CPRIM_1P0
VC
VC
CPRIM_1P0
VC
CPRIM_1P0
CPRIM_1P0
VC
VCCPGPPD
CPGPPD
VC
VC
CPGPPD
VC
CPGPPD
CPRIM_3P3
VC
VC
CPRIM_3P3
VC
CPRIM_3P3
CPGPPA
CATS
VC
VC
CRTC
DCP
RTC
VC
CSPI
CSPI
VC
CSPI
VC
AL22
BA24
BA31
BC42
BD40
AJ41
AL41
AD41
AN5
AD15
AD13
BA20
BA22
BA26
AJ20
AJ21
AJ23
AJ25
BE41
BE43
BE42
BC44
BA45
BC45
BB45
BD3
BE3
BE4
0.0908A
0.403A
0.0879A
0.27262A
0.14107A
0.1318A
0.2875A
+VCCPRI
+VCCAT
+VCCRT
DCPRT
+VCCPRI
0.0121A
0.081A
M_1.0V_AL22
+VCCPRI
+VCCPG
+VCCPG
+VCCPRI
C4
73 *0.1U/16V_4
M_1.0V_AJ20_AD15
0.0066A
S
0.
CPRIM_3.3V
C5
C
09 0.1U/16V_4
M_1.0V_AJ20
92 0.1U/16V_4
C4
+VCCSPI
PPD
+VCCPG
PPA
PPEF
M_3P3
002A
C4
67 *1U/6.3V_4
R2
45 *SHORT_6
44 *SHORT_6
R2
57 *SHORT_6
R2
**L
60*SHORT _6
R2
C5
C4
C5
C8
21*SHORT _6
R2
R2
77*SHORT _6
081U/6.3V_4
+VCCDSW
93*1U /6.3V_4
+VCCPG
29*0.1U/16 V_4
79*0.1U/16 V_4
+VCCPG
+3V_DEEP_SUS
+3V_DEEP_SUS
+3V_DEEP_SUS
+3V_RT
C
+1V_S5
PPBCH
+1V_S5
+1V_S5
PPG
3P3
+VCCPG
PPEF
R3
14*SHORT_6
28*SHORT_6
R3
R7
R7
96*SHORT_6
+VCCPG
ayout Note: +VCCPRIM_1P0 total :5.5167A**
R7
53*SHORT _6
52*SHORT_6
R7
+3V_DEEP_SUS
+3V_DEEP_SUS
+3V_DEEP_SUS
+3V_DEEP_SUS
+3V_DEEP_SUS
+3V_DEEP_SUS
93 *SHORT_6
+3V_DEEP_SUS
PPEF
C8
77
0.1U/16V_4
D D
d R 2689 for NI to +1.0 V_DE EP_S US_20 1412 24
Ad
+1V_S5 +VCCDSW
+1V_S5
C4
45
22U/6.3V_6
C C
+3V_S5
C4
46
22U/6.3V_6
46 *SHORT_4
R2
R2
+V3.
3DX_1.5DX_ADO
+1V_S5
91*0_6
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
_1.0V
C4
C4
03 *SHORT_6
R3
+VCCDSW
_1.0V
R2
97 *SHORT_6
R3
21 *SHORT_6
R3
30 *SHORT_6
02 *SHORT_6
R3
20 *SHORT_6
R2
R2
22 *SHORT_6
R2
56 *SHORT_6
72 1U/6.3V_4
79 *1U/6.3V_4
04 1U/6.3V_4
C5
R2
17*SHORT _6
R2
59*SHORT _6
R2
19*SHORT _6
18*SHORT _6
R2
R2
16*SHORT _6
M_1.0V_AJ20_AA23
+VCCPRI
91 *1U/6.3V_4
C4
0454A
0.
0.0348A
0.0237A
0.0237A
0.0327A
C4
57 *1U/6.3V_4
+VCCAM
94 1U/6.3V_4
C4
89 22U/6.3V_6
C4
0.0248A
+VCCAM
C5
31 1U/6.3V_4
0.0248A
+VCCPCI
C539 1U/6.3V_4
83 1U/6.3V_4
C4
0.095A
+VCCAPLLEBB
0.533A
+VCCPRI
0.01A
+VCCUSB2PLL_1P0
0.01A
+VCCHDAPLL_1P0
0.075A
+VCCDSW
+VCCCLK1
+VCCCLK3
+VCCCLK4
+VCCCLK2
+VCCCLK5
PHY_1P0
PHYPLL_1P0
E3PLL_1P0
M_1.0V_AC17
3P3
Change C2364 from NI to I _20141212
AA23
AA26
AA28
AC23
AC26
AC28
AE23
AE26
BA29
AC17
AN19
BA15
W15
Y23
Y25
N17
R19
U20
V17
R17
U21
U23
U25
U26
V26
A43
B43
C44
C45
V28
AJ5
AL5
K2
K3
U45H
VC
CPRIM_1P0
CPRIM_1P0
VC
CPRIM_1P0
VC
VC
CPRIM_1P0
VC
CPRIM_1P0
CPRIM_1P0
VC
CPRIM_1P0
VC
VC
CPRIM_1P0
VC
CPRIM_1P0
CPRIM_1P0
VC
DSW_1P0
DCP
VCCCLK1
CCLK3
VC
VC
CCLK4
VC
CCLK2
CCLK2
VC
VC
CCLK5
VC
CCLK5
CMPHY_1P0
VC
VC
CMPHY_1P0
VC
CMPHY_1P0
CMPHY_1P0
VC
CMPHY_1P0
VC
VC
CMPHYPLL_1P0
VC
CMPHYPLL_1P0
CPCIE3PLL_1P0
VC
CPCIE3PLL_1P0
VC
VCCAPLLEBB_1P0
CPRIM_1P0
VC
VC
CUSB2PLL_1P0
VC
CUSB2PLL_1P0
CHDAPLL_1P0
VC
VC
CHDA
VC
CDSW_3P3
SPT_PCH_H
+3V_RT
C
CPRIM_3.3V
+VCCRT
C4
1U/6.3V_4
80
81
C4
0.1U/16V_4
47*0_4
R2
3DX_1.5DX_ADO
+V3.
C4
1U/6.3V_4
C4
87
88
0.1U/16V_4
5V
+1.
B B
+3V
+VCCAT
S
C4
69
1U/6.3V_4
for DS3
R2
96*SHO RT_4
64
50
R3
100K_4
P_SUS_ON37
SL
A A
5
4
C5
1U/6.3V_4
55
C5
*10P/50V _4
R3
47
1 2
*short_6
7
U2
5
IN
4
IN
3
ON
/OFF
*IC(5P) G524 3AT11U-Lay
3
OU
GN
+3V_DEEP_SUS+3V_S5
+3V_DEEP_SUS
1
T
2
D
C5
48
0.1U/10V_4
9,10,12,13,16,17
2
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Si
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
PCH 5/6 (POWER)
PCH 5/6 (POWER)
PCH 5/6 (POWER)
Date: Sheet
Date: Sheet
Date: Sheet
1
1A
1A
1A
of
of
of
14
14
14
49Tuesday, August 25, 2015
49Tuesday, August 25, 2015
49Tuesday, August 25, 2015
Page 15
5
4
3
2
1
15
U45I
-H_PCH
SPT
18
AC
VSS
AN4
VSS
10
AN
VSS
BE14
D D
C C
B B
BE1
BE23
BE2
BE32
BE3
BE4
BE9
M3
M4
AA1
AA1
AA2
AA2
AA25
AA2
AA4
AA4
AB10
C1
C2
C3
K1
K2
K3
K3
K4
K4
L12
L13
L15
L41
N1
N1
N1
N22
N2
N35
N3
N4
P1
P19
P2
P4
R1
R1
R2
R2
R3
R3
Y1
Y2
Y2
Y2
Y2
Y2
A1
A2
A3
A3
C2
J7
K4
L4
L8
N4
N5
R5
T1
T2
T4
8
8
7
0
0
8
7
0
7
3
6
2
3
5
2
0
5
9
4
6
1
7
2
5
0
4
2
9
3
8
8
0
1
6
8
9
8
5
2
7
7
8
0
1
9
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SPT_PCH_H
9
OF 12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AR
AR7
U1
AL4
AE2
AE4
AE4
AF18
AF
AF
AF
AF
AF
AF
AF
AG
AG
AG
AG
AG
AG
AG
AH
AH
AH
AH
AH
AH
AH
AH
AH
AH
AH
AJ
AJ14
AJ
AJ17
AJ
AJ26
AJ
AJ29
AJ
AJ32
AJ
AK4
AK4
AU
AV1
AV2
AV2
AV3
AV3
AV6
AW
AW
AW
AW
AW
AY3
AY4
B2
B3
B3
B4
B6
BA1
BB1
BB1
BB2
BB25
BB3
BB34
BC
BD43
5
5
9
2
20
21
23
25
26
28
29
11
13
31
32
33
38
4
1
17
18
20
21
23
25
26
28
29
45
10
15
18
28
31
36
2
7
7
4
7
1
3
13
19
29
37
9
8
5
5
7
0
1
6
1
0
2
C42
D1
D12
D1
D16
D1
D19
D2
D2
D2
D2
D2
D3
D3
D3
D3
D3
E1
E1
E3
E3
G4
H1
H1
H2
H2
H2
H2
H3
U10
U1
U14
U1
U1
U2
U2
U3
U3
U3
U3
V1
V2
V2
V2
V2
V2
V4
W1
W3
W3
W3
W3
Y1
F4
F8
G9
H3
J10
J1
J3
J3
J5
T4
U4
U8
V3
W4
W8
0
5
7
1
4
5
7
9
0
1
3
5
6
3
5
1
3
4
2
7
9
2
4
7
9
5
1
9
2
1
7
8
8
9
1
2
3
8
8
0
1
3
5
9
5
4
1
2
3
8
7
SPT
U45L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SPT_PCH_H
-H_PCH
U45J
AB11
VSS
AB7
VSS
AB14
VSS
1
AB3
VSS
AB32
VSS
8
AB3
VSS
AB4
VSS
AB5
VSS
1
AC
VSS
20
AC
VSS
21
AC
VSS
25
AC
VSS
29
AC
VSS
45
AC
VSS
AB8
VSS
11
AD
VSS
14
AD
VSS
5
AB1
VSS
AD
32
VSS
33
AD
VSS
AD
36
VSS
4
AD
VSS
AD
8
VSS
8
AE1
VSS
AE2
0
VSS
1
AE2
VSS
AE2
5
VSS
8
AE2
VSS
10
AL
VSS
11
AL
VSS
13
AL
VSS
17
AL
VSS
19
AL
VSS
AL24
VSS
29
AL
VSS
AL32
VSS
33
AL
VSS
AL38
VSS
15
AM
VSS
AM17
VSS
19
AM
VSS
AM22
VSS
24
AM
VSS
27
AM
VSS
29
AM
VSS
45
AM
VSS
11
AN
VSS
22
AN
VSS
27
AN
VSS
31
AN
VSS
39
AN
VSS
7
AN
VSS
8
AN
VSS
AP1
1
VSS
AP4
VSS
AR
33
VSS
34
AR
VSS
AR
42
VSS
9
AR
VSS
AT
10
VSS
15
AT
VSS
AT
36
VSS
9
AT
VSS
1
AU
VSS
35
AU
VSS
36
AU
VSS
39
AU
VSS
45
AU
VSS
C4
VSS
OF 12
12
BD
BD45
BD
BE44
BC
D4
A42
B4
B4
BB1
A4
2
44
5
5
4
A4
A3
B2
A2
B1
1
4
C1
D1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RS
VD
VD
RS
SPT_PCH_H
-H_PCH
SPT
AR22
PG
VD
RS
W13
RSVD
U13
RS
VD
P31
RSVD
N31
RS
VD
P27
RS
VD
R27
VD
RS
N29
RS
VD
P29
VD
RS
AN29
RS
VD
R24
VD
RS
P24
VD
RS
AT3
EQ#
PR
AT4
DY#
PR
AY5
U_TRST#
CP
H_TRIGOUT
H_TRIGIN
PC
H_2_CPU_TRIG
AL2
AK1
PC
PC
OF 12
10
PC
H_2_CPU_TRIG8
DMON
H_2_CPU_TRIG_R
PC
R62930_4
PC
H_2_CPU_TRIG_R
PG
DMON 12
XDP_PREQ# 2,16
P_PRDY# 2,16
XD
XD
P_TRST# 2,16
U_2_PCH_TRIG 8
CP
A A
VPCU5,10,29,31,32,34,35,37,38,39,46,47
+3
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Cu
Cu
Cu
stom
stom
stom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
H 6/6 (GND)
H 6/6 (GND)
H 6/6 (GND)
PC
PC
PC
1
1A
1A
1A
of
of
of
15 49Tuesday, August 25, 2015
15 49Tuesday, August 25, 2015
15 49Tuesday, August 25, 2015
Page 16
5
H_
SYS_PWROK_XDP
XD
P_DBRESET_N
D D
VC
Need check Connection
C C
+3
V_DEEP_SUS
S
AP
1
CN1
10
11
12
13
14
B B
15
16
17
18
*ACES_88511-180N
+3
V_S5
72
73
R4
R4
*0_4
*0_4
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
11
12
13
14
15
16
17
18
VCCST_PWRGD2
R7
55 *0_4
SYS_
PWROK10
SM
SM
SUSB# 2,10,16,37,39
SL
SU
SL
RTC_RST# 10
NB
SYS_
SU
VCCST_PWRGD
B_RUN_DAT5,10,17,18,35
B_RUN_CLK5,10,17,18,35
P_S5# 10
SC# 10,37
P_A# 10
SWON# 35,37
SB# 2,10,16,37,39
XD
P_PREQ#2,15
XD
P_PRDY#2,15
CF
CF
CFG22,8
CF
XD
P_BPM02
P_BPM12
XD
CF
CFG52,8
CF
CST_PWRGD
CF
83 *1K_4
R4
PW
R_DEBUG
76 *0_4
R4
R593 *SHORT_4
R5
XDP_TCK110
P_TCK02,10
XD
G0
CF
R595 *0_4
CRB Power_DEBUG have connect to CFG0
R4
75 *0_4
RESET# 10
PC
H_SLP_S0_N 10,37
U16
NC1VCC
2
A
GND3Y
*74AUP1G07GW
4
96 *1K_4
R5
52 *1K_4
R1
XD
XD
no
stuff
V_S5
+3
CF
CF
CF
CF
CFG4
CF
CF
CF
PW
5
C358
*0.1u/16V_4
4
G02
G12
G32,8
G42,8
G62,8
G72
92 *SHORT_4
+3
V_DEEP_SUS
+3
V
P_PREQ_N
P_PRDY_N
G0
R568 1K_4
G1
G2
G3
69 1K_4
R5
G5
G6
G7
VC
CST_PWRGD_XDP
NBSWON#
H_
SYS_PWROK_XDP
B_RUN_DAT_XDP
SM
SM
B_RUN_CLK_XDP
R_DEBUG
+VCCIO
12
TP51
+3V
R141
*10K_4
XD
XD
XD
XDP_TRST_N
CN7
31
31
323229
333328
343427
353526
363625
373724
383823
393922
404021
414120
424219
434318
444417
454516
464615
474714
484813
494912
505011
515110
52529
53538
54547
55556
56565
57574
58583
59592
60601
*S
EC_BSH-030-01-L-D-A-TR
+3
V
P_TDO
P_TDI
P_TMS
30
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
45
C3
0.1U/16V_4
14
2
1
5
4
9
10
12
13
3
CF
G18
CF
G16
G8
CF
CF
G9
G10
CF
CF
G11
G19
CF
G17
CF
CFG12
G13
CF
CF
G14
G15
CF
CK
_XDP_P_CN
CK_XDP_N_CN
XD
P_RST_R_N
XD
P_DBRESET_N
P_TDO
XD
XD
P_TRST_N
XDP_TDI
P_TMS
XD
5
U1
VCC
1A
1O
E
2A
2OE
3A
E
3O
4A
E
4O
*SN74CBTLV3126RGYR
DPAD
GN
R4
R4
R5
R4
1B
2B
3B
4B
D
G18 2
CF
CF
G16 2
G8 2
CF
G9 2
CF
CFG10 2,8
G11 2
CF
CF
G19 2
G17 2
CF
CF
G12 2,8
CFG13 2,8
CF
G14 2
CF
G15 2
84 *0_4
82 *0_4
94 *1K_4
77 *0_4
3
6
8
11
15
7
SYS_
RESET#
P_TDO_CPU 2
XD
XD
P_TDI_CPU 2
XD
P_TMS_CPU 2
XDP_TRST# 2,15
JTAGX_PCH2,10
JTAG_TMS_PCH10
JTAG_TDI_PCH10
JTAG_TDO_PCH10
JTAG_TCK_PCH10
2
_XDP_P 11
CK
CK
_XDP_N 11
PL
TRST# 2,12,19,31,33,34,37
+1.0V
+1
.0V
00
R6
*150/F_4
PW
99
R5
*10K_4
R1
47 51_4
48 *0_4
R1
R149 *0_4
R155 *0_4
R_DEBUG
XDP_TDI
+3V_DEEP_SUS9,10,12,13,14,17
XD
P_TDO
XDP_TCK0
XDP_TMS
XDP_TDI
XDP_TDO
XDP_TCK0
XDP_TCK1
1
16
A A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet of
Date: Sheet of
5
4
3
2
Date: Sheet of
-- HSW XDP & APS
-- HSW XDP & APS
-- HSW XDP & APS
22
22
22
1
1A
1A
1A
16 49Tues day, August 25, 2015
16 49Tues day, August 25, 2015
16 49Tues day, August 25, 2015
Page 17
5
4
3
2
1
JD
P/
M_
A_A[13 :0]4
D D
A_W E#4
M_
A_CAS#4
M_
A_RAS#4
M_
+1
.2VSUS
R4
71
240_4
A_EVEN T#
M_
_THRMTRIP#2,5,11,18
PM
DDR3
M_
A_ACT #4
M_
A_PARIT Y4
M_
A_ALER T#4
_DRAMRST#10,18
78 *1K_4
R4
C4
M_
M_
M_A_A2
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
04 *0.1U/10V_4
M_
A_EVEN T#
A_A0
A_A1
A_A3
A_A4
A_A5
A_A6
A_A7
A_A8
A_A9
A_A10
A_A11
A_A12
A_A13
TP
TP
A_EVEN T#
71
70
Close to PCH
M_
_SA2
A_ODT 0_CPU4
M_
A_ODT 1_CPU4
M_
SM
SM
+1
.2VSUS
8
7
6
4
+1.2VSUS
2
1 3
1
Q4
RC5144E0L
A_BA#04
A_BA#14
M_
A_BG# 04
M_
A_BG# 14
M_
A_CS#04
M_
A_CS#14
M_
A_CKE04
M_
M_
A_CKE14
M_
A_CLKP 04
M_
A_CLKN 04
M_
A_CLKP 14
M_
A_CLKN 14
B_RUN_CLK5,10,16,18,35
B_RUN_DAT5,10,16,18,35
R1
0823 240_4
R1
0824 240_4
R1
0825 240_4
R1
0826 240_4
R1
0828 240_4
R1
0829 240_4
R1
0830 240_4
0831 240_4
R1
U4
8
VCC
SCLK
DXP
SDA
DXN
ALERT#
GND
OVERT#
*EMC1412-1-ACZL-TR
Need Check PN(EOD)
+3
R5
86
47K/F_4
CHA
CHA
CHA
+1
1
2
3
5
V_DEEP_SUS
R587
47K_4
_SA0
_SA1
_SA2
M_
A_CB0
M_
A_CB1
A_CB2
M_
A_CB3
M_
A_CB4
M_
A_CB5
M_
A_CB6
M_
A_CB7
M_
.2VSUS
C8
82 *0.01U/50V_4
DDR_
C881
*2200P/50V_4
DDR_
Main:AL001412003
2nd:AL000431014 TMP431ADGKR(98h)
DDR_
V
+3
C C
Local Thermal Sensor
B B
Co
-lay for ODT
From Intel MOW, ODT directly connection to CPU
DDR_
VTT_CNTL2
A A
SM
B_RUN_CLK5,10,16,18,35
SM
B_RUN_DAT5,10,16,18,35
PM_EXTTS#013
65
R4
R4
*10K_4
*10K_4
CHA
CHA
_SA0
R4
R4
70
10K_4
10K_4
R8
03 *10K/F_4
V
+3
EXTTS#113
DDR_
VTT_CNTL
R588 *10K_4
5
67
_SA1
62
B_RUN_CLK
SM
B_RUN_DAT
SM
PM
_EXTTS#0
CHA
R5
47K/F_4
R4
*10K_4
R4
10K_4
89
63
66
N and F/P
JD
IM2A
144
A0
133
A1
132
A2
131
A3
128
A4
126
A5
127
A6
122
A7
125
A8
121
A9
146
0/AP
A1
120
1
A1
119
2
A1
158
3
A1
151
4/WE #
A1
156
5/CAS#
A1
152
6/RAS#
A1
162
#/C0
S2
165
#/C1
S3
114
T#
AC
143
RITY
PA
116
ERT#
AL
134
ENT#
EV
108
SET#
RE
150
0
BA
145
1
BA
115
0
BG
113
1
BG
149
#
S0
157
#
S1
109
E0
CK
110
E1
CK
137
0
CK
139
0#
CK
138
1
CK
140
1#
CK
155
T0
OD
161
T1
OD
253
L
SC
254
A
SD
256
0
SA
260
1
SA
166
2
SA
92
0
CB
91
1
CB
101
2
CB
105
3
CB
88
4
CB
87
5
CB
100
6
CB
104
7
CB
12
0
DM
33
1
DM
54
2
DM
75
3
DM
178
4
DM
199
DM5
220
DM6
241
DM7
96
DM8
+3
THERMDA
2
THERMDC
VTTT_PG_CTRL 41
+1.2VSUS2,6,10,18,41
DDR_
VTTREF18,41
4
0
DQ
1
DQ
2
DQ
3
DQ
4
DQ
5
DQ
6
DQ
7
DQ
8
DQ
9
DQ
10
DQ
11
DQ
12
DQ
13
DQ
14
DQ
15
DQ
16
DQ
17
DQ
18
DQ
19
DQ
20
DQ
21
DQ
22
DQ
23
DQ
24
DQ
25
DQ
26
DQ
27
DQ
28
DQ
29
DQ
30
DQ
31
DQ
32
DQ
33
DQ
34
DQ
35
DQ
36
DQ
37
DQ
38
DQ
39
DQ
40
DQ
41
DQ
42
DQ
SODIMM 260 PIN
43
DQ
44
DQ
45
DQ
46
DQ
47
DQ
48
DQ
(260P)
DDR4
49
DQ
50
DQ
51
DQ
52
DQ
53
DQ
54
DQ
55
DQ
56
DQ
57
DQ
58
DQ
59
DQ
60
DQ
61
DQ
62
DQ
63
DQ
S0
DQ
S1
DQ
S2
DQ
S3
DQ
S4
DQ
S5
DQ
S6
DQ
S7
DQ
S8
DQ
S#0
DQ
S#1
DQ
S#2
DQ
S#3
DQ
S#4
DQ
DQS#5
DQS#6
DQS#7
DQS#8
V
DDR3
Thermal Sensor
Q47
*METR3904-G
1 3
EMC1412-1-ACZL-TR(98h)
+3
V2,5,9,10,11,12,13,14,16,18,19,21,28,29,30,31,32,33,34,35,36,37,39,40,41,42,45,46,47
M_
8
A_DQ0
M_
7
A_DQ4
M_
20
M_A_DQ 6
21
M_
A_DQ3
4
M_
A_DQ5
3
M_
A_DQ1
16
M_
A_DQ7
17
M_
A_DQ2
28
M_
A_DQ1 4
29
A_DQ1 1
M_
41
A_DQ1 3
M_
42
A_DQ1 5
M_
24
A_DQ1 0
M_
25
A_DQ8
M_
38
A_DQ9
M_
37
A_DQ1 2
M_
50
A_DQ1 7
M_
49
M_
A_DQ2 1
62
M_
A_DQ1 9
63
M_
A_DQ2 2
46
M_
A_DQ1 6
45
M_
A_DQ2 0
58
M_
A_DQ1 8
59
M_
A_DQ2 3
70
M_
A_DQ2 5
71
A_DQ2 8
M_
83
A_DQ2 6
M_
84
A_DQ3 0
M_
66
A_DQ2 4
M_
67
A_DQ2 9
M_
79
A_DQ2 7
M_
80
M_A_DQ 31
174
M_
A_DQ3 7
173
M_
A_DQ3 3
187
M_
A_DQ3 5
186
M_
A_DQ3 9
170
M_
A_DQ3 6
169
M_
A_DQ3 2
183
M_
A_DQ3 4
182
A_DQ3 8
M_
195
A_DQ4 0
M_
194
A_DQ4 1
M_
207
A_DQ4 3
M_
208
A_DQ4 7
M_
191
A_DQ4 5
M_
190
A_DQ4 4
M_
203
M_
A_DQ4 2
204
M_
A_DQ4 6
216
M_
A_DQ5 0
215
M_
A_DQ5 4
228
M_
A_DQ5 1
229
M_
A_DQ5 3
211
M_
A_DQ4 8
212
A_DQ5 2
M_
224
A_DQ4 9
M_
225
A_DQ5 5
M_
237
A_DQ5 6
M_
236
A_DQ6 1
M_
249
A_DQ6 3
M_
250
A_DQ5 8
M_
232
M_A_DQ 57
233
M_
A_DQ6 0
245
M_
A_DQ5 9
246
M_
A_DQ6 2
13
M_
A_DQS P0
34
M_
A_DQS P1
55
M_
A_DQS P2
76
A_DQS P3
M_
179
A_DQS P4
M_
200
A_DQS P5
M_
221
A_DQS P6
M_
242
A_DQS P7
M_
97
A_DQS P8
M_
11
M_
A_DQS N0
32
M_
A_DQS N1
53
M_
A_DQS N2
74
M_
A_DQS N3
177
A_DQS N4
M_
198
M_
A_DQS N5
219
A_DQS N6
M_
240
M_
A_DQS N7
95
A_DQS N8
M_
1uF/10uF 4pcs on each side of connector
+1
.2VSUS
C535 1U/6.3V_4
96 1U/6.3V_4
C4
51 1U/6.3V_4
C5
24 1U/6.3V_4
C5
C4
30 1U/6.3V_4
C5
40 1U/6.3V_4
C498 1U/6.3V_4
41 1U/6.3V_4
C5
27 10U/6.3V_6
C5
C528 10U/6.3V_6
95 10U/6.3V_6
C4
C5
23 10U/6.3V_6
C5
01 10U/6.3V_6
22 10U/6.3V_6
C5
C4
33 10U/6.3V_6
97 10U/6.3V_6
C4
A_DQ[ 63:0] 4
0-7
8-15
16-23
24-31
33-39
40-47
48-55
56-63
M_
A_DQS P[7:0] 4
A_DQS N[7:0] 4
M_
Pl
ace these Caps near So-Dimm1.
DDR_
VTTREF
C5
16 1U/6.3V_4
C5
19 1U/6.3V_4
C5
17 1U/6.3V_4
C503 1U/6.3V_4
10 10U/6.3V_6
C5
V
+3
C4
99 0.1U/16V_4
C5
00 2.2U/6.3V_6
3
240_4
A_DQS P8
M_
240_4
M_
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VR
EF DQ0 M1 Solution
1023 Change R10410
from 2ohm to 24.9ohn
+1
R1
0822
+1
0827
R1
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C533 0.1U/16V_4
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C5
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34 2.2U/6.3V_6
06 0.1U/16V_4
05 2.2U/6.3V_6
C5
0.022U/25V_4
2 1
73
2
IM2B
111
D1
VD
112
D2
VD
117
D3
VD
118
D4
VD
123
D5
VD
124
D6
VD
129
D7
VD
130
D8
VD
135
D9
VD
136
D10
VD
141
D11
VD
142
D12
VD
147
D13
VD
148
D14
VD
153
D15
VD
154
D16
VD
159
D17
VD
160
D18
VD
163
D19
VD
1
S1
VS
5
S2
VS
9
S3
VS
15
S4
VS
19
S5
VS
23
S6
VS
27
S7
VS
31
S8
VS
35
S9
VS
39
S10
VS
43
S11
VS
47
S12
VS
51
S13
VS
57
S14
VS
61
S15
VS
65
S16
VS
69
S17
VS
73
S18
VS
77
S19
VS
81
S20
VS
85
S21
VS
89
S22
VS
93
S23
VS
99
S24
VS
103
S25
VS
107
S26
VS
167
S27
VS
171
S28
VS
175
S29
VS
181
S30
VS
185
S31
VS
189
S32
VS
193
S33
VS
197
S34
VS
201
S35
VS
205
S36
VS
209
S37
VS
213
S38
VS
217
S39
VS
223
S40
VS
227
S41
VS
231
S42
VS
235
S43
VS
239
S44
VS
243
S45
VS
247
S46
VS
251
S47
VS
R3
74 2/F_6
R380 24.9/F_4
VD
VR
SODIMM 260 PIN
(260P)
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+1
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C6
63 2.2U/6.3V/X5R_4
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65 0.1U/10V_4
255
DSPD
257
P1
VP
259
P2
VP
258
T
VT
164
EF_CA_DIMM0
VR
EF_CA
2
S48
VS
6
S49
VS
10
S50
VS
14
S51
VS
18
S52
VS
22
S53
VS
26
S54
VS
30
S55
VS
36
S56
VS
40
S57
VS
44
S58
VS
48
S59
VS
52
S60
VS
56
S61
VS
60
S62
VS
64
S63
VS
68
S64
VS
72
S65
VS
78
S66
VS
82
S67
VS
86
S68
VS
90
S69
VS
94
S70
VS
98
S71
VS
102
S72
VS
106
S73
VS
168
S74
VS
172
S75
VS
176
S76
VS
180
S77
VS
184
S78
VS
188
S79
VS
192
S80
VS
196
S81
VS
202
S82
VS
206
S83
VS
210
S84
VS
214
S85
VS
218
S86
VS
222
S87
VS
226
S88
VS
230
S89
VS
234
S90
VS
238
S91
VS
244
S92
VS
248
S93
VS
252
S94
VS
261
D
GN
262
D
GN
R371
1K/F_4
VREF_CA_DIMM0
72
R3
1K/F_4
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Si
ze D ocument Number Rev
Size Document Num ber Rev
Size Document Num ber Rev
stom
stom
stom
Cu
Cu
Cu
18 -- DDR3 DIMM1-RVS(8.0H)
18 -- DDR3 DIMM1-RVS(8.0H)
18 -- DDR3 DIMM1-RVS(8.0H)
Date: Sheet
Date: Sheet
Date: Sheet
V
+3
+2.5V_SUS
0.5A
DDR_
600mA
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
VTTREF
R2
89*0_4
1
18
DDQ
+V
1A
1A
1A
17 49Tuesday, August 25, 2015
17 49Tuesday, August 25, 2015
17 49Tuesday, August 25, 2015
of
of
of
Page 18
5
4
3
2
1
P/
B_A[13 :0]4
M_
D D
B_W E#4
M_
B_CAS#4
M_
B_RAS#4
M_
M_
B_ACT #4
M_
B_PARIT Y4
M_
+1
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R3
52
240_4
M_
B_EVEN T#
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PM
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61 *1K_4
B_ALER T#4
C5
B_A0
M_
M_B_A1 M_B_DQ 0
M_
B_A2
M_
B_A3
M_
B_A4
M_
B_A5
M_
B_A6
M_
B_A7
B_A8
M_
B_A9
M_
B_A10
M_
B_A11
M_
B_A12
M_
B_A13
M_
73
TP
72
TP
B_EVEN T#
M_
68 *0.1U/10V_4
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Close to PCH
B_BA#04
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42
81
R4
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R4
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80
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R4
86
10K_4
B B
M_
B_BA#14
M_
B_BG# 04
M_
B_BG# 14
M_
B_CS#04
M_
B_CS#14
M_
M_
73
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79
B_CKE04
M_
B_CKE14
M_
B_CLKP 04
M_
B_CLKN 04
M_
B_CLKP 14
M_
B_CLKN 14
B_ODT 0_CPU4
M_
B_ODT 1_CPU4
M_
B_RUN_CLK5,10,16,17,35
SM
B_RUN_DAT5,10,16,17,35
SM
+1
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R1
0832 240_4
R1
0833 240_4
R1
0834 240_4
R1
0835 240_4
R1
0836 240_4
R1
0838 240_4
0839 240_4
R1
0840 240_4
R1
+1
CHB
CHB
CHB
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M_
B_CB0
B_CB1
M_
B_CB2
M_
B_CB3
M_
B_CB4
M_
B_CB5
M_
B_CB6
M_
B_CB7
M_
144
133
132
131
128
126
127
122
125
121
146
120
119
158
151
156
152
162
165
114
143
116
134
108
150
145
115
113
149
157
109
110
137
139
138
140
155
161
253
254
256
260
166
92
91
101
105
88
87
100
104
12
33
54
75
178
199
220
241
96
N and F/P
JD
IM1A
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
0/AP
A1
1
A1
2
A1
3
A1
4/WE #
A1
5/CAS#
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6/RAS#
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AC
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1
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SC
A
SD
0
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1
SA
2
SA
0
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1
CB
2
CB
3
CB
4
CB
5
CB
6
CB
7
CB
0
DM
1
DM
2
DM
3
DM
DM4
DM5
DM6
DM7
DM8
SODIMM 260 PIN
(260P)
DDR4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
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DQ
DQ
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DQ
DQ
DQ
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DQ
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DQS#5
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DQS#7
DQS#8
8
B_DQ1
M_
0
7
1
20
M_
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
S0
S1
S2
S3
S4
S5
S6
S7
S8
S#0
S#1
S#2
S#3
B_DQ6
21
M_
B_DQ3
4
M_
B_DQ5
3
M_
B_DQ4
16
M_
B_DQ7
17
M_
B_DQ2
28
B_DQ1 0
M_
29
B_DQ9
M_
41
B_DQ1 1
M_
42
B_DQ1 2
M_
24
B_DQ1 4
M_
25
B_DQ8
M_
38
B_DQ1 3
M_
37
B_DQ1 5
M_
50
M_
B_DQ2 2
49
M_
B_DQ1 8
62
M_
B_DQ2 0
63
M_
B_DQ2 3
46
M_
B_DQ1 6
45
M_
B_DQ1 7
58
M_
B_DQ2 1
59
M_
B_DQ1 9
70
B_DQ2 7
M_
71
B_DQ2 5
M_
83
B_DQ2 6
M_
84
B_DQ2 4
M_
66
B_DQ3 0
M_
67
B_DQ2 8
M_
79
M_B_DQ 31
80
M_
B_DQ2 9
174
M_
B_DQ3 8
173
M_
B_DQ3 4
187
M_
B_DQ3 7
186
M_
B_DQ3 3
170
M_
B_DQ3 9
169
M_
B_DQ3 5
183
B_DQ3 6
M_
182
B_DQ3 2
M_
195
B_DQ4 5
M_
194
B_DQ4 0
M_
207
B_DQ4 7
M_
208
B_DQ4 2
M_
191
B_DQ4 4
M_
190
M_
B_DQ4 1
203
M_
B_DQ4 6
204
M_
B_DQ4 3
216
M_
B_DQ5 1
215
M_
B_DQ5 2
228
M_
B_DQ5 3
229
M_
B_DQ5 5
211
B_DQ4 8
M_
212
B_DQ5 4
M_
224
B_DQ4 9
M_
225
B_DQ5 0
M_
237
B_DQ6 1
M_
236
B_DQ5 9
M_
249
B_DQ6 3
M_
250
M_B_DQ 56
232
M_
B_DQ6 2
233
M_
B_DQ5 7
245
M_
B_DQ5 8
246
M_
B_DQ6 0
13
M_
B_DQS P0
34
M_
B_DQS P1
55
B_DQS P2
M_
76
B_DQS P3
M_
179
B_DQS P4
M_
200
B_DQS P5
M_
221
B_DQS P6
M_
242
B_DQS P7
M_
97
B_DQS P8
M_
11
M_
B_DQS N0
32
M_
B_DQS N1
53
M_
B_DQS N2
74
B_DQS N3
M_
177
M_
B_DQS N4
198
B_DQS N5
M_
219
M_
B_DQS N6
240
B_DQS N7
M_
95
M_B_DQ SN8
M_
B_DQ[ 63:0] 4
0-7
8-15
16-23
24-31
32-39
40-47
48-55
56-63
M_
B_DQS P[7:0] 4
B_DQS N[7:0] 4
M_
M_
B_DQS P8
M_
B_DQS N8
R1
240_4
R10841
240_4
JD
IM1B
111
VD
D1
112
VD
D2
117
VD
D3
118
VD
D4
+1
.2VSUS
2250mA
.2VSUS
+1
0837
+1
.2VSUS
123
VD
D5
124
VD
D6
129
VD
D7
130
VD
D8
135
VD
D9
136
VD
D10
141
VD
D11
142
VD
D12
147
VD
D13
148
VD
D14
153
VD
D15
154
VD
D16
159
VD
D17
160
VD
D18
163
VD
D19
1
VS
S1
5
VS
S2
9
VS
S3
15
VS
S4
19
VS
S5
23
VS
S6
27
VS
S7
31
VS
S8
35
VS
S9
39
VS
S10
43
VS
S11
47
VS
S12
51
VS
S13
57
VS
S14
61
VS
S15
65
VS
S16
69
VS
S17
73
VS
S18
77
VS
S19
81
VS
S20
85
VS
S21
89
VS
S22
93
VS
S23
99
VS
S24
103
VS
S25
107
VS
S26
167
VS
S27
171
VS
S28
175
VS
S29
181
VS
S30
185
VS
S31
189
VS
S32
193
VS
S33
197
VS
S34
201
VS
S35
205
VS
S36
209
VS
S37
213
VS
S38
217
VS
S39
223
VS
S40
227
VS
S41
231
VS
S42
235
VS
S43
239
VS
S44
243
VS
S45
247
VS
S46
251
VS
S47
VD
VR
SODIMM 260 PIN
(260P)
DDR4
DSPD
VP
VP
EF_CA
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
VS
P1
P2
VT
S48
S49
S50
S51
S52
S53
S54
S55
S56
S57
S58
S59
S60
S61
S62
S63
S64
S65
S66
S67
S68
S69
S70
S71
S72
S73
S74
S75
S76
S77
S78
S79
S80
S81
S82
S83
S84
S85
S86
S87
S88
S89
S90
S91
S92
S93
S94
GN
GN
T
D
D
255
257
259
258
164
2
6
10
14
18
22
26
30
36
40
44
48
52
56
60
64
68
72
78
82
86
90
94
98
102
106
168
172
176
180
184
188
192
196
202
206
210
214
218
222
226
230
234
238
244
248
252
261
262
66 2.2U/6.3V/X5R_4
C6
67 0.1U/10V_4
C6
0.5A
600mA
VR
EF_CA_DIMM1
V
+3
+2.5V_SUS
DDR_
DDR_
VTTREF
VTTREF17,41
18
+3V2,5,9,10,11,12,13,14,16,17,19,21,28,29,30,31,32,33,34,35,36,37,39,40,41,42,45,46,47
.2VSUS2,6,10,17,41
+1
Pl
For EMI RESERVE
.2VSUS
+1
.2VSUS
EC18 *120P/50V_4
12 *120P/50V_4
EC
9 *120P/50V_4
EC
EC
16 120P/50V_4
EC
1 *120P/50V_4
EC
10 *120P/50V_4
EC3 *120P/50V_4
VTTREF
A A
DDR_
EC
8 *120P/50V_4
EC
14 *120P/50V_4
5
+1
EC2 *120P/50V_4
4 *120P/50V_4
EC
13 *120P/50V_4
EC
EC
17 *0.1U/16V_4
EC
7 *0.1U/16V_4
EC
15 *0.1U/16V_4
EC11 *0.1U/16V_4 C454 1U/6.3V_4
4
1uF/10uF 4pcs on each side of connector
+1
.2VSUS
ace these Caps near So-Dimm0.
C4
39 1U/6.3V_4
C576 1U/6.3V_4
58 1U/6.3V_4
C4
50 1U/6.3V_4
C5
C5
36 1U/6.3V_4
C5
75 1U/6.3V_4
C5
52 1U/6.3V_4
C5
47 10U/6.3V_6
C582 10U/6.3V_6
79 10U/6.3V_6
C5
49 10U/6.3V_6
C5
C4
48 10U/6.3V_6
C5
46 10U/6.3V_6
C5
77 10U/6.3V_6
C581 10U/6.3V_6
DDR_
EF_CA_DIMM1
VR
.5V_SUS
+2
VTTREF
C5
86 1U/6.3V_4
C554 1U/6.3V_4
57 1U/6.3V_4
C5
67 1U/6.3V_4
C5
C5
71 1U/6.3V_4
C5
78 0.1U/16V_4
C5
80 2.2U/6.3V_6
C5
60 0.1U/16V_4
C559 2.2U/6.3V_6
V
+3
C5
43 0.1U/16V_4
C545 2.2U/6.3V_6
3
EF DQ1 M1 Solution
VR
SM
DDR_VREF_DQ1_M34
1022 Del R10432
SM
DDR_VREF_DQ1_M3
+1
.2VSUS
R284
1K/F_4
VR
R2
85 2/F_6
90
C4
0.022U/25V_4
2 1
R2
73
24.9/F_4
2
EF_CA_DIMM1
R295
1K/F_4
Si
ze D ocument Number Rev
Size Document Num ber Rev
Size Document Num ber Rev
stom
stom
stom
Cu
Cu
Cu
Date: Sheet
Date: Sheet
Date: Sheet
R2
90*0_4
DDQ
+V
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
17 -- DDR3 DIMM0-STD(4.0H)
17 -- DDR3 DIMM0-STD(4.0H)
17 -- DDR3 DIMM0-STD(4.0H)
1
1A
1A
1A
18 49Tuesday, August 25, 2015
18 49Tuesday, August 25, 2015
18 49Tuesday, August 25, 2015
of
of
of
Page 19
1
PEX_IOVDD/Q : 3300mA
To
than bewteen the PS and GPU
A A
B B
C C
D D
+1.05V_GFX
be placed no fur ther from th e GPU
99 22U/6.3V_6X
C8
00 22U/6.3V_6X
C9
01 22U/6.3V_6X
C9
02 22U/6.3V_6X
C9
C9
03 10U/6.3V_6X
C904 10U/6.3V_6X
C905 10U/6.3V_6X
06 10U/6.3V_6X
C9
PLACE NEAR BALLS
C911 1U/6.3V_4X
C907 1U/6.3V_4X
08 1U/6.3V_4X
C9
09 1U/6.3V_4X
C9
PLACE UNDER BGA
10 4.7U/10V_6X
C9
12 4.7U/10V_6X
C9
PLACE CLOSE TO BGA
C9
32 4.7U/6.3V_4X
C933 1U/6.3V_4X
C9
34 0.1u/16V_4
C9
35 *0.1U/16V_4X
C9
36 *0.1U/16V_4X
PLACE CLOSE TO GPU BALL S
V_GFX
+3
V_MAIN
+3
PLACE CLOSE TO BGA
C9
37 4.7U/6.3V_4X
38 1U/6.3V_4X
C9
PLACE CLOSE TO GPU BALL S
C9
39 0.1u/16V_4
C9
40 0.1u/16V_4
1
VDD33 : 85mA
AG19
AG21
AG22
AG24
AH21
AH25
AG13
AG15
AG16
AG18
AG25
AH15
AH18
AH26
AH27
AJ27
AK27
AL27
AM28
AN28
AC6
AJ28
AL11
AJ4
AJ5
C15
D19
D20
D23
D26
H31
T8
V32
Y1
Y2
Y3
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
J8
K8
L8
M8
2
U50A
N15P-GT
PEX
_IOVDD_1
PEX
_IOVDD_2
PEX
_IOVDD_3
PEX
_IOVDD_4
_IOVDD_5
PEX
_IOVDD_6
PEX
_IOVDDQ_1
PEX
_IOVDDQ_2
PEX
PEX
_IOVDDQ_3
_IOVDDQ_4
PEX
PEX
_IOVDDQ_5
PEX
_IOVDDQ_6
PEX
_IOVDDQ_7
_IOVDDQ_8
PEX
PEX_IOVDDQ_9
_IOVDDQ_10
PEX
_IOVDDQ_11
PEX
_IOVDDQ_12
PEX
_IOVDDQ_13
PEX
_IOVDDQ_14
PEX
NC_
1
NC_
2
NC_
3
4
NC_
5
NC_
6
NC_
7
NC_
8
NC_
NC_
9
NC_
10
NC_
11
NC_
12
NC_
13
NC_
14
15
NC_
16
NC_
17
NC_
18
NC_
19
NC_
NC_
20
NC_
21
NC_
22
NC_
23
NC_
24
3_AON_1
3V
3V
3_AON_2
3V
3_MAIN_1
3V
3_MAIN_2
2
[PEG Interface]
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
PEX
_TSTCLK_OUT
PEX
_TSTCLK_OUT_N
PEX
PEX_CLKREQ_N
PEX
PEX_PLLVDD
PEX
PEX
3.
VD
GN
PEX
_RX0
PEX
_RX0_N
PEX
_RX1
PEX
_RX1_N
_RX2
PEX
_RX2_N
PEX
_RX3
PEX
_RX3_N
PEX
_RX4
PEX
PEX
_RX4_N
_RX5
PEX
PEX
_RX5_N
PEX
_RX6
PEX
_RX6_N
_RX7
PEX
PEX_RX7_N
_RX8
PEX
_RX8_N
PEX
_RX9
PEX
_RX9_N
PEX
_RX10
PEX
_RX10_N
PEX
_RX11
_RX11_N
PEX_RX12
_RX12_N
_RX13
PEX
_RX13_N
_RX14
PEX
_RX14_N
_RX15
PEX
_RX15_N
PEX
_TX0
PEX
_TX0_N
_TX1
PEX
PEX
_TX1_N
_TX2
PEX
_TX2_N
PEX
_TX3
PEX
PEX
_TX3_N
_TX4
PEX
PEX
_TX4_N
PEX
_TX5
PEX
_TX5_N
PEX
_TX6
PEX
_TX6_N
_TX7
PEX
_TX7_N
PEX
_TX8
PEX
_TX8_N
PEX
_TX9
PEX
PEX
_TX9_N
PEX
_TX10
_TX10_N
PEX
_TX11
_TX11_N
PEX
_TX12
_TX12_N
_TX13
PEX
_TX13_N
_TX14
PEX
_TX14_N
PEX
_TX15
_TX15_N
_REFCLK
_REFCLK_N
PEX
_RST_N
_TERMP
STMODE
TE
_PLL_HVDD
_SVDD_3V3
3V_AUX_NC
D_SENSE
D_SENSE
3
AN12
AM12
AN14
AM14
AP14
AP15
AN15
AM15
AN17
AM17
AP17
AP18
AN18
AM18
AN20
AM20
AP20
AP21
AN21
AM21
AN23
AM23
AP23
AP24
AN24
AM24
AN26
AM26
AP26
AP27
AN27
AM27
AK14
PEG
AJ14
PEG
AH14
PEG_RXP1_C
AG14
PEG_RXN1_C
AK15
PEG
AJ15
PEG
AL16
PEG
AK16
PEG
AK17
PEG
AJ17
PEG_RXN4_C
AH17
PEG
AG17
PEG
AK18
PEG
AJ18
PEG
AL19
PEG
AK19
PEG_RXN7_C
AK20
PEG_RXP8_C
AJ20
PEG
AH20
PEG
AG20
PEG
AK21
PEG
AJ21
PEG
AL22
PEG_RXP11_C
AK22
PEG_RXN11_C
AK23
PEG
AJ23
PEG
AH23
PEG
AG23
PEG
AK24
PEG
AJ24
PEG_RXN14_C
AL25
PEG
AK25
PEG
AL13
AK13
AJ26
PEX_
AK26
PEX_
11
AJ
NC
AJ12
PEGX_RST#
AK12
PEX_
AP29
PEX_
AK11
TE
STMODE
AG26
PEX_
AH12
AG12
P8
3V_AUX
3.
L4
L5
3
_RXP0_C
_RXN0_C
_RXP2_C
_RXN2_C
_RXP3_C
_RXN3_C
_RXP4_C
_RXP5_C
_RXN5_C
_RXP6_C
_RXN6_C
_RXP7_C
_RXN8_C
_RXP9_C
_RXN9_C
_RXP10_C
_RXN10_C
_RXP12_C
_RXN12_C
_RXP13_C
_RXN13_C
_RXP14_C
_RXP15_C
_RXN15_C
TSTCLK
TSTCLK#
CLKREQ#
TERMP
PLLVDD
PEX_SVDD_3V3 : 210mA
C9
14 [email protected]/ 10V_4
C9
15 [email protected]/ 10V_4
C9
19 [email protected]/ 10V_4
C9
C9
20 [email protected]/ 10V_4
C9
21 [email protected]/ 10V_4
C9
22 [email protected]/ 10V_4
C9
23 [email protected]/ 10V_4
C924 [email protected]/10V_4
25 [email protected]/ 10V_4
C9
26 [email protected]/ 10V_4
C9
C9
27 [email protected]/ 10V_4
C9
28 [email protected]/ 10V_4
C9
190 [email protected]/10V_4
C1
187 [email protected]/10V_4
C1
C1
189 [email protected]/10V_4
C1
191 [email protected]/10V_4
C1
181 [email protected]/10V_4
C1
C1
179 [email protected]/10V_4
C1
178 [email protected]/10V_4
C1
184 [email protected]/10V_4
C1
185 [email protected]/10V_4
C1183 [email protected]/10V_4
182 [email protected]/10V_4
C1
K_PCIE_VGA 11
CL
CL
K_PCIE_VGA# 11
36 *200/F_4
R8
37 10K_4
R8
39 2.49K/F_4
R8
R8
41 10K_4
PEX_PLLVDD : 150mA
ACE NEAR BGA
PL
VG
A_VCCSENSE 46
VGA_VSSSENSE 4 6
4
PEG_TX0 3
_TX#0 3
PEG
_TX1 3
PEG
PEG
_TX#1 3
PEG
_TX2 3
PEG
_TX#2 3
PEG_TX3 3
PEG_TX#3 3
_TX4 3
PEG
_TX#4 3
PEG
_TX5 3
PEG
PEG
_TX#5 3
PEG
_TX6 3
PEG_TX#6 3
_TX7 3
PEG
_TX#7 3
PEG
_TX8 3
PEG
_TX#8 3
PEG
PEG
_TX9 3
PEG_TX#9 3
PEG_TX10 3
_TX#10 3
PEG
_TX11 3
PEG
PEG
_TX#11 3
PEG
_TX12 3
PEG
_TX#12 3
PEG_TX13 3
PEG_TX#13 3
_TX14 3
PEG
PEG
_TX#14 3
PEG
_TX15 3
PEG
_TX#15 3
C9430.1u/16V_4
C9
444.7U/6.3V_4X
C9
464.7U/6.3V_4X
116
TP
4
PEG
X_RST# 2 2
+3V_GFX
+3
V_GFX
PEG_RX0 3
_RX#0 3
PEG
PEG
_RX1 3
PEG
_RX#1 3
PEG
_RX2 3
PEG
_RX#2 3
PEG_RX3 3
_RX#3 3
PEG
_RX4 3
PEG
PEG
_RX#4 3
PEG
_RX5 3
PEG
_RX#5 3
PEG_RX6 3
PEG_RX#6 3
_RX7 3
PEG
_RX#7 3
PEG
PEG
_RX8 3
PEG
_RX#8 3
PEG
_RX9 3
PEG_RX#9 3
PEG_RX10 3
_RX#10 3
PEG
PEG
_RX11 3
PEG
_RX#11 3
PEG
_RX12 3
PEG
_RX#12 3
PEG_RX13 3
_RX#13 3
PEG
_RX14 3
PEG
PEG
_RX#14 3
PEG
_RX15 3
PEG
_RX#15 3
R840 *SHORT_6
C9
41 4.7U/6.3V_4X
C942 1U/6.3V_4X
C9
45 0.1u/16V_4
CLKREQ#
PEX_
+3V_MAIN
2
31
Q5
3
2N7002KW_115MA
5
GC6:+3V_MAIN
GC6 Power control
+3
V_MAIN_EN22
GC6 PEGX_RST#
DG
PU_HOLD_RST#12,13
.05V_GFX
+1
B2A
PL
ACE NEAR GPU
PLACE NEAR GPU
ACE UNDER GPU BALLS
PL
CL
K_PEGA_REQ# 11
5
6
7
8
19
3V MAIN POWER
13
C9
[email protected]/25V_4
2
C1
210
[email protected]/25V_4
1A-7
35
R8
6_FB_EN
GC
GC6@BAT54CW_200MA
+3
V_GFX
60mil
1
3
Q50
GT@AO3413
60mil
R8
29
*GM@0_8
+3
V_MAIN
N16V stuff not support GC6 2.0.
+3
2
1
*NGC6@0_4
PEG
X_RST#
1
3
2
D3
5
C3A
12
38
R8
GC6@1M_4
Size Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sheet
Date: Sheet
Date: Sheet
7
V
C9
[email protected]/16V_4X
4
3 5
U5
2
GC6@TC7SH08FU(F)
FB
VDDQ_EN 47
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
N1
N1
N1
6P-GT - 1/5 (PCIE)
6P-GT - 1/5 (PCIE)
6P-GT - 1/5 (PCIE)
Tu
Tu
Tu
esday, August 25, 2015 19 49
esday, August 25, 2015 19 49
esday, August 25, 2015 19 49
+3
V_GFX
31
33
R8
*GC6@10K_4
X_RST#
PEG
R8
34
GC6@100K_4
8
1A
1A
1A
of
of
of
+3
V_GFX
3/11 GC6 timing issue from
200K change to 100K
+3
V_GFX
R832
EV@10K_4
TRST#2,12,16,31,33,34,37
PL
2
87
C6
1000p/50V_4
27
R8
GT@10K_4
R830 GT@100K_4
3
1
Q5
GT@2N7002K
1
+3
V
2
1
3 5
PEX_RST_MON#22
SYS_
C930
[email protected]/16V_4X
4
RST_MON#
1
U5
GC6@74AHC1G09GW
U_PEX_RST_HOLD#22
GP
RS
T_MON#
GC6 FBVDDQ_EN
GC
6_FB_EN13,22
GPU_PWR_GD46
6
Page 20
1
AA31
AA29
AA28
AC34
AC33
AA32
AA33
W31
AA34
AD31
AL29
AM32
AF34
AE31
AK30
AN33
AF33
AF30
AK31
AM34
AF32
AA27
AA30
AB27
AB33
AC27
AD27
AE27
AF27
AG27
W27
W30
W33
U30
T31
U29
R34
R33
U32
U33
U28
V28
V29
V30
U34
U31
V34
V33
Y32
Y28
Y29
Y30
Y31
Y34
Y33
V31
P30
F31
F34
M32
M31
G31
E33
M33
M30
H30
E34
M34
B13
B19
E13
E19
H10
H11
H12
H13
H14
H18
H19
H20
H21
H22
H23
H24
M27
N27
P27
R27
T27
T30
T33
Y27
B16
E16
H15
H16
V27
A_CMD0
+1
.5V_GFX
B2A
B2A
FB
FB
A_CMD1
FB
A_CMD2
FB
A_CMD3
A_CMD4
FB
A_CMD5
FB
FB
A_CMD6
FB
A_CMD7
A_CMD8
FB
A_CMD9
FB
A_CMD10
FB
FB
A_CMD11
FB
A_CMD12
FB
A_CMD13
A_CMD14
FB
A_CMD15
FB
FB
A_CMD16
FBA_CMD17
FB
A_CMD18
A_CMD19
FB
A_CMD20
FB
FBA_CMD21
A_CMD22
FB
FB
A_CMD23
A_CMD24
FB
A_CMD25
FB
A_CMD26
FB
A_CMD27
FB
FB
A_CMD28
A_CMD29
FB
A_CMD30
FB
A_CMD31
FB
A_DM0
VM
VM
A_DM1
A_DM2
VM
A_DM3
VM
VM
A_DM4
VM
A_DM5
VM
A_DM6
A_DM7
VM
VM
A_WDQS0
VM
A_WDQS1
A_WDQS2
VM
A_WDQS3
VM
VMA_WDQS4
VM
A_WDQS5
VM
A_WDQS6
A_WDQS7
VM
VM
A_RDQS0
VM
A_RDQS1
A_RDQS2
VM
VM
A_RDQS3
A_RDQS4
VM
VM
A_RDQS5
VM
A_RDQS6
VM
A_RDQS7
FB
A_CMD024
119
TP
A_CMD224
FB
A_CMD324
FB
FB
A_CMD424,25
FB
A_CMD524,25
A_CMD624,25
FB
A_CMD724,25
FB
A_CMD824,25
A A
B B
C C
D D
FB
FB
A_CMD924,25
FB
A_CMD1024,25
A_CMD1124,25
FB
A_CMD1224,25
FB
A_CMD1324,25
FB
TP
118
FB
A_CMD1524,25
FB
A_CMD1625
122
TP
A_CMD1825
FB
FB
A_CMD1925
FBA_CMD2024,25
FB
A_CMD2124,25
A_CMD2224,25
FB
A_CMD2324,25
FB
FBA_CMD2424,25
A_CMD2524,25
FB
FB
A_CMD2624,25
A_CMD2724,25
FB
A_CMD2824,25
FB
A_CMD2924,25
FB
A_CMD3024,25
FB
TP
124
VM
A_DM024
A_DM124
VM
A_DM224
VM
A_DM324
VM
A_DM425
VM
VM
A_DM525
A_DM625
VM
VM
A_DM725
VM
A_WDQS024
VM
A_WDQS124
VM
A_WDQS224
A_WDQS324
VM
A_WDQS425
VM
VM
A_WDQS525
VM
A_WDQS625
VM
A_WDQS725
VMA_RDQS024
VM
A_RDQS124
VM
A_RDQS224
A_RDQS324
VM
A_RDQS425
VM
A_RDQS525
VM
VM
A_RDQS625
VM
A_RDQS725
PLACE CLOSE TO GPU BALLS
47 1U/6.3V_4X
C9
48 1U/6.3V_4X
C9
49 1U/6.3V_4X
C9
C9
50 1U/6.3V_4X
51 0.1U/16V_4X
C9
C9
52 0.1U/16V_4X
C9
53 0.1U/16V_4X
C9
54 0.1U/16V_4X
PLACE CLOSE TO BGA
C955 4.7U/6.3V_4X
56 4.7U/6.3V_4X
C9
C9
57 4.7U/6.3V_4X
58 4.7U/6.3V_4X
C9
C960 10U/6.3V_6X
62 10U/6.3V_6X
C9
C9
64 *22U/6.3V_6X
66 22U/6.3V_6X
C9
1
U5
N15P-GT
FB
FB
FB
FB
FBA_CMD4
FB
FBA_CMD6
FB
FBA_CMD8
FB
FBA_CMD10
FB
FBA_CMD12
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FBA_DQM5
FB
FBA_DQM7
FB
FBA_DQS_WP1
FB
FBA_DQS_WP3
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FBVDDQ_12
FB
FBVDDQ_15
FB
FBVDDQ_17
FB
FBVDDQ_19
FB
FBVDDQ_23
FBVDDQ_24
FBVDDQ_25
FBVDDQ_26
FBVDDQ_27
FBVDDQ_28
FBVDDQ_29
H8
FBVDDQ_30
H9
FBVDDQ_31
L27
FBVDDQ_32
FBVDDQ_33
FBVDDQ_34
FBVDDQ_35
FBVDDQ_36
FBVDDQ_37
FBVDDQ_38
FBVDDQ_39
FBVDDQ_44
FBVDDQ_AON_1
FBVDDQ_AON_2
FBVDDQ_AON_3
FBVDDQ_AON_4
FBVDDQ_AON_5
FBVDDQ_AON_6
FBVDDQ_AON_7
FBVDDQ_AON_8
2
0B
A_CMD0
A_CMD1
A_CMD2
A_CMD3
A_CMD5
A_CMD7
A_CMD9
A_CMD11
A_CMD13
A_CMD14
A_CMD15
A_CMD16
A_CMD17
A_CMD18
A_CMD19
A_CMD20
A_CMD21
A_CMD22
A_CMD23
A_CMD24
A_CMD25
A_CMD26
A_CMD27
A_CMD28
A_CMD29
A_CMD30
A_CMD31
A_DQM0
A_DQM1
A_DQM2
A_DQM3
A_DQM4
A_DQM6
A_DQS_WP0
A_DQS_WP2
A_DQS_WP4
A_DQS_WP5
A_DQS_WP6
A_DQS_WP7
A_DQS_RN0
A_DQS_RN1
A_DQS_RN2
A_DQS_RN3
A_DQS_RN4
A_DQS_RN5
A_DQS_RN6
A_DQS_RN7
VDDQ_1
VDDQ_2
VDDQ_3
VDDQ_4
VDDQ_5
VDDQ_6
VDDQ_7
VDDQ_8
VDDQ_9
VDDQ_10
VDDQ_13
VDDQ_16
VDDQ_18
VDDQ_20
2
[MEMORY I/F A]
FB_VDDQ_SENSE
FB_GND_SENSE
FB_CAL_PD_VDDQ
FB_CAL_PU_GND
FB_CALTERM_GND
FB
A_D00
A_D01
FB
FB
A_D02
A_D03
FB
FBA_D04
A_D05
FB
FBA_D06
A_D07
FB
FBA_D08
FB
A_D09
FBA_D10
FB
A_D11
FBA_D12
FB
A_D13
A_D14
FB
FB
A_D15
A_D16
FB
FB
A_D17
A_D18
FB
A_D19
FB
A_D20
FB
A_D21
FB
A_D22
FB
A_D23
FB
FB
A_D24
A_D25
FB
FB
A_D26
A_D27
FB
FB
A_D28
FB
A_D29
FB
A_D30
FB
A_D31
FB
A_D32
FB
A_D33
A_D34
FB
FB
A_D35
A_D36
FB
FB
A_D37
A_D38
FB
FBA_D39
A_D40
FB
FBA_D41
A_D42
FB
FBA_D43
FB
A_D44
FBA_D45
FB
A_D46
FBA_D47
FB
A_D48
A_D49
FB
FB
A_D50
A_D51
FB
FB
A_D52
A_D53
FB
A_D54
FB
A_D55
FB
A_D56
FB
A_D57
FB
A_D58
FB
FB
A_D59
A_D60
FB
FB
A_D61
A_D62
FB
FB
A_D63
FB
A_CLK0
FB
A_CLK0_N
FB
A_CLK1
A_CLK1_N
FB
FB
A_CMD32
A_CMD33
FB
FBA_CMD34
A_CMD35
FB
_VREF
FB
FB
A_WCK01
FBA_WCK01_N
FB
A_WCK23
FBA_WCK23_N
FBA_WCK45
FBA_WCK45_N
FBA_WCK67
FBA_WCK67_N
FB_CLAMP
FB_DLL_AVDD
FBA_PLL_AVDD
3
L28
M29
L29
M28
N31
P29
R29
P28
J28
H29
J29
H28
G29
E31
E32
F30
C34
D32
B33
C33
F33
F32
H33
H32
P34
P32
P31
P33
L31
L34
L32
L33
AG28
AF29
AG29
AF28
AD30
AD29
AC29
AD28
AJ29
AK29
AJ30
AK28
AM29
AM31
AN29
AM30
AN31
AN32
AP30
AP32
AM33
AL31
AK33
AK32
AD34
AD32
AC30
AD33
AF31
AG34
AG32
AG33
R30
R31
AB31
AC31
R28
AC28
R32
AC32
H26
K31
L30
H34
J34
AG30
AG31
AJ34
AK34
J30
NC
J31
NC
J32
NC
J33
NC
AH31
NC
AJ31
NC
AJ32
NC
AJ33
NC
E1
K27
U27
F1
F2
J27
H27
H25
3
A_DQ0
VM
VM
A_DQ1
VM
A_DQ2
VM
A_DQ3
A_DQ4
VM
A_DQ5
VM
VM
A_DQ6
VM
A_DQ7
A_DQ8
VM
A_DQ9
VM
A_DQ10
VM
VM
A_DQ11
VM
A_DQ12
VM
A_DQ13
A_DQ14
VM
A_DQ15
VM
VM
A_DQ16
VMA_DQ17
VM
A_DQ18
A_DQ19
VM
A_DQ20
VM
VMA_DQ21
A_DQ22
VM
VM
A_DQ23
A_DQ24
VM
A_DQ25
VM
A_DQ26
VM
A_DQ27
VM
VM
A_DQ28
A_DQ29
VM
A_DQ30
VM
A_DQ31
VM
A_DQ32
VM
VM
A_DQ33
A_DQ34
VM
VM
A_DQ35
A_DQ36
VM
A_DQ37
VM
VM
A_DQ38
VM
A_DQ39
VM
A_DQ40
A_DQ41
VM
A_DQ42
VM
VM
A_DQ43
VM
A_DQ44
VM
A_DQ45
A_DQ46
VM
A_DQ47
VM
VMA_DQ48
VM
A_DQ49
VM
A_DQ50
A_DQ51
VM
A_DQ52
VM
A_DQ53
VM
VM
A_DQ54
VM
A_DQ55
A_DQ56
VM
VM
A_DQ57
A_DQ58
VM
VM
A_DQ59
VM
A_DQ60
VM
A_DQ61
A_DQ62
VM
A_DQ63
VM
FB
A_DEBUG0_K
A_DEBUG1_K
FB
FB
A_DEBUG0
FBA_DEBUG1
WCK only for GDDR5
R8
PS_
FB_CLAMP
FB
VDDQ_SENSE
_GND_SENSE
FB
_CAL_PD_VDDQ
FB
_CAL_PU_GND
FB
_CAL_TERM_GND
FB
R8
R8
VMA_DQ0 24
A_DQ1 24
VM
VM
A_DQ2 24
VM
A_DQ3 24
A_DQ4 24
VM
A_DQ5 24
VM
A_DQ6 24
VM
VM
A_DQ7 24
VM
A_DQ8 24
A_DQ9 24
VM
A_DQ10 24
VM
A_DQ11 24
VM
VM
A_DQ12 24
VM
A_DQ13 24
A_DQ14 24
VM
A_DQ15 24
VM
A_DQ16 24
VM
VM
A_DQ17 24
VM
A_DQ18 24
VM
A_DQ19 24
A_DQ20 24
VM
A_DQ21 24
VM
VM
A_DQ22 24
VMA_DQ23 24
VM
A_DQ24 24
A_DQ25 24
VM
A_DQ26 24
VM
VMA_DQ27 24
A_DQ28 24
VM
VM
A_DQ29 24
A_DQ30 24
VM
A_DQ31 24
VM
A_DQ32 25
VM
A_DQ33 25
VM
VM
A_DQ34 25
A_DQ35 25
VM
A_DQ36 25
VM
A_DQ37 25
VM
A_DQ38 25
VM
VM
A_DQ39 25
A_DQ40 25
VM
VM
A_DQ41 25
A_DQ42 25
VM
A_DQ43 25
VM
VM
A_DQ44 25
VM
A_DQ45 25
VM
A_DQ46 25
A_DQ47 25
VM
A_DQ48 25
VM
VM
A_DQ49 25
VM
A_DQ50 25
VM
A_DQ51 25
A_DQ52 25
VM
A_DQ53 25
VM
VMA_DQ54 25
VM
A_DQ55 25
VM
A_DQ56 25
A_DQ57 25
VM
A_DQ58 25
VM
A_DQ59 25
VM
VM
A_DQ60 25
VM
A_DQ61 25
A_DQ62 25
VM
VM
A_DQ63 25
A_CLK0 24
VM
VM
A_CLK0# 24
VM
A_CLK1 25
A_CLK1# 25
VM
R8
R8
56 10K_4
_PLLAVDD
FB
+FB_PLLAVDD : 62mA
.5V_GFX
+1
57 *0_4
58 *0_4
59 40.2/F_4
R8
60 42.2/F_4
R8
61 51.1/F_4
R8
PLACE CLOSE TO GPU BALLS
4
45*60.4/F_4
47*60.4/F_4
C9
4
Memory ODT,CKE,RST
termination PD10K
Data Bit[31:0]
ODT:CMD2
CKE:CMD3
RST:CMD5
TP
127
128
TP
+1
.5V_GFX
59 0.1U/16V_4X
C9
63 0.1U/16V_4X
C9
65 22U/6.3V_6X
.5V_GFX
+1
B2A
5
B_CMD0
B_CMD026
FB
TP
FB
B_CMD226
B_CMD326
FB
B_CMD426,27
FB
B_CMD526,27
FB
FB
B_CMD626,27
FB
B_CMD726,27
B_CMD826,27
FB
B_CMD926,27
FB
B_CMD1026,27
FB
FB
B_CMD1126,27
FB
B_CMD1226,27
B_CMD1326,27
FB
TP
B_CMD1526,27
FB
FB
B_CMD1627
TP
FB
B_CMD1827
B_CMD1927
FB
B_CMD2026,27
FB
FB
B_CMD2126,27
FBB_CMD2226,27
FB
B_CMD2326,27
B_CMD2426,27
FB
B_CMD2526,27
FB
FBB_CMD2626,27
B_CMD2726,27
FB
FB
B_CMD2826,27
B_CMD2926,27
FB
B_CMD3026,27
FB
B_DM026
VM
B_DM126
VM
VM
B_DM226
B_DM326
VM
B_DM427
VM
B_DM527
VM
B_DM627
VM
VM
B_DM727
B_WDQS026
VM
B_WDQS126
VM
VM
B_WDQS226
VM
B_WDQS326
VM
B_WDQS427
B_WDQS527
VM
B_WDQS627
VM
VM
B_WDQS727
B_RDQS026
VM
B_RDQS126
VM
VMB_RDQS226
VM
B_RDQS326
VM
B_RDQS427
B_RDQS527
VM
B_RDQS627
VM
B_RDQS727
VM
A_CMD2
FB
FB
A_CMD3
FBA_CMD5
FB
A_CMD18
FB
A_CMD19
FBB_CMD2
B_CMD3
FB
FB
B_CMD5
B_CMD18
FB
FB
B_CMD19
L23HCB1005KF-330T30
117
120
121
TP
123
+1.05V_GFX
FB
B_CMD1
FB
B_CMD2
FB
FB
B_CMD3
FB
B_CMD4
FB
B_CMD5
B_CMD6
FB
B_CMD7
FB
FB
B_CMD8
FB
B_CMD9
B_CMD10
FB
B_CMD11
FB
B_CMD12
FB
FB
B_CMD13
FB
B_CMD14
FB
B_CMD15
B_CMD16
FB
B_CMD17
FB
FB
B_CMD18
FBB_CMD19
FB
B_CMD20
B_CMD21
FB
B_CMD22
FB
FBB_CMD23
B_CMD24
FB
FB
B_CMD25
B_CMD26
FB
B_CMD27
FB
B_CMD28
FB
B_CMD29
FB
FB
B_CMD30
B_CMD31
FB
B_DM0
VM
VM
B_DM1
B_DM2
VM
VM
B_DM3
B_DM4
VM
B_DM5
VM
VM
B_DM6
VM
B_DM7
B_WDQS0
VM
VM
B_WDQS1
VM
B_WDQS2
VM
B_WDQS3
B_WDQS4
VM
B_WDQS5
VM
VMB_WDQS6
VM
B_WDQS7
B_RDQS0
VM
B_RDQS1
VM
VM
B_RDQS2
VM
B_RDQS3
B_RDQS4
VM
VM
B_RDQS5
B_RDQS6
VM
VM
B_RDQS7
Data Bit[63:32]
ODT:CMD18
CKE:CMD19
RST:CMD5
43 10K_4
R8
R8
46 10K_4
48 10K_4
R8
R8
49 10K_4
50 10K_4
R8
R8
51 10K_4
52 10K_4
R8
R8
53 10K_4
54 10K_4
R8
R8
55 10K_4
C574 close to K27 (under GPU)
C575 close to U27 (under GPU)
C576 near to GPU
5
D13
E14
F14
A12
B12
C14
B14
G15
F15
E15
D15
A14
D14
A15
B15
C17
D18
E18
F18
A20
B20
C18
B18
G18
G17
F17
D16
A18
D17
A17
B17
E17
E11
E3
A3
C9
F23
F27
C30
A24
D10
D5
C3
B9
E23
E28
B30
A23
D9
E4
B2
A9
D22
D28
A30
B23
U5
0C
N15P-GT
FB
B_CMD0
B_CMD1
FB
FB
C_CMD2
B_CMD3
FB
FB
B_CMD4
B_CMD5
FB
FBB_CMD6
C_CMD7
FB
FBB_CMD8
B_CMD9
FB
FBB_CMD10
FB
B_CMD11
FBB_CMD12
FB
B_CMD13
FBB_CMD14
FB
B_CMD15
B_CMD16
FB
FB
B_CMD17
B_CMD18
FB
FB
B_CMD19
B_CMD20
FB
B_CMD21
FB
B_CMD22
FB
B_CMD23
FB
B_CMD24
FB
B_CMD25
FB
FB
B_CMD26
B_CMD27
FB
FB
B_CMD28
B_CMD29
FB
FB
C_CMD30
FB
C_CMD31
FB
C_DQM0
FB
C_DQM1
C_DQM2
FB
FB
C_DQM3
C_DQM4
FB
FB
C_DQM5
C_DQM6
FB
FBC_DQM7
C_DQS_WP0
FB
FBC_DQS_WP1
FB
C_DQS_WP2
FBC_DQS_WP3
FB
C_DQS_WP4
FBC_DQS_WP5
FB
C_DQS_WP6
C_DQS_WP7
FB
FB
C_DQS_RN0
C_DQS_RN1
FB
C_DQS_RN2
FB
C_DQS_RN3
FB
C_DQS_RN4
FB
C_DQS_RN5
FB
C_DQS_RN6
FB
FB
C_DQS_RN7
6
MEMORY I/F C
6
FB
C_D00
C_D01
FB
FB
C_D02
C_D03
FB
FB
C_D04
C_D05
FB
FBC_D06
C_D07
FB
FBC_D08
C_D09
FB
FBC_D10
FB
C_D11
FBC_D12
FB
C_D13
FBC_D14
FB
C_D15
C_D16
FB
FB
C_D17
C_D18
FB
FB
C_D19
C_D20
FB
C_D21
FB
C_D22
FB
C_D23
FB
C_D24
FB
C_D25
FB
FB
C_D26
C_D27
FB
FB
C_D28
C_D29
FB
FB
C_D30
FB
C_D31
FB
C_D32
FB
C_D33
FB
C_D34
FB
C_D35
C_D36
FB
FB
C_D37
C_D38
FB
FB
C_D39
C_D40
FB
FBC_D41
C_D42
FB
FBC_D43
C_D44
FB
FBC_D45
FB
C_D46
FBC_D47
FB
C_D48
FBC_D49
FB
C_D50
C_D51
FB
FB
C_D52
C_D53
FB
FB
C_D54
C_D55
FB
C_D56
FB
C_D57
FB
C_D58
FB
C_D59
FB
C_D60
FB
FB
C_D61
C_D62
FB
FB
C_D63
FB
C_CLK0
FB
C_CLK0_N
FB
C_CLK1
FB
C_CLK1_N
FB
B_CMD32
B_CMD33
FB
FB
B_CMD34
B_CMD35
FB
FBB_WCK01
B_WCK01_N
FB
FBB_WCK23
FB
B_WCK23_N
FBB_WCK45
FB
B_WCK45_N
FBB_WCK67
FBB_WCK67_N
FBB_PLL_AVDD
7
G9
B_DQ0
VM
E9
B_DQ1
VM
G8
B_DQ2
VM
F9
VM
B_DQ3
F11
VM
B_DQ4
G11
VM
B_DQ5
F12
B_DQ6
VM
G12
B_DQ7
VM
G6
VM
B_DQ8
F5
VM
B_DQ9
E6
B_DQ10
VM
F6
B_DQ11
VM
F4
B_DQ12
VM
G4
VM
B_DQ13
E2
VM
B_DQ14
F3
VM
B_DQ15
C2
B_DQ16
VM
D4
B_DQ17
VM
D3
VM
B_DQ18
C1
VMB_DQ19
B3
VM
B_DQ20
C4
B_DQ21
VM
B5
B_DQ22
VM
C5
VMB_DQ23
A11
B_DQ24
VM
C11
VM
B_DQ25
D11
B_DQ26
VM
B11
B_DQ27
VM
D8
B_DQ28
VM
A8
B_DQ29
VM
C8
VM
B_DQ30
B8
B_DQ31
VM
F24
B_DQ32
VM
G23
B_DQ33
VM
E24
B_DQ34
VM
G24
VM
B_DQ35
D21
B_DQ36
VM
E21
VM
B_DQ37
G21
B_DQ38
VM
F21
B_DQ39
VM
G27
VM
B_DQ40
D27
VM
B_DQ41
G26
VM
B_DQ42
E27
B_DQ43
VM
E29
B_DQ44
VM
F29
VM
B_DQ45
E30
VM
B_DQ46
D30
VM
B_DQ47
A32
B_DQ48
VM
C31
B_DQ49
VM
C32
VMB_DQ50
B32
VM
B_DQ51
D29
VM
B_DQ52
A29
B_DQ53
VM
C29
B_DQ54
VM
B29
B_DQ55
VM
B21
VM
B_DQ56
C23
VM
B_DQ57
A21
B_DQ58
VM
C21
VM
B_DQ59
B24
B_DQ60
VM
C24
VM
B_DQ61
B26
VM
B_DQ62
C26
VM
B_DQ63
D12
E12
E20
F20
G14
FB
B_DEBUG0_K
G20
FB
B_DEBUG1_K
C12
FB
B_DEBUG0
C20
B_DEBUG1
FB
F8
E8
A5
A6
D24
D25
WCK only for GDDR5
B27
C27
D6
NC
D7
NC
C6
NC
B6
NC
F26
NC
E26
NC
A26
NC
A27
NC
H17
_PLLAVDD
FB
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
7
VM
B_DQ0 26
B_DQ1 26
VM
VMB_DQ2 26
B_DQ3 26
VM
VM
B_DQ4 26
VM
B_DQ5 26
B_DQ6 26
VM
B_DQ7 26
VM
B_DQ8 26
VM
VM
B_DQ9 26
VM
B_DQ10 26
B_DQ11 26
VM
B_DQ12 26
VM
B_DQ13 26
VM
VM
B_DQ14 26
VM
B_DQ15 26
B_DQ16 26
VM
B_DQ17 26
VM
B_DQ18 26
VM
VM
B_DQ19 26
VM
B_DQ20 26
VM
B_DQ21 26
B_DQ22 26
VM
B_DQ23 26
VM
VM
B_DQ24 26
VMB_DQ25 26
VM
B_DQ26 26
B_DQ27 26
VM
B_DQ28 26
VM
VMB_DQ29 26
B_DQ30 26
VM
VM
B_DQ31 26
B_DQ32 27
VM
B_DQ33 27
VM
B_DQ34 27
VM
B_DQ35 27
VM
VM
B_DQ36 27
B_DQ37 27
VM
B_DQ38 27
VM
B_DQ39 27
VM
B_DQ40 27
VM
VM
B_DQ41 27
B_DQ42 27
VM
VM
B_DQ43 27
B_DQ44 27
VM
B_DQ45 27
VM
VM
B_DQ46 27
VM
B_DQ47 27
VM
B_DQ48 27
B_DQ49 27
VM
B_DQ50 27
VM
VM
B_DQ51 27
VM
B_DQ52 27
VM
B_DQ53 27
B_DQ54 27
VM
B_DQ55 27
VM
VMB_DQ56 27
VM
B_DQ57 27
VM
B_DQ58 27
B_DQ59 27
VM
B_DQ60 27
VM
B_DQ61 27
VM
VM
B_DQ62 27
VM
B_DQ63 27
VM
B_CLK0 26
B_CLK0# 26
VM
B_CLK1 27
VM
VM
B_CLK1# 27
42 *60.4/F_4
R8
44 *60.4/F_4
R8
C262 close to H27 (under GPU)
B2A
C961
0.1U/16V_4X
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
GT - 2/5 (Memory)
GT - 2/5 (Memory)
GT - 2/5 (Memory)
N16P-
N16P-
N16P-
uesday, August 25, 2015 20 49
uesday, August 25, 2015 20 49
uesday, August 25, 2015 20 49
T
T
T
8
8
20
TP
125
TP
126
+1
.5V_GFX
1A
1A
1A
of
of
of
Page 21
1
A A
B B
C C
PLA
CE CLOSE TO GPU PLACE CLOSE TO BALLS
+1.
05V_GFX
D D
05V_GFX
+1.
L24
L25
1
HCB1005KF-330T30
BLM15PX181SN1D_1.5A
C9
74
22U/6.3V_6X
C9
22U/6.3V_6X
C9
75
4.7U/6.3V_4X
2
PLLVDD : 200mA
NV
_PLLVDD
B2A
C9
70
C5
71
0.1U/16V_4X
LVDD
PL
092 Close to AE8
C5090 Close to AD7
C9
76
0.1U/16V_4X
2
C9
77
0.1U/16V_4X
B2A
AH8
AG8
AG9
AJ8
AF7
AG7
AF6
AG6
AF8
AN
AB8
AC7
AC8
AD6
AG10
AP9
AP8
AD8
AE8
AD7
3
U5
N15P-GT
IF
IF
IF
IF
IF
IF
IF
IF
IF
2
NC
IF
IF
IF
IF
DA
DA
DA
PL
SP_
VID_PLLVDD
3
0D
PAB_PLLVDD
PA_IOVDD
PB_IOVDD
PAB_RSET
PC_PLLVDD
PD_PLLVDD
PC_IOVDD
PD_IOVDD
PC_RSET
PEF_PLLVDD
PE_IOVDD
PF_IOVDD
PEF_RSET
CA_VDD
CA_VREF
CA_RSET
LVDD
PLLVDD
[IFPA/B_LVDS]
[IFPC/D_TMDS]
[IFPE/F_DP]
[DACA/B_CRT]
[XTAL IN]
4
PA_TXC
IF
IF
PA_TXC_N
IFPA_TXD0
PA_TXD0_N
IF
IF
PA_TXD1
IF
PA_TXD1_N
PA_TXD2
IF
PA_TXD2_N
IF
IF
PA_TXD3
IF
PA_TXD3_N
PB_TXC
IF
IF
PB_TXC_N
IF
PB_TXD4
PB_TXD4_N
IF
PB_TXD5
IF
IF
PB_TXD5_N
IF
PB_TXD6
PB_TXD6_N
IF
PB_TXD7
IF
IF
PB_TXD7_N
IF
PC_AUX_I2CW_SCL
IF
PC_AUX_I2CW_SDA_N
IF
PD_AUX_I2CX_SDA_N
IF
PE_AUX_I2CY_SDA_N
IF
PF_AUX_I2CZ_SDA_N
IF
PC_L0_N
IF
IF
IF
PC_L1_N
IF
PC_L2_N
IF
IF
IF
PC_L3_N
PD_AUX_I2CX_SCL
IF
IF
PD_L0_N
IF
IF
IF
PD_L1_N
IFPD_L2
PD_L2_N
IF
IF
IF
PD_L3_N
IF
PE_AUX_I2CY_SCL
IF
PE_L0_N
IF
IF
IF
PE_L1_N
IF
PE_L2_N
IF
IF
IF
PE_L3_N
IF
PF_AUX_I2CZ_SCL
IFPF_L0
PF_L0_N
IF
IF
IF
PF_L1_N
IF
PF_L2_N
IF
IF
IF
PF_L3_N
DA
CA_RED
DA
CA_GREEN
CA_BLUE
DA
DA
CA_HSYNC
CA_VSYNC
DA
I2CA_SCL
CA_SDA
I2
XT
XTAL_OUT
XTAL_OUTBUFF
XTAL_SSIN
4
PC_L0
PC_L1
PC_L2
PC_L3
PD_L0
PD_L1
PD_L3
PE_L0
PE_L1
PE_L2
PE_L3
PF_L1
PF_L2
PF_L3
AL_IN
AM6
AN6
AP3
AN3
AN5
AM5
3V_MAIN_PWGD
AL6
AK6
AJ6
AH6
AJ9
AH9
AP6
AP5
AM7
AL7
AN8
AM8
AK8
AL8
AG3
AG2
AK1
AJ1
AJ3
AJ2
AH3
AH4
AG5
AG4
AK3
AK2
AM1
AM2
AM3
AM4
AL3
AL4
AK4
AK5
AB3
AB4
AD2
AD3
AD1
AC1
AC2
AC3
AC4
AC5
AF3
AF2
AE3
AE4
AF4
AF5
AD4
AD5
AG1
AF1
AK9
AL10
AL9
AM9
AN9
R4
R5
CA_ SCL
I2
CA_ SDA
I2
+3V_M
AIN
HW
Reserve
AL_OUTBUFF
XT
H3
XT
AL27_IN
H2
XT
AL27_OUT
J4
XT
AL_OUTBUFF
H1
XT
AL_SSIN
R1
04 EV@ 4.7K_4
PG_1.5VGFX47
R8
71 10K_4
R8
72 10K_4
5
R8
681.8K/F_4
R8
691.8K/F_4
R8
70 *10K_4
R8
5
2
67
C9
*1000p/5 0V_4
67 EV@ 4.7K_4
+3V_GFX
Q8
1 3
EV@
DG
PU_POK2
C9
69
*1000P/5 0V_4
6
MMBT3904-7-F
2
6
+3V
R8
1
C1
47
EV@1000p/50V_4
DG
PU_PGOK-1
Q5
5
EV@METR3904-G
1 3
2
AL27_IN
XT
AL27_OUT
XT
7
+3V_G
FX
62
R8
[email protected]/F_4
3V
_MAIN_PWGD
63
R8
*100K/F_ 4
Q6
1 3
EV@
DTC144EU
_MAIN_PWGD 46,47
3V
+1.05V_GFX and GPU core power EN
FX
+3V_G
+3V
R8
65
2
C9
68
EV@1000P/50V_4
4 1
C9
72
10P/50V_4C
Y5
27M
R8
[email protected]_4
Q5
EV@DTC144EUA
1 3
23
HZ_10
64
4
C9
10P/50V_4C
73
66
R8
EV@100K/F_4
B2A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet
Date: Sheet
Date: Sheet
7
6P-GT - 3/5 (Display)
6P-GT - 3/5 (Display)
6P-GT - 3/5 (Display)
N1
N1
N1
sday, August 25, 2015 21 49
sday, August 25, 2015 21 49
sday, August 25, 2015 21 49
Tue
Tue
Tue
8
21
PU_PWROK 12,13
DG
8
1A
1A
1A
of
of
of
Page 22
1
sistor P/N
Re
4.99K---> CS24992FB26
10K ---> CS31002FB26
15K ---> CS31502FB24
20K ---> CS32002FB29
24.9K --->CS32492FB16
30.1K --->CS33012FB18
34.8K---> CS33482FB22
45.3K ---> CS34532FB18 GM
A A
49.9K ---> CS34992FB10 GT
V_GFX
+3
U_OVT#
R8
89 10K_4
R8
90 10K_4
R8
91 10K_4
R892 100K_4
R8
93 10K_4
94 10K_4
R8
R8
95 10K_4
96 *100K_4
R8
R8
97 10K_4
R8
98 *100K_4
99 10K_4
R8
B B
GP
GP
U_ALERT
U_EVENT#_D
GP
GP
IO12_ACIN
V_MAIN_EN
+3
SYS_
PEX_RST_MON#
GP
U_PEX_RST_HOLD#
MEM_VREF_CTL
PU_PSI
DG
ME
M_VREF_CTL
6_FB_EN
GC
Reserve PU/PD for Debug
+3
V_MAIN
JT
TP
129
130
TP
TP
132
TP
134
136
TP
AG_TMS
JT
AG_TDI
JT
AG_TCK
JT
AG_TRST#
JT
AG_TCK
AG_TMS
JT
AG_TDI
JT
AG_TDO
JT
JT
AG_TRST#
I2
CB_SCL
I2
CB_SDA
I2
CC_SCL
CC_SDA
I2
GF
X_SCL
X_SDA
GF
RAP0
ST
RAP1
ST
ST
RAP2
STRAP3
ST
RAP4
MU
LTISTRAP_REF_G ND
18
R9
40.2K/F_4
AM10
AM11
AN11
R9
03 *10K_4
04 *10K_4
R9
R9
05 *10K_4
07 10K_4
R9
R910 1 .8K/F_4
11 1.8 K/F_4
+3
V_GFX
R9
R9
R9
12 1.8 K/F_4
13 1.8 K/F_4
R9
17 *10K_4
1
C C
D D
AP11
AP12
R7
R6
R2
R3
T4
T3
K4
K3
J2
J7
J6
J5
J3
J1
2
0E
U5
N15P-GT
JT
AG_TCK
[MISC_GPIO/I2C/JTAG/THER]
AG_TMS
JT
AG_TDI
JT
JT
AG_TDO
JT
AG_TRST_N
I2
CB_SCL
I2
CB_SDA
I2
CC_SCL
CC_SDA
I2
I2
CS_SCL
CS_SDA
I2
TH
ERMDN
ERMDP
TH
RAP0
ST
STRAP1
RAP2
ST
ST
RAP3
RAP4
ST
MU
LTISTR AP_REF_GND
2
[MIOA]
[MIOB]
[MISC2_ROM]
RO
RO
BU
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GP
GPIO18
GP
GP
GP
M_SCLK
M_CS_N
ROM_SI
M_SO
RO
FRST_N
OV
IO10
IO11
IO12
IO13
IO14
IO15
IO16
IO17
IO19
IO20
IO21
ERT
3
P6
IO0
M3
IO1
L6
IO2
P5
IO3
P7
IO4
L7
IO5
M7
IO6
N8
IO7
L3
IO8
M2
IO9
L1
M5
N3
M4
N4
P2
R8
M6
R1
P3
P4
P1
H4
H6
H5
H7
L2
M1
3
ST
ST
ST
ST
ST
*ME2N7002DKW- G_115MA
GC
6_FB_EN
*ME2N7002DKW- G_115MA
U_EVENT#_D
GP
GC
6_FB_EN
+3
V_MAIN_EN
GP
U_EVENT#_D
PEX_RST_MON#
SYS_
U_ALERT
GP
M_VREF_CTL
ME
GP
IO12_ACIN
PU_PSI
DG
U_PEX_RST_HOLD#
GP
ROM_SCLK
M_SI
RO
RO
M_SO
GPU_BUFRST
R916 *10K_4
GPU_OVT#
RAP0
RAP1
RAP2
RAP3
RAP4
+3
V_GFX
Q5
6A
1
R9
02 0_4
V_GFX
+3
6B
Q5
5
09 0_4
R9
TP
TP
TP
TP
TP138
4
STRAP0
DG : STUFF 50KΩ PU TO 3.3V_AON
R8
73
49.9K/F_4
1 2
R8
81
*4.99K/F_4
2
6
34
131
133
135
137
GP
R9
06 *0_4
08 0_4
R9
GC
6_FB_EN 13,19
V_MAIN_EN 19
+3
SYS_
PW
DG
GP
U_PEX_RST_HOLD# 19
U_THROTTING#38
4
00 *0_4
R9
R9
01 0_4
PEX_RST_MON# 19
M-VID 46
PU_PSI 46
R8
74
*45.3K/F_4
R8
82
*4.99K/F_4
5
R8
75
*15K/F_4
R8
83
*24.9K/F_4
R8
*34.8K/F_4
R8
*4.99K/F_4
EC_FB_CLAMP 37
6_FB_EN 13,19
GC
76
84
N16P-GT-A2 VRAM Configuration Table:
_CLAMP_REQ# 37
FB
DG
PU_EVENT# 13
B2A
ROM_SCLK 0001
ROM_SI
ROM_SO
STRAP0
STRAP1
STRAP2
STRAP3
STRAP4
2
GP
IO12_ACIN
1
7A
Q5
ME2N7002DK W-G_115MA
+3
V_GFX
5
Q57B
ME2N7002DK W-G_115MA
5
GPU_OVT# dGPU_OTP#
R9
19
*EV@0_4
GPIO12 AC detect
AC high
DC low
6
+3
V_GFX
R8
77
*20K/F_4
R8
85
*45.3K/F_4
RO
RO
RO
M_SI
M_SO
M_SCLK
R8
78
*EV@XXX
86
PU +3V_MAIN
4.99K
10K
15K
1010
20K
24.9K
30.1K
1100
1101
34.8K
45.3K
DESCRIPTION
0110 (0x6)
2Gb
1000 (0x8)
0101 (0x5)
4Gb
0001 (0x1) DDR3 256MBx16,1000MHz MICRON
0010 (0x2)
DDR3 128MBx16,1000MHz
DDR3 128MBx16,1000MHz0111 (0x7)
DDR3 128MBx16,1000MHz
DDR3 256MBx16,1000MHz
DDR3 256MBx16,1000MHz SAMSUNG
N16P-GT-A2 (GB4b-128)
6
34
Logical
Strapping Bit3
RAMCFG[3]
DEVID_SEL
Strapping Bit2
SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSEDSOR3_EXPOSED
RAMCFG[2]
PCIE_CFG
Keep footprint to PU to 3V3_AON and PD to GND [Stuff 49.9K PU]
Keep footprint to PU to 3V3_AON and PD to GND [Do Not Stuff
PEGX_RST# 19
PU_OTP# 37
dG
PU_OPP# 37
dG
B2A
6
R8
79
*4.99K/F_4
87
R8
4.99K/F_4
PD
00001000
00011001
0010
00111011
0100
0101
01101110
01111111
Vendor Vendor P/NROM_SI
HYNIX
MICRON
SAMSUNG
HYNIX
7
+3
V_MAIN
R8
80
*10K/F_4
N16P-GT-A2
GB4b-128
N16V-GM-B1 GB2-64
88
R8
4.99K/F_4
GB2b-64
Mutil-level mode strapping:
For N16P-GT-A2 :
R886=40.2k PD
1.ROM_SCLK =4.99K PD
2.ROM_SO = 4.99K PD
3.ROM_SI= Memory strap setting
4.STRAP0 = 49.9k PU
5.Strap4~1 = Reserve Pull up and Pull down
QCI P/N
H5TC2G63FFR-11C
MT41J128M16JT-093G:K
K4W2G1646Q-BC1A
H5TC4G63CFR-11C
MT41J256M16HA-093G:E
K4W4G1646D-BC1A
LogicalLogical
Strapping Bit1
RAMCFG[1]
SMB_ALT_ADDR
+3
V_GFX
R914
2.2K_4
GF
X_SCL
X_SDA
GF
R915
2.2K_4
Logical
Strapping Bit0
RAMCFG[0]
VGA_DEVICE
V_MAIN
+3
4 3
1
Q5
ME2N7002DK W-G_115MA
7
5
2
6
8
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
GT - 4/5 (MISC)
GT - 4/5 (MISC)
GT - 4/5 (MISC)
N16P-
N16P-
N16P-
esday, Au gust 25, 2015 22 49
esday, Au gust 25, 2015 22 49
esday, Au gust 25, 2015 22 49
Tu
Tu
Tu
34.8K Pull down
45.3K Pull down
4.99K Pull UP
30.1K Pull down
10K Pull down
15K Pull down
XXXX
0001
0001
GFx SMBus Isolation
2N
D_MBCLK 10,37
2ND_MBDATA 10,37
8
22
DevIDPackage
0x139A
0x1299
0x1346N16S-GM-S-A2
ROM_SI
8
of
of
of
B2B
1A
1A
1A
Page 23
1
VDD/XVDD : 43A
+VG
PU_CORE
A A
B B
C C
D D
AA12
AA14
AA16
AA19
AA21
AA23
AB13
AB15
AB17
AB18
AB20
AB22
AC12
AC14
AC16
AC19
AC21
AC23
M12
M14
M16
M19
M21
M23
N13
N15
N17
N18
N20
N22
P12
P14
P16
P19
P21
P23
R13
R15
R17
R18
R20
R22
U13
U15
U17
U18
U20
U22
V13
V15
V17
V18
V20
V22
W12
W14
W16
W19
W21
W23
Y13
Y15
Y18
Y17
Y20
Y22
1
U50F
N15P-GT
D_001
VD
VD
D_002
VD
D_003
D_004
VD
D_005
VD
VD
D_006
VD
D_007
D_008
VD
D_009
VD
VD
D_010
VD
D_011
D_012
VD
D_013
VD
VD
D_014
VD
D_015
D_016
VD
D_017
VD
VD
D_018
VDD_019
D_020
VD
VD
D_021
VD
D_022
D_023
VD
D_024
VD
VD
D_025
VD
D_026
D_027
VD
D_028
VD
VD
D_029
VD
D_030
D_031
VD
D_032
VD
VD
D_033
VD
D_034
D_035
VD
D_036
VD
VD
D_037
VDD_038
D_039
VD
VD
D_040
VD
D_041
D_042
VD
T12
D_043
VD
T14
VD
D_044
T16
VD
D_045
T19
D_046
VD
T21
D_047
VD
T23
VD
D_048
VD
D_049
D_050
VD
D_051
VD
VD
D_052
VD
D_053
D_054
VD
VD
D_055
VD
D_056
VDD_057
D_058
VD
D_059
VD
VD
D_060
D_061
VD
D_062
VD
VD
D_063
VD
D_064
D_065
VD
D_066
VD
VD
D_067
VD
D_068
D_069
VD
D_070
VD
VD
D_071
VD
D_072
[GPU VDD]
2
+VG
U1
D_001
XVD
U2
XVD
D_002
U3
XVD
D_003
U4
D_004
XVD
U5
D_005
XVD
U6
XVD
D_006
U7
XVD
D_007
U8
D_008
XVD
V1
D_009
XVD
V2
XVD
D_010
V3
XVD
D_011
V4
D_012
XVD
V5
D_013
XVD
V6
XVD
D_014
V7
XVD
D_015
V8
D_016
XVD
W2
D_017
XVD
W3
XVD
D_018
W4
XVDD_019
W5
D_020
XVD
W7
XVD
D_021
W8
XVD
D_022
Y4
D_026
XVD
Y5
D_027
XVD
Y6
XVD
D_028
Y7
XVD
D_029
Y8
D_030
XVD
2
PU_CORE
3
0G
U5
N15P-GT
A2
D_1
GN
AA17
D_2
GN
AA18
GN
D_3
AA20
GND_4
AA22
D_5
GN
AB12
GN
D_6
AB14
GN
D_7
AB16
D_8
GN
AB19
D_9
GN
AB2
GN
D_10
AB21
GN
D_11
A33
D_12
GN
AB23
D_13
GN
AB28
GN
D_14
AB30
GN
D_15
AB32
D_16
GN
AB5
D_17
GN
AB7
GN
D_18
AC13
GN
D_19
AC15
D_20
GN
AC17
D_21
GN
AC18
GN
D_22
AA13
GND_23
AC20
D_24
GN
AC22
GN
D_25
AE2
GN
D_26
AE28
D_27
GN
AE30
D_28
GN
AE32
GN
D_29
AE33
GN
D_30
AE5
D_31
GN
AE7
D_32
GN
AH10
GN
D_33
AA15
GN
D_34
AH13
D_35
GN
AH16
D_36
GN
AH19
GN
D_37
AH2
GN
D_38
AH22
D_39
GN
AH24
D_40
GN
AH28
GN
D_41
AH29
GND_42
AH30
D_43
GN
AH32
GN
D_44
AH33
GN
D_45
AH5
D_46
GN
AH7
D_47
GN
AJ7
GN
D_48
AK10
GN
D_49
AK7
D_50
GN
AL12
D_51
GN
AL14
GN
D_52
AL15
GN
D_53
AL17
D_54
GN
AL18
D_55
GN
AL2
GN
D_56
AL20
GN
D_57
AL21
D_58
GN
AL23
GN
D_59
AL24
GN
D_60
AL26
GND_61
AL28
D_62
GN
AL30
D_63
GN
AL32
GN
D_64
AL33
D_65
GN
AL5
D_66
GN
AM13
GN
D_67
AM16
GN
D_68
AM19
D_69
GN
AM22
D_70
GN
AM25
GN
D_71
AN1
GN
D_72
AN10
D_73
GN
AN13
D_74
GN
AN16
GN
D_75
AN19
GN
D_76
AN22
D_77
GN
AN25
GN
D_78
AN30
GN
D_79
AN34
GND_80
AN4
D_81
GN
AN7
D_82
GN
AP2
GN
D_83
AP33
D_84
GN
B1
D_85
GN
B10
GN
D_86
B22
GN
D_87
B25
GN
D_88
B28
GN
D_89
B31
D_90
GN
B34
D_91
GN
B4
D_92
GN
B7
D_93
GN
C10
GN
D_94
C13
GN
D_95
C19
GN
D_96
C22
GN
D_97
C25
GND_98
C28
GND_99
C7
GND_100
3
4
[GPU GND]
4
GN
GN
D_101
GN
D_102
GN
GN
D_103
GND_104
D_105
GN
GN
D_106
GN
D_107
D_108
GN
D_109
GN
GN
D_110
GN
D_111
D_112
GN
D_113
GN
GN
D_114
GN
D_115
D_116
GN
D_117
GN
GN
D_118
GN
D_119
D_120
GN
D_121
GN
GN
D_122
GND_123
D_124
GN
GN
D_125
GN
D_126
D_127
GN
D_128
GN
GN
D_129
GN
D_130
D_131
GN
D_132
GN
GN
D_133
GN
D_134
D_135
GN
D_136
GN
GN
D_137
GN
D_138
D_139
GN
D_140
GN
GN
D_141
GND_142
D_143
GN
GN
D_144
GN
D_145
D_146
GN
D_147
GN
GN
D_148
GN
D_149
D_150
GN
D_151
GN
GN
D_152
GN
D_153
D_154
GN
D_155
GN
GN
D_156
GN
D_157
D_158
GN
GN
D_159
GN
D_160
GND_161
D_162
GN
D_163
GN
GN
D_164
D_165
GN
D_166
GN
GN
D_167
GN
D_168
D_169
GN
D_170
GN
GN
D_171
GN
D_172
D_173
GN
D_174
GN
GN
D_175
GN
D_176
D_177
GN
GN
D_178
GN
D_179
GND_180
D_181
GN
D_182
GN
GN
D_183
D_184
GN
D_185
GN
GN
D_186
GN
D_187
GN
D_188
GN
D_189
D_190
GN
D_191
GN
D_192
GN
D_193
GN
GN
D_194
GN
D_195
GN
D_196
GN
D_197
GND_198
GND_199
GND_200
D_OPT_1
D_OPT_2
D2
D31
D33
E10
E22
E25
E5
E7
F28
F7
G10
G13
G16
G19
G2
G22
G25
G28
G3
G30
G32
G33
G5
G7
K2
K28
K30
K32
K33
K5
K7
M13
M15
M17
M18
M20
M22
N12
N14
N16
N19
N2
N21
N23
N28
N30
N32
N33
N5
N7
P13
P15
P17
P18
P20
P22
R12
R14
R16
R19
R21
R23
T13
T15
T17
T18
T2
T20
T22
AG11
T28
T32
T5
T7
U12
U14
U16
U19
U21
U23
V12
V14
V16
V19
V21
V23
W13
W15
W17
W18
W20
W22
W28
Y12
Y14
Y16
Y19
Y21
Y23
AH11
C16
W32
5
+VG
PU_CORE
6
78 1U/6.3V_4X
C9
79 1U/6.3V_4X
C9
C9
80 1U/6.3V_4X
C9
81 1U/6.3V_4X
C9
82 1U/6.3V_4X
C9
83 1U/6.3V_4X
84 1U/6.3V_4X
C9
85 1U/6.3V_4X
C9
86 4.7U/10V_6X
C9
C9
87 4.7U/10V_6X
C9
88 4.7U/10V_6X
C9
89 4.7U/10V_6X
90 4.7U/10V_6X
C9
91 *4.7U/10V_6X
C9
C9
92 4.7U/10V_6X
C9
93 4.7U/10V_6X
94 4.7U/10V_6X
C9
C9
95 *4.7U/10V_6X
C9
96 4.7U/10V_6X
97 *4.7U/10V_6X
C9
C9
98 *4.7U/10V_6X
C9
99 4.7U/10V_6X
C1000 4.7U/10V_6X
7
PLAC
E UNDER GPU
B2A
B2A
B2A
8
23
PLACE NEAR GPU
12
C1
001 22U/6.3V_6X
12
002 22U/6.3V_6X
C1
12
003 22U/6.3V_6X
C1
12
004 22U/6.3V_6X
C1
12
C1
005 22U/6.3V_6X
12
C1
006 22U/6.3V_6X
12
007 22U/6.3V_6X
C1
008 4.7U/10V_6X
C1
009 4.7U/10V_6X
C1
C1
010 *4.7U/10V_6X
011 4.7U/10V_6X
C1
012 4.7U/10V_6X
C1
013
C1
+
1 2
EV@330u_2.5V_3528
5
6
B2A
B2A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet
Date: Sheet
Date: Sheet
6P-GT - 5/5 (Power)
6P-GT - 5/5 (Power)
6P-GT - 5/5 (Power)
N1
N1
N1
Tue
Tue
Tue
7
ZRY
ZRY
ZRY
sday, August 25, 2015
sday, August 25, 2015
sday, August 25, 2015
of
23
of
23
of
23
8
1A
1A
1A
49
49
49
Page 24
5
4
3
2
1
24
M1
FB
A_ZQ0
M8
VR
EFCA
H1
VR
EFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A1
0/AP
R7
1
A1
N7
2/BC
A1
T3
A1
3
T7
A14
M7
NC
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
E
CK
K1
OD
T
L2
CS
J3
S
RA
K3
CA
S
L3
WE
F3
DQ
SL
G3
SL
DQ
E7
DM
L
D3
U
DM
C7
DQ
SU
B7
SU
DQ
T2
SET
RE
L8
ZQ
J1
NC#
J1
L1
L1
NC#
J9
J9
NC#
L9
NC#
L9
96-
BALL
SDRAM DDR3
VRAM _DDR3_HYNIX_256MX16
C_VMA0
VREF
VREF
D_VMA0
FB
A_CMD920,25
D D
C C
B B
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
VMA_
VMA_
FB
FB
FB
FB
FB
FB
VMA_
VMA_
VMA_
VMA_
FB
GN
A_CMD1120,25
A_CMD820,25
A_CMD2520,25
A_CMD1020,25
A_CMD2420,25
A_CMD2220,25
A_CMD720,25
A_CMD2120,25
A_CMD620,25
A_CMD2920,25
A_CMD2320,25
A_CMD2820,25
A_CMD2020,25
A_CMD420,25
A_CMD1220,25
A_CMD2720,25
A_CMD2620,25
A_CMD320
A_CMD220
A_CMD020
A_CMD3020,25
A_CMD1520,25
A_CMD1320,25
VMA_
VMA_
A_CMD520,25
D
139
TP
CLK020
CLK0#20
WDQS320
RDQS320
DM320
DM220
WDQS220
RDQS220
R9
21 243/F_4
A_CMD9
FB
A_CMD11
A_CMD8
FB
A_CMD25
FB
A_CMD10
FB
A_CMD24
FB
FB
A_CMD22
FB
A_CMD7
FB
A_CMD21
A_CMD6
FB
A_CMD29
FB
A_CMD23
FB
A_CMD28
FB
FB
A_CMD20
FB
A_CMD4
FB
A_A15_1
A_CMD12
FB
A_CMD27
FB
FB
A_CMD26
CLK0
VMA_
CLK0#
VMA_
A_CMD3
FB
FB
A_CMD2
FB
A_CMD0
FBA_CMD30
A_CMD15
FB
A_CMD13
FB
A_CMD5
FB
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQU7
D#B2
VD
D#D9
VD
VD
D#G7
VD
D#K2
D#K8
VD
D#N1
VD
VD
D#N9
VD
D#R1
D#R9
VD
VD
DQ#A1
DQ#A8
VD
DQ#C1
VD
VD
DQ#C9
VDDQ#D2
DQ#E9
VD
VD
DQ#F1
VD
DQ#H2
DQ#H9
VD
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSSQ
VSSQ
#D1
VSSQ
#D8
VSSQ
VSSQ
VSSQ
VSSQ
#G1
VSSQ
VSSQ
#G9
E3
L0
F7
L1
F2
L2
F8
L3
H3
L4
H8
L5
G2
L6
H7
L7
D7
U0
C3
U1
C8
U2
C2
U3
A7
U4
A2
U5
B8
U6
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
A9
B3
B3
E1
E1
G8
G8
J2
J2
J8
J8
M1
M1
M9
M9
P1
P1
P9
P9
T1
T1
T9
T9
B1
#B1
B9
#B9
D1
D8
E2
#E2
E8
#E8
F9
#F9
G1
G9
GN
D
+1.
5V_GFX
5V_GFX
+1.
5V_GFX
+1.
R9
22
1.33K/F_4
R9
25
1.33K/F_4
Please close to M1
+1.
5V_GFX
DQ25 20
VMA_
DQ31 20
VMA_
DQ26 20
VMA_
DQ28 20
VMA_
VMA_
DQ27 20
VMA_
DQ30 20
VMA_
DQ24 20
DQ29 20
VMA_
DQ17 20
VMA_
VMA_
DQ22 20
VMA_
DQ18 20
VMA_
DQ23 20
VMA_
DQ16 20
DQ21 20
VMA_
DQ19 20
VMA_
DQ20 20
VMA_
Frame buffer CLK Termination
VMA_
CLK0
C_VMA0
VREF
C1
014
0.01U/50V_4X
20 162/F_4
R9
5V_GFX
+1.
R9
23
1.33K/F_4
R9
26
1.33K/F_4
CLK0#
VMA_
D_VMA0
VREF
C1
015
0.01U/50V_4X
140
TP
WDQS120
VMA_
VMA_
RDQS120
VMA_
DM120
DM020
VMA_
WDQS020
VMA_
VMA_
RDQS020
R9
24 243/F_4
D
GN
Please close to M2
+1.
5V_GFX
C_VMA0
VREF
VREF
D_VMA0
FB
A_CMD9
FB
A_CMD11
A_CMD8
FB
A_CMD25
FB
A_CMD10
FB
A_CMD24
FB
FB
A_CMD22
FB
A_CMD7
FB
A_CMD21
A_CMD6
FB
A_CMD29
FB
A_CMD23
FB
A_CMD28
FB
FB
A_CMD20
FB
A_CMD4
FB
A_A15_2
A_CMD12
FB
A_CMD27
FB
FB
A_CMD26
CLK0
VMA_
CLK0#
VMA_
A_CMD3
FB
FB
A_CMD2
FB
A_CMD0
FBA_CMD30
A_CMD15
FB
A_CMD13
FB
A_CMD5
FB
FB
A_ZQ1
M2
M8
VR
EFCA
H1
VR
EFDQ
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A1
0/AP
R7
1
A1
N7
2/BC
A1
T3
A1
3
T7
A14
M7
NC
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CK
K1
OD
L2
CS
J3
RA
K3
CA
L3
WE
F3
DQ
G3
DQ
E7
DM
D3
DM
C7
DQ
B7
DQ
T2
RE
L8
ZQ
J1
NC#
L1
NC#
J9
NC#
L9
NC#
VRAM _DDR3_HYNIX_256MX16
E
T
S
S
SL
SL
L
U
SU
SU
SET
J1
L1
J9
L9
96-
BALL
SDRAM DDR3
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VDDQ#D2
VD
VD
VD
VD
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQU7
D#B2
D#D9
D#G7
D#K2
D#K8
D#N1
D#N9
D#R1
D#R9
DQ#A1
DQ#A8
DQ#C1
DQ#C9
DQ#E9
DQ#F1
DQ#H2
DQ#H9
#B1
#B9
#D1
#D8
#E2
#E8
#F9
#G1
#G9
E3
L0
F7
L1
F2
L2
F8
L3
H3
L4
H8
L5
G2
L6
H7
L7
D7
U0
C3
U1
C8
U2
C2
U3
A7
U4
A2
U5
B8
U6
A3
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
A9
B3
B3
E1
E1
G8
G8
J2
J2
J8
J8
M1
M1
M9
M9
P1
P1
P9
P9
T1
T1
T9
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
GN
D
+1.
+1.
5V_GFX
5V_GFX
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
DQ13 20
DQ9 20
DQ14 20
DQ8 20
DQ15 20
DQ11 20
DQ12 20
DQ10 20
DQ6 20
DQ1 20
DQ5 20
DQ3 20
DQ4 20
DQ0 20
DQ7 20
DQ2 20
C1
016 0.1U/16V_4X
C1
018 0.1U/16V_4X
C1
020 0.1U/16V_4X
C1
022 0.1U/16V_4X
C1
024 0.1U/16V_4X
C1
026 0.1U/16V_4X
C1
028 0.1U/16V_4X
030 0.1U/16V_4X
C1
032 0.1U/16V_4X
C1
034 1U/6.3V_4X
C1
036 1U/6.3V_4X
C1
C1
A A
5
4
038 1U/6.3V_4X
C1
040 1U/6.3V_4X
C1
042 *4.7U/6.3V_4X
C1
044 *4.7U/6.3V_4X
046 10U/6.3V_6X
C1
048 10U/6.3V_6X
C1
B2A B2A
3
C1
017 0.1U/16V_4X
C1
019 0.1U/16V_4X
C1
021 0.1U/16V_4X
C1
023 0.1U/16V_4X
C1
025 0.1U/16V_4X
C1
027 0.1U/16V_4X
C1
029 0.1U/16V_4X
031 0.1U/16V_4X
C1
033 0.1U/16V_4X
C1
035 1U/6.3V_4X
C1
037 1U/6.3V_4X
C1
C1
039 1U/6.3V_4X
C1
041 1U/6.3V_4X
C1
043 *4.7U/6.3V_4X
C1
045 *4.7U/6.3V_4X
047 10U/6.3V_6X
C1
049 10U/6.3V_6X
C1
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
6P-GT_DDR3 - A1
6P-GT_DDR3 - A1
6P-GT_DDR3 - A1
N1
N1
N1
sday, August 25, 2015 24 49
sday, August 25, 2015 24 49
sday, August 25, 2015 24 49
Tue
Tue
Tue
1
1A
1A
1A
of
of
of
Page 25
5
4
3
2
1
M3
FB
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
G3
E7
D3
C7
B7
T2
L8
A_ZQ2
J1
L1
J9
L9
VRAM _DDR3_HYNIX_256MX16
VREFCA
EFDQ
VR
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
0/AP
A1
A1
1
A1
2/BC
3
A1
4
A1
NC
BA0
BA1
BA2
CK
CK
CK
E
T
OD
CS
RA
S
S
CA
WE
SL
DQ
DQ
SL
L
DM
DM
U
SU
DQ
DQ
SU
RE
SET
ZQ
J1
NC#
NC#
L1
NC#
J9
L9
NC#
BALL
96SDRAM DDR3
C_VMA1
VREF
D_VMA1
VREF
FB
A_CMD920,24
FB
A_CMD1120,24
FB
A_CMD820,24
VMA_
VMA_
VMA_
VMA_
FB
VMA_
VMA_
A_CMD520,24
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
VMA_
VMA_
FB
FB
FB
FB
FB
FB
WDQS720
RDQS720
WDQS620
RDQS620
A_CMD2520,24
A_CMD1020,24
A_CMD2420,24
A_CMD2220,24
A_CMD720,24
A_CMD2120,24
A_CMD620,24
A_CMD2920,24
A_CMD2320,24
A_CMD2820,24
A_CMD2020,24
A_CMD420,24
141
TP
A_CMD1220,24
A_CMD2720,24
A_CMD2620,24
CLK120
CLK1#20
A_CMD1920
A_CMD1820
A_CMD1620
A_CMD3020,24
A_CMD1520,24
A_CMD1320,24
DM720
DM620
R9
GN
D
D D
C C
B B
A_CMD9
FB
A_CMD11
FB
A_CMD8
FB
A_CMD25
A_CMD10
FB
A_CMD24
FB
A_CMD22
FB
A_CMD7
FB
FB
A_CMD21
FB
A_CMD6
FB
A_CMD29
A_CMD23
FB
A_CMD28
FB
A_CMD20
FB
A_CMD4
FB
FB
A_A15_3
FB
A_CMD12
A_CMD27
FB
A_CMD26
FB
VMA_
CLK1
VMA_
CLK1#
A_CMD19
FB
FB
A_CMD18
FB
A_CMD16
FB
A_CMD30
FB
A_CMD15
FBA_CMD13
A_CMD5
FB
28 243/F_4
DQL0
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
VD
D#B2
VD
D#D9
D#G7
VD
D#K2
VD
VD
D#K8
VD
D#N1
D#N9
VD
D#R1
VD
VD
D#R9
DQ#A1
VD
VD
DQ#A8
VD
DQ#C1
DQ#C9
VD
DQ#D2
VD
VD
DQ#E9
VDDQ#F1
DQ#H2
VD
VD
DQ#H9
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSSQ#B1
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
#D1
#D8
#G1
#G9
E3
F7
L1
F2
L2
F8
L3
H3
L4
H8
L5
G2
L6
H7
L7
D7
U0
C3
U1
C8
U2
C2
U3
A7
U4
A2
U5
B8
U6
A3
U7
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
A9
B3
B3
E1
E1
G8
G8
J2
J2
J8
J8
M1
M1
M9
M9
P1
P1
P9
P9
T1
T1
T9
T9
B1
B9
#B9
D1
D8
E2
#E2
E8
#E8
F9
#F9
G1
G9
GN
D
5V_GFX
+1.
+1.
5V_GFX
+1.
5V_GFX
R9
1.33K/F_4
R9
1.33K/F_4
Please close to M3
+1.
5V_GFX
VMA_
DQ63 20
VMA_
DQ57 20
DQ62 20
VMA_
DQ59 20
VMA_
DQ61 20
VMA_
DQ56 20
VMA_
VMA_
DQ60 20
VMA_
DQ58 20
DQ55 20
VMA_
DQ51 20
VMA_
DQ54 20
VMA_
VMA_
DQ48 20
VMA_
DQ52 20
VMA_
DQ50 20
VMA_
DQ53 20
DQ49 20
VMA_
Frame buffer CLK Termination
VMA_
29
32
CLK1
VREF
050
C1
0.01U/50V_4X
R9
27 162/F_4
+1.
C_VMA1
5V_GFX
R9
1.33K/F_4
R9
1.33K/F_4
VMA_
CLK1#
30
33
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VREF
D_VMA1
051
C1
0.01U/50V_4X
C_VMA1
VREF
D_VMA1
VREF
FB
A_CMD9
FB
A_CMD11
FB
A_CMD8
A_CMD25
FB
A_CMD10
FB
A_CMD24
FB
A_CMD22
FB
FB
A_CMD7
FB
A_CMD21
FB
A_CMD6
A_CMD29
FB
A_CMD23
FB
A_CMD28
FB
A_CMD20
FB
FB
A_CMD4
FB
142
TP
WDQS520
RDQS520
DM520
DM420
WDQS420
RDQS420
R9
D
GN
Please close to M4
+1.
5V_GFX
A_A15_4
A_CMD12
FB
A_CMD27
FB
A_CMD26
FB
VMA_
CLK1
CLK1#
VMA_
A_CMD19
FB
FB
A_CMD18
FB
A_CMD16
FB
A_CMD30
FBA_CMD15
A_CMD13
FB
A_CMD5
FB
31 243/F_4
FB
M4
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
G3
E7
D3
C7
B7
T2
L8
A_ZQ3
J1
L1
J9
L9
VRAM _DDR3_HYNIX_256MX16
EFCA
VR
VR
EFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A1
0/AP
A1
1
2/BC
A1
3
A1
A1
4
NC
BA0
BA1
BA2
CK
CK
CK
E
OD
T
CS
S
RA
S
CA
WE
DQ
SL
DQ
SL
DM
L
DM
U
DQ
SU
DQ
SU
RE
SET
ZQ
NC#
J1
NC#
L1
J9
NC#
L9
NC#
96SDRAM DDR3
BALL
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
VD
D#B2
D#D9
VD
D#G7
VD
VD
D#K2
VD
D#K8
D#N1
VD
D#N9
VD
VD
D#R1
VD
D#R9
VD
DQ#A1
VD
DQ#A8
DQ#C1
VD
DQ#C9
VD
VD
DQ#D2
VDDQ#E9
DQ#F1
VD
VD
DQ#H2
VD
DQ#H9
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSSQ
VSSQ
VSSQ
#D1
#D8
VSSQ
VSSQ
VSSQ
VSSQ
#G1
VSSQ
#G9
VSSQ
E3
L0
F7
L1
F2
L2
F8
L3
H3
L4
H8
L5
G2
L6
H7
L7
D7
U0
C3
U1
C8
U2
C2
U3
A7
U4
A2
U5
B8
U6
A3
U7
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
A9
B3
B3
E1
E1
G8
G8
J2
J2
J8
J8
M1
M1
M9
M9
P1
P1
P9
P9
T1
T1
T9
T9
B1
#B1
B9
#B9
D1
D8
E2
#E2
E8
#E8
F9
#F9
G1
G9
GN
D
+1.
+1.
5V_GFX
5V_GFX
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
VMA_
DQ45 20
DQ44 20
DQ41 20
DQ46 20
DQ40 20
DQ43 20
DQ42 20
DQ47 20
DQ33 20
DQ39 20
DQ32 20
DQ38 20
DQ34 20
DQ37 20
DQ35 20
DQ36 20
25
C1
052 0.1U/16V_4X
C1
054 0.1U/16V_4X
C1
056 0.1U/16V_4X
C1
058 0.1U/16V_4X
C1
060 0.1U/16V_4X
C1
062 0.1U/16V_4X
C1
064 0.1U/16V_4X
066 0.1U/16V_4X
C1
068 0.1U/16V_4X
C1
070 1U/6.3V_4X
C1
072 1U/6.3V_4X
C1
074 1U/6.3V_4X
C1
C1
A A
5
4
076 1U/6.3V_4X
C1
078 *4.7U/6.3V_4X
C1
080 *4.7U/6.3V_4X
082 10U/6.3V_6X
C1
084 10U/6.3V_6X
C1
B2A B2A
3
C1
053 0.1U/16V_4X
C1
055 0.1U/16V_4X
C1
057 0.1U/16V_4X
C1
059 0.1U/16V_4X
C1
061 0.1U/16V_4X
C1
063 0.1U/16V_4X
C1
065 0.1U/16V_4X
067 0.1U/16V_4X
C1
069 0.1U/16V_4X
C1
071 1U/6.3V_4X
C1
073 1U/6.3V_4X
C1
075 1U/6.3V_4X
C1
C1
077 1U/6.3V_4X
C1
079 *4.7U/6.3V_4X
C1
081 *4.7U/6.3V_4X
083 10U/6.3V_6X
C1
085 10U/6.3V_6X
C1
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
6P-GT_ DDR3 - A2
6P-GT_ DDR3 - A2
6P-GT_ DDR3 - A2
N1
N1
N1
sday, August 25, 2015 25 49
sday, August 25, 2015 25 49
sday, August 25, 2015 25 49
Tue
Tue
Tue
1
1A
1A
1A
of
of
of
Page 26
5
4
3
2
1
26
M5
FB
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
G3
E7
D3
C7
B7
T2
L8
B_ZQ0
J1
L1
J9
L9
VRAM _DDR3_HYNIX_256MX16
VR
EFCA
EFDQ
VR
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
0/AP
A1
1
A1
A1
2/BC
A13
4
A1
NC
BA0
BA1
BA2
CK
CK
E
CK
T
OD
CS
RA
S
CAS
WE
SL
DQ
SL
DQ
L
DM
U
DM
SU
DQ
SU
DQ
RE
SET
ZQ
J1
NC#
L1
NC#
NC#
J9
NC#
L9
96-
BALL
SDRAM DDR3
VREF
C_VMB0
VREF
D_VMB0
FB
D D
C C
B B
VMB_
VMB_
VMB_
VMB_
FB
VMB_
VMB_
B_CMD520,27
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FBB_CMD2620,27
VMB_
VMB_
FB
FB
FB
FB
FB
FB
WDQS120
RDQS120
WDQS320
RDQS320
GN
B_CMD920,27
B_CMD1120,27
B_CMD820,27
B_CMD2520,27
B_CMD1020,27
B_CMD2420,27
B_CMD2220,27
B_CMD720,27
B_CMD2120,27
B_CMD620,27
B_CMD2920,27
B_CMD2320,27
B_CMD2820,27
B_CMD2020,27
B_CMD420,27
TP
143
B_CMD1220,27
B_CMD2720,27
CLK020
CLK0#20
B_CMD320
B_CMD220
B_CMD020
B_CMD3020,27
B_CMD1520,27
B_CMD1320,27
DM120
DM320
R9
D
B_CMD9
B_CMD11
FB
B_CMD8
FB
B_CMD25
FB
B_CMD10
FB
FB
B_CMD24
FB
B_CMD22
FB
B_CMD7
B_CMD21
FB
B_CMD6
FB
B_CMD29
FB
B_CMD23
FB
FB
B_CMD28
FB
B_CMD20
FB
B_CMD4
FB
B_A15_1
B_CMD12
FB
FB
B_CMD27
FB
B_CMD26
CLK0
VMB_
CLK0#
VMB_
FB
B_CMD3
FB
B_CMD2
FBB_CMD0
B_CMD30
FB
B_CMD15
FB
B_CMD13
FB
FB
B_CMD5
35 243/F_4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQU6
DQ
D#B2
VD
VD
D#D9
VD
D#G7
D#K2
VD
D#K8
VD
VD
D#N1
VD
D#N9
D#R1
VD
D#R9
VD
DQ#A1
VD
DQ#A8
VD
VD
DQ#C1
VDDQ#C9
DQ#D2
VD
VD
DQ#E9
VD
DQ#F1
DQ#H2
VD
DQ#H9
VD
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#T9
VSSQ
VSSQ
#D1
VSSQ
VSSQ
#D8
VSSQ
VSSQ
VSSQ
VSSQ
#G1
VSSQ
#G9
E3
L0
F7
L1
F2
L2
F8
L3
H3
L4
H8
L5
G2
L6
H7
L7
D7
U0
C3
U1
C8
U2
C2
U3
A7
U4
A2
U5
B8
A3
U7
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
A9
B3
B3
E1
E1
G8
G8
J2
J2
J8
J8
M1
M1
M9
M9
P1
P1
P9
P9
T1
T1
T9
B1
#B1
B9
#B9
D1
D8
E2
#E2
E8
#E8
F9
#F9
G1
G9
GN
D
+1.
5V_GFX
Frame buffer CLK Termination
5V_GFX
+1.
+1.
5V_GFX
37
R9
1.33K/F_4
39
R9
1.33K/F_4
Please close to M5
5V_GFX
+1.
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
CLK0
DQ12 20
DQ8 20
DQ15 20
DQ9 20
DQ14 20
DQ11 20
DQ13 20
DQ10 20
DQ24 20
DQ28 20
DQ27 20
DQ31 20
DQ26 20
DQ30 20
DQ25 20
DQ29 20
VREF
34 162/F_4
R9
C_VMB0
086
C1
0.01U/50V_4X
087
C1
1U/6.3V_4X
VMB_
+1.
CLK0#
5V_GFX
38
R9
1.33K/F_4
40
R9
1.33K/F_4
VREF
C_VMB0
VREF
D_VMB0
B_CMD9
FB
B_CMD11
FB
B_CMD8
FB
B_CMD25
FB
FB
B_CMD10
FB
B_CMD24
FB
B_CMD22
B_CMD7
FB
B_CMD21
FB
B_CMD6
FB
B_CMD29
FB
FB
B_CMD23
FB
B_CMD28
FB
B_CMD20
FB
B_CMD4
B_A15_2
TP
144
VMB_
WDQS020
VMB_
RDQS020
DM020
VMB_
DM220
VMB_
VMB_
WDQS220
VMB_
RDQS220
R9
D
GN
VREF
D_VMB0
088
C1
0.01U/50V_4X
Please close to M6
5V_GFX
+1.
FB
FB
B_CMD12
FB
B_CMD27
FB
B_CMD26
CLK0
VMB_
VMB_
CLK0#
FB
B_CMD3
FBB_CMD2
B_CMD0
FB
B_CMD30
FB
B_CMD15
FB
FB
B_CMD13
FB
B_CMD5
36 243/F_4
089
C1
1U/6.3V_4X
FB
M6
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
G3
E7
D3
C7
B7
T2
L8
B_ZQ1
J1
L1
J9
L9
VRAM _DDR3_HYNIX_256MX16
EFCA
VR
EFDQ
VR
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
0/AP
A1
A1
1
A12/BC
3
A1
A1
4
NC
BA0
BA1
BA2
CK
CK
CK
E
T
OD
CS
RAS
S
CA
WE
SL
DQ
DQ
SL
L
DM
DM
U
SU
DQ
DQ
SU
RE
SET
ZQ
J1
NC#
NC#
L1
NC#
J9
L9
NC#
96SDRAM DDR3
BALL
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQU5
DQ
DQ
VD
D#B2
VD
D#D9
D#G7
VD
D#K2
VD
VD
D#K8
VD
D#N1
D#N9
VD
D#R1
VD
VD
D#R9
DQ#A1
VD
VD
DQ#A8
VDDQ#C1
DQ#C9
VD
VD
DQ#D2
VD
DQ#E9
DQ#F1
VD
DQ#H2
VD
VD
DQ#H9
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#T1
VSS#
VSSQ
VSSQ
VSSQ
#D1
VSSQ
#D8
VSSQ
VSSQ
VSSQ
VSSQ
#G1
#G9
VSSQ
E3
L0
F7
L1
F2
L2
F8
L3
H3
L4
H8
L5
G2
L6
H7
L7
D7
U0
C3
U1
C8
U2
C2
U3
A7
U4
A2
B8
U6
A3
U7
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
A9
B3
B3
E1
E1
G8
G8
J2
J2
J8
J8
M1
M1
M9
M9
P1
P1
P9
P9
T1
T9
T9
B1
#B1
B9
#B9
D1
D8
E2
#E2
E8
#E8
F9
#F9
G1
G9
GND
+1.
+1.
5V_GFX
5V_GFX
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
DQ4 20
DQ3 20
DQ5 20
DQ2 20
DQ6 20
DQ0 20
DQ7 20
DQ1 20
DQ20 20
DQ23 20
DQ18 20
DQ22 20
DQ16 20
DQ21 20
DQ19 20
DQ17 20
C1
090 0.1U/16V_4X
C1
092 0.1U/16V_4X
C1
094 0.1U/16V_4X
C1
096 0.1U/16V_4X
C1
098 0.1U/16V_4X
100 0.1U/16V_4X
C1
102 0.1U/16V_4X
C1
104 0.1U/16V_4X
C1
106 0.1U/16V_4X
C1
108 1U/6.3V_4X
C1
C1
A A
5
4
110 1U/6.3V_4X
C1
112 1U/6.3V_4X
C1
114 1U/6.3V_4X
C1
116 *4.7U/6.3V_4X
C1
118 *4.7U/6.3V_4X
120 10U/6.3V_6X
C1
122 10U/6.3V_6X
C1
B2A B2A
3
C1
091 0.1U/16V_4X
C1
093 0.1U/16V_4X
C1
095 0.1U/16V_4X
C1
097 0.1U/16V_4X
C1
099 0.1U/16V_4X
101 0.1U/16V_4X
C1
103 0.1U/16V_4X
C1
105 0.1U/16V_4X
C1
107 0.1U/16V_4X
C1
109 1U/6.3V_4X
C1
C1
111 1U/6.3V_4X
C1
113 1U/6.3V_4X
C1
115 1U/6.3V_4X
C1
117 *4.7U/6.3V_4X
C1
119 *4.7U/6.3V_4X
121 10U/6.3V_6X
C1
123 10U/6.3V_6X
C1
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
6P-GT_DDR3 - B1
6P-GT_DDR3 - B1
6P-GT_DDR3 - B1
N1
N1
N1
sday, August 25, 2015 26 49
sday, August 25, 2015 26 49
sday, August 25, 2015 26 49
Tue
Tue
Tue
1
1A
1A
1A
of
of
of
Page 27
5
4
3
2
1
M7
FB
M8
H1
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
M2
N8
M3
J7
K7
K9
K1
L2
J3
K3
L3
F3
G3
E7
D3
C7
B7
T2
L8
B_ZQ3
J1
L1
J9
L9
VRAM _DDR3_HYNIX_256MX16
EFCA
VR
VR
EFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A1
0/AP
A1
1
2/BC
A1
3
A1
A1
4
NC
BA0
BA1
BA2
CK
CK
CK
E
OD
T
CS
S
RA
S
CA
WE
DQ
SL
DQ
SL
DM
L
DM
U
DQ
SU
DQ
SU
RE
SET
ZQ
NC#
J1
NC#
L1
J9
NC#
L9
NC#
BALL
96SDRAM DDR3
C_VMB1
VREF
D_VMB1
VREF
FB
B_CMD920,26
FB
B_CMD1120,26
VMB_
VMB_
VMB_
VMB_
FB
VMB_
VMB_
B_CMD520,26
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
FB
VMB_
VMB_
FB
FB
FB
FB
FB
FB
WDQS520
RDQS520
WDQS620
RDQS620
B_CMD820,26
B_CMD2520,26
B_CMD1020,26
B_CMD2420,26
B_CMD2220,26
B_CMD720,26
B_CMD2120,26
B_CMD620,26
B_CMD2920,26
B_CMD2320,26
B_CMD2820,26
B_CMD2020,26
B_CMD420,26
145
TP
B_CMD1220,26
B_CMD2720,26
B_CMD2620,26
CLK120
CLK1#20
B_CMD1920
B_CMD1820
B_CMD1620
B_CMD3020,26
B_CMD1520,26
B_CMD1320,26
DM520
DM620
R9
D
GN
D D
C C
B B
B_CMD9
FB
B_CMD11
FB
B_CMD8
B_CMD25
FB
B_CMD10
FB
B_CMD24
FB
B_CMD22
FB
FB
B_CMD7
FB
B_CMD21
FB
B_CMD6
B_CMD29
FB
B_CMD23
FB
B_CMD28
FB
B_CMD20
FB
FB
B_CMD4
FB
B_A15_3
B_CMD12
FB
B_CMD27
FB
B_CMD26
FB
VMB_
CLK1
CLK1#
VMB_
B_CMD19
FB
FB
B_CMD18
FB
B_CMD16
FB
B_CMD30
FBB_CMD15
B_CMD13
FB
B_CMD5
FB
42 243/F_4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
VD
D#B2
D#D9
VD
D#G7
VD
VD
D#K2
VD
D#K8
D#N1
VD
D#N9
VD
VD
D#R1
VD
D#R9
VD
DQ#A1
VD
DQ#A8
DQ#C1
VD
DQ#C9
VD
VD
DQ#D2
VDDQ#E9
DQ#F1
VD
VD
DQ#H2
VD
DQ#H9
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSSQ
VSSQ
VSSQ
#D1
#D8
VSSQ
VSSQ
VSSQ
VSSQ
#G1
VSSQ
#G9
VSSQ
E3
L0
F7
L1
F2
L2
F8
L3
H3
L4
H8
L5
G2
L6
H7
L7
D7
U0
C3
U1
C8
U2
C2
U3
A7
U4
A2
U5
B8
U6
A3
U7
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
A9
B3
B3
E1
E1
G8
G8
J2
J2
J8
J8
M1
M1
M9
M9
P1
P1
P9
P9
T1
T1
T9
T9
B1
#B1
B9
#B9
D1
D8
E2
#E2
E8
#E8
F9
#F9
G1
G9
GN
D
+1.
5V_GFX
5V_GFX
+1.
+1.
5V_GFX
44
R9
1.33K/F_4
46
R9
1.33K/F_4
Please close to M7
5V_GFX
+1.
VMB_
DQ46 20
DQ41 20
VMB_
DQ45 20
VMB_
DQ43 20
VMB_
DQ44 20
VMB_
VMB_
DQ42 20
VMB_
DQ47 20
VMB_
DQ40 20
DQ54 20
VMB_
DQ49 20
VMB_
VMB_
DQ55 20
VMB_
DQ48 20
VMB_
DQ52 20
VMB_
DQ50 20
DQ53 20
VMB_
DQ51 20
VMB_
Frame buffer CLK Termination
VMB_
VREF
C_VMB1
124
C1
0.01U/50V_4X
CLK1
R9
12
41 162/F_4
125
C1
2.2U/6.3V_4X
CLK1#
VMB_
+1.
5V_GFX
45
R9
1.33K/F_4
47
R9
1.33K/F_4
Please close to M8
5V_GFX
+1.
VMB_
WDQS420
VMB_
RDQS420
VMB_
VMB_
VMB_
WDQS720
VMB_
RDQS720
GN
VREF
D_VMB1
126
C1
0.01U/50V_4X
TP
DM420
DM720
D
146
R9
43 243/F_4
12
127
C1
2.2U/6.3V_4X
VREF
C_VMB1
VREF
D_VMB1
FB
B_CMD9
B_CMD11
FB
B_CMD8
FB
B_CMD25
FB
B_CMD10
FB
FB
B_CMD24
FB
B_CMD22
FB
B_CMD7
B_CMD21
FB
B_CMD6
FB
B_CMD29
FB
B_CMD23
FB
FB
B_CMD28
FB
B_CMD20
FB
B_CMD4
FB
B_A15_4
B_CMD12
FB
FB
B_CMD27
FB
B_CMD26
CLK1
VMB_
CLK1#
VMB_
FB
B_CMD19
FB
B_CMD18
FBB_CMD16
B_CMD30
FB
B_CMD15
FB
B_CMD13
FB
FB
B_CMD5
FB
M8
M8
VR
H1
VR
N3
A0
P7
A1
P3
A2
N2
A3
P8
A4
P2
A5
R8
A6
R2
A7
T8
A8
R3
A9
L7
A1
R7
A1
N7
A1
T3
A13
T7
A1
M7
NC
M2
BA0
N8
BA1
M3
BA2
J7
CK
K7
CK
K9
CK
K1
OD
L2
CS
J3
RA
K3
CAS
L3
WE
F3
DQ
G3
DQ
E7
DM
D3
DM
C7
DQ
B7
DQ
T2
RE
L8
B_ZQ2
ZQ
J1
NC#
L1
NC#
J9
NC#
L9
NC#
VRAM _DDR3_HYNIX_256MX16
EFCA
EFDQ
0/AP
1
2/BC
4
E
T
S
SL
SL
L
U
SU
SU
SET
J1
L1
J9
L9
96-
BALL
SDRAM DDR3
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQU6
DQ
D#B2
VD
VD
D#D9
VD
D#G7
D#K2
VD
D#K8
VD
VD
D#N1
VD
D#N9
D#R1
VD
D#R9
VD
DQ#A1
VD
DQ#A8
VD
VD
DQ#C1
VDDQ#C9
DQ#D2
VD
VD
DQ#E9
VD
DQ#F1
DQ#H2
VD
DQ#H9
VD
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#
VSS#T9
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
VSSQ
#B1
#B9
#D1
#D8
#E2
#E8
#F9
#G1
#G9
E3
L0
F7
L1
F2
L2
F8
L3
H3
L4
H8
L5
G2
L6
H7
L7
D7
U0
C3
U1
C8
U2
C2
U3
A7
U4
A2
U5
B8
A3
U7
B2
D9
G7
K2
K8
N1
N9
R1
R9
A1
A8
C1
C9
D2
E9
F1
H2
H9
A9
A9
B3
B3
E1
E1
G8
G8
J2
J2
J8
J8
M1
M1
M9
M9
P1
P1
P9
P9
T1
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
GN
D
+1.
+1.
5V_GFX
5V_GFX
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
VMB_
DQ36 20
DQ32 20
DQ37 20
DQ33 20
DQ38 20
DQ35 20
DQ39 20
DQ34 20
DQ60 20
DQ58 20
DQ63 20
DQ56 20
DQ61 20
DQ59 20
DQ62 20
DQ57 20
27
C1
128 0.1U/16V_4X
C1
130 0.1U/16V_4X
C1
132 0.1U/16V_4X
C1
134 0.1U/16V_4X
C1
136 0.1U/16V_4X
138 0.1U/16V_4X
C1
140 0.1U/16V_4X
C1
142 0.1U/16V_4X
C1
144 0.1U/16V_4X
C1
146 1U/6.3V_4X
C1
C1
A A
5
4
148 1U/6.3V_4X
C1
150 1U/6.3V_4X
C1
152 1U/6.3V_4X
C1
154 *4.7U/6.3V_4X
C1
156 *4.7U/6.3V_4X
158 10U/6.3V_6X
C1
160 10U/6.3V_6X
C1
B2A B2A
C1
129 0.1U/16V_4X
C1
131 0.1U/16V_4X
C1
133 0.1U/16V_4X
C1
135 0.1U/16V_4X
C1
137 0.1U/16V_4X
139 0.1U/16V_4X
C1
141 0.1U/16V_4X
C1
143 0.1U/16V_4X
C1
145 0.1U/16V_4X
C1
147 1U/6.3V_4X
C1
C1
149 1U/6.3V_4X
C1
151 1U/6.3V_4X
C1
153 1U/6.3V_4X
C1
155 *4.7U/6.3V_4X
C1
157 *4.7U/6.3V_4X
159 10U/6.3V_6X
C1
161 10U/6.3V_6X
C1
3
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
6P-GT_DDR3 - B2
6P-GT_DDR3 - B2
6P-GT_DDR3 - B2
N1
N1
N1
sday, August 25, 2015 27 49
sday, August 25, 2015 27 49
sday, August 25, 2015 27 49
Tue
Tue
Tue
1
1A
1A
1A
of
of
of
Page 28
5
4
3
2
1
28
TO VGA
DP
D D
V
+3
30 mils
C2
10u/6.3V_6
L5 80o
35
hm@100MHz
RX_IVDD33
43
C2
0.1u/16V_4
42
C2
*0.1u/16V_4
20mils
15mils
_IVDD
RX
IVDDO Pin32 is Regulator Power output 1.8V
IV
DDO
35
C3
0.1u/16V_4
20mils
38
C2
0.1u/16V_4
R1
09 *SHORT_6
DDO
IV
10
40
29
U1
4
CRT
V
C3
62*0 .1u/16V_4
190.1u/16V_4
10mils
C2
_HPD
CRT_TXP0_C
_TXN0_C
CRT
CRT
_TXP1_C
CRT
_TXN1_C
CRT
_AUXP_C
CRT
_AUXN_C
10mils
550.1u/16V_4
CRT_HPD13
C3
_AVCC
_AVCC
R1
R1
10*2.2K_4
11*2.2K_4
11 0.1u/1 6V_4
C300 0.1u/ 16V_4
95 0.1u/1 6V_4
C2
C2
80 0.1u/1 6V_4
34 0.1u/1 6V_4
C3
C3
33 0.1u/1 6V_4
+3
0929 modify
C2
CRT
C C
B B
V
+3
IV
DDO
30mils
R1
38*100K_4
R1
39*100K_4
L4 80ohm@100MHz
C2
37
10u/6.3V_6
CRT
_AUXN
CRT_AUXP
CRT_AUXP3
CRT_AUXN3
20mils 10mils
+5V
_TXP03
CRT
_TXN03
CRT_TXP13
CRT_TXN13
CRT
_AUXP
CRT
_AUXN
RX
RX
IT6515 stuff
IT6516 un-stuff
33
D
HP
22
RX
0P
23
RX
0N
25
RX
1P
26
RX
1N
19
RX
AUXP
18
RX
AUXN
15
DCA
UXP
14
DCA
UXN
21
AVC
C
27
AVC
C
28
C
ASPVC
36
SDA
PC
35
PCSCL
D
PW
31
R1
12
*10K_4
30
DD
DD
DD33
OV
OV
IV
IT6515FN
11
20
39
37
32
DD
DD
DD
IVDD
IV
IV
IVDDO
D
GN
41
IV
UVDDH
MC
URDB
PSCL
IS
PSDA
IS
VG
ADDCCLK
VG
ADDCSDA
VSY
HS
YNC
VD
IORP
IOGP
IOB
RS
RS
VD
CO
IT6515FN_QFN-40
DD33
IV
all stage need confirm 6515 or 6516
IT6515 stuff 0 ohm
IT6516 un-stuff 0 ohm
38
5V
MCU
24
G
12
13
17
16
1
NC
2
6
DC
9
8
7
P
34
VD
3
VG
ET
DA
MP
A_RST
5
4
URDBG
R1
08 *0_6
DDCCL
DDCDA
VSYNC
YNC
HS
C2
64
0.1u/16V_4
CRT_RED
CRT
_GRE
CRT_BLU
K_R
T_R
20mils
R1
34 22/J_4
R1
35 22/J_4
VSYN
HS
DA
C_VDDC
C261
7u/10V_6
4.
R1
17 200/F_4
19
TP
C 29
YNC 29
TP
12
C265
0.1u/16V_4
CRT
hm@100MHz
DAC_VDDC
VDD5
DDCCL
DDCDA
CRT
_RED 29
CRT_GRE 29
CRT
_BLU 29
DA
C_VDDC
20mils
L780o
K 29
T 29
20mils
IV
DDO
+3V2,5,9,10,11,12,13,14,16,17,18,19,21,29,30,31,32,33,34,35,36,37,39,40,41,42,45,46,47
+5V13,29,30,32,33,35,39,45
A A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Si
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
to VGA iT6165
to VGA iT6165
to VGA iT6165
DP
DP
DP
1
1A
1A
1A
of
of
of
49Tuesday, August 25 , 2015
49Tuesday, August 25 , 2015
49Tuesday, August 25 , 2015
28
28
28
Page 29
5
CRT
V
BP7+9
BP7-9
C
Y
C
Y
7002K
5
4
5
4
C1_SCL_C
I2
I2
C1_SDA_C
+3
2
V
CRT
HSYNC
VSYNC
CRT
PC
US
US
*0_4
*TSI@0_4
+3
BP7+
BP7-
TP
H_BRIGHT11
1
+5
+5
V
V
ED
P_HPD13
ED
ED
Bo
_INT
C2
41
0.1u/16V_4
34
C2
0.1u/16V_4
VI
N
C9
4.
Add 10 ohm
Prevent CPU
damage
P_AUXP3
P_AUXN3
ED
P_TXP13
ED
P_TXN13
ED
P_TXP03
P_TXN03
ED
8 *0_4
R1
R1
5 *0_4
60 *0_4
R4
R4
57 *0_4
P_TXP23
ED
EDP_TXN23
P_TXP33
ED
EDP_TXN33
ard_ID413
S5
R1
10K
_4
TP
C6
1000p/
7u/25V_8
1A-5
50V_4
LC
DVCC
R1
3 *SHORT_4
1 33_4
R1
ED
ED
ED
EDP_TXN1
ED
EDP_TXN0
ED
ED
ED
ED
R454 33_4
Prevent ESD/EOS Layout near device
_INT
S0
2014/01/10 Remove U29 and add U40 and U41.
1C-1
1
U1
1
OE
VC
D D
C C
HS
VSYN
2013/
12/12 change eDP pin define
colayout FHD Panel for A2 stage
YNC28
C28
R4
68 *100K_4
R464 *100K_4
P_HPD
ED
C1
/50V_4
180P
HS
VSYN
Prevent ESD/EOS Layout near device
B B
Touch Panel-I2C
Touch Panel-USB
eDP 4k*2k
#
2
YNC
A
3
GN
D
M74VHC1GT125DF2G
U9
1
#
OE
VC
2
C
A
3
D
GN
M7
4VHC1GT125DF2G
P_AUX_C
ED
R2
TP
_RST#
1 *100K_4
R1
2 *TSI@10K_4
EDP_AUX#_C
eDP FHD
US
US
TS
_EN37
_EN
TS
R5
2014/03/11 Add R698 for TS_EN short TP_INT,
1C1-2
for issue debug.
Touch Panel interrupt
A A
TP
_INT_PCH13
S5
5
3
Q2
2N
R6
CRT
CRT
CRT_BLU28
P_AUXP
P_AUXN
P_TXP1
P_TXP0
CCD-USB
P_TXP2
P_TXN2
P_TXP3
P_TXN3
C660
180P/50V_4
4
_RED28
_GRE28
TP
_PWR
C6
0.1u/16V_4
5 *SHORT_8
R2
V
+3
V
+5
+3
V
C2
9 .1U/16V_4
C21 .1U/16V_4
82 .1U/16V_4
C6
C680 .1U/16V_4
84 .1U/16V_4
C6
C683 .1U/16V_4
C662 .1U/16V_4
C6
61 .1U/16V_4
C671 .1U/16V_4
C6
64 .1U/16V_4
4
88
VI
N
IGHT
BR
ED
P_HPD_R
BOARD_ID4_TOUCH_S
86
C6
1000p/50V_4
MA
X 1.5A
C6
91
*1u/6.3V_4
US
BP8+9
BP8-9
US
_EN
TS
R1
30
75/F_4
CCD_
PWR
C7
0.
1u/10V_4_X7R
R1
6 *SHORT_8
R1
7 *SHORT_8
C6
92
*1u/6.3V_4
DVCC_R
LC
4 *SHORT_6
R1
R4
74 *SHORT_6
69 *0_4
R4
P_AUX_C
ED
ED
P_AUX#_C
ED
P_TXP1_C
EDP_TXN1_C
P_TXP0_C
ED
EDP_TXN0_C
56 *SHORT_4
R4
R4
55 *SHORT_4
*SHORT_4
R8
ll Sensor (HSR)
Ha
2
D2
*VPORT_6
R1
R1
19
25
75/F_4
75/F_4
HSYNC
CRT
VDD5
CRT
VSYNC
CRT
K
DDCCL
_R1
CRT
CRT
_G1
T
DDCDA
CRT
_B1
C8
50V_4
1000p/
BLIGHT
V_
CCD_
PWR
_PWR
TP
_RST#
TP
_ON
BL
BP8+_R
US
US
BP8-_R
P_TXP2_C
ED
ED
P_TXN2_C
_EN_CR
TS
P_TXP3_C
ED
ED
P_TXN3_C
TP
_INT
+3
VPCU
R4
45
R4
*SHORT_6
21
C658
4.7U/10V_6
t:AL009249000 -- BCD
1s
2nd:AL009132001 -- ANC
06
C3
5.6p/16V_4
U1
1
1
2
2
3
GN
4
4
5
5
*RClamp0524P
U1
1
1
2
2
3
GN
4
4
5
5
*RClamp0524P
CN2
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
49 *100K_4
1
3
MR1
AH9249NTR-G1
+5
2
3
2
V
C2
5.6p/16V_4
D_3/8
D_3/8
5
G_
G_
G_
0
G_
3
Q4
0
3
T
OU
IN
GN
D
AP2331SA-7
L9
L8
L6
57
94
C2
5.6p/16V_4
10
CRT
10
9
9
7
CRT
7
6
DDCCL
6
10
10
9
9
7
DDCDA
7
6
6
4
CRT
CRT
CRT
CRT
1
2
HSYNC
VSYNC
VDD5
K
_R1
_G1
_B1
T
CRT
BLM18BB470_6
BLM18BB470_6
BLM18BB470_6
C2
5.6p/16V_4
C8
VDD5
05 *0.1u/16V_4
CRT
VDD5
CRT
_R1
_G1
CRT
CRT
_B1
93
56
05
C2
C3
5.6p/16V_4
5.6p/16V_4
C8
08 *0.22u/6.3V_4
01 *220p/50V_4
C8
99 0.1u/16V_4
C7
C2
32 10p/50V_4
C2
40 10p/50V_4
00 *10p/50V_4
C8
C8
04 *10p/50V_4
D PowerLCD CONNECTOR
LC
ED
P_VDD_EN11
uch screen level shift I2C(reserve)
To
S5
I2
C1_SDA13
C1_SCL13
I2
1
04071-001
50398-
PCH_BLON11
PC
H_BLON_EC37
LI
D#
21
3
D2
*VPORT_6
3
6
7
2
8
3
9
4
10
5
CRT
CRT
CRT
DDCCL
DDCDA
R4
8 *short_4
+3
R4
R3 *short_4
2
CN5
1617
111
CRT
_11
TP
20
T
DDCDA
CRT
HSYNC
VSYNC
CRT
DDCCL
K
+3
V
U1
6
IN
4
IN
3
N/OFF
O
243AT11U
G5
7
R3
100K_4R19 *100K_4
R3
5 *TSI@0_4
Q4
6
2
5
1
43
R22 *TSI@0_4
PC
H_BLON_R
R2
100K_4
Q1
7002DW
2N
1B-3 2013/12/10 change Q3.3 from +3V to +3VPCU.
VDD5
VSYNC
HSYNC
1u/
V
CRT
K
T
6.3V_4
C45
2
12
13
14
15
CONN
ED
*T
P_VDD_EN_R
SI@2N7002DW
*short_4
T 28
DDCDA
DDCCL
K 28
T
DDCDA
DDCCL
K
Power trace tracking
1
OU
T
2
C3
5
*0.1u/16V_4
+3
V
R2
6
*TSI@10K_4
+3
V
R9
_4
10K
BL
6
1 3
1
Size Document N umber Rev
Size Document N umber Rev
Size Document N umber Rev
Date: Sheet
Date: Sheet
Date: Sheet
I2C1_SDA_C
C1_SCL_C
I2
R7
_4
10K
5
GN
GN
R2
*TSI@10K_4
BL#
4 3
D
D
7
2
1
VDD5
612.2K_4
CRT
R5
542.2K_4
R5
V2,5,9,10,11,12,13,14,16,17, 18,19,21,28,30,31,32,33,34,35,36,37,39, 40,41,42,45,46,47
+3
+5
V13,28,30,32,33,35,39,45
+3
VPCU5,10,31,32,34,35,37,38,39,46,47
N38,39,40,41,42,43,44,45,46,47
VI
C4
C3
8
*2.2u/10V_8
0
3
0.1u/16V_4
S0
TPD->100kHz,TS=400Khz
Intel design guide suggestion
MCP PIN 10u.
Per inch 3u TS=3x5inch
400kHz10~100u =2.4~0.4k.
100Khz 10~100u=9k~1k.
+3VPCU
0
R1
*100K_4
D#
LI
LID591#,EC intrnal PU
D1
1N
4148WS
_ON
2
Q3
DT
C144EUA
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
/LVDS/CAMERA/LID
/LVDS/CAMERA/LID
/LVDS/CAMERA/LID
CRT
CRT
CRT
1
29
DVCC
LC
C3
9
0.01u/50V_4
LI
D# 37
EC
_FPBACK# 37
C3
22u/6.3V_8
29
29
29
DVCC
LC
4
1A
1A
1A
of
of
of
49Monday, September 07, 2015
49Monday, September 07, 2015
49Monday, September 07, 2015
Page 30
H
DMI
5
<HDM>
4
3
2
1
30
om PCH
Fr
IN
82 0.1u/16V_4
+3
V
R2
*1M_4
R2
65 *120/F_4
R2
55 *120/F_4
R2
51 *120/F_4
48 *120/F_4
R2
HDM
72
EM
HDM
1
C4
C4
78 0.1u/16V_4
C4
77 0.1u/16V_4
C4
76 0.1u/16V_4
C4
75 0.1u/16V_4
C4
74 0.1u/16V_4
C4
71 0.1u/16V_4
C4
70 0.1u/16V_4
I_DDCCLK_SW13
I_DDCDATA_SW13
R2
49 *0_4
V
+3
+3
V
PS8407 -> vendor suggestion stuff
5.49k CS25492FB12
PS8201 -> Stuff 4.99k CS24992FB26
2
3
6
Q2
2N7002K
R2
58 *0_4
I
IN
T_HDMITX2N_C
T_HDMITX1N_C
IN
IN
T_HDMITX0N_C
T_HDMICLK-_C
IN
D D
DDCCLK & DDCDATA PU near PS8407
+3
V
70 *2.2K_4
R2
R2
71 *2.2K_4
PS8
407 internal hav e PU , need modify
HDM
I-detect
C C
I_DDCCLK_SW
HDM
I_DDCDATA_SW
HDM
IN
_D23
_D2#3
IN
_D13
IN
_D1#3
IN
_D03
IN
_D0#3
IN
_CLK3
IN
IN
_CLK#3
S0 S0
IN
T_HDMI_HPD13
IN
T_HDMITX2P_C
IN
T_HDMITX1P_C
IN
T_HDMITX0P_C
B B
INT_HDMICLK+_C
T_HDMITX2P_C_R
IN
T_HDMITX2N_C_R
IN
T_HDMITX1P_C_R
IN
T_HDMITX1N_C_R
IN
T_HDMITX0P_C_R
IN
T_HDMITX0N_C_R
IN
T_HDMICLK+_C_R
IN
T_HDMICLK-_C_R
HDM
I_DDCCLK_SW
HDM
I_DDCDATA_SW
I_MB_HPD_R
HDM
38 4.99K_4
R2
I_MB_HPD_R
HDM
HDM
I4K2K_PRE
I4K2K_ISET
HDM
I4K2K_DDCBUF
HDM
HDM
I4K2K_EN
I4K2K_EQ
HDM
I4K2K_CFG
HDM
1
2
4
5
6
7
9
10
38
39
3
36
8
16
34
14
13
17
23
18
U2
3
_D2+
IN
_D2-
IN
_D1+
IN
_D1-
IN
_D0+
IN
_D0-
IN
_CLK+
IN
IN_CLK-
L_SRC
SC
A_SRC
SD
HP
D_SRC
PD
#
I2C_STL_EN
E
PR
IS
ET
DDCB
DCI
N_EN/SCL_CTL
EQ
/I2C_ADDR0
CF
G/I2C_ADDR1
RE
XT
201
PS8
VC
VC
UF/SDA_CTL
VC
VC
VC
GN
GN
GN
GN
GN
GN
GN
GN
GN
GN
C4
85
0.1u/16V_4
PS8407 ->vendor suggestion stuff 4.7k
CS24702JB38
PS8201 -> No stuff
T_D2+
OU
T_D2-
OU
T_D1+
OU
T_D1-
OU
T_D0+
OU
T_D0-
OU
T_CLK+
OU
OUT_CLK-
L_SINK
SC
A_SINK
SD
HP
D_SINK
VC
C33[1]
VCC33[2]
CTX15[1]
CTX15[2]
CRX15[1]
CRX15[2]
CTA15[1]
GN
GN
D_PAD[1]
D_PAD[2]
D_PAD[3]
D_PAD[4]
D_PAD[5]
D_PAD[6]
D_PAD[7]
D_PAD[8]
D_PAD[9]
D_PAD[10]
D1]
D[2]
V
+3
30
29
27
26
25
24
22
21
32
33
28
11
37
20
31
12
40
19
15
35
41
42
43
44
45
46
47
48
49
50
C4
0.01u/50V_4
260m
65
HDM
I4K2K_PRE
HDMI4K2K_ISET
HDMI4K2K_EQ
I4K2K_CFG
HDM
HDMI4K2K_DDCBUF
I4K2K_EN
HDM
IN
T_HDMITX2P_C
IN
T_HDMITX2N_C
IN
T_HDMITX1P_C
IN
T_HDMITX1N_C
IN
T_HDMITX0P_C
IN
T_HDMITX0N_C
IN
T_HDMICLK+_C
IN
T_HDMICLK-_C
HDM
I_DDCCLK_MB
HDM
I_DDCDATA_MB
I_MB_HPD
HDM
A (30mils)
Reserve no stuff
HDM
I_DDCCLK_MB
HDM
I_DDCDATA_MB
R2
682.2K_4
R2
692.2K_4
V
+5
D3
2RB501V-40
21
D3
1RB501V-40
21
HDMI connector
+3
V
+1
.5V
V
+5
5
Q4
3
C4
0.1u/16V_4
+3
V
R2
29
*4.7K_4
R2
28
*4.7K_4
IN
AP2331SA-7
84
1
OU
T
2
GN
D
+3
V
C4
0.1u/16V_4
R2
80
*4.7K_4
R2
79
*4.7K_4
61
66
C4
*220p/50V_4
D6
*A
C4
62
0.1u/16V_4
+3
V
R2
26
*4.7K_4
R2
27
*4.7K_4
Z5125-01J
HDM
+3
+1.5V
V
R6
*4.7K_4
I_MB_HPD
C4
86
0.1u/16V_4
76
34 *SHORT_4
R2
12
35
R2
20K_4
+3
V
R2
4.7K_4
IN
T_HDMITX2P_C
IN
T_HDMITX2N_C
T_HDMITX1P_C
IN
IN
T_HDMITX1N_C
T_HDMITX0P_C
IN
T_HDMITX0N_C
IN
T_HDMICLK+_C
IN
T_HDMICLK-_C
IN
I_DDCCLK_MB
HDM
I_DDCDATA_MB
HDM
I_5V
HDM
HP
C4
63
0.01u/50V_4
39
_DET_CN
CN1
0
20
SH
ELL1
1
D2
+
2
D2 Shield
3
-
D2
4
D1
+
5
D1
Shield
6
D1
-
7
D0
+
8
D0
Shield
9
D0
10
CK
11
CK
12
CK
13
CE
14
NC
15
DDC
16
DDC
17
GN
18
+5
19
HP
HDMI connector
C4
64
0.01u/50V_4
+3
V
R2
40
*4.7K_4
+
Shield
Remote
CLK
DATA
D
V
DET
23
GN
D
22
GN
D
21
SH
ELL2
Pre
NC(Low) dB
1(High)
0
1.6
dB
M2.5
dB
default
+13%
-13%
12.4 HDMI ID disable
4.3
8.6
Output pre-emphasis settingPre
ISET
Power trace tracking
A A
+3
V2,5,9,10,11,12,13,14,16,17,18,19,21,28,29,31,32,33,34,35,36,37,39,40,41,42,45,46,47
V13,28,29,32,33,35,39,45
+5
ISET
EQ
CFG
DDCBUF
DCIN_EN
5
4
TMDS output swing adjustment
Receiver equalization setting
Configuration pin
enable active DDC buffer
DC coupling enable
CFGEQ
dB
dB
HDMI ID enable
dB
N/A
3
default
active DDC buffer with
default threshold
active DDC buffer without
internal pull up resistor
PS8401A
Pin
12
VDDRX
15
GND
ISET
34
37
VDD33
DCIN_ENDDCBUF
default,AC coupling input
DC coupling input
N/A
PS8201A
NC
NC
NC
NC
2
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
HDM
HDM
HDM
I (PS8407 4k*2k)
I (PS8407 4k*2k)
Date: Sheet of
Date: Sheet of
Date: Sheet of
I (PS8407 4k*2k)
1
30 49Tuesday, August 25, 2015
30 49Tuesday, August 25, 2015
30 49Tuesday, August 25, 2015
1A
1A
1A
Page 31
5
4
3
2
1
Giga LAN (LAN)
LA
NVCC
AL2
05 12p/50V_4
XT
C4
1
2
Y1
25M
HZ +-30PPM
4
29
12
28
AL2
CKXT
KREQB
CL
13
XT
27
AL1
CKXT
P
HSI
14
AL1
26
D0
LE
N
HSI
15
PCI
3
06 12p/50V_4
C4
25
D2
D1
LE
LE
LA
IS
CLK_P
CLK_N
REF
REF
16
E_REQ_LAN#_R
REG
OUT
VDDREG
DVDD1
NWAKEB
OLA TEB
PERST
HSO
HSO
34
TP
32
TP
33
TP
24
23
22
0
21
20
19
B
18
N
17
P
CL
K_PCIE_LANN 11
CL
K_PCIE_LANP 11
PCI
PCI
E_LAN_WAKE#_R
PCI
OLATEB
IS
B
PERST
E_RX4-_LAN_C
PCI
PCIE_RX4+_LAN_C
E_TXN4_LAN 9
E_TXP4_LAN 9
REG
OUT
LA
NVCC
VDD1
0
15 0.1u/16V_4
C4
C419 0.1u/16V_4
IO
AC No Stuff
77 *SHORT_4
R1
R176 *0_4
+3V
R1
73
1K_4
PL
TRST# 2,12,16,19,33,34,37
AC_RST# 3 4,37
IO
E_RXN4_LAN 9
PCI
E_RXP4_LAN 9
PCI
Co
nsider VCC33 may be connected to Main
Power or chipset/b ios's GPO, the pull-low
resistor R14 can be NC only when Main Power
or chipset/bi os's GPO can ensure to dri ve the
ISOLATEB pin to a voltage level < 0.8V at the
system state S3~S5.
If the ISOLATEB pin can not be well-controlled to
a voltage lev el < 0.8V at S3~S5, the p ull-low
resistor R14 is needed to make sure the LAN
chip is well isolated.
R172
*15K_4
For RTL8111H
Place 0.1uF,4.7uF CAP close to each VDD33 pin-- 11, 32
RTL8111H (LDO mode)
REG
OUT
D D
VDD1
0
0
VDD1
C C
MD
MD
MD
MD
MD
MD
I_0+
I_0-
I_1+
I_1I_2+
I_2-
R1
LA
VDD1
0
57 2.49K/F_4
LA
NVCC
U18
33
D
GN
1
MD
IP0
2
IN0
MD
3
AVDD1
4
IP1
MD
5
IN1
MD
6
MD
IP2(NC)
7
MD
IN2(NC)
8
AVDD1
MD
MDI_3-
NVCC
0
0
I_3+
RSET
mils
10
32
3
AVDD3
RTL8111H-CG
IP3(NC)
MD
9
31
10
30
RSET
IN3(NC)
MD
11
0
AVDD1
3
AVDD3
40 mils (Iout=1A)
C4
23
0.1u/16V_4
C8
41
0.1u/16V_4
C4
4.7U/6.3V_6
C8
26
43
4.7U/6.3V_6
close to each VDD10 pin-- 3, 8, 22, 30
40 mils (Iout=1A) 40 mils (Iout=1A)
R1
64 *SHORT_8
07
C4
0.1u/16V_4
11
C4
0.1u/16V_4
C4
0.1u/16V_4
cl
ose to each VDD10 pin-- 22
(reserve)
18
13
C4
0.1u/16V_4
42
C8
0.1u/16V_4
12
C4
*1U/6.3V_4
VDD1
31
0
14
C4
*0.1u/16V_4
Le
akage circuit (MPC)
+3V
R1
CLK_PCIE_REQ4# have PU 10k.
B B
S0
CLK_PCIE_LAN_REQ#11
99
*10K/F_4
3
Q2
2N7002K
4
97 *0/J_4
R1
EC_PCU
63 *SHORT_4
PCI
E_WAKE#10,34
PCI
E_LAN_WAKE#10
AC_LAN_W AKE#37
IO
Re
serve IOAC No Stuff
5
R2
*IOAC@10K_4
1
37
R2
**IOAC@100K/J_4
36
+3VPCU
A A
**[email protected]/16V_4
IOAC_LANPW R#37
C4
56
R6
R6
09 *0_4
11 *0_4
R6
Q2
5 *IOAC@AO3413
3
2
55
C4
**IOAC@1000p/50V_4
+3V_LA
N
98
R1
*IOAC@0_8
+3V
2
R6
C4
10u/6.3V_6
+3V
1
2
3
3
Q4
2N7002K
12 *0/J_4
35
R1
85
10K/F_4
MAIN POWER(3V_S0)
PCI
E_REQ_LAN#_R
LANVCC
R6
13
1K_4
1
PCI
E_LAN_WAKE#_R
52
C8
0.1u/16V_4
4
29
C4
*0.1u/16V_4
LA
LANVCC
NVCC
+3V_S5
Stuff
14 *SHORT_8
R2
31
C4
*0.1u/16V_4
Tramsformer
MD
I_0+
MD
I_0-
MD
I_1+
MD
I_1-
I_2+
MD
I_2-
MD
I_3+
MD
I_3-
MD
C8
37
0.01U/50V/X7R_4
3
2
U4
1
TC
2
TD
3
TD
4
TC
5
TD
6
TD
7
TC
8
TD
9
TD
10
TCT4
11
TD
12
TD
MC
T1
MX1
1+
MX1
1-
T2
MC
2+
MX2
2-
MX2
MC
T3
MX3
3+
MX3
3-
MCT4
4+
MX4
4-
MX4
GND
TRANSFOR MER
25
24
T1
23
+
22
-
21
T2
20
+
19
-
18
T3
17
+
16
-
15
14
+
13
-
Layout:All termination
signal should have 30
mil trace
LAN_MCT0
LA
N_MX0+
LA
N_MX0-
LA
N_MCT1
LA
N_MX1+
LA
N_MX1-
LA
N_MCT2
N_MX2+
LA
N_MX2-
LA
N_MCT3
LA
N_MX3+
LA
N_MX3-
LA
83 75/F_6
75 75/F_6
R1
R1
2
R168 75/F_6
R158 75/F_6
RM9
TE
29
C8
1000P/3KV_1808
RJ
45 Connector
CN9
N_MX0+
LA
LA
N_MX0N_MX1+
LA
N_MX2+
LA
N_MX2-
LA
N_MX1-
LA
N_MX3+
LA
N_MX3-
LA
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Si
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
1
2
3
4
5
6
7
8
LAN_RJ45
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
KB/T
KB/T
KB/T
P/FAN
P/FAN
P/FAN
1
9
10
31 49Monday, S eptembe r 07, 20 15
31 49Monday, S eptembe r 07, 20 15
31 49Monday, S eptembe r 07, 20 15
of
of
of
1A
1A
1A
Page 32
5
Co
dec(ADO)
D D
+1
.5VA
C6
16
C6
15
10u/6.3V_4
AD
OGND
Place next to pin 40
Analog
Digital
C C
B B
Co
A A
L15
PVD
D
PB
T
ied at one point only under
the codec or near the codec
R4
03 *0_4
R4
37 *0_4
06 *0_4
R4
R401 *0_4
07 *0_4
R4
R411 *SHORT_4
C6
56 *1000p/50V_4
99 *0.1u/16V_4
C5
OGND
AD
Cap need near AVDD1 and AVDD2
power source input
dec PWR 5V(ADO)
+5
V
C634
*0.1u/16V_4
0.1u/16V_4
Y16080 8T-600Y -N(60, 3A)
C617
*10u/6.3V_6
C5
10u/6.3V_4
C5
10u/6.3V_4
L19
U3
1
3
IN
2
GN
1
SH
*G923-330T1UF
R4
10 *0_4
D
DN
AD
OGND
C6
22 10u/6.3V_4
C5
95
94
0.1u/16V_4
Low is power down
amplifier output
C5
93
92
0.1u/16V_4
R3
67 *SHORT_6
V
+3
ANALOG DIGITAL
HCB2012KF220T60/6A/22ohm_8
4
OUT
5
SET
AD
DM
DM
OGND
V_PVDD
+5
L_S
L_S
R_SPK-
R_
PD
TP
54
IC_DAT_L
IC_CLK_L
R4
R409
*10K/F_4
PK+
PK-
SPK+
#
97
C5
0.1u/16V_4
08 *29.4K/F_4
+A
ZA_VDD
37
38
39
40
41
42
43
44
45
46
47
48
49
+A
79 *SHORT_4
R3
CB
P
AVSS2
O2-CAP
LD
AVDD2
PVD
D1
L+
SPK-
L-
SPK-
SPK-R-
SPK-
R+
D2
PVD
PD
B
SPDIF-OUT
DGND
ZA_VDD
84
C5
10u/6.3V_4
R3
78 22_4
C5
10p/50V_4
2410u/6.3V_4
C6
36
VDD
CP
DD
DV
1
70
C6
*10u/6.3V_6
252.2u/6.3V_4
C6
35
N
CB
IO0/DMIC-DATA
GP
2
IC_DATDMIC_CLK
DM
21
C730, C787 close U37 pin3 and L65
5
282.2u/6.3V_4
C6
34
VEE
CP
IO1/DMIC-CLK
GP
3
+5VA
ADOGND
33
-OUT-R
HP
SS
DV
4
DET
R3
DC-
77 *SHORT_4
31
32
-OUT-L
HP
C255
AL
ATA-OUT
SD
5
6
23
C6
*0.1u/16V_4
4
HP
-R2
-L2
HP
NE1-VREFO-L
LI
LI
NE1-VREFO-R
MI
C2-VREFO
DEC_VREF
CO
IN
T_AMIC-VREFO
30 2.2U/6.3V_4
C6
C6
29 10u/6.3V_4
R4
05 100K_4
AD
OGND
OGND
AD
C6
0.1u/16V_4
+5
VA
C6
31
10u/6.3V_4
Place next to pin 26
27
25
26
28
29
30
EF
VR
C2-VREFO
MI
NE1-VREFO-L
NE1-VREFO-R
LI
LI
ATA-IN
DD-IO
O3-CAP
T-CLK
BI
LD
SD
DV
7
8
9
C5
89 10u/6.3V_4
AC
Z_SDIN
D1
AVSS1
AVD
O1-CAP
LD
MI
C2-R/SLEEVE
MI
MIC2-L/RING2
MO
IFO/FRONT JD
SPD
MI
C2/LIN2 JD
HP/LINE1 JD
C
BEEP
SETB
SYN
RE
PC
10
11
12
PC
R3
76 33_4
88 *22p/50V_4
C5
LI
NE2-L
LI
NE2-R
NE1-L
LI
LINE1-R
C-CAP
NO-OUT
BEEP
U2
9
NC
24
23
22
LI
21
LI
20
R3
analog
19
18
SL
17
RING2
16
15
14
13
SEN
6Vrms
1.
C5
61 0.1u/16V_4
NE1-L
NE1-R
96 *SHORT_6
digital
C6
EEVE
Placement near Audio Codec
SEA
R3
R3
BEEP
62
C5
100p/50V_4
H_AZ_C ODEC_ RST# 1 0
PC
PC
H_AZ_C ODEC_ SYNC 10
PC
H_AZ_C ODEC_ SDIN0 10
H_AZ_C ODEC_ BITCLK 10
PC
H_AZ_C ODEC_ SDOUT 10
PC
AD
OGND
+3
VPCU
13 10u/6.3V_4
ace width of SLEEVE & RING2
tr
are required at least 40mil and
its length should be asshort as possible
90 200K_4
86 100K_4
_1
R3
56 22K_4
57
R3
4.7K_4
DV
DD_IO
Mute(ADO)
+AZA_VDD +1.5V
R349
1K_4
#
PD
R344
*10K/J_4
C5
53
*1u/10V_4
D8
D7
3
DC-
DC-
27
AD
OGND
_JD#
HP
+3
V
Ch
ange 47K to 22K for PCBEEP
D1
0 1N4148WS
D9
C5
87
0.1u/16V_4
Place next to pin 9
3
*RB500V-40
Q2
RB500V-40
*PJA138K
DET circuit(ADO)
+5
V
R3
60
*100K_4
Z_SPKR 10,12
AC
PC
BEEP_EC 37
+3V+1
CPU 1.5V
2
.5V
DET
R3
IC_DATA010
DM
DM
IC_CLK010
Analog
Digital
1N4148WS
70 *SHORT_4
R3
R3
66 *0_4
C5
90
10u/6.3V_4
2
1
7
AM
59 *0_4
H_AZ_C ODEC_ RST#
PC
P_MUTE# 37
2
R3
68 *SHORT_6
V
+5
+1
5V
1 3
45
R3
*1M_6
0
Q3
*DTC144EU
3
96
C5
*10u/6.3V_4
1
PVD
D
1
Q3
*AO3404
2
D-Mic (MIC)
+3
V_INT_DMIC-VREFO
05 *0_4
R6
06 *0_4
R6
DM
IC_DAT_L
R6
07 0_4
IC_CLK_L
DM
08 0_4
R6
CO-LAYOUT
03 *0_4
R6
1.Single DMIC
NSM0407DT (AL472376000)
SPM0437HD4H (AL000437000)
2.Dual DMIC
NSM0410DT (W/ Fortemedia algorithm)
Main MIC CS need connect to second MIC DATA
iversal Audio Jack
Un
C2-VREFO
MI
SLEEVE
RI
-L2
HP
HP
-R2
NE1-L
LI
LI
NE1-VREFO-L
LINE1-VREFO-R
NE1-R
LI
Co
21 2.2K/J_4
R4
R4
36 2.2K/J_4
NG2
50 4.7U/6.3V_6
C6
R4
28 4.7K_4
22 4.7K_4
R4
C6
45 4.7U/6.3V_6
dec PWR 1.5V(ADO)
DM
DM
44*10p/50V_4
C8
IC_DAT_L2
IC_CLK_L2
8*TVS/6pF_4
12
D2
R432
*10K/J_4
45*10p/50V_4
C8
Po
wer (ADO)
Demodulation Filter
+3
V
32
C5
*0.1u/16V_4
Vset =1.25V
Vout =Vset[1+AR(1,2)/AR(2,GND)]
DUAL_EN:PU
Single_GND:PD
C8
48 10u/6.3V_4
47 0.1u/16V_4
C8
46 10p/50V_4
C8
9
U1
6
5
4
12
D29*TVS/6pF_4
Single DMIC
DUAL MAIN
17 *SHORT_4
R4
R4
35 *SHORT_4
R4
31 62/F_4
24 62/F_4
R4
R425
*10K/J_4
1
D/EN
D
GN
VD
2
CS
DA
TA
3
D
K
GN
CL
SPM0437HD4H-B
ADPHONE/MIC/LINE combo (ADO)
HE
41
C6
C6
100p/50V_4
100p/50V_4
AD
OGND
69 *SHORT_6
R3
4
U3
3
2
1
+3
13
R2
*SP@0_4
DM
IC_CS
12
R2
SP@0_4
52
55
C6
100p/50V_4
IN
D
GN
DN
SH
*G923-330T1UF
V
07
R2
*0_4
R2
06 *0_4
08
R2
SP@0_4
DM
IC_DAT_L1
SLEEVE_R
RI
HP
HP
HP
48
C6
100p/50V_4
.5VA
+1
4
OU
T
5
87 *8.2K/F_4
R4
SET
R4
*10K/F_4
Single
PU: only SPM0437HD4H
PD: SPM0437HD4H & NSM0407DT Shared
Dual
PU & PD : NC
+3
V_INT_DMIC-VREFO
IC_CLK_L1
DM
43*10p/50V_4
42*10p/50V_4
D5*T
12
C4
C4
VS/6pF_4
NG2_R
-L3
-R3
_JD#
12
12
0
D2
AZ5125-01H.R7G
AZ5125-01H.R7G
1
+3
V_INT_DMIC-VREFO
88
37 *10u/6.3V_4
C4
38 *0.1u/16V_4
C4
36 *10p/50V_4
C4
U2
6
VD
5
DA
4
CL
*NSM0410DT
D4*T
12
DUAL SECOND
VS/6pF_4
12
1
D2
C5
*0.1u/16V_4
0
D/EN
D
GN
CS
TA
D
K
GN
4
D3
*AZ5125-01H.R7G
OGND
AD
32
85
1
V
+3
2
3
mbo Jack
Co
CN
20
4
3
1
2
5
6 7
2SJ3080-077111F
AD
OGND
ANALOG DIGITAL
Internal Speaker
40mil for each signal
SPK+
R_
R_
L_S
L_S
4
05 *SHORT_6
R8
SPK-
R8
10 *SHORT_6
PK-
24 *SHORT_6
R8
PK+
25 *SHORT_6
R8
4 ohm : 40mil for each signal
1003 change 0603type
86
C8
*68p/50V_4
96
C8
*68p/50V_4
85
C8
*68p/50V_4
SPK+_1
R_
SPK-_1
R_
PK-_1
L_S
L_S
PK+_1
98
C8
*68p/50V_4
1B-2
1B-5 2013/12/17 Change CN14 pin define
3
CN
345
2
1
SPK_CONN_4P
2013/12/04 Change PN and footprint.
17
6
.5V
+1
1U/6.3V_4
2
L18
12
C6
HCB1608KF-121T30_3A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
ALC255/HP/SPK
ALC255/HP/SPK
ALC255/HP/SPK
Date: Sheet
Monday, September 07, 2015 4932
Date: Sheet
Monday, September 07, 2015 4932
Date: Sheet
Monday, September 07, 2015 4932
1
of
of
of
1A
1A
1A
Page 33
5
4
3
2
1
2.5" SATA HDD (HDD) SATA ODD Connector(Remove)
3
CN1
23
D23
GN
1
GN
D1
2
SA
RX
P
RXN
D2
GN
N
TX
TX
GN
HDD CONN
P
GN
D3
3V
3.
3.
3V
3.
3V
GND
D
GN
D
GN
5V
5V
5V
D
GN
VD
RS
GN
D
12V
12V
12V
D24
D D
TA_TXP0_C
3
SATA_TXN0_C
4
5
TA_RXN0_C
SA
6
SA
TA_RXP0_C
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
24
DE
VSLP0_R
+5
V_HDD
R339 *0_4
0.01u/50V_4
99 *0_4
R2
60m
C526
ODD Power (SATA)(Remove)
C C
il
14 0.01u/50V_4
C6
07 0.01u/50V_4
C6
C598 0.01u/50V_4
C591 0.01u/50V_4
1B-4
C525
0.01u/50V_4
VSLP0 9,34
DE
C513
*0.1u/16V_4
C512
*0.1u/16V_4
AC
CEL_IN T2# 35
SA
TA_TXP0 11
SA
TA_TXN0 11
TA_RXN0 11
SA
SA
TA_RXP0 11
C5
11
10u/6.3V_6
+5
V
10 *SHORT_8
R3
C5
30
+
*100u/6.3V_3528
Connect to G-sensor INT2
LE23
HO
*H-TC315BC354D134P2
1
HO
LE19
*H-O138X114D138X114N
1
HOLE14
HOLE6
*O-ZRY-2
*O-ZRY-1
LE31
HO
*SPAD-RE1330X140NP
1
HO
LE27
*H-TC140BC315D140PB
1
HOLE15
HOLE5
*O-ZRY-3
*O-ZRY-4
LE3
HO
*h-tc315bc354d217p2
1
HO
LE28
*H-TC140I180BC315D140PB
1
HOLE22
*O-ZRY-5
HOLE11
*h-c256d134p2
LE24
HO
*H-TC315BC354D134P2
1
HO
LE8
*H-TC161BC256D161PB
1
HOLE29
*O-ZRY-12
LE26
HO
*H-TC315BC354D217P2
1
HO
LE7
*H-TC161BC256D161PB
1
HOLE21
*H-C118D118pb
HO
*H-O152X93D152X93N
HO
*H-TC315BC354D134P2
HO
LE13
*H-TC161BC256D161PB
1
LE20
LE25
1
HOLE16
*O-ZRY-7
33
HO
LE12
*H-TC161BC256D161PB
1
HOLE9
HOLE30
*O-ZRY-10
*O-ZRY-11
1
1
1
1
SP@ BOM
TPM@10u/6.3V_6C860
[email protected]/16V_4C863
[email protected]/16V_4C866
[email protected]/16V_4C867
17
20
23
26
22
27
21
15
16
28
NPCT650
+3V3_TPM
24
U44
LAD3
LAD2/SPI_IRQ
LAD1/MOSI
LAD0/MISO
LFRAME/SCS
SERIRQ
LCLK/SCLK
CLKRUN/GPIO04
LRESET/SPI_RST
LPCPD
+3V3_TPM_VSB
10
19
D3
D1
D2
VD
VD
VD
D1
GN
4
11
GPIO0/XOR_OUT
D2
GN
18
SLB9655 STUFF
R655 *TPM_I@0_6
R654 TPM_N@0_6
TPM@10u/6.3V_6C857
[email protected]/16V_4C859
5
VSB
PP
GPX/GPIO2
GPIO1
GPIO3/BADD
TEST
NC1
NC2
NC3
NC4
D3
D4
GN
GN
*TPM@NPCT650
25
+3V_S5
+3V
7
TPM_PP
6
GPX
2
1
9
TPM_BADD
8
3
12
13
14
BADD SELECTION
01EEh - EFh
'1' - pin is left open.
'0' - pin is pulled down.
GPXLPCPD
R669 *[email protected]_4
SLB9655 STUFF
R684 **TPM_N@10K_4
TPM_LRESET#
R683
*TPM_I@0_4
SLB9655 STUFF
7Eh - 7Fh
+3V3_TPM+3V3_TPM
+3V3_TPM
B B
TPM NPCT650 (TPM)
AL000650K01 :NPCT650AAAWX
AL009655K01 : SNI SLB9655TT1.2
CLKRUN#10,37
PLTRST#2,12,16,19,31,34,37
AL009655K01
AL000650K01
PLTRST#
LPC_LAD39,34,37
LPC_LAD29,34,37
LPC_LAD19,34,37
LPC_LAD09,34,37
LPC_LFRAME#9,34,37
IRQ_S ERIRQ9,37
PCLK_TPM9
R686 TPM_N@0_4
R687 0_4
SLB9655 Un-STUFF
R660 *[email protected]_4
TPMM 1.2
TPMM 2.0
A A
A,B,C P/N:AL009655K01(SLB9655TT1.2- FW4.31)
RAMP P/N: AL000650K01 (NPCT650AAAWX)
+3V_S5
+3V
R967 TPM@0_6
R685 *TPM@0_6
LPC_LAD3
LPC_LAD2
LPC_LAD1
LPC_LAD0
LPC_LFRAME#
IRQ_S ERIRQ
PCLK_TPM
TPM_CLKRUN#CLKRUN#
TPM_LRESET#
LPCPD
1
SLB9655 STUFFSLB9655 STUFF
5
4
3
1
1
1
1
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
HDD/ODD/TPM NPCT650
HDD/ODD/TPM NPCT650
HDD/ODD/TPM NPCT650
Date: Sheet of
Date: Sheet of
2
Date: Sheet of
1
1
1
1
1A
1A
1A
33 49Tuesday, August 25, 2015
33 49Tuesday, August 25, 2015
33 49Tuesday, August 25, 2015
Page 34
5
NG
FF_M.2 WiFi & BT (NGF)
US
BP6+9
US
BP6-9
D D
E_TXP3_WLAN9
PCI
PCI
E_TXN3_WLAN9
E_RXP3_WLAN9
PCI
E_RXN3_WLAN9
PCI
CLK_PCI
E_WLANP11
CLK_PCI
CLK_PCI
LP
E_WLANN11
CLK_PCI
_LPC9
LP
C_LFRAME#9,33,37
C_LFRAME#
_LPC
R163
R165 *SHORT_4
AN_CLKREQ#
WL
AN_WAKE_R#
WL
*SHORT_4
CLK_PCI
LP
C_LFRAME#_C
For Debud Card use
Low
High
Reserve only for Inte l module no need to stuff by default 11/24
7
R162
V_S5
+3
C C
SCLK10
SU
SWAP PCIE 10 & 11
B B
SAT
A_RXN1/PEG_RXN10_L211
A_RXP1/PEG_RXP10_L211
SAT
SATA_TXN1/PEG_TXN10_L211
SAT
A_TXP1/PEG_TXP10_L211
SAT
A_RXP3/PEG_RXP9_L011
A_RXN3/PEG_RXN9_L011
SAT
SATA_TXN3/PEG_TXN9_L011
SAT
A_TXP3/PEG_TXP9_L011
CLK_PCI
CLK_PCI
U1
**10K_4
NC1VCC
2
SU
SCLK
A
GND3Y
*74AUP1G 07GW
PEG_RXN12_L3
PEG
_RXN12_L311
PEG
_RXP12_L3
_RXP12_L311
PEG
PEG
PEG_TXP12_L311
PEG
PEG
PEG
PEG
E_NGFF1_N11
E_NGFF1_P11
NGFF3_D ET11
_TXN12_L3
PEG
_TXN12_L311
PEG
_TXP12_L3
PEG_RXN11_L1 PEG_RXN11_L1_N
_RXN11_L111
PEG
_RXP11_L1
_RXP11_L111
_TXN11_L1
PEG
_TXN11_L111
PEG
_TXP11_L1
_TXP11_L111
SATA_RXN1/PEG_RXN10_L2
A_RXP1/PEG_RXP10_L2
SAT
A_TXN1/PEG_TXN10_L2
SAT
SAT
A_TXP1/PEG_TXP10_L2
SAT
A_RXP3/PEG_RXP9_L0
A_RXN3/PEG_RXN9_L0
SAT
A_TXN3/PEG_TXN9_L0
SAT
SAT
A_TXP3/PEG_TXP9_L0
CLK_PCI
E_NGFF1_N
E_NGFF1_P
CLK_PCI
FF3_DE T
NG
4
CN
8
NGFF
1
GND
3
USB_D+
5
USB_D-
7
GND
9
SDIO CLK(O)
11
SDIO CMDIO)
13
SDIO DAT0(IO)
15
SDIO DAT1(IO)
17
SDIO DAT2(IO)
19
SDIO DAT3(IO)
21
SDIO Wake(I)
23
SDIO Reset
25
KEY1
27
KEY2
29
KEY3
31
KEY4
33
GND
35
PETp0
37
PETn0
39
GND
41
PERp0
43
PERn0
45
GND
47
REFCLKP0
49
REFCLKN0
51
GND
53
CLKREQ0#
55
PEWake0#
57
GND
59
PETp1
61
PETn1
63
GND
65
PERp1
67
PERn1
69
GND
71
_LPC_C
Reserved1
73
Reserved2
75
GND
WLAN_NGFF CONN(Type 2230)
Mini card +3V power enable
Mini card +3V power disable
+3
V_S5
L_VDD
+W
5
12
R140
C372
0K_4
*1
*0
.1u/16V_4
4
WI
FI_SUSCLK
R949 *SHORT_4
R950
*SHORT_4
0.
1u/10V_4C1171
0.
1u/10V_4C1170
R954 *SHORT_4
R955
*SHORT_4
1u/10V_4C1174
0.
0.
1u/10V_4C1175
R952 *SHORT_4
R953
*SHORT_4
1u/10V_4C1172
0.
0.
1u/10V_4C1173
R958 *SHORT_4
*SHORT_4
R959
1u/10V_4C1176
0.
0.
1u/10V_4C1177
3
Q5
9
2
2N7002K
1
3.3Vaux
3.3Vaux
PCM_CLK
PCM_SYNC
PCM_IN
PCM_OUT
UART W ak e
UART R x
UART T x
UART C TS
UART R TS
Clink RESET
CLink DATA
CLink CLK
SUSCLK(32KHz)
PERST0#
W_DISABLE#2
W_DISABLE#1
NFC I 2C SM DA TA
NFC I 2C SM CL K
NFC I 2C IR Q
NFC Re set #
RESERVED3
RESERVED4
RESERVED5
3.3Vaux
3.3Vaux
AC_WLANPWR#37
IO
PEG_RXN12_L3_N
PEG
PEG
PEG
PEG
PEG
PEG
PEG_RXN6_L10_N
PEG
PEG
PEG
SAT
SAT
SAT
SAT
R961
NG
+W
2
4
6
LED#1
8
10
12
14
16
LED#2
18
GND
20
22
24
Key 5
26
Key 6
28
Key 7
30
Key 8
32
34
36
38
40
42
44
COEX3
46
COEX2
48
COEX1
50
52
54
56
58
60
62
64
66
68
70
72
74
_RXP12_L3_N
_TXN12_L3_N
_TXP12_L3_N
_RXP11_L1_N
_TXN11_L1_N
_TXP11_L1_N
_RXP6_L10_N
_TXN6_L10_N
_TXP6_L10_N
A_RXP3/PEG_RXP9_L0_N
A_RXN3/PEG_RXN9_L0_N
A_TXN3/PEG_TXN9_L0_N
A_TXP3/PEG_TXP9_L0_N
+3
FF3_PE DET
3
+3
VPCU 5,10,29,31,32,35,37,38 ,39,46,47
+1
.5V 1 4,30,32,45
V 2,5,9,10,11,12 ,13,14,16,17,18,19,21,28,29,30 ,31,32,33,35,36,37,39,40,41,42,45,46,47
+3
L_VDD
L_VDD
+W
/6.3V_6C320
10u
0.
1u/16V_4C299
0.
1u/16V_4C838
0.
1u/16V_4C839
APU Internal PU
1u/16V_4C840
0.
APU External nu-PU
WL
AN_CLKREQ#
S0
IOAC
WL
AN_WAKE_R#
S0
FI_SUSCLK
WI
R590
WL
R597
AN_RST#
_POWERON
BT
_EN
RF
R598
LP
C_LAD0_C
C_LAD1_C
LP
R601
C_LAD2_C
LP
R602
C_LAD3_C
LP
R604
L_VDD
+W
VPCU
+3
[email protected] U/16V_4
**I
AC_WLANPWR#
IO
Re
serve IOAC No Stuff
Reserver +1.5v for WIFI module
.5V
+1
[email protected] U/16V_4
**I
AC_WLANPWR#
IO
No Stuff
V3_SATA_N1
1M_4
R968
_4
*0
C425
C428
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
51
53
55
57
59
61
63
65
67
69
71
73
75
*IOAC@0_4
*SHORT_4
_POWERON 37
BT
_EN 37
RF
*SHORT_4
*SHORT_4
*SHORT_4
*SHORT_4
*I
*IOAC@1 0K_4
CN
21
GND
GND
PERn3
PERp3
GND
PETn3
PETp3/NOTCH
GND/NOTCH
PERn2/NOTCH
PERp2/NOTCH
GND/CONFIG_0
PETn2
PETp2
GND
PERn1
PERp1
GND
PETn1
PETp1
GND
PERn0/SATA-B+
PERp0/SATA-BGND
PETn0/SATA-APETp0/SATA-A+
GND
REFCLKn
REFCLKp
GND
NOTCH
NOTCH
NOTCH
NOTCH
NC
PEDET
GND
GND
GND
PL
TRST#
LP
C_LAD0
C_LAD1
LP
C_LAD2
LP
C_LAD3
LP
R188
**I
R187
OAC@10 K_4
R190
**I
R189
NGFF
AC No Stuff
IO
Q2
1
OAC@10 0K/J_4
Q2
1
OAC@10 0K/J_4
NOTCH/ 3.3 V
NOTCH/ 3.3 V
NOTCH/ 3.3 V
NOTCH/ 3.3 V
CLKREQ#
SUSCLK(32KHz)
D
D
GN
GN
76
77
AC_RST# 31,37
IO
PL
TRST# 2,12,16,19,31,33,37
C_LAD0 9,33,37
LP
C_LAD1 9,33,37
LP
C_LAD2 9,33,37
LP
C_LAD3 9,33,37
LP
1 *IOAC@AO3413
2
C424
**I
OAC@10 00p/50 V_4
2 *IOAC@AO3413
2
C427
**I
OAC@10 00p/50 V_4
3.3V
3.3V
NC
NC
DAS
NC
NC
NC
NC
NC
NC
NC
NC
NC
DEVSLP
NC
NC
NC
NC
NC
PERST#
PEWake#
N/C
N/C
NOTCH
NOTCH
NOTCH
NOTCH
3.3V
3.3V
3.3V
NGFF_SS D
+3
3
+3
V_WLAN
3
+3
V_WLAN
+3V3_SATA_N1
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
DEVSLP_N
40
42
44
46
48
50
NG
52
PCIE_CLKREQ_NGFF1#
54
56
58
60
62
64
+3
66
68
70
72
74
V
R169
7K/J_4
4.
FF1_RS T#
V3_SATA_N1
2
akage circuit (MPC)
Le
+W
L_VDD
R174
2N7002DW
7K/J_4
4.
4 3
1
R167 *0/J_4
R171
WIFI card reset (non-IOAC)
WIFI card reset (IOAC)
Debug card reset
R614
OAC@0_ 8
*I
C849
0u/6.3V_6
*1
C1162
V3_SATA_N1_N+3V3_SATA_N1
+3
108
TP
R951
R956
1
*SHORT_4
*10K_4
R957
R960
*SHORT_4
109
TP
TP
150
5
2
6
Q1
*0/J_4
*SHORT_8
PL
+3
9
DEVSLP0
V
C409
*0
TRST#
+W
L_VDD
C410
.1u/16V_4
**0
+3V3_SATA_N1 +3V
*150u/6.3V_3528
+
10u
/6.3V_6C1165
1u/10V_4C1166
0.
0.
1u/10V_4C1167
1u/10V_4C1168
0.
0.
1u/10V_4C1169
E_CLKREQ_NGFF1# 11
PCI
R170
0K_4
*1
R166
*0_4
.1u/16V_4
DEVSLP0
IOAC
+W
R948
EC_PCU
L_VDD
1
34
S0
PCI
E_CLKREQ_WLAN# 11
IO
AC_WLAN_WAKE# 37
PCI
E_WAKE# 10,31
S0
St
uff
+3
V
R610
*SHORT_8
C408
.1u/16V_4
**0
10u
*SHORT_8
9,33
/6.3V_6C1163
1u/10V_4C1164
0.
A A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ni-Card/WL/3G/SIM
ni-Card/WL/3G/SIM
ni-Card/WL/3G/SIM
Mi
Mi
Mi
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
1A
1A
1A
34
34
34
of
of
of
49Monday, Sept ember 0 7, 2015
49Monday, Sept ember 0 7, 2015
49Monday, Sept ember 0 7, 2015
Page 35
5
YBOARD (KBC)
KE
9
CN1
1
MX
0
2
MX
3
MX
4
MX3
5
MX
6
MX
7
MX
8
MX
9
MY
D D
KB CONN
C C
17
10
MY16
11
MY15
12
14
MY
13
13
MY
14
12
MY
15
MY
11
16
MY
10
17
MY9
18
MY8
19
7
MY
20
6
MY
21
5
MY
22
MY
4
23
MY
3
24
MY2
25
1
MY
26
0
MY
27
28
29
30
2 1
1
2
4
5
6
7
D33
*VPORT_6
MX0 37
MX
MX
MX
MX
MX
MX6 37
MX7 37
MY
MY
MY
MY
MY
MY12 37
MY11 37
MY
MY
MY
MY
MY
MY5 37
MY
MY
MY
MY
MY
R7
91 33_4
1 37
2 37
3 37
4 37
5 37
17 37
16 37
15 37
14 37
13 37
10 37
9 37
8 37
7 37
6 37
4 37
3 37
2 37
1 37
0 37
10
C8
180P/50V_4
<EMI>
MX
MX
MX
MX7
MY
MY
MY
MY
MY
MY6
MY5
MY
MY
MY
MY
MY
MX0
MX1
MX
MX
MY
MY
MY
MY12
SWON# 16,37
NB
Prevent ESD/EOS
Layout near
device
1
4
5
6
3
2
1
0
7
4
11
10
9
8
2
3
15
14
13
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
KB_BL LED (KBC)
R105
KBL@10K_4
+G
R1
22 *4.7K_4
R1
13 *4.7K_4
2
R1
_SEN_PW
+5
V
1
3
07GS@0_6
@RB500V-40
G_
G_
C173 [email protected]/6.3 V_6
4
Q1
KBL@AO3413
il 20mil
20m
+5
V_KB
C1
71
[email protected]/10V_6
C230
[email protected]/16V_4
+G
MBDATA_R
MBCLK_R
R1
R1
_SEN_PW
G_
G_
_SEN_PW
+G
C236
GS@10u/6.3V_6
D2GS@RB500V-40
D3GS
R1
21 G S@0_4
20 GS@0_4
14 GS@0_4
C2
63 *33P/50V_4
39 *33P/50V_4
C2
MBDATA_R
MBCLK_R
R9
C1
[email protected]/50V_4
9 *KBL@short_4
72
2013/10/22 change CN25 pin define for spec.1A-7
2013/10/23 change CN25 footprint.1A-8
AC
CEL_INTA_R
AC
CEL_INT2_R
MBDATA_R
G_
G_MBCLK_R
+5
V
KB_BL_LED37
B B
2
Q1
5
KBL@DTC144EU
1 3
G-sensor(ACS)
+3
V
CEL_INTA#13
AC
CEL_INT2#33
+G
AC
SM
SM
_SEN_PW
B_RUN_DAT5,10,16,17,18
B_RUN_CLK5,10,16,17,18
5
CEL_INTA#
AC
A A
C231
*22P/50V_4
CP
5
*220P_8P4R
1
CP
*220P_8P4R
CP
2
*220P_8P4R
3
CP
*220P_8P4R
CP6
*220P_8P4R
CP
4
*220P_8P4R
+3VPCU
MX
7
MX6
MX5
4
MX
+5
V_KB_R
0
U1
1
Vdd_IO
14
VD
11
IN
9
IN
7
SA0
6
SD
4
SC
8
CS
*GS@LIS3DHTR
4
1 *10K_10P8R
RP
10
9
8
7 4
D
RE
SERVED
T1
SERVED
RE
T2
A
L
4
1
MX
2
MX
3
MX2
MX3
56
CN3
346
2
1
KBL
@KB_backlight
NC
NC
GN
D
D
GN
GN
D
D
GN
3
2014/01/13 Change TP power rail from +3V_S5
U3
2
1
4
G991P11U
R415
10K_4
R4
R419 *short_4
9
N
VI
ON
/F
VSET
1C-2
18 *short_4
R4
R4332.2K_4
3
VO
5
D
GN
6
D
GN
7
GN
D
8
GN
D
1A-1
to +3V_SUS.
+3
272.2K_4
UCHPAD BOARD CONN (TPD I2C/PS2 co-lay)
TO
R4
TPD->100kHz,TS=400Khz
Intel design guide suggestion
MCP PIN 10u.
Per inch 3u TS=3x5inch
400kHz10~100u =2.4~0.4k.
100Khz 10~100u=9k~1k.
26 *TDI@0_4
R4
TDI@2N7002 DW
SM
B1ALERT#10,12
1
4 3
Q3
4
R4
34 *TDI@0_4
V
+3
R5
57
*10K_4
CPUFAN#37
S5
I2C0_SDA13
I2C0_SCL13
FAN (THM)
0
1
CPU
+3V_S5
6
2
5
+3
14 *short_4
CLK37
TP
DATA37
TP
C_TP_SDA_R
I2
C_TP_SCL_R
I2
V
C7
97
2.2U_6
ANPWR = 1.6*VSET
F
R416
10K_4
S5
+5V
1 2
1A-4
2
2014/01/15 reserve TP power rail +3V_S5.1C-4
2014/02/17 Add Q47 for PTP
1C1-1
power EN and soft up R694\C713.
and C712\C686.
3
+
C6
39
3
0.22u/25V_6
D_EN37
TP
2013/10/18 Change CN21 Pin8 for
1A-5
I2C/PS2 TPD idendify.
2013/10/29 Change CN21 power rail to S5
change Q42 direction and net name,
reseve PS2 PU to +3V.
R1
10K_4
2
06
C6
1A-12
CN4
1
2
3
FA
*AO3413
Q3
44 *1000p/50V_4
N_3P
V_S5
PTP_PWR_EN#37
TP
D_INT#13,37
FANSIG37
L22
+T
PVDD
*0.1u/16V_4
TH_FAN_POW ERTH_ FAN_POWER
96
C7
2.2U_6
1 2
*SHORT_6
C6
42
98
C7
.01U/50V_4
C654
1u/16V_4
0.
20 *0_4
R4
30mils
33
C2
*.01U/50V_4
R429 *SHORT_6
1
C643
*0
.1u/16V_4
+3V
2013/10/15 change pin define and add pwm IC U17.
2013/10/17 Change U17 to G991P11U and PU U17 pin1.
C640
1u/16V_4
0.
il
50m
TPCLK_R
TPDATA_R
C_TP_SDA_R
I2
C_TP_SCL_R
I2
TP
D_INT#
*10p/50V_4
C893
1
35
TP CN
789
6
5
4
3
2
1
CN16
10
+T
PVDD
2013/10/24 Add alert on U17.1 for CPU themal tempture.1A-9
D1
ber
R4
44 *short_4
52 *0_4
R4
2013/10/31CN15 Pin2/3 swap.1A-13
48 *short_4
R4
R4
53 *0_4
+3VPCU
+3
V_S5
2
+3
VPCU
+3
V_S5
+3
VPCU
39P/50V_4
for ESD
59
C6
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Si
ze Document Nu mber Rev
Size Document Nu mber Rev
Size Document Nu mber Rev
Date: Sheet of
Date: Sheet of
Date: Sheet of
KB/
KB/
KB/
TP/FAN
TP/FAN
TP/FAN
1
1A
1A
1A
35
35
35
49Monday, September 07, 2015
49Monday, September 07, 2015
49Monday, September 07, 2015
5
40 *1M_4
R4
R4
PO
WER LED(UIF)
Po
wer LED
PW
2
3
10
15
5
12
13
16
Battery
BAT
BAT
RLED#37
SU
SLED#37
R4
R4
LED0#37
LED1#37
R4
3
41 *1M_4
R4
39 *1M_4
47 390/F_4
R4
R446 390/F_4
43 *1M_4
42 *1M_4
51 390/F_4
R4
50 390/F_4
D2
+3
VPCU
V
+3
+3
VPCU
5 *5.5V/25V/410P_4
1 2
D2
Blue
LE
2 3
1
LED_AMBER/BLUE
Am
1 2
D24 *5.5V/25V/410P_4
VPCU
+3
1 2
6 *5.5V/25V/410P_4
Blue
LED2
2 3
1
LED_AMBER/BLUE
Amber
1 2
D2
7 *5.5V/25V/410P_4
Page 36
US
B Charger to 3.0 (UBC)
D D
GMT:AL003703000(G3703)
TI:AL002544001(TPS2544)
Silergy:
5
+5
VPCU
80 mils (Iout=2A)
C583
1U/10V_4
B_OC0#9
US
B_BC_ON37
US
B_CHARGE_ON37
US
B_CLT137
US
R358 100K_4
R354 10 K_4
VPCU
+5
R353 10 K_4
U2
8
1
IN
OU
IM_LO
IL
IM_HI
IL
9
ATUS
ST
D_PAD
GN
13
ULT
FA
4
IM_SEL
IL
GN
5
EN
DM
DP
6
L1
CT
7
CT
L2
L2
_OUT
CT
DM
8
CT
L3
L3
_OUT
CT
DP
TPS2544RTER
USB 3.0 Connector (UB3)
V_S5
+5
07
C5
1u/6.3V_4
BON#
US
B_OC1#
US
able: Low Active /2.5A
En
BCD:AL0028 22000
GMT:AL000524007
PAD5 *esd-6x3
1
US
B3_RXN0_R
PAD6 *esd-6x3
1
US
B3_RXP0_R
PAD7 *esd-6x6
1
PAD8 *esd-6x6
1
0722 Added PAD1-4
as ESD protection
PAD18 *esd-6x3
1
US
B3_RXN1_R
PAD17 *esd-6x3
1
US
B3_RXP1_R
PAD19 *esd-6x6
1
PAD20 *esd-6x6
1
0722 Added PAD1-4
as ESD protection
U25
5
1
IN
OU
T
2
GN
D
4
3
/E
/O
N
C
G524B2T11U
PAD9 *esd-6x3
1
US
BP0-_R
PAD10 *esd-6x3
1
US
BP0+_R
PAD11 *esd-6x6
1
PAD12 *esd-6x6
1
C C
PAD21 *esd-6x3
1
US
BP1-_R
PAD23 *esd-6x3
1
US
BP1+_R
PAD22 *esd-6x6
1
PAD24 *esd-6x6
1
B B
US
BON#37
US
B_OC1#9
_IN
_IN
T
D
12
15
16
17
14
11
10
2
3
IL
IL
US
US
Close USB3.0
4
IM_LO
(RILIM_LO 1.2A)
IM_HI
(RILIM_HI 2.3A)
BP0-_C
BP0+_C
PAD1 *esd-6x3
PAD2 *esd-6x3
PAD3 *esd-6x6
PAD4 *esd-6x6
PAD13 *esd-6x3
PAD14 *esd-6x3
PAD15 *esd-6x6
PAD16 *esd-6x6
C521
470P/50V_4
mils (Iout=2A)
80
R3
83
R384
39K/F_4
20K/F_4
iPAD charging current is about 2.1A so set on 2.3A
1.2A current limit of USB 3.0 SDP mode
BP0- 9
US
BP0+ 9
US
1
US
B3_TXN0_R
1
US
B3_TXP0_R
1
1
1
US
B3_TXN1_R
1
US
B3_TXP1_R
1
1
BPWR1
US
C514
C515
100U/6.3V_1206
0.1u/16V_4
US
BPWR0
+
69
C5
100u/6.3V_1206
C572
470P/50V_4
3
C601
0.1u/16V_4
CTL1 CTL2 CTL3 ILIM_SEL
SDP 1 1 1 0
CDP 1 1 1 1
2
1
36
DCP 0 1 1 X
RILIM_LO is optional and the ILIM_LO pin may be left unconnected if the following conditions are met:
1. ILIM_SEL is always set high
2. Load Detection - Port Power Management is not used
3. Mouse / Keyboard wake function is not used
If conditions 1 and 2 are met but the mouse / keyboard wake function is also desired, it is recommended to use
RILIM_LO < 80.6 kΩ.
The following equation programs the typical current limit:
(1)
RILIM_XX corresponds to either RILIM_HI or RILIM_LO as appropriate.
R392 *SHORT_4
L17
1
US
BP0-_C
US
BP0+_C
C619 *1 .6P/50V_4
B3_RXN09
US
B3_RXP09
US
C618 *1 .6P/50V_4
B3_TXN09
US
B3_TXP09
US
US
US
US
B3_TXN19
US
B3_TXP19
C605 0.1 u/16V_4
C603 0.1 u/16V_4
BP1-9
BP1+9
C558 *1 .6P/50V_4
B3_RXN19
US
B3_RXP19
US
C556 *1 .6P/50V_4
C542 0.1 u/16V_4
C538 0.1 u/16V_4
US
B3_TXN0_C
US
B3_TXP0_C
B3_TXN1_C
US
B3_TXP1_C
US
2
2
3
*MCM2012B900GBE/400mA/90ohm
R394 *SHORT_4
R400 *SHORT_4
*M
CM2012B900GBE/400mA/90ohm
3
2
2
L20
R397 *SHORT_4
R389 *SHORT_4
*M
CM2012B900GBE/400mA/90ohm
3
2
2
L16
R387 *SHORT_4
R338 *SHORT_4
L11
2
2
3
*MCM2012B900GBE/400mA/90ohm
R341 *SHORT_4
R348 *SHORT_4
*M
CM2012B900GBE/400mA/90ohm
3
2
2
L12
R343 *SHORT_4
R331 *SHORT_4
CM2012B900GBE/400mA/90ohm
*M
3
2
2
L10
R329 *SHORT_4
U
SBP0-_R
1
US
443
443
1
443
1
1
443
443
1
443
1
BP0+_R
US
BPWR0
CN15
USB3.0 CONN
1
US
VB
1
2
D-
2
3
D+
3
4
4
GND
C604
*1.6P/50V_4
US
C537
*1.6P/50V_4
BPWR1
5
5
6
6
7
7
8
8
9
9
CN12
USB3.0 CONN
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
SSRX-
SSRX-
SSRX+
GND
SSTXSSTX+
12
VB
DD+
GND
SSRX+
GND
SSTXSSTX+
12
11111010131312
US
11111010131312
US
B3_RXN0_R
1
US
B3_RXP0_R
US
B3_TXN0_R
1
US
B3_TXP0_R
C610
*1.6P/50V_4
1
U
SBP1-_R
US
BP1+_R
US
B3_RXN1_R
1
US
B3_RXP1_R
B3_TXN1_R
US
1
B3_TXP1_R
US
C544
*1.6P/50V_4
IOS_typ(mA) = 50,250/{RILIM_XX(KΩ)+0.1}
US
BPWR0
US
C600
0.1u/16V_4
BPWR1
C520
0.1u/16V_4
U30
1
US
B3_TXP0_R
O 1
I/
O 6
I/
2
D
VD
D_2
GN
3
1
NC_
2
NC_
4
US
BP0-_R
O 2
I/
O 5
I/
5
US
B3_RXP0_R
O 3
I/
D_1
O 4
I/
GN
11
USB30_ESD_AZ1 065-06F.R7 G
USB protection diodes for ESD.
USB protection diodes for ESD.
USB protection diodes for ESD.USB protection diodes for ESD.
as close as possible to USB connector pins.
as close as possible to USB connector pins.
as close as possible to USB connector pins.as close as possible to USB connector pins.
U26
1
US
B3_TXP1_R
O 1
I/
O 6
I/
2
D
VD
D_2
GN
3
1
NC_
NC_
4
US
BP1-_R
US
USB protection diodes for ESD.
USB protection diodes for ESD.
USB protection diodes for ESD.USB protection diodes for ESD.
as close as possible to USB connector pins.
as close as possible to USB connector pins.
as close as possible to USB connector pins.as close as possible to USB connector pins.
B3_RXP1_R
USB30_ESD_AZ1 065-06F.R7 G
O 2
I/
O 5
I/
5
I/
O 3
D_1
I/
O 4
GN
11
10
US
B3_TXN0_R
9
8
7
US
BP0+_R
6
US
B3_RXN0_R
10
US
B3_TXN1_R
9
8
2
7
US
BP1+_R
6
B3_RXN1_R
US
V_S5
USB2.0 DB (UB2)
US
B_OC2#9
A A
+5
1u/6.3V_4
U32
49
C6
5
1
IN
OU
T
2
GN
D
4
/E
N
G524B2T11U
3
/O
C
US
BP4-9
US
BP4+9
BON#
US
B_OC2#
US
En
able: Low Active /2.5A
BCD:AL0028 22000
GMT:AL000524007
5
C894
470P/50V_4
C638
0.1u/16V_4
BPWR2
US
R826 *0_4
4
BPWR2
US
C637
10U/6.3V_6
CN18
1
2
3
4
5
6
7
8
91011
50501-01401-001
C888
100U/6.3V_1206
12
Card Reader (CRD)
V
+3
R430 *SHORT_6
V_CR
+3
C651
4.7U/6.3V_6
C653
0.1u/16V_4
3
R438 6.2 K/F_4
US
BP9-9
US
BP9+9
R423
C647
*0_4
0.1u/16V_4
C646
1u/10V_4
F
RRE
C_XD
VC
REG
SD
C657 1u/10V_4
U33
1
RRE
F
2
DM
3
DP
4
3V
3_IN
5
CA
RD_3V3
6
SD
REG
D
GN
25
TP
V18XD_CD#
XD_D7
24
23
8
V1
RTS5170
_CD#
XD
7
SD_WP/MS_D1
59
TP
65
66
TP
TP
SP14
SD_D2/MS_D5
SD_D3/MS_D4
20
21
22
3
4
_D7
SP1
SP1
XD
SP18SP29SP310SP411SP5
SP2
SD_D1/MS_D7
SD_D0/MS_D6
58
TP
TP
64
CN1
_WP/MS_D1
SD
_CDZ
SD
reserve for EMI
_D2/MS_D5
SD
_D1/MS_D7
SP11
19
1
2
18
SP1
SP1
_CMD
SD
SP1
0
17
IO0
GP
GP
IO0
16
SP9
SP9
15
_CLK
SD
SP8
14
SP7
SP7
13
_CDZ
SD
SP6
12
SP5
60
2
SD
_D0/MS_D6
SD
R412 *SHORT_4
_CLK
SD
reserve for EMI
C_XD
VC
_CMD
SD
TP63
_D3/MS_D4
SD
TP62
C668
TP61
*0.1u/16V_4
C635
4.7u/6.3V_6
_CLK_R
SD
C636
0.1u/16V_4
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: She et of
Date: She et of
Date: She et of
11
WP
10
CD
9
DA
TA2
8
DA
TA1
7
DA
TA0
6
VS
S2
5
CL
K
4
VD
D
3
VS
S1
2
1
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
USB3/Charger/CR/USB2 DB
USB3/Charger/CR/USB2 DB
USB3/Charger/CR/USB2 DB
1
D
D
CM
D
CD/
DATA3
GN
GN
13
12
16
NC
17
NC
D
D
GN
GN
SD-CARD
14
15
1A
1A
1A
36 49Monday, September 07, 2015
36 49Monday, September 07, 2015
36 49Monday, September 07, 2015
Page 37
5
(KBC)
EC
R4
13 2.2_6
1 2
+3VPCU
+3VPCU_EC and +3V_RTC
minimum trace width 12mils.
D D
+3
VPCU
LPC_LFRAME#9,33,34
D1
9
R816
SDMK0340L-7-F
100K_4
1 2
2 1
89
C8
1u/6.3V_4
K_PCI_EC
CL
17
R8
C C
B B
*22_4
C8
90
*10p/50V_4
IO
AC_WLANPW R#34
TS
_EN29
C8
87 180P/50V _4
Prevent ESD/EOS Layout near device
L13
BL
M15AG121SN1D(120,500MA)_4
12 mils
C606
C633
0.1u/16V_4
0.1u/16V_4
+3
V
+3
V_S5
C_LAD09,33,34
LP
C_LAD19,33,34
LP
C_LAD29,33,34
LP
C_LAD39,33,34
LP
11 *0_4
ESPI
PL
TRST#2,12,16,19,31,33,34
CL
K_PCI_EC9
SI
O_EXT_SMI#9,12
SI
O_EXT_SCI#13
R8
_RST#9
IO
Q_SERIRQ9,33
IR
SI
O_RCIN#9
AC_WLAN_W AKE#34
BL_LED35
KB_
SWON#10
DNB
TH
RM_MO INTOR15
SU
SB#2,10,16,39
EC_PWROK10
PC
H_BLON_EC29
CPUFAN#35
AC_LAN_WAKE#31
IO
_WR#10,12
ME
P_MUTE#32
AM
TP148
AC
TE
MP_MB AT38
PC
BEEP_EC32
Su
son_2.5V41
TP
H_SPI_CLK_EC12
PC
_CS0#_UR_ME12
SPI
H_SPI_SI_EC12
PC
PC
H_SPI_SO_EC12
S5
PTP_PWR_EN#35
21 *SHORT_4
R8
TP
Pin 80 EC_APWROK reserve TP
IN38
149
MY
1635
MY
1735
07 33_4
R8
_ON39,40,45
035
MY
135
MY
MY
235
335
MY
MY
435
MY
535
635
MY
MY735
835
MY
MY935
MY
1035
MY
1135
1235
MY
MY
1335
1435
MY
MY
1535
C611
0.1u/16V_4
18 *2.2_6
R8
1 2
1 2
R9
66 2.2_6
114
92 *SHORT_4
R7
D_POWER
OD
TP
111
EC
_ODD_EJ_R
PR
OCHOT_EC
_EN_ R
TS
S5
_ON
C563
0.1u/16V_4
PL
TRST#_EC
WR
C566
0.
1u/16V_4
EC
AGND
ST#
C609
0.1u/16V_4
C892
0.
1u/16V_4
10
9
8
7
22
13
6
17
126
5
15
23
14
4
16
113
123
80
119
33
88
81
87
109
108
71
72
73
35
34
122
95
94
105
101
102
103
56
57
32
100
125
36
37
38
39
40
41
42
43
44
45
46
51
52
53
54
55
MX035
MX
135
MX
235
MX
335
MX
435
535
MX
MX
635
735
MX
+A
+3VPCU_EC
+3
U4
4
3VPCU
11/11 FAE
suggestion
pin106 +3V_RTC
change to
+3VPCU_EC
C626
0.1u/16V_4
V_EC
9
LA
D0/GPM0(3)
LA
D1/GPM1(3)
LA
D2/GPM2(3)
LAD3/GPM3(3)
CRST#/GPD2
LP
CCLK/GPM4(3)
LP
RAME#/GPM5(3)
LF
CPD#/GPE6
LP
GA
20/GPB5(3)
SER
IRQ/GPM6(3)
EC
SMI#/GPD4(3)
EC
SCI#/GPD3
WRST#
ST#/GPB6(3)
KBR
PWUREQ#/BBO/SMCLK2ALT/GPC7(3)
0/GPC0
CRX
CT
X0/TMA0/GPB2(3)
DA
C4/DCD0#/GPJ4(3)
DSR0#/GPG6
NT/CTS0#/GPD5
GI
DAT1/RTS0#/GPF3
PS2
C5/RIG0#/GPJ5(3)
DA
CLK1/DTR0#/GPF2
PS2
D/SOU T0/GPB 1
TX
RX
D/SIN0/GPB0
AD
C5/DCD1#/GPI5(3)
AD
C6/DSR1#/GPI6(3)
AD
C7/CTS1#/GPI7(3)
RTS1#/GPE5
M7/RIG1#/GPA7
PW
R1#/SBUSY/GPG1/ID7
DT
X1/SOUT1/GPH2/SMDAT3/ID2
CT
1/SIN1/SMCLK3/GPH1/ ID1
CRX
FS
CK/GPG7
FS
CE#/GPG3
FM
OSI/GPG4
FM
ISO/GPG5
KSO16/SMOSI/GPC3(3)
17/SMISO/GPC5(3)
KSO
PWM6/SSCK/GPA6
E0#/GPG2
SSC
E1#/GPG0
SSC
0/PD0
KSO
KSO
1/PD1
KSO
2/PD2
KSO
3/PD3
KSO4/PD4
KSO
5/PD5
KSO6/PD6
KSO
7/PD7
KSO
8/ACK#
9/BUSY
KSO
KSO
10/PE
11/ERR#
KSO
KSO
12/SLCT
13
KSO
14
KSO
15
KSO
C602
0.1u/16V_4
11
26
50
92
114
121
C
BY
BY
BY
BY
BY
VC
VST
VST
VST
VST
VST
LPC
CIR
EXTERNAL SERIAL FLASH
SPI ENABLE
KBMX
0/STB#
1/AFD#
2/INIT#
3/SLIN#
4
5
6
KSI
KSI
KSI
KSI
KSI
KSI
KSI
58
59
60
61
62
63
64
VPCU_ECPLL
+3
L21
BLM15AG121SN1D(120,500MA)_4
C632
1u/16V_4
0.
106
127
74
84
C
AVC
BY(PLL)
BY_FSPI
CLK/GPE3
VST
VST
EG
99
3
83
82
20
19
H7
GP
T/GPE7
AD/GPE1
CS#/GPE2
EG
EG
L80LLA
LAT/BAO/GPE0
L80H
GPIO
IT8987E/CX
LQFP
UART port
7
KSI
VSS
VSS27VSS
1
49
65
L14
BLM15AG121SN1D(120,500MA)_4
WAKE UP
RI
VSS
AVSS
VSS
75
91
104
AGND
EC
+3
ACPRESENT 10
PC
BT
SL
FB
SL
US
USB_BC_ON 3 6
USB_CHARGE_ON 36
CLKRUN# 10,33
SM
CLK0/GPB3
SM
DAT0/GPB4
SM
CLK1/GPC1
SMDAT1/GPC2
I/SMCLK2/GPF6(3)
PEC
DAT2/PECIRQT#/GPF7(3)
PS/2
PS2
CLK0/CEC/TMB0/GPF0
PS2
DAT0/TMB1/GPF1
PS2
CLK2/GPF4
PS2DAT2/GPF5
M0/GPA0
PW
M1/GPA1
PW
PW
M2/GPA2
M3/GPA3
PW
PW
M4/GPA4
PW
M5/GPA5
TACH0A /GPD6 (3)
CH1A/ TMA1/G PD7(3)
TA
RI0/G PC4(3)
TM
RI1/G PC6(3)
TM
PW
RSW/GPE4
RI
1#/GPD0(3)
RI
2#/GPD1
AD
C0/GPI0(3)
AD
C1/GPI1(3)
ADC2/GPI2(3)
C3/GPI3(3)
AD
ADC4/GPI4(3)
TA
CH2/G PJ0(3)
DA
C2/TACH0B/GPJ2(3)
DA
C3/TACH1B/GPJ3(3)
VPCU_EC
H_SLP_S0_N 10,16
_POWERON 34
P_SUS#_EC 10
_CLAMP_REQ# 22
P_SUS_ON 14
GP
(For PLL Power)
BT
_POWERON
_CLAMP_REQ#
FB
98
96
97
93
SM BUS
5/GPH5
6/GPH6
3/GPH3
4/GPH4
ID
ID
ID
ID
SM
KRUN#/ID0/GPH0
CL
PWM
NG#/PWRFAIL#/CK 32KOUT/LPCRST#/GPB7
A/D D/A
CLOCK
ORE
VC
12
AJ
C891
1u/16V_4
0.
089870F02 IT8987E/CX
3
BON# 36
J1(3)
J7
GP
GP
J6
IT8987/CX
110
111
115
116
117
118
85
86
89
90
24
25
28
29
30
31
47
48
120
124
107
18
21
112
66
67
68
69
70
76
77
78
79
2
128
Pr
event ESD/EOS Layout near device
97 33_4
R7
C8
80
180P/50V_4
CLK
MB
DATA
MB
D_MBCLK
2N
D_MBDATA
2N
EC
_PECR_R
R3
20 180P/50V_4
C6
SUSLED#
dG
PU_OTP#
SWON#
NB
PG
HW
ICMNT
C574 10u/6.3V_6
PU_OPP#
dG
EC
_FB_CLAMP
04 33_4
R8
C8
83
180P/50V_4
TP
D_EN 35
CLK 38
MB
MB
DATA 38
2N
D_MBCLK 10,22
2N
D_MBDATA 10,22
95 33_4
99 33_4
R3
Prevent ESD/EOS Layout near device
AC_RST# 31,34
IO
EC
_FPBACK# 29
TP
CLK 35
TP
DATA 35
RLED# 35
PW
BATLED1# 35
SLED# 35
SU
LED0# 35
BAT
INON_EC 1 0
MA
US
B_CLT1 36
FA
NSIG 35
SUSACK#_EC 10
SUSON_EC 10
PU_OTP# 22
dG
SWON# 16 ,35
NB
SU
SC# 10,16
HW
PG 2,10
RS
MRST# 10
MNT 38
IC
AGND
EC
dG
PU_OPP# 22
VR
ON_EC 10
IO
AC_LANPWR# 31
WROK_C 10
DP
_FB_CLAMP 22
EC
H_PWROK 2,10
PC
SU
SWARN#_EC 10
TP
115
Prevent ESD/EOS Layout near device
SM
BUS ARRANGEMENT TABLE
Bus 1
SM
SM Bus 2
SM Bus 3
SM
Bus 4
EC
_PECI 2
LI
D# 29
Prevent ESD/EOS Layout near device
R3
62 33_4
C565
180P/50V_4
+1
V_S5_ON 40
D_INT# 13,35
TP
Battery
PCH/VGA
2
S5
_ON
NB
SWON#
PU_OTP#
dG
PU_OPP#
dG
_CLAMP_REQ#
FB
MA
INON_EC
SON_EC
SU
ON_EC
VR
H_SPI_SI_EC
PC
PC
H_SPI_SO_EC
82 10K_4
R3
R3
85 10K_4
04 EV@10K_4
R4
63 EV@10K_4
R3
14 EV@10K_4
R8
R8
12 100K_4
R4
02 100K_4
64 100K_4
R3
00 *10K_4
R8
01 *10K_4
R8
1
+3
VPCU
37
+3
V_GFX
SM BUS PU(KBC)
VPCU
+3
MB
_EN 34
RF
PR
OCHOT_EC
HWPG(KBC)
CLK
MB
DATA
D_MBCLK
2N
D_MBDATA
2N
R8
100K_4
DDR=1.5V, D1 DNP and D2 POP
DDR=1.35V, D1 POP and D2 DNP
HW
PG_1.5V45
HW
PG_2.5V41
HW
PG_VDDR41
PG_1VS540
HW
S_HWPG39
SY
TP
57
CGTX_PWRGD
VC
TP
53
HWPG_+VCCEOPIO
56
TP
HWPG_+VCCOPC
15
R3
R3
R3
R3
3
2
1
D1
D2
88 4.7K_4
91 4.7K_4
93 4.7K_4
98 4.7K_4
2
Q3
2N7002K
D1
6 RB5 00V-40
3 *RB5 00V-40
D1
D1
8 *RB5 00V-40
D1
1 *RB5 00V-40
7 *RB5 00V-40
D1
5 *RB5 00V-40
D1
2 *RB5 00V-40
D1
D14 *RB 500V-40
+3
V_S5
H_
PROCHOT# 2 ,38,42
V
+3
R8
10K_4
13
PG
HW
+3
VPCU
NB
SWON#
A A
23
R8
10K_4
97
C8
0.1u/16V_4
Re
serve switch for test
(MP remove)
SW
*POWER_SW
1
5
6
5
2
3
42
Re
set SW (FSW)
16 *0_4
R6
15 *0_4
R6
+3V_RTC
12
C8
*0.1u/25V_6
12
18
R6
100K_4
BI
_GATE
SW
53
42
3
POWER_SW
6
5
1
BI38
4
PJA138K
Q4
3
Vgs = 1.5V
2
1
4
R6
17
*10K_4
C850
*0
.1u/16V_4
1
2
Q4
*PJ4N3KDW
3
+3
V_RTC
VPCU
+3
ST#
WR
Vgs = 1.5V
6
2
5
1
4 3
serve no stuff
Re
VPCU5,10,29,31,32,34,35,38,39,46,47
+3
+3
V_GFX19,21,22,47
V2,5,9,10,11,12,13,14,16,17,18,19,21,28,29,30,31,32,33,34,35,36,39,40,41,42,45,46,47
+3
V_S52,10,12,13,14,16,31,33,34,35,39,41,45,46
+3
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
KBC
KBC
KBC
IT8587
IT8587
Date: Sheet
Date: Sheet
2
Date: Sheet
IT8587
1
1A
1A
1A
49Tuesday, Augu st 25, 2015
49Tuesday, Augu st 25, 2015
49Tuesday, Augu st 25, 2015
of
37
of
37
of
37
Page 38
5
4
3
2
1
-V
BAT
PC
110
10U/25V_8
38
of
of
of
38
38
38
1A
1A
1A
49Monday, Septe mber 07, 2015
49Monday, Septe mber 07, 2015
49Monday, Septe mber 07, 2015
PC
11
2200p/50V_6
PC
2200p/50V_6
6
PR
*4.7_6
PC
7
*680p/50V_6
GP
102
1
PQ
AON6414AL
3
2
5
1
4
161
PR
*SHORT_6
N
VI
PC
10u/25V_8
PL
1
6.8uH_7X7X3
U_THROTTING# 22
*0.01u/50V_4
PC2
104
PR
145
0.01/F_0612
1 2
24780_S
24780_S
PR
*SHORT_4
PR
153
*SHORT_4
RP
RN
REGN MAX voltage 6.5V
V_ILIM=20*(VSRP-VSRN)=20*Ichg*Rsr
=0.793V for 3.965A current limit
ILIM=0.793V
Rsr = 0.01ohm
Si
ze D ocument Number Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet
Date: Sheet
Date: Sheet
BAT
-V
152
PC
PC
106
2200p/50V_6
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
arger (BQ24780S)
arger (BQ24780S)
arger (BQ24780S)
Ch
Ch
Ch
107
10U/25V_8
1
24
PC
118
1n/50V_4
4
PC
100P/50V_4
157 10K_4
154 *10K_4
12
PR
316K/F_4
PQ
AON6414AL
5
PR
5
20_1206
1
PC
PR156
100K/F_4
4
PR
PR
PR
PR
PR
PR
100P/50V_4
3
2
1
PR
4.02K/F_4
PC
0.47u/25V_6
142 *SHORT_4
148 *SHORT_4
150 *SHORT_4
139 *SHORT_4
144 *SHORT_4
146 *SHORT_4
0.01u/50V_4
VA VA1
PD
6
SV1040
2
PJ
1
2
3
4
D D
C C
B B
A A
Power conn
PC
PC
112
11 *0_4
PR
9 100_4
PR
7
100_4
2 1
1
2200p/50V_6
PR
100K/F_4
PR
100K/F_4
2 1
PD
PDZ5.6B
2
108
2
1
PR
100_4
8
GN6V
RE
BAT
-V
TEMP_MBAT
10 1M_4
PR
*47p/50V_4
0.1u/50V_6
IN37
AC
s -> PR4 CS31692FB11 16.9K 1/16W +-1% (0402) For 177W
Di
PC
113
0.1u/50V_6
111
PC
*100p/50V_4
PR
MB
CLK_R
DATA_ R
MB
PD
PDZ5.6B
5
00801-V01
50458-
89
7
6
5
4
3
2
1
10
1
PJ
PC
8
*47p/50V_4
2 1
PC
1
3
2
3
PD
P4SMAFJ20A
MNT37
IC
1
TP
PM
PM
ON42
9
ON
TE
+3
VPCU
CLK 37
MB
MBDATA 37
4
PR
16.9K/F_4
37
BI
MP_MBAT 37
Unstuff
+3VPCU
3
PR
137K/F_4
MB
MB
ICMNT
10
PC
PR
143
866K/F_4
DATA
CLK
0.1u/50V_6
6
PC
*100P/50V_4
PR
PR
4
141
101
PC109
PC121
24780_A
24780_V
24780_A
24737_B
24737_C
24737_I
24737_C
47n/50V_6
VA2
CDRV
CC
CDET
M#
MPOUT
LIM
PR151
100K_4
24780_C
MSRC
MPIN
140
PR
4.02K/F_4
28
11
12
16
14
21
13
3
4
6
5
7
8
9
PC
1u/25V_6
CM
AC
VC
AC
AC
SD
SC
IA
ID
PM
TB
CM
IL
CM
24780_A
24780_A
100
5
PC
ACP
PU
BQ24780S
BATPRES
15
158 *SHORT_4
PR
MP_MBAT
TE
H_
PR147
*100K_4
1
ACN
3
GND
PAD29GND30GND31GND32GND33GND
22
155 *0_4
PR
PROCHOT#
3
PC
0.1u/50V_6
BA
BA
HI
PH
LD
0.1u/50V_6
2
SRC
DRV
C
DET
OK
A
L
DP
CHG
ON
_STAT
POUT
IM
PIN
PROCHOT
GND35GND36GND37GND
10
38
+V
CCIO
Check with HW side
P.
36 VCC_CORE have PU to +1V
PR
177
0.01/F_0612
1 2
CP
CN
3
18
TDRV
17
TSRC
24
RE
GN
25
BT
ST
26
DRV
27
ASE
23
ODRV
20
SR
P
19
SR
N
34
H_
PR
*SHORT_4
PR
*SHORT_4
ATDRV
24780_B
ATSRC
24780_B
GN6V
RE
24780_R
EGN
149
PR
*SHORT_6
24780_B
ST
H
24780_D
24780_LX
L
24780_D
PR
159 10/F_6
160 10/F_6
PR
PROCHOT# 2,37,42
N
VI
164
CN
24780_A
24780_A
163
105
PC
2.2u/10V_6
PC
103
47n/50V_6
RP
24780_S
24780_S
RN
CP
PC
0.1u/25V_4
114
PC
0.1u/25V_4
PC
0.1u/25V_4
PC
12
0.1u/50V_6
PR
162 10/F_6
52
4
4
116
115
PQ
22
AON7410
3
1
52
PQ
23
AON7410
3
1
Power charger circuit reserve 2N7002 for GPU throtting
3
2
MPOUT
24737_C
1
PQ
*EV@2N7002K
2
2
Page 39
5
VI
N
12
+
PC
D D
VPCU
+5
+5VPCU
5 Volt +/- 5%
TDC : 6.77A
PEAK : 9.03A
OCP : 11A
Width : 280mil
6227
PC
220u/6.3V_6X4.2
C C
P:11A
OC
ripple current)
L(
=(9-5)*5/(2.2u*0.3M*9)
=3.367A
cp=12- (3.367 /2)=9. 316A
Io
Vth=(9.316A*14.5mOhm)+1mV=136.089mV
R(Ilim)=(136.089mV*8)/10uA
~108.87K
6212
33u/25V_6x4.5
+
6226
PC
0.1u/50V_6
PR6281
15.8K/F_4
PR6120
10K/F_4
PC
10u/25V_8
2.2uH_7X7X3
6220
+1
PL6013
5V
6288
PR
*4.7_6
PC
0.1u/50V_6
6097
SYS_
PC
2200p/50V_4
PC
*680p/50V_6
PR
6275
22_8
SHDN#2,45
6218
6221
4
5V_ALWP
+1
1
1
52
3
52
3
PD
1PS302
PD
1PS302
6004
6008
SYS_
PQ
AON7410
4
4
PQ
AON7752
2
1
2
1
PC
0.1u/50V_6
SHDN#
6209
SYS_
6056
6055
HWPG37
SYS_
3
3
SHDN#
*SHORT_4
6215
PC
0.1u/50V_6
0.1u/50V_6
3
PR
6130
*SHORT_6
6284
7
20
16
17
18
15
2
14
6285
VL 3V
6219 10u/ 6.3V_6
PC
PG
OOD
EN
1
DRVH1
VBST
1
SW
1
L1
DRV
VFB1
VO
1
VCLK
19
CLK
51225_V
13
EG5
VR
TPS51225RUKR
1
CS
1
51225_CS151225_C
6124 110K/F_4
PR
+3
VPCU
PR
6278
6287
PR
1/F_6
6099
PC
PC
6211
0.1u/50V_6
PR
6283
*SHORT_4
51225_E
51225_DH1
51225_V
51225_S
51225_D
51225_F
N1
BST1
W1
L1
B1
PR
*100K/F_4
PR
*SHORT_6
_LDO
PR
6280
10K/F_4
IN
6100 0.1u /25V_4
6098 4.7u/6.3V_6
PC
25
D
GN
3
EG3
VR
D
24
6125
PR
*SHORT_6
DRV
VBST2
DRV
GND23GN
SW
VF
GND
GN
PC
6
SYS_
EN
H2
B2
SHDN#
2
10
51225_D
H2
9
51225_VBST2
8
W2
51225_S
2
11
51225_D
L2
D
L2
4
51225_F
B2
21
22
B2
S0->S5 & S0->S3
Power of sequence 1us
SUSB# -> VCCIO
OC
L(ripple current)
=(9-3.3)*3.3/(3.3u*0.355M*9)
~1.784A
Iocp=8-( 1.784/ 2)=7.108A
Vth=(7.108A*14.5mOhm)+1mV=104.066mV
R(Ilim)=(104.066mV*8)/10uA
=83.25K
A
51225_V
12
VIN
6010
PU
2
CS
GND
5
26
S2
6122 84.5K/F_4
PR
PR
6286
1/F_6
P:8A
2
AON7410
PC
6213
0.1u/50V_6
AON7752
1
39
N
VI
PC
6214
2200p/50V_4
52
PQ
6054
4
3
1
PL6012
3.3uH_7X7X3
52
6289
PC
*680p/50V_6
PR
6290
*10K/F_4
6222
PR
*4.7_6
4
PQ
6053
3
1
+5
VPCU
PC
6216
10u/25V_8
VPCU
+3
3.3 Volt +/- 5%
TDC : 4.57A
PEAK : 6.09A
OCP : 8A
Width : 160mil
PR
6279
6.49K/F_4
6225
PC
0.1u/50V_6
PR6121
10K/F_4
IND
MA
6224
PC
220u/6.3V_6X4.2
+3
VPCU
+
IND
1
37
PQ
MDV1528Q
+5V_S5
MA
3
MAIND 40,45
VPCU
+5
52
4
3
1
TDC : 3.77A
PEAK : 5.02A
Width : 160mil
38
PQ
MDV1528Q
SB#2,10,16,37
SU
VPCU
+3
3
2
PQ33
AO3404
+5V
1
TDC : 0.49A
PEAK : 0.66A
Width : 20mil
2
B B
3/
11
Change 22 ohm to 220 ohm for Audio bo bo sound (S3)
N
VI
PR288
1M_6
3
_ON37,40,45
S5
A A
2
PQ
DTC144EU
5
2
1 3
36
PR289
1M_6
1
PR269
22_8
PQ32
2N7002K
+5V_S5+3V_S5
PR138
220_8
3
2
PQ21
2N7002K
1
5V
N
+1
VI
PR287
PR286
*1M_6
1M_6
3
2
PQ35
2N7002K
1
4
PC247
*2.2n/50V_4
VPCU
+5
52
4
S5D MAIND S5DMAIND
3
TDC : 3A
PEAK : 4A
Width : 120mil
3
2
PQ
6057
*2N7002K
1
VPCU
+3
3
2
1
TD
PEAK : 1.73A
Width : 60mil
3
2
PQ
6058
*2N7002K
1
PQ34
AO3404
+3V_S5+3V
C : 1.3A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
Date: Sheet
EM 5V/3V (TPS51225)
EM 5V/3V (TPS51225)
EM 5V/3V (TPS51225)
SYST
SYST
SYST
1
1A
1A
1A
39 49Tuesday, August 25, 2015
39 49Tuesday, August 25, 2015
39 49Tuesday, August 25, 2015
of
of
of
Page 40
5
4
3
2
1
40
N
D D
VPCU
+5
V
+3
PC
223
51211V
51211V
51211V
51211V
51211V
B=0.7V
1u/10V_4
_DRVH
_VBST
_SW
_DRVL
_FB
PR
264
*SHORT_6
PC
0.1u/50V_6
PR263
100K/F_4
PG_1VS537
HW
_ON37,39,45
S5
+1V_S5_ON37
C C
OCP=15A
L ripple current
=(19-1)*1/(0.68u*290k*19)
=4.804A
Vtrip=15-(4.804/2)*4.9mohm
=61.729mV
Rlimit=61.729mV/10uA*8=49.383Kohm
PR
266 *0_4
115 *SH ORT_4
PR
114
PR
*100K/F_4
PR
265 49.9K/F_4
PR
268 470K/F_4
51211V
51211V
51211V
_EN
_TRIP
_TST
1
PGOOD
3
EN
2
TR
5
TS
12
GN
IP
RT8237CZQW
T
D
D
D
GN
GN
13
14
7
IN
V5
13
PU
D
GN
15
16
DRVH
VBST
DRV
D
GN
9
10
8
SW
6
L
11
GN
D
FB
4
VF
31
PQ
AON6978
222
2
D1
G1
1
S1/D2
8
G2
S2
RDSon=4.9mohm
D1
D1
9
S2
S2
567
51211V
PC
220
2200p/50V_6
0.68uH_7X7X3
_SW
112
PR
*4.7_6
PC
81
*680p/50V_6
PL
PC
221
10u/25V_8
12
116
PR
4.3K/F_4
217
PC
0.1u/50V_6
267
PR
10K/F_4
VI
+
219
PC
330u/2.5V_6X4.2
V_S5 10,11,14
+1
+1
V_S5
+1
V_S5
1.0 Volt +/- 5%
TDC : 9.52A
PEAK : 12.69A
OCP : 15A
Width : 400mil
V_S5
+1
N
B B
SON10,41
SU
A A
5
2
PQ
DTC144EU
1 3
8
VI
PR
84
1M_6
PR83
1M_6
4
2
CCSTPLL
+V
3
1
PR
86
22_8
PQ9
2N7002K
5V
+1
3
2
2N7002K
1
PR
1M_6
PQ10
N
VI
PR
87
3
85
*1M_6
SU
PC62
*2.2n/50V_4
SD
AO3404
V_S5
+1
3
2
PQ
29
1
TDC : 0.2A
PEAK : 0.27A
Width : 20mil
PR
*0_6
+V
255
CCSTPLL
5
MA
IND39,45
MA
IND
4
213
30
PQ
AON6414AL
+VCCIO
TDC : 4.13A
PEAK : 5.5A
Width : 180mil
+V
PR
256
*SHORT_6
CCIO
+1
.0V
+1.0V
TDC : 0.03A
PEAK : 0.04A
Width : 20mil
+VCCIO3,6,16,38,42,45
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
+1
+1
+1
V_S5 (RT8237CZQW)
V_S5 (RT8237CZQW)
Date: Sheet
Date: Sheet
Date: Sheet
2
V_S5 (RT8237CZQW)
1
1A
1A
1A
of
of
of
49Tuesday, August 25, 2015
49Tuesday, August 25, 2015
49Tuesday, August 25, 2015
40
40
40
Page 41
5
C : 0.45A
TD
PEAK : 0.6A
Width : 40mil
TDC : 0.38A
PEAK : 0.5A
MA
INON10, 45
SU
SON10,40
PR
*0_4
Width : 20mil
292
PR
*SHORT_4
PR
291
*SHORT_4
294
PR
200K/F_4
293
PR
110K/F_4
296
51216_S551216_S3
PR
100K/F_4
D D
PG_VDDR37
HW
C C
PC
263
0.22u/10V_4
+3
295
DDQ
+V
V
3
51216_S
51216_S
5
ODE
51216_M
51216_T
RIP
VREF=1.8V
262
PC
0.1u/16V_4
20
17
16
19
18
26
51216_R
PR
10K/F_4
PG
S3
S5
MODE
TR
PAD
299
OOD
IP
EF
22
6
PC
258
10u/6.3V_6
PAD
F
RE
DDR_
21
PAD
FIN
RE
8
EFIN
51216_R
4
VTTREF
4/16 Chaneg +VDDQ_VTT to DDR_VTTREF
PC
257
10u/6.3V_6
2
3
1
4
5
9
TREF
VT
DQSNS
VD
G5316RZ1D
T
VT
DOIN
TSNS
TGND
VT
PU
17
PAD
25
VL
VT
PAD
PAD
23
24
12
IN
V5
14
DRV
H
15
VBST
13
SW
11
DRV
L
10
PGND
D
GN
7
298
PR
*SHORT_6
ose to IC
Cl
PC
10u/6.3V_6
51216_D
51216_V
51216_S
51216_D
3
2
1
41
Gr
eater than or equal 40mil
VPCU
+5
PC
252
RVH
PR
2/F_6
BST
W
RVL
259
1u/10V_4
52
PQ
39
AON7410
297
PC
0.1u/50V_6
4
256
3
1
52
4
40
PQ
3
AON7752
1
51216_S
W
PC254
2200p/50V_4
PL16
1uH_7X7X3
PC253
10u/25V_8
260
PC
0.1u/50V_6
+
255
PC
330u/2.5V_6X4.2
VI
N
+1.2VSUS
1.2 Volt +/- 5%
TDC : 6.6A
PEAK : 8.8A
OCP : 11A
Width : 280mil
.2VSUS
+1
.2VSUS 2,6,10,17,18
+1
RDSon=14.5mohm
Close to out put cap
PR
20K/F_4
290 *0_4
VTTT_PG_CTRL17
DDR_
OCP=11A
L ripple current
=(19-1.2)*1.2/(1u*400k*19)
=2.81A
Vtrip=11-(2.81/2)*14.5mohm
B B
A A
=139.123mV
Rlimit=139.123mV/10uA*8=111.29Kohm
Su
PR
4/16 Chaneg DDR3L to DDR4
Adding +2.5V Power Rail
PG_2.5V37
HW
SUSON
PR304 *0_4
son_2.5V37
5
PR303 *SHORT_4
51216_S
3
PR
PR271 10K_4
PC
300
0.01u/50V_4
DDR4=1.2V
PR299=10K/F_4
PR300=20K/F_4
V_S5
+3
301 *SHORT_4
261
PR285 *SHORT_6
15
PU
5
PG
1
EN
234
PC
APW8824
47uF/4V_4
0.
R2
4
Mode Frequency Discharge mode
200K 400K Tracking Discharge
100K 300K Tracking Discharge
S3 S5
S0
S3 (mainon off)
1
0
S4/S5
PC243
4.7U/6.3V_6
4
6
N
VI
FB
PR
15K/F_4
3
LX
2
GN
D
R1
278
PR
47.5K/F_4
302
PL
8824LX
2.5V
2.2uH/1.85A_2.5X2X1.2
PR273 *SHORT_4
Vo=(0.6(R1+R2)/R2)
15
PC228
3
/6.3V_6
10U
1
1
+2
.5V_SUS 17,18
PC231
0U/6.3V_6
*1
ON
ON ON
OFF
PC232
1U/16V_4
0.
ON
OFF OFF00
+2.5V_SUS
2.5Volt +/- 5%
TDC : 0.75A
PEAK : 1A
Width : 40mil
+2.5V_SUS
VTTREF+1.35VSUS
ON
OFF
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Date: Sheet
Date: Sheet
2
Date: Sheet
1.2V (G5316RZ1D)
1.2V (G5316RZ1D)
1.2V (G5316RZ1D)
DDR4
DDR4
DDR4
1
1A
1A
1A
41 49Tuesday, August 25, 2015
41 49Tuesday, August 25, 2015
41 49Tuesday, August 25, 2015
of
of
of
Page 42
5
IM
VP8 Vcore Controller
4
3
2
1
PROG239PR
ISEN2_A22IS
ISL95855_PROG3
38
PW
FCCM_C
IS
IS
CO
IM
PWM3_A
PW
PW
23
PR199 2.55K/F_4
3
PR41
100/F_4
OG3
PR
PR
UMN_C
UMP_C
RT
FB
MP_C
ON_C
M2_A
M1_A
EN3_A
ISL95855_PROG4
37
OG4
PR
OG5
M_C
N_C
_C
CM_A
FC
24
PR32
182K/F_4
36
35
34
33
32
31
30
29
28
27
26
25
PR195
PC144
+VCCSTPLL
PR43
*110/F_4
PR188
16.9K/F_4
ISL958 55_PW M_C
ISL958 55_FCCM _C
ISL958 55_ISUM N_C
ISL958 55_ISUM P_C
ISL958 55_RTN_C
ISL958 55_FB_ C
ISL958 55_COMP _C
ISL958 55_IMON_ C
ISL958 55_PW M3_A
ISL958 55_PW M2_A
ISL958 55_PW M1_A
ISL958 55_FCCM _A
PC138
2200p/50V_4
1K/F_4
220p/50V_4
PR44
45.3/F_4
PR35
PR191
110K/F_4
5.62K/F_4
PR185 121K/F_4
PR183 *SHORT_4
PR182 *SHORT_4
PR168 *SHORT_4
PR174 *SHORT_4
PR179 *SHORT_4
PR178 *SHORT_4
PC128 0.022U/25V_4
PC134 0.022U/25V_4
PC137 0.022U/25V_4
PR186 280/F_4
PC20
1000p/50V_4
PC17
ISEN3_ A 43
ISEN2_ A 43
ISEN1_ A 43
PR189
1K/F_4
VR_SVID_DATA
VR_SVID_ALERT#
VR_SVID_CLK
PC140
0.1u/25V_4
0.1u/25V_4
Rail A
PC136
PC147
*0.01u/50V_4
PR202 *SHORT_4
PC143
*0.01u/50V_4
PR197 *SHORT_4
PC141
0.01u/50V_4
PR192
909K/F_4
Ra
PWM_C 44
FCCM_C 44
PWM3_A 43
PWM2_A 43
PWM1_A 43
FCCM_A 4 3
0.1u/25V_4
il C
+VCCCORE
Ra
il A3 phaseVCORE
42
Rail B2 phaseVCCGT
Ra
il C1 phaseVCCSA
PC132
PR172
2200p/50V_4
PR170 100K_4
PC142
1 2
0.22u/25V_4
PR201
10_4
PR196
10_4
1K/F_4
PR173
590/F_4
PC14
PC124
0.1u/25V_4
0.015u/25V_4
PR171
PR18 2K/F_4
4.02K/F_4
PC130 33p/50V_4
PC129 330P/50V_4
12
PC139
0.01u/25V_4
2
PC120
Cl
ose to
Vcore Choke
PR38
11K/F_4
PC15
8200PF/50V_4
PR246
10K/F_4_3435NTC
12
PR40
2.61K/F_4
VCORE_SENSE 7
VCORESS_SENSE 7
PC131
0.047U/10V_4
1 2
PR13
PC123
PR180 2.1K/F_4
330P/50V_4
ISUMN_A 4 3
ISUMP_ A 4 3
1K/F_4
1000p/50V_4
ose to
Cl
VCCSA Choke
12
PR22
11K/F_4
12
PC13
*0.01U/50V_4
PR169 *SHORT_4
PC127
*0.01U/50V_4
PR176 *SHORT_4
PC135
0.01U/50V_4
ISUMN_C 44
PR247
10K/F_4_3435NTC
PR181
2.61K/F_4
ISUMP_ C 44
+VCCSA
PR14
10_4
VSA_SENSE 6
VSASS_SENSE 6
PR15
10_4
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
U_CORE (ISL95855HRTZ-T)
U_CORE (ISL95855HRTZ-T)
U_CORE (ISL95855HRTZ-T)
CP
CP
CP
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
1A
1A
1A
42 49Tuesd ay, A ugus t 25 , 20 15
42 49Tuesd ay, A ugus t 25 , 20 15
42 49Tuesd ay, A ugus t 25 , 20 15
+5V_S5
44
45
LK
ERT#
SC
AL
ISL95829HRTZ-T
MP_A
_A
CO
FB
16
17
ISL95855_FB_A
ISL95855_COMP_A
PC145 33p/50V_4
VIN
PR39 100K/F_4
PR193 1/F_6
ISL95855_VIN
ISL95855_VCC
ISL95855_PROG1
ISL95855_PROG2
41
42
43
40
A
N
C
VI
SD
OG1
VC
PU5
N_A
UMN_A
UMP_A
EN1_A
RT
IS
IS
IS
18
20
19
21
ISL95855_RTN_A
ISL95855_ISUMP_A
ISL95855_ISUMN_A
PR42
2K/F_4
PR45
2K/F_4
PC18 330p/25V_4
PC19 3.3n/50V_4
PR53 102K/F_4
PC156 330P/50V_4
217
PR
1 2
Cl
VGTU Choke
PR232 11.3K/F_4
PC155 33p/50V_4
PC23
3.3n/50V_4
+VCCGT
PR59
10_4
PR57 *SHORT_4
PR55 *SHORT_4
PR54
10_4
2.61K/F_4
PR214
PR242
10K/F_4_3435NTC
ose to
0.01U/50V_4
0.01U/50V_4
11K/F_4
1 2
D D
VCCGT_SENSE5
VCCGTSS_SENSE5
C C
ISUMP_ B44
ISUMN_B44
PC24
0.1U/25V_4
B B
ylake H42 - 45W
Sk
PR52
2K/F_4
PC158
PC160
PC21
12
0.022u/25V_4
Close to
VGTU MOS
PR230
470K_4_4700NTC
PR231 27.4K/F_4
PR50
PC22
PC154
*0.01U/50V_4
PC150
0.15u/10V_4
1K/F_4
220p/50V_4
PR219
1K/F_4
0.022U/25V_4
0.022U/25V_4
PR51
PR49
301/F_4
PC152
PC151
PR211
2.94K/F_4
PC157
PC153
2200P/50V_4
VR_SVID_DATA2
VR_SVID_ALERT#2
VR_SVID_CLK2
H_PROCHOT#2,37,38
IMVP_P WRGD2
2K/F_4
VRON10
PMON38
680p/50V_4
FCCM_B44
PWM1_B44
PWM2_B44
Rail B
PR194 10/F_4
PR198 *SHORT_4
PR200 49.9/F_4
+3V +VCCIO
PR207
PR204
10K/F_4
10K/F_4
PR213 *SHORT_4
PR212 *SHORT_4
PR210 *SHORT_4
PR208 *SHORT_4
PR206 *SHORT_4
ISEN1_ B 44
ISEN2_ B 44
*SHORT_4
PR203
PR205
*SHORT_4
(3+2+1 Phase)
ore
Vc
Icc
TDC PL256A
Icc Max68A
OC
P88A
A A
Fsw750KHz
VCORE L/L
R_DC_LL1.8mV/A
R_AC_LL1.8mV/A
CGT
VC
Icc
TDC PL239A
Icc Max54A
OCP68A
Fsw750KHz
VC
ORE L/L
R_DC_LL2.65mV/A
R_AC_LL2.65mV/A
5
CSA
VC
Icc
TDC PL210A
Icc Max11A
OCP15A
Fsw150KH
z
VCORE L/L
R_DC_LL9.1mV/A
R_AC_LL9.1mV/A
4
ISL958 55_SDA
ISL958 55_ALE RT
ISL958 55_SCL K
ISL958 55_VR_ HOT
ISL958 55_VR_ READY
ISL958 55_VR_ EN
46
47
48
PR209
*10K/F_4
49
_EN
EP
+3V
ISL958 55_PSY S ISL958 55_PRO G5
ISL958 55_IMON_ B
ISL958 55_NTC_B
ISL958 55_COMP _B
ISL958 55_FB_ B
ISL958 55_RTN_B
ISL958 55_ISUM P_B
ISL958 55_ISUM N_B
ISL958 55_FCCM _B
ISL958 55_PW M1_B
ISL958 55_PW M2_B
PR46
VR
_READY
1
VR_HOT#
PSYS
VR
2
ON_B
IM
3
NTC_B
4
CO
MP_B
5
_B
FB
6
RT
N_B
7
UMP_B
IS
8
IS
UMN_B
9
IS
EN1_B
10
ISEN2_B
11
FC
CM_B
12
M1_B
PW
M2_B
ON_A
IM
NTC_A
PW
14
15
13
ISL95855_IMON_A
ISL95855_NTC_A
PR227 470K_4_4700NTC
PR228 27.4K/F_4
97.6K/F_4
Close to
PC148 330P/50V_4
Vcore MOS
PR229 11.3K/F_4
Page 43
5
4
3
2
1
VCORE-3 phase
N
VI
N
VI
12
2200P/50V_6
5
4
2200P/50V_6
4
4
+
DCR=
PR
24 100K/F_4
PR20 100K/F_4
DCR=0.66mOhm
30 100K/F_4
PR
PR
34 100K/F_4
161
PC
33U/25V_6x4.5
0.66mOhm
51
47
PC
PC
22u/6.3V_8
0.1u/10V_4
49
54
PC
PC
0.1u/10V_4
22u/6.3V_8
50
PC
22u/6.3V_8
IS
EN2_A 42,43
EN3_A 42,43
IS
52
PC
22u/6.3V_8
IS
EN1_A 42,43
ISEN3_A 42,43
CCCORE
+V
+VCCCORE
+
187
PC
330u/2V_7343
+
57
PC
330u/2V_7343
+V
CCCORE 7,42
177
PC
167
PC
0.1U/50V_6
0.1U/50V_6
33
PC
PL
0.15uH_7X7X4
1 2
3
N
VI
27
PC
PL
0.15uH_7X7X4
1 2
3
34
178
PC
170
0.1u/25V_6
68
PR
2.2/F_6
PC39
1000P/50V_4
IS
UMP_A42,43
IS
EN1_A42,43
UMN_A42, 43
IS
165
PC
0.1u/25V_6
PR
65
2.2/F_6
30
PC
1000P/50V_4
IS
UMP_A42,43
EN2_A42,43
IS
ISUMN_A42, 43
PC
PC
10u/25V_8
10u/25V_8
ASE_A1
PH
29 3.65K/F_6
PR
PR
28 100K/F_4
PR21 10/F_4
28
168
PC
PC
10u/25V_8
10u/25V_8
PH
ASE_A2
37 3.65K/F_6
PR
PR
36 100K/F_4
PR
31 10/F_4
67
PR
V_S5
+5
Ra
il A
M1_A42
PW
FCCM_A42, 43
Rail A
PW
M2_A42
CM_A42,43
FC
*SHORT_4
172
PC
237 *SHORT_4
PR
238 *SHORT_4
PR
62
PR
V_S5
+5
*SHORT_4
166
PC
PR225 *SHORT_4
PR
226 *SHORT_4
D D
C C
PU
4.7u/6.3V_4
4.7u/6.3V_4
C
VC
1
PWM
2
CM
FC
7 AOZ5029QI-5
PU
23
PVCC
24
C
VC
1
M
PW
2
FCCM
9 AOZ5029QI-5
23
PVC
C
24
6
VI
N
22
VI
N
4
*SHORT_6
GH
3
BO
OT
234
PR
5
VSW
H
13
VSW
H
19
ND
ND
GL
20
GL
PG
PG
9
21
6
N
VI
22
VIN
4
*SHORT_6
GH
3
BO
OT
PR224
5
H
VSW
13
VSW
H
19
ND
ND
GL
20
GL
PG
PG
9
21
Vc
Icc TDC PL 256A
Icc Max68A
OCPA
FswMHz
VCORE L/L
R_DC_LL1.8mV/A
R_AC_LL1.8mV/A
43
ore
B B
32
176
PC
*SHORT_6
PC169
0.1u/25V_6
PR71
2.2/F_6
PC
1000P/50V_4
ISUMP_A42, 43
EN3_A42, 43
IS
UMN_A42,43
IS
PC
10u/25V_8
PHASE_A3
38
PR66
+5V_S5
*SHORT_4
Rail A
PWM3_A42
FC
CM_A42,43
A A
235 *SHORT_4
PR
PR
236 *SHORT_4
5
173
PC
4.7u/6.3V_4
PU8 AOZ5029QI-5
23
C
PVC
24
VCC
1
PW
M
2
FC
CM
ND
PG
21
6
VI
N
22
N
VI
4
GH
3
BOOT
233
PR
5
VSWH
13
H
VSW
19
ND
GL
20
GL
PG
9
4
175
PC
10u/25V_8
0.1U/50V_6
PR
16 3.65K/F_6
PR17 100K/F_4
26 10/F_4
PR
3
VI
N
31
PC
PL
7
0.15uH_7X7X4
1 2
3
2200P/50V_6
4
PR
PR
DCR=0.66mOhm
48
PC
27 100K/F_4
23 100K/F_4
0.1u/10V_4
55
PC
22u/6.3V_8
ISEN1_A 42,43
EN2_A 42,43
IS
2
CCCORE
+V
+
53
PC
PC186
22u/6.3V_8
330u/2V_7343
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
ORE (ISL95855HRTZ-T)
ORE (ISL95855HRTZ-T)
ORE (ISL95855HRTZ-T)
VC
VC
VC
Date: Sheet
Date: Sheet
Date: Sheet
1A
1A
1A
43 49Monday, September 07, 2015
43 49Monday, September 07, 2015
43 49Monday, September 07, 2015
of
of
of
1
Page 44
5
4
3
2
1
IS
EN1_B
44
VCCGT-2 phase
VI
PR61
V_S5
+5
*SHORT_4
162
V_S5
PC
PR221 *SHORT_ 4
PR222 *SHORT_ 4
PR69
*SHORT_4
182
PC
PR244 *SHORT_ 4
PR245 *SHORT_ 4
D D
il B
Ra
M1_B42
PW
CM_B42,44
FC
+5
C C
Rail B
M2_B42
PW
CM_B42,44
FC
4.7u/6.3V_4
4.7u/6.3V_4
PU6 AOZ5029QI-5
23
CC
PV
24
C
VC
1
M
PW
2
CM
FC
ND
PG
21
PU11 AOZ5029QI-5
23
CC
PV
24
C
VC
1
M
PW
2
CM
FC
ND
PG
21
6
N
VI
22
N
VI
4
GH
3
OT
BO
PR220
5
WH
VS
13
WH
VS
19
ND
GL
20
GL
PG
9
6
N
VI
22
N
VI
4
GH
3
OT
BO
PR243
5
WH
VS
13
WH
VS
19
ND
GL
20
GL
PG
9
*SHORT_6
*SHORT_6
PC159
0.1u/25V_6
IS
UMP_B42,44
IS
EN1_B42,44
IS
UMN_B42,44
PC181
0.1u/25V_6
IS
IS
IS
25
PC
10u/25V_8
1000P/50V_4
183
PC
10u/25V_8
1000P/50V_4
UMP_B42,44
EN2_B42,44
UMN_B42,44
PR63
2.2/F_6
PC29
PR72
2.2/F_6
PC42
PH
PH
ASE_B1
ASE_B
163
PC
10u/25V_8
PR223 3.65 K/F_6
PR218 10 0K/F_4
PR216 10 /F_4
40
PC
10u/25V_8
PR58 3.65K/F_6
PR47 100K/F_4
PR56 10/F_4
N
N
VI
26
164
PC
PC
0.1U/50V_6
2200P/50V_6
PL3
0.15uH_7X7X4
1 2
3
4
DCR=0.66mOhm
44
PC
0.1u/10V_4
CCGT 5,7,42
+V
+V
CCGT
46
199
PC
PC
22u/6.3V_8
22u/6.3V_8
+
185
PC
330u/2V_7343
VC
VCORE L/L
CGT
Icc TDC PL239A
c Max 54A
Ic
OCPA
FswMHz
R_DC_LL2.65mV/A
R_AC_LL2.65mV/A
PR215 100K/F_4
VI
N
41
184
PC
PC
0.1U/50V_6
2200P/50V_6
PL8
0.15uH_7X7X4
1 2
3
4
PR48 100K/F_4
DCR=0.66mOhm
IS
EN2_B 42,4 4
+V
CCGT
45
PC
22u/6.3V_8
EN1_B 42,4 4
IS
+
43
198
PC
PC
22u/6.3V_8
330u/2V_7343
61
PC
0.1u/10V_4
PR6291 *0_ 4
IS
EN2_B
8/
24 reserve the GT short-c ircuit
B B
VCCSA-1 phase
PR64
+5
V_S5
*SHORT_4
174
PC
il C
Ra
PW
M_C42
FC
CM_C42
A A
5
4.7u/6.3V_4
PR240 *SHORT_ 4
PR241 *SHORT_ 4
PU10 AOZ5029QI-5
23
PV
CC
24
VC
C
1
PW
M
2
FC
CM
ND
PG
9
21
4
6
VI
N
22
VI
N
4
GH
3
BO
OT
PR239
5
VS
WH
13
VS
WH
19
ND
GL
20
GL
PG
*SHORT_6
PC171
0.1u/25V_6
PR70
2.2/F_6
PC37
1000P/50V_4
UMP_C42
IS
UMN_C42
IS
36
180
PC
PC
10u/25V_8
10u/25V_8
ASE_C
PH
PR25 3.65K/F_6
PR19 10/F_4
3
179
PC
0.1U/50V_6
PL6
0.47uH_7X7x3
1 2
3
35
PC
2200P/50V_6
4
VI
N
DCR=4.2mOhm
196
PC
0.1u/10V_4
2
CSA
+V
CCSA 6,42
CCSA
+V
58
195
PC
PC
22u/6.3V_8
22u/6.3V_8
VC
Icc TDC PL210A
Icc Max11A
OCPA
Fs
wMHz
VCORE L/L
R_DC_LL9.1mV/A
R_AC_LL9.1mV/A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
VCCGTU/VCCSA (ISL95855HRTZ-T)
VCCGTU/VCCSA (ISL95855HRTZ-T)
VCCGTU/VCCSA (ISL95855HRTZ-T)
Date: She et of
Date: She et of
Date: She et of
1
1A
1A
1A
44 49Monday, September 07, 2015
44 49Monday, September 07, 2015
44 49Monday, September 07, 2015
Page 45
5
4
3
2
1
45
+1
.5V 14,30,32,34
+1.5V
83
PC
2200p/50V_4
1.5Volt +/- 5%
TDC : 0.38A
PEAK : 0.51A
Width : 20mil
+1
.5V
IND 39,40
MA
D D
C C
Re
move 1.8V
VI
N
HW
PG_1.5V37
INON10,41
MA
N
VI
284 *SHORT_4
PR
270 10K_4
PR
11
3/
Change 22 o hm to 22 0 ohm fo r Audio bo bo sound (S3)
+3
PR
V_S5
282 *SHORT_4
PU
14
5
PG
1
EN
PC
233
APW8824
47uF/4V_4
0.
R2
V
+5
4
6
N
VI
FB
PR
15K/F_4
+V
GN
4.7U/6.3V_6
LX
D
283
CCIO
242
PC
3
2
R1
PR
277
22.6K/F_4
8002LX1.05V
PL
2.2uH/1.85A_2.5X2X1.2
PR
Vo=(0.6(R1+R2)/R2)
.0V
+1
14
272
*SHORT_4
229
227
PC
/6.3V_6
10U
5V
+1
230
PC
PC
1U/16V_4
0U/6.3V_6
0.
*1
+3
V
Thermal protection
PD
4
1 3
DA2J10100L
117
PR
1M_6
2
1
3
PR
*SHORT_6
PQ13
AO3409
121
S_SHDN# 2,39
SY
INON
2
PR
128
*100K/F_6
PQ
DTC144EU
1 3
MA
Need fine tune
for thermal protect point
Note placement position
TEMP=85C
2
S5
_ON37,39,40
B B
S5
_ON
PQ
14
DTC144EU
VLVL
PR
126
1M_4
INON_ON_G
MA
123
PR
18
1M_4
PR
129
22_8
3
2
PQ19
2N7002K
1
PR
137
220_8
3
2
PQ20
2N7002K
1
PR
119
22_8
3
2
PQ16
2N7002K
1
PR
118
*22_8
3
2
PQ15
*2N7002K
1
PR
127
1M_4
IND
MA
3
2
PQ17
2N7002K
1
PR122
PR
200K/F_4
125
PR
60
10K/F_4_3435NTC
3
2
_ON
S5
A A
3
PQ
2N7002K
1
1.47K/F_4
LM
393_PIN2
2.
469V
PR
124
200K/F_4
3
+
2
-
5
+
6
-
For EC control thermal protection (output 3.3V)
5
84
PC84
0.1u/50V_6
1
PU
2A
AS393MTR-E1
7
PU
2B
AS393MTR-E1
PR120
200K_6
PC82
0.1u/50V_6
4
3
2
PQ12
2N7002K
1
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
+1
+1
+1
.5V/Thermal Protect
.5V/Thermal Protect
.5V/Thermal Protect
Date: Sheet
Date: Sheet
3
2
Date: Sheet
1
1A
1A
1A
49Tuesday, August 25, 2015
49Tuesday, August 25, 2015
49Tuesday, August 25, 2015
of
45
of
45
of
45
Page 46
5
D D
-EN
1658R
PR
EV@100K/F_4
258
_MAIN_PWGD21,47
3V
PU_EN13
VG
DG
PU_PSI22
PW
M-VID22
1658R
VI
N
PU_PSI
DG
M-VID
PW
-VREF
PR
259 EV@43K/F_4
218 *[email protected]/50V_4
PC
1 2
260 *EV@1/F_4
PR
343 EV@0_4
PR
PR
98 *EV@0_4
PR
99 EV@*SHORT_4
PR
103 EV@*SHORT_4
1 2
78 EV@1U/10V_4
PC
261
PR
*EV@499K/F_4
PU High on HW side
C C
+3
DG
PU_PSI
V_S5
PR
100
*EV@10K_4
102
PR
*EV@0_4
+3
VPCU
PR
101
*EV@10K_4
Phase Number of Operation
M-SVID : Config B
PW
Check PWM-SVID by SKU
B B
Standby
Function
*EV@1U/10V_4
PC
76
R1
PR
106
EV@20K/F_4
EV@2700P/50V_4
2
12
80
PC
3
1
12
C
105
PR
*[email protected]/F_4
PQ
11
*EV@2N7002K
PR
EV@20K/F_4
PR
EV@2K/F_4
PR
EV@18K/F_4
PR
EV@0_4
107
R2
113
R3
110
R4
111
R5
+V
GPU_CORE
4
PR
262 [email protected]/F_4
1658R
-OCS/CB
1658R
-EN
-PSI
1658R
-VID
1658R
1658R
-VREF
1658R
-REFADJ
77
-REFIN
PC
1658R
12
3
V_S5
+5
94
PR
EV@*SHORT_6
PR
96
-BOOT1
12
-PVCC
1658R
18
1
PU
OC
S/CB
EN
PSI
VI
D
VR
EF
RE
FADJ
RE
FIN
11
-FB
1658R
EV@
UP1658RQKF
FB
109
PR
EV@*SHORT_4
C
PVC
TP
9
3
4
5
8
6
7
*[email protected]/50V_4
79
PC
*EV@22P/50V_4
PC
72
EV@1U/10V_4
1
1658R
BO
OT1
UG
ATE1
PH
ASE1
LG
ATE1
BO
OT2
UG
ATE2
PH
ASE2
LG
ATE2
PG
OOD
CO
D
FB
RTN
GN
21
26
-BOOT1
2
1658R
-UGATE1
20
1658R
-PHASE1
19
-LGATE1
1658R
15
-BOOT2
1658R
14
1658R
-UGATE2
16
1658R
-PHASE2
17
1658R
-LGATE2
13
-PG
1658R
12
-COMP
1658R
MP
10
23
TP
-FBRTN
1658R
PR104
EV@16K/F_6
108
PR
EV@*SHORT_4
12
75
PC
EV@4700P/25V_4
257 EV@10K_4
PR
1 2
PR
97 EV@*SHORT_4
12
216
PC
EV@22P/50V_4
1658R
1658R
1658R
1658R
V
+3
GP
U_PWR_GD 19
1658R
1658R
1658R
1658R
-UGATE1
-PHASE1
-LGATE1
-BOOT2
-UGATE2
-PHASE2
-LGATE2
PC
[email protected]/25V_6
95
PR
PC
[email protected]/25V_6
PQ
28
EV@AON6414AL
74
73
PQ
EV@AON6752
4
4
25
PQ
EV@AON6752
PQ
26
EV@AON6414AL
4
4
27
5
213
5
213
5
213
5
213
2
1
46
VI
N
N
VI
12
66
PC
EV@10u/25V_8
DCR=
191
PC
212
PC
EV@10u/25V_8
192
PC
1.2m ohm
[email protected]/16V_4
1.2m ohm
[email protected]/16V_4
67
PC
EV@10u/25V_8
+
190
201
PC
PC
EV@10u/6.3V_8
211
PC
EV@10u/25V_8
+
60
189
PC
PC
EV@10u/6.3V_8
71
PC
PQ
41
EV@AON6414AL
5
4
213
5
4
213
PQ
EV@AON6752
PQ
43
EV@AON6414AL
5
4
213
5
4
213
PQ
EV@AON6752
PC68
PR
[email protected]/F_6
PC
EV@1000p/50V_6
42
VI
N
PC69
PR91
[email protected]/F_6
PC
44
EV@1000p/50V_6
EV@2200p/50V_4
[email protected]_10X10X4
89
64
EV@2200p/50V_4
[email protected]_10X10X4
65
[email protected]/50V_6
9
PL
70
PC
[email protected]/50V_6
10
PL
DCR=
+
214
PC
EV@33U/25V_6x4.5
GPU_CORE
+V
+
328
PC
EV@330u/2V_7343
EV@330u/2.5V_6X4.2
GPU_CORE
+V
+
203
PC
EV@330u/2V_7343
EV@330u/2.5V_6X4.2
PR
76
*EV@100_4
73 EV@*SHORT_4
VGA_VCCSENSE19
A_VSSSENSE19
VG
A A
Parallel
PR
PR74 EV@*SHORT_4
75
PR
*EV@100_4
R1
R2
R3
R4
R5
C
5
4
Config BComponent Value
20K
20K
2K
18K
0-ohm
2.7nF
3
2
N16P-GT
OpenVR Config:B
+VGPU_CORE
Countinue current:42.2A
Peak current:80A
OCP:A
FSW:300KHz
L/L=0mV/A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet
Date: Sheet
Date: Sheet
PU_CORE (UP1658)
PU_CORE (UP1658)
PU_CORE (UP1658)
+VG
+VG
+VG
Mo
Mo
Mo
nday, Septem ber 07, 20 15 46 4 9
nday, Septem ber 07, 20 15 46 4 9
nday, Septem ber 07, 20 15 46 4 9
1
of
of
of
1A
1A
1A
Page 47
5
4
3
2
1
47
+1
.05V_GFX19,20,21
+3
V_GFX19,21,22,37
D D
67
TP
HW
VPCU
+3
C C
check ok 10/21
dG
PU_PWR_EN12,13
190
PR
*EV@100K/F_4
PG_1.05VGFX
V
+3
125
PC
[email protected]/50V_4
79
PR
EV@*SHORT_4
PC
56
*EV@1u/10V_4
187
PR
*EV@0_4
126
PC
EV@10U/6.3V_6
PR
EV@10_6
165
554P
117
PC
12
G_0.95V
554S
EV@1U/6.3V_4
2
PR
78
EV@100K_4
VIN_0.95V
PU
4
9
10
8
11
EV@RT8068AZQW
PQ
5
1 3
EV@PDTC143TT
*EV@2200P/50V_4
4
PG
PV
IN
PV
IN
SV
IN
GN
D
VI
N
16
PC
PR
80
EV@1M_4
81
PR
EV@1M_4
PR
NC
LX
LX
NC
FB
EN
2
33
1
2
3
7
6
5
+3
V_GFX
3
1
_0.95V
554LX
554NC_0.95V
554F
B_0.95V
554E
N_0.95V
PR
77
EV@22_8
PQ4
EV@2N7002K
PL
2
EV@1uH_7X7X3
PC
*EV@22P/50V_4
PC
119
*EV@68P/50V_4
PR
EV@*SHORT_4
PC133
*[email protected]/16V_4
5V
+1
3
2
1
122
184
PR
EV@1M_4
PQ7
EV@2N7002K
82
554F
3V
B_0.95V_S
R1
R2
EV@10K/F_4
_MAIN_PWGD
dGPU_D
PC
*[email protected]/50V_4
PR
PR
59
PR
167
EV@*SHORT_4
166
175
+3
2
ch
149
PC
=0.6*(R1+R2)/R2
Vo
3V
_MAIN_PWGD 21,46
eck ok 10/21
VPCU
3
6
PQ
EV@AO3404
1
[email protected]/16V_4
+3
V_GFX
146
PC
EV@22U/6.3V_6
+1.05V_GFX
TDC : 1.57 A
PEAK : 2.09A
Width : 80mil
.05V_GFX
+1
V_GFX
+3
TDC : 0.05 A
PEAK : 0.06A
Width : 20mil
N
B B
208
PR
254
671V
CC
PR
252
EV@100K/F_4
PG_1.5VGFX21
HW
PR251 EV@200K/F_4
FB
VDDQ_EN19
A A
5
FB
VDDQ_EN
PR
93
EV@*SHORT_6
PR
PR
249 EV@*SHORT_4
253 EV@*SHORT_4
*[email protected]/16V_4
*EV@499K/F_4
1
N
VI
5VGFX_EN
5VGFX_PG
4
13
EN
4
PG
3
LP#
12
PU
5
EV@NB671GQ-Z
NC1
6
NC2
92
14
PR
AGND
C
VC
EV@*SHORT_4
11
CC
671V
CC
671V
PC
EV@1u/6.3V_4
1.
1.
PC
207
PR
248
EV@1/F_6
1.5VGFX_BST 1.5VGFX_BST1
10
[email protected]/50V_6
BST
8
1.
5VGFX_SW
SW1
9
SW2
15
SW3
16
SW4
7
VOUT
2
PGND
FB
12
1.
EF=0.604V
VR
206
PC
204
PC
205
[email protected]/16V_4
5VGFX_FB
3
PC
EV@2200p/50V_6
88
PR
*4.7_6
PC63
*680p/50V_6
209
PC
[email protected]/50V_6
11
PL
[email protected]_7X7X3
PR
EV@82K/F_4
250
PR
[email protected]/F_4
213
215
PC
EV@10u/25V_8
90
PC210
PC
EV@10u/25V_8
[email protected]/50V_6
193 EV@22u/6.3V_8
200 EV@22u/6.3V_8
188 [email protected]/50V_6
PC202 EV@22u/6.3V_8
PC
PC
PC
2
VI
.5V_GFX
+1
+1.5V_GFX
1.5 Volt +/- 5%
TDC : 4.62 A
PEAK : 6.16A
194 EV@22u/6.3V_8
PC
Size Document Num ber Rev
Size Document Num ber Rev
Size Document Num ber Rev
Date: Sheet
Date: Sheet
Date: Sheet
Width : 200mil
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
.5V_GFX/+1.05V_GFX/+3V_GFX
.5V_GFX/+1.05V_GFX/+3V_GFX
.5V_GFX/+1.05V_GFX/+3V_GFX
+1
+1
+1
esday, August 25, 2015 47 49
esday, August 25, 2015 47 49
esday, August 25, 2015 47 49
Tu
Tu
Tu
1
1A
1A
1A
of
of
of
Page 48
5
4
3
2
1
Mo
del
te
Da
1. FIRST RELEASED
A
CH
ANGE LIST
1. L23,L24 change to correct footprint 0402.
2. Correct CN14 UART from 3V to 5V.
(Page13)
(Page30)3. Nostuff R270,R271,and stuff R268,R2699,D31,D32 for DDC HDMI 7-13 issue.
D D
B
(Page2)4. Nostuff U22,C441,R200,and stuff R182.
(Page14)5. Chagne HDA power to +3V R296,unstuff R247.
(Page32)6. Chagne Code DVDD-IO to +3V R370 ,unstuff R366.
(Page02)7. Add R204 and unstuff R178 for VCCST_PWRGD.
(Page32)8. Change R424,R431 to 62ohm for Audio EA.
(Page32)9. Unstuff R207 and stuff R208 for DMIC.
(Page2)10. Stuff 50ohm for CATERR#.
(Page6)11. Unstuff R132,R133,R576 for CPU_OPC_COMP.
(Page10)12. Reserve U54,U55,U56 and add R970,R971,R972.
(Page2)13. Add U53,C812 for VCCST PWRGD timing issue.
(Page17,18)14. Change Jdim1,Jdim2 footprint to fix SMT issue.
(Page28)15. Change U14 to version 6516 =>AL006516001 , so unstuff R108, unstuff R110,R111.
(Page30)16. Change U23 to version 8201 =>AL008201003 , so R238 change to 4.99K, unstuff R229.
(Page34)17. SWAP NGFF PCIE10&11, stuff R952/R953 , R949/R950 , C1170/C1171 ,C1172/C1173.
18. Add C687 for Pltrst#. (Page19)
19. Reserve C85 for VID . (Page02)
C C
(Page12)20. Unstuff R732 for PCH_SPI_IO3, it is ES sample only.
21. Shortpad 0402 for R316,R301,R661,R656,R3,R4,R48,R99,R448,R444,R414,R418,R419,R182,R540,R543,R556,R998,R999
Shortpad 0603 for R347
C
22. Del R720,R319 ,Unstuff R719 ,stuff R718,R278,R723,R317 (Page11)
23. Shortpad 0402 for PR139,PR142,PR144,PR146,PR148,PR150,PR152,PR153,PR158,PR163,PR164
Shortpad 0603 for PR149,PR161.
(Page38)
24. Shortpad 0402 for PR6278,PR6283
Shortpad 0603 for PR6125,PR6130,PR6285.
Shortpad 0603 for PR6125,PR6130,PR6285.
Remove JP6018,JP6021,JP6017,JP6019.
(Page39)
25. Shortpad 0402 for PR115.
Shortpad 0603 for PR164,PR256.
Remove JP9,JP10.
(Page40)
26. Shortpad 0402 for PR291,PR292,PR301,PR303,PR273
Shortpad 0603 for PR285,PR298.
B B
27. Shortpad 0402 for PR57,PR55,PR203,PR205,PR213,PR212,PR198,PR210,PR208,PR206,
Remove JP13,JP16,JP17
(Page41)
(Page42)PR182,PR183,PR168,PR174,PR179,PR178,PR202,PR197,PR169,PR176
28. Shortpad 0402 for PR67,PR237,PR238,PR62,PR225,PR226,PR66,PR235,PR236
Shortpad 0603 for PR234,PR224,PR233
Remove JP4
(Page43)
29. Shortpad 0402 for PR61,PR221,PR222,PR69,PR244,PR245,PR64,PR240,PR241
Shortpad 0603 for PR220,PR243,PR239
Remove JP3,JP5
(Page44)
30. Shortpad 0402 for PR282,PR284,PR272
Shortpad 0603 for PR121
Remove JP12
(Page45.)
31. Shortpad 0402 for PR98,PR99,PR103,PR73,PR74,PR109,PR108,PR97
Shortpad 0603 for PR94
Remove JP7
(Page46.)
32. Shortpad 0402 for PR184,PR167,PR79,PR249,PR253,PR92
Shortpad 0603 for PR93
A A
Remove JP1,JP2,JP6,JP8
33. C861,C864 change from 10P to 18P for CRB time issue.
(Page47.)
(Page11)
34. Change PR125 from 1.47k to 1.2K(CS21202FB13). (Page45)
35. Change U1 PN from 5243 to 5245, due to EOL. (Page29)
36. Add R369 and reserve U34 LDO circuit. (Page32)
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet
Date: Sheet
Date: Sheet
ange list
ange list
ange list
Ch
Ch
Ch
5
48 49Tuesday, August 25, 2015
48 49Tuesday, August 25, 2015
48 49Tuesday, August 25, 2015
1A
of
of
of
PART NUMBER: DRAWING BY: REVISON:
4
PROJECT MODEL :
C NO.
DO
1A
1A
ZRY
3
APPRO VED BY:
DATE:
2
1
Page 49
5
4
3
2
1
Mo
del
te
Da
CH
ANGE LIST
37. PR56 and PR216 change from 1ohm to 10ohm , it is fix black screen issue.
38. Shortpad 0402: R202, R553, R127, R142, R144, R151, R156, R123, R243, R233, R631, R691, R223, R635,
R658, R628, R458, R324, R276, R724, R246, R296, R592, R593, R455, R456, R13, R234,
R435, R417, R377, R370, R952, R953, R163, R165, R958, R959, R598, R601, R602, R604,
R949, R950, R960, R954, R955, R956, R792, R821
D D
39. Shortpad 0603: R754, R244, R245, R216, R256, R796, R219, R321, R218, R260, R314, R793, R277, R222,
R217, R303, R302, R257, R220, R753, R328, R330, R259, R221, R297, R752, R109, R474,
C2
40. Shortpad 0805: R25, R16, R17, R164, R214, R310, R951, R610, R948
R14, R445, R810, R805, R824, R825, R396, R367, R368, L22, R429, R430
41. Reserve PR6291 for ISEN2_B and ISEN1B the GT short circuit. (page44)
42. Change USB3 Tx and Rx signal from port1 to port6, it is fix crystal issue. (page9)
43. Follow the change list 42, R991 change to NC and R990 connect to +3V_DEEP_SUS. (page13)
44. PR229 and PR232 change from 10kohm to 11.3kohm for VR thermal alert follow ZRW setting 110 degree.
45. PR125 change from 1.2kohm to 1.47kohm for h/w shut down sensor setting 85 degree.
46. PR56 and PR216 change from 10ohm to 1ohm. Its short turn solution no run to next C2 stage (page44)
1. Shortpad 0402: R565 , R115 , R340 , R619 , R351 , R623 , R707 , R8 , R663 , R177 , R379 , R392 , R397 ,
R331 , R329 , R348 , R400 , R389 , R343 , R341 , R412 , R394 , R338 , R387
2. Shortpad 0603: R369
3. Remove R460 , R457 for touch panel (page29)
4. Unstuff SW2 for cost down (page37)
C C
5. Reserve TPM U44 (page33) and G sensor U10 (page35)
6. PR19 , PR21, PR31 , PR26 , PR216 , PR56 change from 1ohm to 10ohm for balck screen issue (pag43-44)
7. R769 change from 100K to 10K follow TP issue
MV
8. U41.A36 and U41.A37 connect with GND, The reason to GND these pins is to minimize risk from ESD/EMI
B B
A A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Date: Sheet
Date: Sheet
Date: Sheet
ange list
ange list
ange list
Ch
Ch
Ch
5
49 49Tuesday, September 08, 2015
49 49Tuesday, September 08, 2015
49 49Tuesday, September 08, 2015
1A
of
of
of
PART NUMBER: DRAWING BY: REVISON:
4
PROJECT MODEL :
C NO.
DO
1A
1A
ZRY
3
APPRO VED BY:
DATE:
2
1
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