Acer aspire V5-591G Schematic
1
V/+5V S5
+3
PG.39
+1
A A
.05V/+1.5V
PG.40/45
CP
U Core
PG.42~
43
DDR4
PG.41
Cha
rge
PG.38
VGA POWER
47
PG.46~
B B
VC
CGT/VCCSA
PG.44
2
IN
SOD
IMM1
Max. 16GB
STD
SOD
STD
HDD
PG.17
IMM2
Max. 16GB
PG.18
PG.33
3
4
TEL SYSTEM DIAGRAM
PEG
2400MT/s
L
DDR4
Channel A
2400MT/s
DDR4
L
Channel B
SATA2 6GB/s
INTEL
Sky
Lake-H
Processor : Daul / Quad Core
Power : 45 (Watt)
Package : BGA1400
Size : 42 x 28 (mm)
PG.2~8
I
DM
eDP (5.4Gb/s)
DDI
DDI
eD
2
1
5
U
GP
6P-GT
N1
P1
9~P23
P
eD
P Conn.
IT
E6515
PS8
407
P28
P30
TAL 27MHz
X'
P29
6
VR
AM
DDR3
A Conn.
VG
DMI Conn.
H
P24~P27
P29
P3
7
8
01
0
INTEL PCH
US
nx Point
Ly
PCI-E x 1
Port4
LA
N
RTL8111GSH
10/
100/1000
Port3
WLA
COMBO
BT
N
B 2.0
US
PORT7
PG.34PG.31
PCI-E x 4
C C
PG.34
PG.37
FA
SATA0~1 6GB/s
LPC
NROM
G- Sensor
FF SSD
NG
KBC
E IT8987E/BX
IT
LPC Interface
TPM
PAGE 33 NPCT650
SLG3NB3454
L
D D
GreenCLK
25MHz
TPKB
PG.35PG.35 PG.35PG.12
PAGE 33
Power : Watt
Package : FCBGA837
Size : 23 x 23 (mm)
PG.9~
DIO
AU
CO
DEC
AL
P3
5
C255
Speaker
15
PAGE 32
Az
alia
US
PG.32
Dual Digital MIC
B 3.0
PORT1,2
US
PAGE 32
B3-1 & USB3-2
B 2.0
US
B3.0 Ports
Un
X2
PG.36
PORT1,2
iversal HP
We
bcam
PG.29
PORT9
PORT5
DB IO Port
PG.36
P3
2
Ca
rd Reader
To
uch Screen
PG.36
PORT10
PORT8
PG.29
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
1
2
3
4
5
6
7
OCK DIAGRAM
OCK DIAGRAM
OCK DIAGRAM
BL
BL
BL
Date: Sheet of
Date: Sheet of
Date: Sheet of
8
1A
1A
1A
149Monday, September 07, 2015
149Monday, September 07, 2015
149Monday, September 07, 2015
5
4
3
2
1
Host CLK:
Trace length < 11000 MILS
Trace spacing = 15 ,20 MILS, Impendence 90 ohm
K_CPU_BCLKP11
CL
K_CPU_BCLKN11
CL
U_PCI_BCLKP11
D D
H_
PECI (50ohm)
Route on micro strip only
Spacing > 18 mils
Trace Length: 15 inch
CP
U RESET#
C C
HPECI Ra,Ca n eed placement close to EC.
H_PECI11
PC
_PECI37
EC
U_PLTRST#R11
CP
TRST#12,16,19,31,33,34,37
PL
CP
U_PLTRST# (50o hm)
Trace Length: 10~17 inches
R563 13/F_4
02 *47P/50V_4
C8
PROCHOT# (50ohm)
Trace Length <11 inches
THERMTRIP# (50ohm)
Trace Length: 1.1~12 inches
Ra
Ca
PROCHOT#37,38,42
H_
Ch
ange net name_20141203
PM
_SYNC (50ohm)
Trace Length: 1~11.25 inches
R5
41 *1.5K/F_4
R5
42 *750/F_4
_THRMTRIP#5,11,17,18
PM
+V
CCSTPLL
R6
26 1K_4
Rb need placment near PCH
_PECI
EC
07
C8
Cb
47P/50V_4
_THRMTRIP#
PM
Rb
+V
CP
U_PCI_BCLKN11
CP
CL
K_DPLL_NSCCLKP11
K_DPLL_NSCCLKN11
CL
R5
67 499/F_4
Cb need placment near VR
DDR_VTT_CNTL17
PROCPWRGD (50ohm)
Trace Length: 1~11.25 inches
CST_PWRGD16
VC
OCPWRGD10
PR
R553 *SHORT_4
CCSTPLL
+V
SKT
SKT
CCSTPLL
OCC_N_R13
H_
R5
PM
_SYNC11
OCC_N_R
R5
71 49.9/F_4
New CN to PCH pin Y44_20141203
R5
PM_DOWN11
H_
59 20_4
R14 need change to 20ohm
PD
HW
CPU CORE SVID
Layout note: need routing together and ALERT need between CLK and DATA.
B B
A A
OSE TO CPU
CL
PLACE THE PU RESISTORS
H_
CPU_SVIDALRT#
ACE THE PU RESISTORS
PL
CLOSE TO V R
PULL UP IS IN THE VR MODULE
_SVID_CLK_R
VR
OSE TO CPU
CL
PLACE THE PU RESISTORS
CPU_SVIDDAT
H_
R5
45 220/F_4
R540 *SHORT_4
5
CCSTPLL
+V
38
R5
56.2/F_4
55
C7
*0.1U/16V_4
CCSTPLL
+V
5
C8
R5
39
*54.9/F_4
*1000p/50V_4
CCSTPLL
+V
44
R5
100/F_4
SVI
SVI
43 *SHORT_4
R5
D ALERT
VR
_SVID_ALERT# 42
D CLK
SVI
_SVID_CLK 42
VR
D DATA
_SVID_DATA 42
VR
4
VC
CST_PWRGD
R1
17
C4
*0.1u/16V_4
CPU thermal trip
VP_PWR GD42
IM
SKYLAKE Processor (CLK,MISC,JTAG)
AKE_HALO
SKYL
U41E
BCLKP
LKN
BC
I_BCLKP
PC
PCI_BCLKN
CLK24P
CL
K24N
DALERT#
VI
DSCK
VI
DSOUT
VI
OCHOT#
PR
DDR_
VTT_CNTL
VC
CST_PWRGD
PR
OCPWRGD
RE
SET#
PM
_SYNC
_DOWN
PM
PEC
I
ERMTRIP#
TH
OCC#
SKT
PROC_SELECT#
CATERR#
SKL_H_BGA_BGA
CRB is via +1.05V PGVCCST PWRGD
5
20
4
+VCCSTPLL
12
41
3
BGA1440
5
OF 14
U2
1
VC
C
GN
Y
74AUP1G07GW
V
+3
R2
00
*10K_4
PR
PR
PR
PR
PR
OC_TRST#
OC_PREQ#
PR
PROC_PRDY#
G_RCOMP
CF
1
NC
2
A
3
D
VP_PWR GD_3V 10
IM
CFG[0]
G[1]
CF
CFG[2]
G[3]
CF
CFG[4]
CF
G[5]
CFG[6]
CF
G[7]
CFG[8]
CF
G[9]
G[10]
CF
CF
G[11]
G[12]
CF
CF
G[13]
G[14]
CF
G[15]
CF
G[17]
CF
G[16]
CF
G[19]
CF
CF
G[18]
BPM
BPM
BPM
BPM
OC_TDO
OC_TDI
OC_TMS
OC_TCK
#[0]
#[1]
#[2]
#[3]
H_
VR
_SVID_CLK_R
H_CPU_SVIDDAT
PROCHOT#_R
60 *10K_4
R5
80 *100K/F_4
R1
H_
PM_DOWN_R
CCSTPLL
+V
79 60.4/F_4
K_CPU_BCLKP
CL
K_CPU_BCLKN
CL
CP
U_PCI_BCLKP
U_PCI_BCLKN
CP
K_DPLL_NSCCLKP
CL
CL
K_DPLL_NSCCLKN
CPU_SVIDALRT#
VTT_CNTL
DDR_
CST_PWRGD
VC
OCPWRGD
PR
PM_DOWN_R
H_
EC
_PECI
56 *SHORT_4
81 *0_4
R1
CA
R1
78
*1K_4
Shortpad change
to 60.4 ohm. 11/6
U2
NC1VCC
2
A
GND3Y
*74AUP1G07GW
BH31
BH32
BH29
BR30
BT13
BT31
BP35
BM34
BP31
BT34
BR33
SKT
OCC_N
BM30
TERR#
.0V
+1
R2
03
1K_4
VC
2
82 *SHORT_4
R1
B31
A32
D35
C36
E31
D31
H13
J31
BN1
+3
V_S5
C4
0.1u/16V_4
CST_PWRGD_R
5
C4
*0.1u/16V_4
4
BN25
G0
CF
BN27
G1
CF
BN26
CF
G2
BN28
CF
G3
BR20
G4
CF
BM20
G5
CF
BT20
G6
CF
BP20
CF
G7
BR23
CF
G8
BR22
CF
G9
BT23
G10
CF
BT22
G11
CF
BM19
CF
G12
BR19
CFG13
BP19
CF
G14
BT19
G15
CF
BN23
CFG17
BP23
G16
CF
BP22
CF
G18
BN22
G19
CF
BR27
P_BPM0
XD
BT27
P_BPM1
XD
BM31
XD
P_BPM2
BT30
P_BPM3
XD
BT28
P_TDO_CPU
XD
BL32
XD
P_TDI_CPU
BP28
P_TMS_CPU
XD
BR28
P_TRST#_CPU
XD
BP30
P_TRST#
XD
BL30
XD
P_PREQ#
BP27
XD
P_PRDY#
BT25
G_RCOMP
CF
VC
CST_PWRGD_EN_L
IM
VP_PWR GD_3V
+V
PM
_THRMTRIP#
CCSTPLL
R1
*1K_4
+V
2
86
CF
G0 16
CF
G1 16
G2 8,16
CF
G3 8,16
CF
G4 8,16
CF
CF
G5 8,16
CF
G6 8,16
G7 16
CF
G8 16
CF
G9 16
CF
CF
G10 8,16
CF
G11 16
CF
G12 8,16
G13 8,16
CF
G14 16
CF
CF
G15 16
CF
G17 16
G16 16
CF
G18 16
CF
CFG19 16
TP
TP
XD
XD
XD
R300 *0_4
XD
XD
XD
R1
4
3
U5
TC7SH08FU
R9
69 *0_4
CCSTPLL
3
Q2
FDV301N
1
R191
1K_4
2
1 3
Q2
3 MMBT3904 -7-F
2
XD
P_BPM0 16
P_BPM1 16
XD
17
18
CP
U XDP
P_TDO_CPU 16
P_TDI_CPU 16
P_TMS_CPU 16
P_TRST# 15,16
P_PREQ# 15,16
P_PRDY# 15,16
2949.9/F_4
V_S5
+3
C8
12 0.1u/16V_4
2
1
3 5
0
R1
84
1 2
*100K_4
JT
AGX_PCH 10,16
SB#
SU
CST_PWRGD_EN
VC
No
SYS_SHDN# 39,45
02
ocessor pull-up (CPU)
Pr
PROCHOT#
H_
XD
P_TDO_CPU
P_TMS_CPU
XD
P_TDI_CPU
XD
P_PREQ#
XD
P_TRST#_CPU
XD
XD
P_TRST#
SB# 10,16,37,39
SU
CPU VDDQ
Del R2574_20141217
te: please keep plane is enough for VDDQ 2. 8A
66 1K_4
R5
R5
78 51_4
77 *51_4
R5
R5
58 *51_4
R5
72 *51_4
R5
79 *51_4
R5
64 51_4
A
B2
S0->S5 & S0->S3
Power of sequence 1us
SUSB# -> VCCST_PWRGD
R204 *0_4
R2
02 *SHORT_4
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Cu
Cu
Cu
stom
stom
stom
Date: Sheet
Date: Sheet
Date: Sheet
02 -- SKYPAKE 1/20(eDP/DDI)
02 -- SKYPAKE 1/20(eDP/DDI)
02 -- SKYPAKE 1/20(eDP/DDI)
PC
H_PWROK
HW
R2
10K_4
+1
.0V
+1
65 *SHORT_4
R5
R5
70 *0_4
PG
05
.2VSUS
03 0.1U/16V_4
C4
C4
02 *0.1U/16V_4
1
Pl
PC
HW
acement close to CPU.
+1
.0V
CCSTPLL
+V
H_PWROK 10,37
PG 10,37
1A
1A
1A
of
of
of
249Monday, September 07, 2015
249Monday, September 07, 2015
249Monday, September 07, 2015
5
PEG_RX1519
_RX#1519
PEG
_RX1419
PEG
_RX#1419
PEG
PEG
_RX1319
_RX#1319
D D
Lane Reversed
C C
dGPU PEG*16
PEG
_RCOMP
Trace length < 400 MILS
Trace width = 12 MILS
Trace spacing = 15 MILS
DM
I
PEG
PEG
_RX1219
PEG
_RX#1219
PEG
_RX1119
PEG_RX#1119
_RX1019
PEG
_RX#1019
PEG
_RX919
PEG
PEG
_RX#919
PEG
_RX819
PEG
_RX#819
PEG_RX719
_RX#719
PEG
_RX619
PEG
_RX#619
PEG
PEG
_RX519
PEG
_RX#519
PEG
_RX419
PEG
_RX#419
_RX319
PEG
PEG_RX#319
_RX219
PEG
_RX#219
PEG
_RX119
PEG
PEG
_RX#119
PEG
_RX019
PEG_RX#019
CCIO
+V
DM
I_RXP09
DM
I_RXN09
DM
I_RXP19
DMI_RXN19
I_RXP29
DM
I_RXN29
DM
I_RXP39
DM
DM
I_RXN39
4
SKYLAKE Processor (DMI,PEG,FDI)
E25
D25
E24
F24
E23
D23
E22
F22
E21
D21
E20
F20
E19
D19
E18
F18
D17
E17
F16
E16
D15
E15
F14
E14
D13
E13
F12
E12
D11
E11
F10
E10
PEG
R1
94 24.9/F_4
_COMP
G2
D8
E8
E6
F6
D5
E5
J8
J9
PEG
PEG
PEG
PEG
PEG
PEG_RXN[2]
PEG_RXP[3]
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG
PEG_RXN[10]
PEG_RXP[11]
PEG
PEG
PEG
PEG
PEG
PEG_RXP[14]
PEG
PEG
PEG
PEG
DM
DMI_RXN[0]
DM
DM
DM
DM
DM
DM
SKYL
U41C
_RXP[0]
_RXN[0]
_RXP[1]
_RXN[1]
_RXP[2]
_RXN[3]
_RXP[4]
_RXN[4]
_RXP[5]
_RXN[5]
_RXP[6]
_RXN[6]
_RXP[7]
_RXN[7]
_RXP[8]
_RXN[8]
_RXP[9]
_RXN[9]
_RXP[10]
_RXN[11]
_RXP[12]
_RXN[12]
_RXP[13]
_RXN[13]
_RXN[14]
_RXP[15]
_RXN[15]
_RCOMP
I_RXP[0]
I_RXP[1]
I_RXN[1]
I_RXP[2]
I_RXN[2]
I_RXP[3]
I_RXN[3]
SKL_H_BGA_BGA
BGA1440
AKE_HALO
3
OF 14
_TXP[0]
PEG
_TXN[0]
PEG
_TXP[1]
PEG
PEG
_TXN[1]
PEG
_TXP[2]
PEG_TXN[2]
PEG_TXP[3]
_TXN[3]
PEG
_TXP[4]
PEG
_TXN[4]
PEG
PEG
_TXP[5]
PEG
_TXN[5]
PEG
_TXP[6]
PEG
_TXN[6]
_TXP[7]
PEG
_TXN[7]
PEG
_TXP[8]
PEG
_TXN[8]
PEG
PEG
_TXP[9]
PEG
_TXN[9]
PEG
_TXP[10]
PEG_TXN[10]
PEG_TXP[11]
_TXN[11]
PEG
_TXP[12]
PEG
PEG
_TXN[12]
PEG
_TXP[13]
PEG
_TXN[13]
PEG_TXP[14]
PEG
_TXN[14]
_TXP[15]
PEG
_TXN[15]
PEG
DM
I_TXP[0]
DMI_TXN[0]
I_TXP[1]
DM
I_TXN[1]
DM
I_TXP[2]
DM
DM
I_TXN[2]
DM
I_TXP[3]
DM
I_TXN[3]
B25
A25
B24
C24
B23
A23
B22
C22
B21
A21
B20
C20
B19
A19
B18
C18
A17
B17
C16
B16
A15
B15
C14
B14
A13
B13
C12
B12
A11
B11
C10
B10
B8
A8
C6
B6
B5
A5
D4
B4
C_
PEG_TX15
C_
PEG_TX#15
C_
PEG_TX14
C_PEG_TX#14
PEG_TX13
C_
PEG_TX#13
C_
PEG_TX12
C_
C_
PEG_TX#12
C_
PEG_TX11
C_
PEG_TX#11
C_PEG_TX10
PEG_TX#10
C_
PEG_TX9
C_
PEG_TX#9
C_
C_
PEG_TX8
C_
PEG_TX#8
C_
PEG_TX7
C_
PEG_TX#7
PEG_TX6
C_
C_PEG_TX#6
PEG_TX5
C_
PEG_TX#5
C_
PEG_TX4
C_
C_
PEG_TX#4
C_
PEG_TX3
C_PEG_TX#3
C_PEG_TX2
PEG_TX#2
C_
PEG_TX1
C_
PEG_TX#1
C_
C_
PEG_TX0
C_
PEG_TX#0
3
194 EV@0.22u/10V_4
C1
C1
195 EV@0.22u/10V_4
C1
200 EV@0.22u/10V_4
C1
198 EV@0.22u/10V_4
C1197 EV@0.22u/10V_4
196 EV@0.22u/10V_4
C1
201 EV@0.22u/10V_4
C1
199 EV@0.22u/10V_4
C1
C1
202 EV@0.22u/10V_4
C1
203 EV@0.22u/10V_4
C1
208 EV@0.22u/10V_4
C1
206 EV@0.22u/10V_4
205 EV@0.22u/10V_4
C1
C1204 EV@0.22u/10V_4
209 EV@0.22u/10V_4
C1
207 EV@0.22u/10V_4
C1
13 EV@0.22u/10V_ 4
C8
C8
11 EV@0.22u/10V_ 4
C8
14 EV@0.22u/10V_ 4
C815 EV@0.22u/10V _4
C817 EV@0.22u/10V _4
16 EV@0.22u/10V_ 4
C8
19 EV@0.22u/10V_ 4
C8
18 EV@0.22u/10V_ 4
C8
C8
22 EV@0.22u/10V_ 4
C8
20 EV@0.22u/10V_ 4
C8
23 EV@0.22u/10V_ 4
C8
25 EV@0.22u/10V_ 4
27 EV@0.22u/10V_ 4
C8
26 EV@0.22u/10V_ 4
C8
28 EV@0.22u/10V_ 4
C8
30 EV@0.22u/10V_ 4
C8
DM
I_TXP0 9
DM
I_TXN0 9
DM
I_TXP1 9
DMI_TXN1 9
I_TXP2 9
DM
I_TXN2 9
DM
I_TXP3 9
DM
DM
I_TXN3 9
PEG_TX15 19
_TX#15 19
PEG
_TX14 19
PEG
_TX#14 19
PEG
PEG
_TX13 19
_TX#13 19
PEG
PEG
_TX12 19
PEG_TX#12 19
PEG
_TX11 19
PEG_TX#11 19
_TX10 19
PEG
_TX#10 19
PEG
_TX9 19
PEG
PEG
_TX#9 19
PEG
_TX8 19
PEG
_TX#8 19
PEG_TX7 19
_TX#7 19
PEG
_TX6 19
PEG
_TX#6 19
PEG
PEG
_TX5 19
PEG
_TX#5 19
PEG
_TX4 19
PEG_TX#4 19
_TX3 19
PEG
PEG_TX#3 19
_TX2 19
PEG
_TX#2 19
PEG
_TX1 19
PEG
PEG
_TX#1 19
PEG
_TX0 19
PEG
_TX#0 19
Lane
Reversed
2
1
03
SKYL
AKE_HALO
U41D
B B
A A
5
HDM
I
CRT
CRT
CRT
CRT
CRT
4
_AUX_C
_AUX#_C
K36
K37
J35
J34
H37
H36
J37
J38
D27
E27
H34
H33
F37
G38
F34
F35
E37
E36
F26
E26
C34
D34
B36
B34
F33
E33
C33
B33
A27
B27
DDI1_TXP[0]
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI2_AUXN
DDI3_TXP[0]
DDI
DDI
DDI
DDI
DDI
DDI
DDI
DDI3_AUXP
DDI
_D2
IN
_D230
IN
IN
_D2#30
IN
IN_D130
_D1#30
IN
IN_D030
IN
_D0#30
IN
_CLK30
_CLK#30
IN
_AUXP28
_AUXN28
_D2#
_D1
IN
_D1#
IN
_D0
IN
_D0#
IN
IN_CLK
IN
_CLK#
_TXP028
CRT
_TXN028
CRT
_TXP128
CRT
CRT_TXN128
R998*short_4
R9
99*short_4
1_TXN[0]
1_TXP[1]
1_TXN[1]
1_TXP[2]
1_TXN[2]
1_TXP[3]
1_TXN[3]
1_AUXP
1_AUXN
2_TXP[0]
2_TXN[0]
2_TXP[1]
2_TXN[1]
2_TXP[2]
2_TXN[2]
2_TXP[3]
2_TXN[3]
2_AUXP
3_TXN[0]
3_TXP[1]
3_TXN[1]
3_TXP[2]
3_TXN[2]
3_TXP[3]
3_TXN[3]
3_AUXN
SKL_H_BGA_BGA
BGA1440
4 OF 14
PR
EDP_TXP[0]
ED
P_TXN[0]
ED
P_TXP[1]
P_TXN[1]
ED
ED
P_TXN[2]
P_TXP[2]
ED
ED
P_TXN[3]
P_TXP[3]
ED
P_AUXP
ED
P_AUXN
ED
ED
P_DISP_UTIL
ED
P_RCOMP
OC_AUDIO_CLK
PR
PROC_AUDIO_SDI
OC_AUDIO_SDO
D29
E29
F28
E28
B29
A29
B28
C28
C26
B26
A33
D37
G27
G25
G29
eDP
P_TXP0 29
ED
P_TXN0 29
ED
EDP_TXP1 29
P_TXN1 29
ED
EDP_TXN2 29
ED
P_TXP2 29
ED
P_TXN3 29
P_TXP3 29
ED
P_AUXP 29
ED
ED
P_AUXN 29
ED
P_DISP_UTIL
EDP_RCOMP
DP
P_RCOMP
eD
Trace length < 100 Mils
Trace Width 20 Mils Trace Spacing 25 Mils
D_AZACPU_SO
AU
TP87
1624.9/F_4
R1
+V
& PEG Compensation
R1
27 *SHORT_4
R1
26 20_4
CCIO 6 ,16,38,40,42, 45
+V
.0V 2,5,6,10,1 6,40,45
+1
3
CCIO
D_AZACPU_SCLK 10
AU
AU
D_AZACPU_SDO 10
D_AZACPU_SDI 10
AU
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
2
B 1/5 (PCIE&DMI&FDI)
B 1/5 (PCIE&DMI&FDI)
B 1/5 (PCIE&DMI&FDI)
SN
SN
SN
Date: Sheet
Date: Sheet
Date: Sheet
1
1A
1A
1A
349Tuesday, Augu st 25, 2015
349Tuesday, Augu st 25, 2015
349Tuesday, Augu st 25, 2015
of
of
of
5
4
3
2
1
SK
YLAKE Processor (DDR3)
CHANNEL B
SKYLAKE_HALO
BGA1440
DDR1
_RAS#/DDR1_CAB[3]/DDR1_MA[16]
DDR1
_WE#/DDR1_CAB[2]/DDR1_MA[14]
DDR1
_CAS#/DDR1_CAB[1]/DDR1_MA[15]
_BA[0]/DDR1_CAB[4]/DDR1_BA[0]
DDR1
DDR1
_BA[1]/DDR1_CAB[6]/DDR1_BA[1]
_BA[2]/DDR1_CAA[5]/DDR1_BG[0]
DDR1
_MA[0]/DDR1_CAB[9]/DDR1_MA[0]
DDR1
DDR1_MA[1]/DDR1_CAB[8]/DDR1_MA[1]
_MA[2]/DDR1_CAB[5]/DDR1_MA[2]
DDR1
DDR1_MA[5]/DDR1_CAA[0]/DDR1_MA[5]
DDR1
_MA[6]/DDR1_CAA[2]/DDR1_MA[6]
DDR1_MA[7]/DDR1_CAA[4]/DDR1_MA[7]
DDR1
_MA[8]/DDR1_CAA[3]/DDR1_MA[8]
DDR1_MA[9]/DDR1_CAA[1]/DDR1_MA[9]
DDR1
_MA[10]/DDR1_CAB[7]/DDR1_MA[10]
_MA[11]/DDR1_CAA[7]/DDR1_MA[11]
DDR1
DDR1
_MA[12]/DDR1_CAA[6]/DDR1_MA[12]
_MA[13]/DDR1_CAB[0]/DDR1_MA[13]
DDR1
DDR1
_MA[14]/DDR1_CAA[9]/DDR1_BG[1]
_MA[15]/DDR1_CAA[8]/DDR1_ACT#
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
DDR1
OF 14
2
DDR1_CKP[0]
_CKN[0]
DDR1
DDR1_CKN[1]
DDR1
_CKP[1]
DDR1_CLKP[2]
DDR1
_CLKN[2]
DDR1_CLKP[3]
DDR1
_CLKN[3]
DDR1
_CKE[0]
_CKE[1]
DDR1
DDR1
_CKE[2]
_CKE[3]
DDR1
_CS#[0]
DDR1
_CS#[1]
DDR1
_CS#[2]
DDR1
_CS#[3]
DDR1
_ODT[0]
DDR1
DDR1
_ODT[1]
_ODT[2]
DDR1
DDR1
_ODT[3]
DDR1_MA[3]
_MA[4]
DDR1
_PAR
DDR1
_ALERT#
DDR1
_DQSN[0]/DDR0_DQSN[2]
_DQSN[1]/DDR0_DQSN[3]
_DQSN[2]/DDR0_DQSN[6]
_DQSN[3]/DDR0_DQSN[7]
_DQSN[4]/DDR1_DQSN[2]
_DQSN[5]/DDR1_DQSN[3]
DDR1
_DQSN[6]
DDR1
_DQSP[0]/DDR0_DQSP[2]
_DQSP[1]/DDR0_DQSP[3]
_DQSP[2]/DDR0_DQSP[6]
_DQSP[3]/DDR0_DQSP[7]
_DQSP[4]/DDR1_DQSP[2]
_DQSP[5]/DDR1_DQSP[3]
_DQSN[7]
DDR1_DQSP[6]
_DQSP[7]
DDR1
_DQSP[8]
DDR1
DDR1_DQSN[8]
DDR_VREF_CA
DDR0_VREF_DQ
DDR1_VREF_DQ
AM9
AN9
AM8
AM7
AM11
AM10
AJ10
AJ11
AT8
AT10
AT7
AT11
AF11
AE7
AF10
AE10
AF7
AE8
AE9
AE11
AH10
AH11
AF8
AH8
AH9
AR9
AJ9
AK6
AK5
AL5
AL6
AM6
AN7
AN10
AN8
AR11
AH7
AN11
AR10
AF9
AR7
AT9
AJ7
AR8
BP9
BL9
BG9
BC9
AC9
W9
R9
M9
BR9
BJ9
BF9
BB9
AA9
V9
P9
L9
AW9
AY9
BN13
BP13
BR13
B_BA#0
M_
M_
B_BA#1
B_BG#0
M_
M_
B_A0
M_
B_A1
M_
B_A2
B_A3
M_
B_A4
M_
M_
B_A5
M_
B_A6
M_
B_A7
B_A8
M_
B_A9
M_
M_B_A10
M_
B_A11
M_
B_A12
B_A13
M_
B_BG#1
M_
B_ACT#
M_
M_
B_PARITY
B_ALERT#
M_
M_
B_DQSN0
M_
B_DQSN1
M_
B_DQSN2
B_DQSN3
M_
B_DQSN4
M_
M_
B_DQSN5
M_
B_DQSN6
B_DQSN7
M_
B_DQSP0
M_
M_
B_DQSP1
M_
B_DQSP2
M_
B_DQSP3
M_
B_DQSP4
B_DQSP5
M_
M_
B_DQSP6
M_B_DQSP7
_VREF
SM
SM
DDR_VREF_DQ0_M3
DDR_VREF_DQ1_M3
SM
M_
M_
M_
M_
M_
M_
B_RAS# 18
M_
B_WE# 18
M_
B_CAS# 18
M_
M_
M_
R1
46*1K _4
R154*1K _4
M_
M_B_CS#1 18
M_
M_
M_
B_CLKP0 18
B_CLKN0 18
B_CLKN1 18
B_CLKP1 18
B_CKE0 18
B_CKE1 18
B_CS#0 18
B_ODT0_CPU 18
B_ODT1_CPU 18
B_BA#0 18
M_
B_BA#1 18
M_
M_
B_BG#0 18
B_A[13:0] 18
M_
B_BG#1 18
M_
B_ACT# 18
B_PARITY 18
M_
B_ALERT# 18
M_
B_DQSN[7:0] 18
B_DQSP[7:0] 18
M_
AKE_HALO
A_DQ[63:0]17
D D
C C
B B
M_
VD_V10 must be grounded
RS
A_DQ0
M_
A_DQ1
M_
A_DQ2
M_
M_
A_DQ3
M_
A_DQ4
M_
A_DQ5
A_DQ6
M_
A_DQ7
M_
M_
A_DQ8
M_A_DQ9
M_
A_DQ10
A_DQ11
M_
A_DQ12
M_
M_A_DQ13
A_DQ14
M_
M_
A_DQ15
A_DQ16
M_
A_DQ17
M_
A_DQ18
M_
A_DQ19
M_
M_
A_DQ20
A_DQ21
M_
A_DQ22
M_
A_DQ23
M_
A_DQ24
M_
M_
A_DQ25
A_DQ26
M_
M_
A_DQ27
A_DQ28
M_
A_DQ29
M_
M_
A_DQ30
M_
A_DQ31
M_
A_DQ32
A_DQ33
M_
A_DQ34
M_
M_
A_DQ35
M_
A_DQ36
M_
A_DQ37
A_DQ38
M_
A_DQ39
M_
M_A_DQ40
M_
A_DQ41
M_
A_DQ42
A_DQ43
M_
A_DQ44
M_
A_DQ45
M_
M_
A_DQ46
M_
A_DQ47
A_DQ48
M_
M_
A_DQ49
A_DQ50
M_
M_
A_DQ51
M_
A_DQ52
M_
A_DQ53
A_DQ54
M_
A_DQ55
M_
M_
A_DQ56
M_
A_DQ57
A_DQ58
M_
M_
A_DQ59
A_DQ60
M_
M_
A_DQ61
M_
A_DQ62
M_
A_DQ63
U41A
BR6
DDR0_DQ[0]
BT6
DDR0
_DQ[1]
BP3
DDR0_DQ[2]
BR3
DDR0
_DQ[3]
BN5
DDR0_DQ[4]
BP6
DDR0
_DQ[5]
BP2
_DQ[6]
DDR0
BN3
DDR0
_DQ[7]
BL4
_DQ[8]
DDR0
BL5
DDR0
_DQ[9]
BL2
_DQ[10]
DDR0
BM1
_DQ[11]
DDR0
BK4
_DQ[12]
DDR0
BK5
_DQ[13]
DDR0
BK1
_DQ[14]
DDR0
BK2
_DQ[15]
DDR0
BG4
DDR0
_DQ[16]/DDR0_DQ[32]
BG5
_DQ[17]/DDR0_DQ[33]
DDR0
BF4
DDR0
_DQ[18]/DDR0_DQ[34]
BF5
_DQ[19]/DDR0_DQ[35]
DDR0
BG2
DDR0
_DQ[20]/DDR0_DQ[36]
BG1
DDR0
_DQ[21]/DDR0_DQ[37]
BF1
DDR0
_DQ[22]/DDR0_DQ[38]
BF2
DDR0
_DQ[23]/DDR0_DQ[39]
BD2
DDR0
_DQ[24]/DDR0_DQ[40]
BD1
DDR0
_DQ[25]/DDR0_DQ[41]
BC4
_DQ[26]/DDR0_DQ[42]
DDR0
BC5
DDR0
_DQ[27]/DDR0_DQ[43]
BD5
_DQ[28]/DDR0_DQ[44]
DDR0
BD4
DDR0
_DQ[29]/DDR0_DQ[45]
BC1
_DQ[30]/DDR0_DQ[46]
DDR0
BC2
DDR0_DQ[31]/DDR0_DQ[47]
AB1
_DQ[32]/DDR1_DQ[0]
DDR0
AB2
DDR0_DQ[33]/DDR1_DQ[1]
AA4
_DQ[34]/DDR1_DQ[2]
DDR0
AA5
DDR0_DQ[35]/DDR1_DQ[3]
AB5
DDR0
_DQ[36]/DDR1_DQ[4]
AB4
DDR0_DQ[37]/DDR1_DQ[5]
AA2
DDR0
_DQ[38]/DDR1_DQ[6]
AA1
DDR0_DQ[39]/DDR1_DQ[7]
V5
DDR0
_DQ[40]/DDR1_DQ[8]
V2
_DQ[41]/DDR1_DQ[9]
DDR0
U1
DDR0
_DQ[42]/DDR1_DQ[10]
U2
_DQ[43]/DDR1_DQ[11]
DDR0
V1
DDR0
_DQ[44]/DDR1_DQ[12]
V4
_DQ[45]/DDR1_DQ[13]
DDR0
U5
_DQ[46]/DDR1_DQ[14]
DDR0
U4
_DQ[47]/DDR1_DQ[15]
DDR0
R2
_DQ[48]/DDR1_DQ[32]
DDR0
P5
_DQ[49]/DDR1_DQ[33]
DDR0
R4
_DQ[50]/DDR1_DQ[34]
DDR0
P4
DDR0
_DQ[51]/DDR1_DQ[35]
R5
_DQ[52]/DDR1_DQ[36]
DDR0
P2
DDR0
_DQ[53]/DDR1_DQ[37]
R1
_DQ[54]/DDR1_DQ[38]
DDR0
P1
DDR0
_DQ[55]/DDR1_DQ[39]
M4
DDR0
_DQ[56]/DDR1_DQ[40]
M1
DDR0
_DQ[57]/DDR1_DQ[41]
L4
DDR0
_DQ[58]/DDR1_DQ[42]
L2
DDR0
_DQ[59]/DDR1_DQ[43]
M5
DDR0
_DQ[60]/DDR1_DQ[44]
M2
_DQ[61]/DDR1_DQ[45]
DDR0
L5
DDR0
_DQ[62]/DDR1_DQ[46]
L1
_DQ[63]/DDR1_DQ[47]
DDR0
BA2
_ECC[0]
DDR0
BA1
DDR0_ECC[1]
AY4
_ECC[2]
DDR0
AY5
DDR0_ECC[3]
BA5
_ECC[4]
DDR0
BA4
DDR0_ECC[5]
AY1
DDR0
_ECC[6]
AY2
DDR0_ECC[7]
DDR CHANNEL A
SKL_H_BGA_BGA
SKYL
BGA1440
DDR0
_BA[0]/DDR0_CAB[4]/DDR0_BA[0]
DDR0
_BA[1]/DDR0_CAB[6]/DDR0_BA[1]
_BA[2]/DDR0_CAA[5]/DDR0_BG[0]
DDR0
_RAS#/DDR0_CAB[3]/DDR0_MA[16]
DDR0
DDR0
_WE#/DDR0_CAB[2]/DDR0_MA[14]
_CAS#/DDR0_CAB[1]/DDR0_MA[15]
DDR0
_MA[0]/DDR0_CAB[9]/DDR0_MA[0]
DDR0
DDR0_MA[1]/DDR0_CAB[8]/DDR0_MA[1]
_MA[2]/DDR0_CAB[5]/DDR0_MA[2]
DDR0
DDR0_MA[5]/DDR0_CAA[0]/DDR0_MA[5]
DDR0
_MA[6]/DDR0_CAA[2]/DDR0_MA[6]
DDR0_MA[7]/DDR0_CAA[4]/DDR0_MA[7]
DDR0
_MA[8]/DDR0_CAA[3]/DDR0_MA[8]
_MA[9]/DDR0_CAA[1]/DDR0_MA[9]
DDR0
DDR0
_MA[10]/DDR0_CAB[7]/DDR0_MA[10]
_MA[11]/DDR0_CAA[7]/DDR0_MA[11]
DDR0
DDR0
_MA[12]/DDR0_CAA[6]/DDR0_MA[12]
_MA[13]/DDR0_CAB[0]/DDR0_MA[13]
DDR0
_MA[14]/DDR0_CAA[9]/DDR0_BG[1]
DDR0
_MA[15]/DDR0_CAA[8]/DDR0_ACT#
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0
DDR0_DQSP[4]/DDR1_DQSP[0]
DDR0
DDR0_DQSP[6]/DDR1_DQSP[4]
DDR0
OF 14
1
DDR0_CKP[0]
DDR0
_CKN[0]
DDR0_CKP[1]
DDR0
_CKN[1]
DDR0_CLKP[2]
DDR0
_CLKN[2]
_CLKP[3]
DDR0
DDR0
_CLKN[3]
DDR0
_CKE[0]
_CKE[1]
DDR0
_CKE[2]
DDR0
_CKE[3]
DDR0
_CS#[0]
DDR0
_CS#[1]
DDR0
DDR0
_CS#[2]
_CS#[3]
DDR0
_ODT[0]
DDR0
DDR0
_ODT[1]
DDR0
_ODT[2]
DDR0
_ODT[3]
DDR0_MA[3]
DDR0
_MA[4]
_PAR
DDR0
_ALERT#
DDR0
DDR0
_DQSN[0]
_DQSN[1]
DDR0
_DQSN[2]/DDR0_DQSN[4]
_DQSN[3]/DDR0_DQSN[5]
_DQSN[4]/DDR1_DQSN[0]
_DQSN[5]/DDR1_DQSN[1]
_DQSN[6]/DDR1_DQSN[4]
_DQSN[7]/DDR1_DQSN[5]
DDR0
_DQSP[0]
_DQSP[1]
DDR0
_DQSP[2]/DDR0_DQSP[4]
_DQSP[3]/DDR0_DQSP[5]
_DQSP[5]/DDR1_DQSP[1]
_DQSP[7]/DDR1_DQSP[5]
DDR0
_DQSP[8]
DDR0_DQSN[8]
AG1
AG2
AK2
AK1
AL3
AK3
AL2
AL1
AT1
AT2
AT3
AT5
AD5
AE2
AD2
AE5
AD3
AE4
AE1
AD4
AH5
AH1
AU1
AH4
AG4
AD1
AH3
AP4
AN4
AP5
AP2
AP1
AP3
AN1
AN3
AT4
AH2
AN2
AU4
AE3
AU2
AU3
AG3
AU5
BR5
BL3
BG3
BD3
AA3
U3
P3
L3
BP5
BK3
BF3
BC3
AB3
V3
R3
M3
AY3
BA3
A_BA#0
M_
M_
A_BA#1
A_BG#0
M_
M_
A_A0
A_A1
M_
A_A2
M_
M_
A_A3
M_
A_A4
M_
A_A5
A_A6
M_
A_A7
M_
M_A_A8
M_
A_A9
M_
A_A10
A_A11
M_
A_A12
M_
A_A13
M_
M_
A_BG#1
M_
A_ACT#
M_
A_PARITY
A_ALERT#
M_
M_
A_DQSN0
A_DQSN1
M_
A_DQSN2
M_
M_
A_DQSN3
M_
A_DQSN4
A_DQSN5
M_
M_
A_DQSN6
A_DQSN7
M_
M_
A_DQSP0
M_
A_DQSP1
M_
A_DQSP2
A_DQSP3
M_
M_
A_DQSP4
M_A_DQSP5
M_
A_DQSP6
M_
A_DQSP7
B_DQ[63:0]18
A_CLKP0 17
M_
A_CLKN0 17
M_
A_CLKP1 17
M_
M_
A_CLKN1 17
M_A_CKE0 17
M_
A_CKE1 17
A_CS#0 17
M_
M_
A_CS#1 17
A_ODT0_CPU 17
M_
M_
A_ODT1_CPU 17
A_BA#0 17
M_
A_BA#1 17
M_
A_BG#0 17
M_
A_RAS# 17
M_
A_WE# 17
M_
M_
A_CAS# 17
M_
A_A[13:0] 17
A_BG#1 17
M_
A_ACT# 17
M_
M_
A_PARITY 17
M_
A_ALERT# 17
M_
A_DQSN[7:0] 17
A_DQSP[7:0] 17
M_
R1
R1
R1
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_B_DQ11
M_
M_
M_
M_B_DQ15
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_B_DQ42
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
M_
SM
95121/F_4
SM
9375/F_4
SM
92100/F_4
B_DQ0
B_DQ1
B_DQ2
B_DQ3
B_DQ4
B_DQ5
B_DQ6
B_DQ7
B_DQ8
B_DQ9
B_DQ10
B_DQ12
B_DQ13
B_DQ14
B_DQ16
B_DQ17
B_DQ18
B_DQ19
B_DQ20
B_DQ21
B_DQ22
B_DQ23
B_DQ24
B_DQ25
B_DQ26
B_DQ27
B_DQ28
B_DQ29
B_DQ30
B_DQ31
B_DQ32
B_DQ33
B_DQ34
B_DQ35
B_DQ36
B_DQ37
B_DQ38
B_DQ39
B_DQ40
B_DQ41
B_DQ43
B_DQ44
B_DQ45
B_DQ46
B_DQ47
B_DQ48
B_DQ49
B_DQ50
B_DQ51
B_DQ52
B_DQ53
B_DQ54
B_DQ55
B_DQ56
B_DQ57
B_DQ58
B_DQ59
B_DQ60
B_DQ61
B_DQ62
B_DQ63
_RCOMP_0
_RCOMP_1
_RCOMP_2
U41B
BT11
DDR1_DQ[0]/DDR0_DQ[16]
BR11
_DQ[1]/DDR0_DQ[17]
DDR1
BT8
DDR1_DQ[2]/DDR0_DQ[18]
BR8
DDR1
_DQ[3]/DDR0_DQ[19]
BP11
DDR1_DQ[4]/DDR0_DQ[20]
BN11
DDR1
_DQ[5]/DDR0_DQ[21]
BP8
DDR1_DQ[6]/DDR0_DQ[22]
BN8
DDR1
_DQ[7]/DDR0_DQ[23]
BL12
_DQ[8]/DDR0_DQ[24]
DDR1
BL11
DDR1
_DQ[9]/DDR0_DQ[25]
BL8
_DQ[10]/DDR0_DQ[26]
DDR1
BJ8
DDR1
_DQ[11]/DDR0_DQ[27]
BJ11
_DQ[12]/DDR0_DQ[28]
DDR1
BJ10
_DQ[13]/DDR0_DQ[29]
DDR1
BL7
_DQ[14]/DDR0_DQ[30]
DDR1
BJ7
_DQ[15]/DDR0_DQ[31]
DDR1
BG11
_DQ[16]/DDR0_DQ[48]
DDR1
BG10
_DQ[17]/DDR0_DQ[49]
DDR1
BG8
DDR1
_DQ[18]/DDR0_DQ[50]
BF8
_DQ[19]/DDR0_DQ[51]
DDR1
BF11
DDR1
_DQ[20]/DDR0_DQ[52]
BF10
_DQ[21]/DDR0_DQ[53]
DDR1
BG7
DDR1
_DQ[22]/DDR0_DQ[54]
BF7
DDR1
_DQ[23]/DDR0_DQ[55]
BB11
DDR1
_DQ[24]/DDR0_DQ[56]
BC11
DDR1
_DQ[25]/DDR0_DQ[57]
BB8
DDR1
_DQ[26]/DDR0_DQ[58]
BC8
DDR1
_DQ[27]/DDR0_DQ[59]
BC10
_DQ[28]/DDR0_DQ[60]
DDR1
BB10
DDR1
_DQ[29]/DDR0_DQ[61]
BC7
_DQ[30]/DDR0_DQ[62]
DDR1
BB7
DDR1
_DQ[31]/DDR0_DQ[63]
AA11
_DQ[32]/DDR1_DQ[16]
DDR1
AA10
DDR1_DQ[33]/DDR1_DQ[17]
AC11
_DQ[34]/DDR1_DQ[18]
DDR1
AC10
DDR1_DQ[35]/DDR1_DQ[19]
AA7
_DQ[36]/DDR1_DQ[20]
DDR1
AA8
DDR1_DQ[37]/DDR1_DQ[21]
AC8
DDR1
_DQ[38]/DDR1_DQ[22]
AC7
DDR1_DQ[39]/DDR1_DQ[23]
W8
DDR1
_DQ[40]/DDR1_DQ[24]
W7
DDR1_DQ[41]/DDR1_DQ[25]
V10
DDR1
_DQ[42]/DDR1_DQ[26]
V11
_DQ[43]/DDR1_DQ[27]
DDR1
W11
DDR1
_DQ[44]/DDR1_DQ[28]
W10
_DQ[45]/DDR1_DQ[29]
DDR1
V7
DDR1
_DQ[46]/DDR1_DQ[30]
V8
_DQ[47]/DDR1_DQ[31]
DDR1
R11
_DQ[48]
DDR1
P11
_DQ[49]
DDR1
P7
_DQ[50]
DDR1
R8
_DQ[51]
DDR1
R10
_DQ[52]
DDR1
P10
DDR1
_DQ[53]
R7
_DQ[54]
DDR1
P8
DDR1
_DQ[55]
L11
_DQ[56]
DDR1
M11
DDR1
_DQ[57]
L7
DDR1
_DQ[58]
M8
DDR1
_DQ[59]
L10
DDR1
_DQ[60]
M10
DDR1
_DQ[61]
M7
DDR1
_DQ[62]
L8
_DQ[63]
DDR1
AW11
_ECC[0]
DDR1
AY11
DDR1
_ECC[1]
AY8
_ECC[2]
DDR1
AW8
DDR1_ECC[3]
AY10
_ECC[4]
DDR1
AW10
DDR1_ECC[5]
AY7
_ECC[6]
DDR1
AW7
DDR1_ECC[7]
G1
DDR_RCOMP[0]
H1
DDR_RCOMP[1]
J2
DDR_RCOMP[2]
SKL_H_BGA_BGA
DDR
04
_VREF 17
SM
TP
74
DDR_VREF_DQ1_M3 18
SM
A A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Cu
Cu
Cu
stom
stom
stom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
B 2/5 (DDR3 I/F)
B 2/5 (DDR3 I/F)
B 2/5 (DDR3 I/F)
SN
SN
SN
1
1A
1A
1A
of
of
of
449Tuesday, August 25, 2015
449Tuesday, August 25, 2015
449Tuesday, August 25, 2015
5
4
3
2
1
SKYLAKE Processor (POWER)
.5V 14,30,32,34,45
+1
low SKL H EDS page 133 to 45W(GT4+OPC): +VCCGT=104A/12A (GTx)
Fol
Follow SKL H EDS page 133 to 45W(GT2): +VCCGT=55A
Follow SKL H DG page 574 to place Cap
D D
+
C C
B B
22uF x 14, 10uF x 35, 1uF x 68
C3
C2
00
197
PC
330u/2V_7343
22U/6.3V_6
C7
52
22U/6.3V_6
C7
62
22U/6.3V_6
94
C1
10U/6.3V_6
26
C3
10U/6.3V_6
27
C3
10U/6.3V_6
C3
61
1U/6.3V_4
C3
83
1U/6.3V_4
C2
02
1U/6.3V_4
22U/6.3V_6
C7
22U/6.3V_6
C7
22U/6.3V_6
C7
10U/6.3V_6
C2
10U/6.3V_6
C3
10U/6.3V_6
C2
1U/6.3V_4
C2
1U/6.3V_4
C2
1U/6.3V_4
C3
C1
10
22U/6.3V_6
C7
53
22U/6.3V_6
C2
63
22U/6.3V_6
65
C2
10U/6.3V_6
09
C2
10U/6.3V_6
28
C7
10U/6.3V_6
C2
18
1U/6.3V_4
C1
89
1U/6.3V_4
C7
51
1U/6.3V_4
C3
29
91
22U/6.3V_6
C7
75
50
22U/6.3V_6
C3
24
55
22U/6.3V_6
13
21
C2
10U/6.3V_6
42
07
C3
10U/6.3V_6
64
88
C1
10U/6.3V_6
C3
27
64
1U/6.3V_4
C3
94
93
1U/6.3V_4
C2
91
52
1U/6.3V_4
07
22U/6.3V_6
C7
51
22U/6.3V_6
C3
52
22U/6.3V_6
76
C7
10U/6.3V_6
39
C3
10U/6.3V_6
74
C7
10U/6.3V_6
C2
16
1U/6.3V_4
C3
63
1U/6.3V_4
C3
51
1U/6.3V_4
C1
95
22U/6.3V_6
C3
08
22U/6.3V_6
C3
53
22U/6.3V_6
73
C7
10U/6.3V_6
40
C3
10U/6.3V_6
60
C7
10U/6.3V_6
41
C7
47U/6.3VS_8
C3
17
1U/6.3VS_4
C3
81
1U/6.3VS_4
C7
82
1U/6.3VS_4
+V
CCGT7,42,44
47U/6.3VS_8
C7
49
22U/6.3V_6
C3
09
22U/6.3V_6
C3
54
22U/6.3V_6
25
C2
10U/6.3V_6
41
C3
10U/6.3V_6
72
C7
10U/6.3V_6
42
C7
C2
29
1U/6.3V_4
C7
83
1U/6.3V_4
C2
79
1U/6.3V_4
+V
CCGT
AJ29
AJ30
AJ31
AJ32
AJ33
AJ34
AJ35
AJ36
AK31
AK32
AK33
AK34
AK35
AK36
AK37
AK38
AL13
AL29
AL30
AL31
AL32
AL35
AL36
AL37
AL38
AM13
AM14
AM29
AM30
AM31
AM32
AM33
AM34
AM35
AM36
AN13
AN14
AN31
AN32
AN33
AN34
AN35
AN36
AN37
AN38
AP13
AP14
AP29
AP30
AP31
AP32
AP35
AP36
AP37
AP38
AR29
AR30
AR31
AR32
AR33
AR34
AR35
AR36
AT14
AT31
AT32
AT33
AT34
AT35
AT36
AT37
AT38
AU14
AU29
AU30
AU31
AU32
AU35
AU36
AU37
AU38
U41N
CGT
VC
CGT
VC
VCCGT
VCCGT
VC
CGT
VC
CGT
CGT
VC
CGT
VC
CGT
VC
VCCGT
VCCGT
VC
CGT
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VCCGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
VCCGT
VCCGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VCCGT
VCCGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VCCGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
VCCGT
VCCGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VCCGT
VCCGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VCCGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
VCCGT
VCCGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
CGT
VC
VCCGT
VCCGT
VC
CGT
VC
CGT
VC
CGT
CGT
VC
VC
CGT
VCCGT
CGT
VC
CGT
VC
VC
CGT
VC
CGT
SKL_H_BGA_BGA
SKY
LAKE_HALO
BGA1440
14
OF 14
VCCGTX
VCCGTX
VC
CGTX
VC
CGTX
CGTX
VC
CGTX
VC
CGTX
VC
VCCGTX
VCCGTX
VC
CGTX
CGTX
VC
CGTX
VC
CGTX
VC
CGTX
VC
VCCGTX
VC
CGTX
VC
CGTX
VC
CGTX
VC
CGTX
CGTX
VC
VCCGTX
VCCGTX
VC
CGT_SENSE
VSSG
TX_SENSE
T_SENSE
VSSG
VCCGTX_SENSE
AF29
AF30
AF31
AF32
AF33
AF34
AG13
AG14
AG31
AG32
AG33
AG34
AG35
AG36
AH13
AH14
AH29
AH30
AH31
AH32
AJ13
AJ14
AH38
AH35
AH37
AH36
R5
*100/F_4
R5
*100/F_4
4+4e, Support eDRAM Only, GTX 12A
ed c aps.. .
Ne
CCGT
+V
50
VC
CGT_SENSE 42
86
TP
VCCGTSS_SENSE 42
85
TP
49
VPCU
+3
CCGT
+V
C785
C287
1U/6.3V_4
92
C2
1U/6.3V_4
28
C2
1U/6.3V_4
76
C2
1U/6.3V_4
99
C3
1U/6.3V_4
C7
94
1U/6.3V_4
C385
1U/6.3V_4
46
C3
1U/6.3V_4
66
C2
1U/6.3V_4
95
C3
1U/6.3V_4
03
C2
1U/6.3V_4
C3
60
1U/6.3V_4
1U/6.3V_4
32
C3
1U/6.3V_4
74
C2
1U/6.3V_4
93
C7
1U/6.3V_4
26
C2
1U/6.3V_4
C3
62
1U/6.3V_4
+1
.2VSUS 2,6,10,17,18,41
Thrm Protect
IO
R2
15
*16.5K/F_4
RM_MOINTOR
TH
R2
31
*3.3K/F_4
For
75 degree, 1.2 v limit, (HW)
41
R2
1 2
00K_4 NTC
*1
C325
1U/6.3VS_4
54
C2
1U/6.3VS_4
17
C2
1U/6.3VS_4
96
C3
1U/6.3VS_4
78
C2
1U/6.3VS_4
C3
97
1U/6.3VS_4
68
C4
*0.1U/16V_4
C275
1U/6.3V_4
84
C7
1U/6.3V_4
77
C2
1U/6.3V_4
50
C2
1U/6.3V_4
15
C2
1U/6.3V_4
C7
92
1U/6.3V_4
1 2
05
C4
53
*0.1U/16V_4
TH
RM_MOINTOR1 37
C288
1U/6.3VS_4
53
C2
1U/6.3VS_4
92
C1
1U/6.3VS_4
04
C2
1U/6.3VS_4
80
C3
1U/6.3VS_4
C3
82
1U/6.3VS_4
C290
1U/6.3V_4
91
C2
1U/6.3V_4
49
C2
1U/6.3V_4
84
C3
1U/6.3V_4
65
C3
1U/6.3V_4
C3
98
1U/6.3V_4
Local CPU Thermal Sensor
U4
0
B_RUN_CLK10, 16,17,18,35
VC
C Output Decoupli ng Recommendations
A A
5
4
3
SM
SM
B_RUN_DAT10,16,17, 18,35
CPU_THRMTRIP#
R5
55 10K/F_4
+3
V
+1
.0V
PM_THRMTRIP#2,11,17,18
R562*4.7K_4
1 3
*METR3904-G
8
VC
SC
LK
7
DX
SD
A
6
ERT#
DX
AL
4
GN
OV
ERT#
*TMP431ADGKR
2
8
Q3
U_THRMTRIP#
CP
2
C8
06 0.01U/50 V_4
1
C
2
CP
P
3
N
5
D
U_THERMDA
09
C8
2200P/50V_4
CP
U_THERMDC
AL000431014
V
+3
CP
U Thermal Sensor
9
Q3
2
*METR3904-G
1 3
TMP431ADGKR(98h)
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
SNB 3/5 (POWER)
SNB 3/5 (POWER)
SNB 3/5 (POWER)
Date: Sheet
Date: Sheet
Date: Sheet
1
549Monday, S eptember 07, 2015
549Monday, S eptember 07, 2015
549Monday, S eptember 07, 2015
1A
1A
1A
of
of
of
5
4
3
2
1
06
Fol
low SKL H EDS page 135 to 45W(GT2): VCCSA=11.1A (GTx)
D D
+VCCSA42,
44
C1
22U/6.3V_6
C7
10U/6.3V_6
C C
C2
87
10U/6.3V_6
C3
22u/6.3V_6
C7
90
22U/6.3V_6
05
C7
1U/6.3V_4
57
C3
22u/6.3V_6
C3
1U/6.3V_4
88
C7
86
10U/6.3V_6
66
50
73
C2
19
22U/6.3VS_6
C7
78
10U/6.3V_6
C2
08
1U/6.3V_4
18
C3
22U/6.3VS_6
C3
93
1U/6.3V_4
+VCCI
Follow SKL H EDS P136 to 45W: VCCIO
+VCCIO = 0.95V
B B
+VDDQC+VCCSTG+VCCPLL_O
86
73
C3
C2
10U/6.3V_6
+VCCI
O
A A
5
C3
56
*1U/6.3V_ 4
C4
1U/6.3V_4
C3
59
*22U/6.3V _6
01
1U/6.3V_4
C7
89
22U/6.3VS_6
C1
81
10U/6.3V_6
C2
96
1U/6.3V_4
O
31
C3
22U/6.3VS_6
C3
44
10U/6.3V_6
C
00
C4
+VCCSA
J30
K29
K30
K31
K32
K33
K34
K35
L31
L32
L35
L36
L37
L38
M29
M30
M31
M32
M33
M34
M35
M36
AG12
G15
G17
G19
G21
H15
H16
H17
H19
H20
H21
H26
H27
J15
J16
J17
J19
J20
J21
J26
J27
SKYLAKE_HALO
U41I
VC
CSA
11.1 A
CSA
VC
CSA
VC
VC
CSA
VC
CSA
CSA
VC
CSA
VC
VC
CSA
VCCSA
CSA
VC
VC
CSA
VC
CSA
CSA
VC
CSA
VC
VC
CSA
VC
CSA
CSA
VC
CSA
VC
VC
CSA
VC
CSA
CSA
VC
CSA
VC
CIO
VC
5.5 A
CIO
VC
VC
CIO
VCCIO
CIO
VC
VC
CIO
VC
CIO
CIO
VC
CIO
VC
VC
CIO
VC
CIO
CIO
VC
CIO
VC
VC
CIO
VC
CIO
CIO
VC
CIO
VC
VC
CIO
VC
CIO
CIO
VC
VC
CIO
SKL_H_BGA_BGA
C2
98
1U/6.3V_4
Close CPUUnder CPU
4
BG
A1440
O
1U/6.3V_4
0.26 A
9
C2
97
2.8 A
0.12 A
0.145 A
VC
VSSSA_
VC
VSSI
OF 14
+VCCPLL+VCCI
VD
VD
VD
VD
VD
VD
VD
VD
VDDQ
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
VD
DQC
VD
VCCPLL_OC
CPLL_OC
VC
CST
VC
VC
CSTG
CSTG
VC
VC
CPLL
VC
CPLL
CSA_SENSE
SENSE
CIO_SENSE
O_SENSE
Follow SKL H EDS page 135 45W: VDDQ=2.8A
+1.
2VSUS
+1.
AA6
DQ
AE12
DQ
AF5
DQ
AF6
DQ
AG5
DQ
AG9
DQ
AJ12
DQ
AL11
DQ
AP6
AP7
DQ
AR12
DQ
AR6
DQ
AT12
DQ
AW6
DQ
AY6
DQ
J5
DQ
J6
DQ
K12
DQ
K6
DQ
L12
DQ
L6
DQ
R6
DQ
T6
DQ
W6
DQ
Y12
BH13
G11
H30
H29
G30
H28
J28
M38
M37
H14
J14
2VSUS 2,10,17,18,41
47
59
40
PLL
C2
1U/6.3V_4
ohm near CPU
100
VSA_
SENSE 42
VSASS_
SENSE 42
R151*SHORT_6
56*SH ORT_6
R1
R1
15*SHORT_6
R1
18*0_ 6
23*SH ORT_6
R1
3
C4
22U/6.3VS_6
C4
10U/6.3V_6
C4
10U/6.3V_6
60
+1.
+1.
52
49
51
2VSUS
2VSUS
+VCCST
+1.0V
C4
22U/6.3VS_6
C4
10U/6.3V_6
C4
10U/6.3V_6
+VDDQ
+VCCPLL_O
+VCCST
+VCCPLL
51 *100/F_4
R5
R5
46 *100/F_4
VCCI
O_VCCSENSE
O_VSSSENSE
VSSI
C
+VDDQ
C
+VCCPLL_O
+VCCSTG
+VCCPLL +VCCST
C4
21
22U/6.3VS_6
C4
60
10U/6.3V_6
C4
50
10U/6.3V_6
C
+VCCST
C
G
+VCCSA
R1
44 *SHORT_4
42 *SHORT_4
R1
+VCCI
C4
44
22U/6.3VS_6
C4
22
10U/6.3V_6
C4
34
10U/6.3V_6
O
45
R1
100_4
43
R1
100_4
PLL
PLL
+1.
+VCCST
+
C5
02
*330U/2V _7343
C4
32
10U/6.3V_6
C4
16
10U/6.3V_6
0V 2,5,10,16,40,45
PLL 2,10,40,42
EDRAM Only, PLACE CAPS IN ACK SIDE
BJ17
BJ19
BJ20
BK17
BK19
BK20
BL16
BL17
BL18
BL19
BL20
BL21
BM17
BN17
BJ23
BJ26
BJ27
BK23
BK26
BK27
BL23
BL24
BL25
BL26
BL27
BL28
BM24
BL15
BM16
BL22
BM22
BP15
BR15
BT15
BP16
BR16
BT16
BN15
BM15
BP17
BN16
91
TP
TP
24
29
TP
28
TP
TP
30
TP
27
OPC_COMP
76*49.9/F_4
CPU_
R5
CPU_
R1
R1
2
OPCE_COMP
33*49.9/F_4
CPU_
OPCE_COMP2
32*49.9/F_4
BM14
BL14
BJ35
BJ36
AT13
AW13
AU13
AY13
BT29
BR25
BP25
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Si
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
SNB 4/5 (POWER & GND)
SNB 4/5 (POWER & GND)
SNB 4/5 (POWER & GND)
Date: Sheet
Date: Sheet
Date: Sheet
SKYLAKE_HALO
U41J
BG
VC
COPC
3.8 A
COPC
VC
COPC
VC
VC
COPC
VC
COPC
COPC
VC
COPC
VC
VC
COPC
VCCOPC
COPC
VC
VC
COPC
VC
COPC
COPC
VC
COPC
VC
RS
VD
VD
RS
VD
RS
RS
VD
RS
VD
VD
RS
VD
RS
RS
VD
RS
VD
VD
RS
VD
RS
RS
VD
RSVD
VC
COPC_SENSE
PC_SENSE
VSSO
RS
VD
RS
VD
VC
CEOPIO
2.8 A
VC
CEOPIO
CEOPIO
VC
RS
VD
RS
VD
VD
RS
VCCEOPIO_SENSE
PIO_SENSE
VSSEO
RS
VD
VD
RS
VC
C_OPC_1P8
C_OPC_1P8
VC
RS
VD
RS
VD
ZV
M#
MS
M#
ZV
M2#
MS
M2#
C_RCOMP
OP
CE_RCOMP
OP
OP
CE_RCOMP2
SKL_H_BGA_BGA
A1440
0.05 A
10
1
OF 14
1A
1A
1A
of
of
of
9Monday, September 07, 2015
9Monday, September 07, 2015
64
64
64
9Monday, September 07, 2015
5
4
3
2
1
AV29
AV30
AV31
AV32
AV33
AV34
AV35
AV36
AW14
AW31
AW32
AW33
AW34
AW35
AW36
AW37
AW38
AY29
AY30
AY31
AY32
AY35
AY36
AY37
AY38
BA13
BA14
BA29
BA30
BA31
BA32
BA33
BA34
BA35
BA36
BB13
BB14
BB31
BB32
BB33
BB34
BB35
BB36
BB37
BB38
BC29
BC30
BC31
BC32
BC35
BE33
BE34
BE35
BE36
+V
CCGT
07
󱋨󱋨󱋨󱋨󲙵󲙵󲙵󲙵 n
et name
C_SENSE
SENSE
CCCORE
+V
CCCORE 42,43
+V
Follow SKL H DG page 573 to place Cap
V32
VCC
V33
C
VC
V34
C
VC
V35
C
VC
V36
C
VC
V37
C
VC
V38
VC
C
W13
VC
C
W14
VC
C
W29
VC
C
W30
VC
C
W31
VCC
W32
C
VC
W35
C
VC
W36
C
VC
W37
C
VC
W38
C
VC
Y29
VC
C
Y30
VC
C
Y31
VC
C
Y32
VC
C
Y33
VC
C
Y34
VCC
Y35
C
VC
Y36
VCC
L14
C
VC
P29
C
VC
P30
C
VC
P31
VC
C
P32
C
VC
P33
VC
C
P34
VC
C
P35
VC
C
P36
VCC
R13
VC
C
R31
VCC
R32
C
VC
R33
C
VC
R34
C
VC
R35
C
VC
R36
C
VC
R37
VC
C
R38
VC
C
T29
VC
C
T30
VC
C
T31
VC
C
T32
VCC
T35
C
VC
T36
C
VC
T37
C
VC
T38
C
VC
U29
C
VC
U30
VC
C
U31
VC
C
U32
VC
C
U33
VC
C
U34
VC
C
U35
VCC
U36
C
VC
V13
VCC
V14
C
VC
V31
C
VC
P14
C
VC
AG37
AG38
22uF x 12, 10uF x 28, 1uF x 63
C3
C3
0.1U/10V_4
1 2
C2
0.1U/10V_4
1 2
C180
0.1U/10V_4
1 2
C2
0.1U/10V_4
1 2
C2
0.1U/10V_4
1 2
69
82
44
45
88
0.1U/10V_4
1 2
81
C2
0.1U/10V_4
1 2
C739
0.1U/10V_4
1 2
76
C3
0.1U/10V_4
1 2
91
C3
0.1U/10V_4
1 2
R5
48 *100_4
R5
47 *100_4
C3
87
0.1U/10V_4
1 2
71
C3
0.1U/10V_4
1 2
C283
0.1U/10V_4
1 2
79
C3
0.1U/10V_4
1 2
48
C2
0.1U/10V_4
1 2
CCCORE
+V
ORE_SENSE 42
VC
ORESS_SENSE 42
VC
C2
C2
0.1U/10V_4
1 2
C2
0.1U/10V_4
1 2
C370
0.1U/10V_4
1 2
C7
0.1U/10V_4
1 2
C3
0.1U/10V_4
1 2
47
70
0.1U/10V_4
1 2
1 2
84
82
C1
0.1U/10V_4
1 2
1 2
C745
0.1U/10V_4
1 2
1 2
40
69
C2
0.1U/10V_4
1 2
1 2
92
90
C3
0.1U/10V_4
1 2
1 2
Se
nse resistor should be placed within 2
inches (50.8 mm) o f the processor soc ket
Trace Impendence 50 ohm
C3
78
0.1U/10V_4
67
C2
0.1U/10V_4
C375
0.1U/10V_4
95
C7
0.1U/10V_4
06
C2
0.1U/10V_4
1 2
1 2
1 2
1 2
1 2
C2
71
0.1U/10V_4
77
C3
0.1U/10V_4
C286
0.1U/10V_4
75
C1
0.1U/16V_4
67
C3
0.1U/10V_4
C3
0.1U/10V_4
1 2
C3
0.1U/10V_4
1 2
C214
0.1U/10V_4
1 2
C2
0.1U/10V_4
1 2
C3
0.1U/10V_4
1 2
C3
89
74
0.1U/10V_4
1 2
72
66
C2
0.1U/10V_4
1 2
C246
0.1U/10V_4
1 2
68
87
C1
0.1U/10V_4
1 2
68
85
C2
0.1U/10V_4
1 2
CCCORE
+V
U41G
AC13
AC14
AC29
AC30
AC31
AC32
AC33
AC34
AC35
AC36
AD13
AD14
AD31
AD32
AD33
AD34
AD35
AD36
AD37
AD38
AA13
AA31
AA32
AA33
AA34
AA35
AA36
AA37
AA38
AB29
AB30
AB31
AB32
AB35
AB36
AB37
AB38
AE13
AE14
AE30
AE31
AE32
AE35
AE36
AE37
AE38
AF35
AF36
AF37
AF38
K13
K14
L13
N13
N14
N30
N31
N32
N35
N36
N37
N38
P13
SKYLAKE_HALO
BG
VCC
C
VC
C
VC
C
VC
C
VC
C
VC
VC
C
VC
C
VC
C
VC
C
VC
C
VCC
C
VC
C
VC
C
VC
C
VC
C
VC
VC
C
VC
C
VC
C
VC
C
VC
C
VCC
C
VC
VCC
C
VC
C
VC
C
VC
VC
C
C
VC
VC
C
VC
C
VC
C
VCC
VC
C
VCC
C
VC
C
VC
C
VC
C
VC
C
VC
VC
C
VC
C
VC
C
VC
C
VC
C
VCC
C
VC
C
VC
C
VC
C
VC
C
VC
VC
C
VC
C
VC
C
VC
C
VC
C
VCC
C
VC
VCC
C
VC
C
VC
C
VC
SKL_H_BGA_BGA
A1440
VC
VSS_
7 OF 14
D D
C757
C211
22U/6.3V_6
22U/6.3V_6
C C
B B
C1
85
22U/6.3V_6
48
C3
10U/6.3V_6
83
C1
1U/6.3V_4
43
C3
1U/6.3V_4
C7
70
22U/6.3V_6
37
C3
10U/6.3V_6
89
C1
1U/6.3V_4
69
C7
1U/6.3V_4
Follow SKL H EDS page 131 to 45W(GT2): VCC_CORE=68A
C3
23
22U/6.3V_6
86
C1
22U/6.3V_6
C324
22U/6.3V_6
C3
47
22U/6.3V_6
58
C7
10U/6.3V_6
43
C7
1U/6.3V_4
01
C2
1U/6.3V_4
C7
48
22U/6.3V_6
97
C1
22U/6.3V_6
C759
22U/6.3V_6
C7
77
22U/6.3V_6
61
C7
10U/6.3V_6
99
C1
1U/6.3V_4
90
C7
1U/6.3V_4
C3
22
22U/6.3V_6
84
C1
22U/6.3V_6
C223
22U/6.3V_6
C7
47
22U/6.3V_6
12
C3
10U/6.3V_6
C7
67
10U/6.3V_6
79
C1
1U/6.3V_4
81
C7
1U/6.3V_4
C3
13
22U/6.3V_6
76
C1
22U/6.3V_6
C212
22U/6.3V_6
C3
36
22U/6.3V_6
10
C2
10U/6.3V_6
C3
49
10U/6.3V_6
80
C7
1U/6.3V_4
30
C3
1U/6.3V_4
C7
44
22U/6.3V_6
98
C1
22U/6.3V_6
C314
22U/6.3V_6
C2
22
22U/6.3V_6
71
C7
10U/6.3V_6
C3
38
10U/6.3V_6
15
C3
1U/6.3VS_4
21
C3
1U/6.3VS_4
C1
78
47U/6.3VS_8
C1
96
22U/6.3V_6
46
C7
22U/6.3V_6
C220
22U/6.3V_6
C7
56
22U/6.3V_6
68
C7
10U/6.3V_6
C7
54
10U/6.3V_6
74
C1
1U/6.3V_4
79
C7
1U/6.3V_4
C1
77
47U/6.3VS_8
CCGT
+V
CCGT 5,42,44
+V
U41H
SKYLAKE_HALO
A1440
BJ37
BJ38
BL36
BL37
BT37
BG
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VCCGT
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VCCGT
CGT
VC
VCCGT
CGT
VC
CGT
VC
CGT
VC
VC
CGT
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VCCGT
VC
CGT
VCCGT
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VCCGT
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
SKL_H_BGA_BGA
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VCCGT
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VCCGT
CGT
VC
VCCGT
CGT
VC
CGT
VC
CGT
VC
VC
CGT
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VCCGT
VC
CGT
VCCGT
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VCCGT
CGT
VC
CGT
VC
CGT
VC
CGT
VC
CGT
VC
VC
CGT
VC
CGT
VC
CGT
8
OF 14
BG34
BG35
BG36
BH33
BH34
BH35
BH36
BH37
BH38
BM36
BM37
BN36
BN37
BN38
BP37
BP38
BR37
BE38
BF13
BF14
BF29
BF30
BF31
BF32
BF35
BF36
BF37
BF38
BG29
BG30
BG31
BG32
BG33
BC36
BC37
BC38
BD13
BD14
BD29
BD30
BD31
BD32
BD33
BD34
BD35
BD36
BE31
BE32
BE37
Ch
ange R2053 to NI_20141203
VC
ORE_SENSE
A A
5
4
VC
R5
ORESS_SENSE
52*49.9/F_4
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Si
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
stom
stom
stom
Cu
Cu
Cu
SN
SN
SN
B 4/5 (POWER & GND)
B 4/5 (POWER & GND)
B 4/5 (POWER & GND)
Date: Sheet
Date: Sheet
3
2
Date: Sheet
1
1A
1A
1A
749Tuesday, Augu st 25, 2015
749Tuesday, Augu st 25, 2015
749Tuesday, Augu st 25, 2015
of
of
of
5
4
3
2
1
Haswell Processor (GND)
AW
AW
AW
BA38
BA3
BA12
BA1
BA10
AY3
AY3
AY1
AY1
AW
AW
AW
AW
AW
AV3
AV3
AU
AU
AU
AU
AU
AT30
AT
AR
AR37
AR
AR13
AP3
AP3
AP1
AP1
AP1
AN
AN
AN
AM
AM
AM
AM
AM
AM
AM
AM
AL
AL
AL
AL12
AL
BB4
BB3
BB2
BB1
BA9
BA8
BA7
BA6
AU
AU
AU
AU
AT6
AR
AR4
AR
AR
AR
AP9
AP8
AN
AN
AL9
AL
AL7
AL
U41M
VSS
VSS
VSS
VSS
VSS
7
VSS
VSS
1
VSS
VSS
VSS
VSS
VSS
VSS
B9
VSS
4
VSS
3
VSS
4
VSS
2
VSS
30
VSS
29
VSS
12
VSS
5
VSS
4
VSS
3
VSS
2
VSS
1
VSS
8
VSS
7
VSS
34
VSS
33
VSS
12
VSS
11
VSS
10
VSS
9
VSS
8
VSS
7
VSS
6
VSS
VSS
29
VSS
VSS
38
VSS
VSS
14
VSS
VSS
5
VSS
VSS
3
VSS
2
VSS
1
VSS
4
VSS
3
VSS
2
VSS
1
VSS
0
VSS
VSS
VSS
30
VSS
29
VSS
12
VSS
6
VSS
5
VSS
38
VSS
37
VSS
12
VSS
5
VSS
4
VSS
3
VSS
2
VSS
1
VSS
34
VSS
33
VSS
14
VSS
VSS
10
VSS
VSS
8
VSS
VSS
4
VSS
SKL_H_BGA_BGA
SKYL
AKE_HALO
BGA1440
13 OF 14
0
AK3
VSS
9
AK2
VSS
AK4
VSS
38
AJ
VSS
AJ37
VSS
6
AJ
VSS
AJ5
VSS
4
AJ
VSS
AJ3
VSS
2
AJ
VSS
AJ1
VSS
34
AH
VSS
33
AH
VSS
12
AH
VSS
6
AH
VSS
30
AG
VSS
29
AG
VSS
11
AG
VSS
10
AG
VSS
8
AG
VSS
7
AG
VSS
6
AG
VSS
AF
14
VSS
13
AF
VSS
AF
12
VSS
4
AF
VSS
AF
3
VSS
2
AF
VSS
AF
1
VSS
4
AE3
VSS
AE3
3
VSS
AE6
VSS
30
AD
VSS
29
AD
VSS
12
AD
VSS
11
AD
VSS
10
AD
VSS
AD9
VSS
8
AD
VSS
AD7
VSS
6
AD
VSS
AC38
VSS
37
AC
VSS
AC12
VSS
6
AC
VSS
AC5
VSS
4
AC
VSS
3
AC
VSS
2
AC
VSS
1
AC
VSS
4
AB3
VSS
3
AB3
VSS
AB6
VSS
0
AA3
VSS
9
AA2
VSS
2
AA1
VSS
0
A3
VSS
A2
8
VSS
6
A2
VSS
A2
4
VSS
2
A2
VSS
A2
0
VSS
8
A1
VSS
A1
6
VSS
4
A1
VSS
A1
2
VSS
0
A1
VSS
A9
VSS
A6
VSS
B37
FVSS
NCT
B3
NCTFVSS
A34
FVSS
NCT
A4
NCTFVSS
A3
FVSS
NCT
CF
G[3] (PHYSICAL_DEBUG_ENABLED (DFX PRIVACY))
Enable; SET DFX ENABLED BIT IN DEBUG
0
1 , Disable;
3
H_2_CPU_TRIG15
PC
CF
CF
G32,16
G22,16
CF
CFG42,16
CFG52,16
CFG62,16
CFG102,16
CFG122,16
CF
G132,16
G3
G2
CF
CFG4
CFG5
CFG6
CFG10
CFG12
CF
G13
U41F
AKE_HALO
SKYL
BGA1440
8
Y3
VSS
7
Y3
VSS
Y14
VSS
3
Y1
VSS
Y11
VSS
0
Y1
VSS
Y9
D D
C C
B B
W3
W33
W1
V3
V2
V1
U3
U3
T3
T3
T1
T1
T1
T1
T1
R30
R2
R12
P3
P37
P1
N3
N3
N1
N1
N1
M1
M1
M1
L34
L33
L30
L29
K3
K1
K1
Y8
Y7
4
2
W5
W4
W3
W2
W1
0
9
2
V6
8
7
U6
4
3
4
3
2
1
0
T9
T8
T7
T5
T4
T3
T2
T1
9
8
2
P6
4
3
2
1
0
N9
N8
N7
N6
N5
N4
N3
N2
N1
4
3
2
M6
8
1
0
K9
K8
K7
K5
K4
K3
K2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SKL_H_BGA_BGA
OF 14
6
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NCTFVSS
K1
6
J3
J33
2
J3
J25
2
J2
J18
0
J1
J7
J4
H35
2
H3
5
H2
2
H2
8
H1
2
H1
1
H1
8
G2
6
G2
4
G2
3
G2
2
G2
G2
0
8
G1
G1
6
4
G1
G1
2
0
G1
G9
G8
G6
G5
G4
6
F3
1
F3
9
F2
7
F2
F25
3
F2
F21
9
F1
F17
5
F1
F13
1
F1
F9
F8
F5
F4
F3
F2
8
E3
5
E3
4
E3
E9
E4
3
D3
D3
0
8
D2
D2
6
4
D2
D2
2
0
D2
D1
8
6
D1
D1
4
2
D1
0
D1
D9
D6
D3
7
C3
C31
9
C2
C27
D38
Processor Strapping
U41L
SKYL
AKE_HALO
BGA1440
7
C1
VSS
3
C1
VSS
C9
VSS
32
BT
VSS
BT26
VSS
24
BT
VSS
BT21
VSS
18
BT
VSS
BT14
VSS
12
BT
VSS
BT9
VSS
5
BT
VSS
36
BR
VSS
34
BR
VSS
29
BR
VSS
26
BR
VSS
24
BR
VSS
21
BR
VSS
18
BR
VSS
14
BR
VSS
12
BR
VSS
7
BR
VSS
BP3
4
VSS
3
BP3
VSS
BP2
9
VSS
6
BP2
VSS
BP2
4
VSS
1
BP2
VSS
BP1
8
VSS
4
BP1
VSS
BP1
2
VSS
BP7
VSS
34
BN
VSS
31
BN
VSS
30
BN
VSS
29
BN
VSS
24
BN
VSS
BN21
VSS
20
BN
VSS
BN19
VSS
18
BN
VSS
BN14
VSS
12
BN
VSS
BN9
VSS
7
BN
VSS
BN4
VSS
2
BN
VSS
38
BM
VSS
35
BM
VSS
28
BM
VSS
27
BM
VSS
26
BM
VSS
23
BM
VSS
21
BM
VSS
13
BM
VSS
12
BM
VSS
9
BM
VSS
BM
6
VSS
2
BM
VSS
BL
29
VSS
9
BK2
VSS
BK1
5
VSS
4
BK1
VSS
BJ
32
VSS
31
BJ
VSS
BJ
25
VSS
22
BJ
VSS
14
BH
VSS
12
BH
VSS
9
BH
VSS
8
BH
VSS
5
BH
VSS
BH4
VSS
1
BH
VSS
BG38
VSS
13
BG
VSS
BG12
VSS
33
BF
VSS
BF12
VSS
9
BE2
VSS
BE6
VSS
BD9
VSS
BC34
VSS
BC12
VSS
BB12
VSS
SKL_H_BGA_BGA
e CFG signals have a default value of '1' if not terminated on the board.
Th
NCT
NCT
NCT
NCT
NCTFVSS
NCT
12
OF 14
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
FVSS
FVSS
FVSS
FVSS
FVSS
C2
C2
C21
C1
C15
C1
C8
C5
BM29
BM
BM18
BM
BM
BM
BM
BM
BL
BL
BL
BL
BK2
BK2
BK1
BK6
BJ
BJ
BJ
BJ
BH
BH
BH
BH
BH
BH
BG
BG
BG
BF34
BF
BE30
BE5
BE4
BE3
BE2
BE1
BD38
BD
BD
BD
BD
BD
BD
BD
BC
BC
BC
BC
BB3
BB2
BB6
BB5
C2
BT36
BT35
BT4
BT3
BR38
5
3
9
1
25
11
8
7
5
3
38
35
13
6
5
2
3
30
29
15
12
11
10
7
6
3
2
37
14
6
6
37
12
11
10
8
7
6
33
14
13
6
0
9
1 0
FG2
A A
C
(PEG Static Lane Reversal)
FG4
C
(DP Presence Strap)
C
FG7
(PEG Defer Training)
5
Normal Operation Lane Reversed
Disable; No physical DP attached to eDP
PEG
train immediately following
xxRESETB de assertion
4
Enable; An ext DP device is connected to eDP
PEG
wait for BIOS training
Haswell Processor (RESERVED, CFG)
SKYLAKE_HALO
A1440
BG
11
OF 14
CP
U_2_PCH_TRIG
CP
U_2_PCH_TRIG 15
G[6:5] (PCIE Port Bifurcation S traps)
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Cu
Cu
Cu
stom
stom
stom
Date: Sheet
Date: Sheet
Date: Sheet
TP
95
TP
98
96
TP
94
TP
TP
97
TP
93
CP
CP
U_2_PCH_TRIG_R
R1
24 *1K_4
R1
28 1K_4
R580 1K_4
R5
82 *1K_4
R5
83 *1K_4
R5
81 *1K_4
R5
84 *1K_4
R5
85 *1K_4
U_2_PCH_TRIG_R
U41K
D1
RSVD_TP
E1
VD_TP
RS
E3
RSVD_TP
E2
VD_TP
RS
BR1
RS
VD_TP
BT2
RSVD_TP
BN35
RSVD
J24
VD
RS
H24
RS
VD
BN33
VD
RS
BL34
RS
VD
N29
VD
RS
R14
VD
RS
AE29
VD
RS
AA14
VD
RS
A36
RS
VD
A37
VD
RS
H23
OC_TRIGIN
PR
J23
PR
OC_TRIGOUT
F30
RS
VD
E30
RS
VD
B30
RS
VD
C30
VD
RS
G3
VD
RS
J3
RS
VD
BR35
VD
RS
BR31
RSVD
BH30
RS
VD
SKL_H_BGA_BGA
9130_4
R5
CF
11: (Default) x16 - Device 1 functions 1 and 2 disabled
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
2
08
BM33
RSVD_TP
BL33
VD_TP
RS
BJ14
VD_TP
RS
BJ13
RSVD_TP
BK28
RSVD
BJ28
RS
VD
18
BJ
VSS
BJ16
RS
VD_TP
BK16
VD_TP
RS
BK24
VD_TP
RS
BJ24
VD_TP
RS
BK21
VD
RS
BJ21
VD
RS
BT17
VD
RS
BR17
RS
VD
BK1
8
VSS
BJ34
RS
VD_TP
BJ33
RS
VD_TP
G13
RS
VD
AJ8
VD
RS
BL31
RS
VD
B2
NCTF
B38
F
NCT
BP1
NCTF
BR2
F
NCT
C1
NCTF
C38
NCT
F
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
B 5/5 (GND)
B 5/5 (GND)
B 5/5 (GND)
SN
SN
SN
1
TP
TP
TP
TP21
TP
TP
TP
TP
TP
TP
89
90
22
14
15
16
13
25
92
1A
1A
1A
of
of
of
849Tuesday, September 08, 2015
849Tuesday, September 08, 2015
849Tuesday, September 08, 2015
5
4
3
2
1
U45B
IECOMP_P
L27
DM
I_RXN0
N27
I_RXP0
DM
C27
DM
I_TXN0
B27
I_TXP0
DM
E24
DMI_RXN1
G24
I_RXP1
DM
B28
DMI_TXN1
A28
I_TXP1
DM
G27
DMI_RXN2
E26
DM
I_RXP2
B29
DMI_TXN2
C29
DM
I_TXP2
L29
DMI_RXN3
K29
DM
I_RXP3
B30
I_TXN3
DM
A30
DM
I_TXP3
B18
PC
IE_RCOMPN
C17
IE_RCOMPP
PC
H15
IE1_RXN/USB3_7_RXN
PC
G15
IE1_RXP/USB3_7_RXP
PC
A16
IE1_TXN/USB3_7_TXN
PC
B16
IE1_TXP/USB3_7_TXP
PC
B19
PC
IE2_TXN/USB3_8_TXN
C19
IE2_TXP/USB3_8_TXP
PC
E17
PC
IE2_RXN/USB3_8_RXN
G17
IE2_RXP/USB3_8_RXP
PC
L17
PC
IE3_RXN/USB3_9_RXN
K17
PC
IE3_RXP/USB3_9_RXP
B20
PC
IE3_TXN/USB3_9_TXN
C20
PC
IE3_TXP/USB3_9_TXP
E20
PC
IE4_RXN/USB3_10_RXN
G19
PC
IE4_RXP/USB3_10_RXP
B21
IE4_TXN/USB3_10_TXN
PC
A21
PC
IE4_TXP/USB3_10_TXP
K19
IE5_RXN
PC
L19
PC
IE5_RXP
D22
IE5_TXN
PC
C22
PCIE5_TXP
G22
IE6_RXN
PC
E22
PCIE6_RXP
B22
IE6_TXN
PC
A23
PCIE6_TXP
L22
PC
IE7_RXN
K22
PCIE7_RXP
C23
PC
IE7_TXN
B23
PCIE7_TXP
K24
PC
IE8_RXN
L24
IE8_RXP
PC
C24
PC
IE8_TXN
B24
IE8_TXP
PC
SPT_PCH_H
I_TXN03
DM
DM
I_TXP03
DM
I_RXN03
DM
I_RXP03
I_TXN13
DM
I_TXP13
DM
DM
I_RXN13
DM
I_RXP13
I_TXN23
D D
PC
IE_RXN3_WLAN34
IE_RXP3_WLAN34
WL
AN
LAN
C C
PC
IE_TXN3_WLAN34
PC
PC
IE_TXP3_WLAN34
IE_RXN4_LAN31
PC
PC
IE_RXP4_LAN31
IE_TXN4_LAN31
PC
PC
IE_TXP4_LAN31
DM
I_TXP23
DM
I_RXN23
DM
DM
I_RXP23
DM
I_TXN33
DM
I_TXP33
I_RXN33
DM
I_RXP33
DM
90 100/F_4
R6
C8
70 0.1U/16V_4
C8
69 0.1U/16V_4
72 0.1U/16V_4
C8
C8
71 0.1U/16V_4
PCIECOMP_N
PC
IE_TXN3_WLAN_C
PC
IE_TXP3_WLAN_C
PC
IE_TXN4_LAN_C
PC
PC
IE_TXP4_LAN_C
SPT-H_PCH
I
DM
PC
Ie/USB 3
USB 2.0
OF 12
2
GP
P_E9/USB2_OC0#
GP
P_E10/USB2_OC1#
GP
P_E11/USB2_OC2#
P_E12/USB2_OC3#
GP
GP
P_F15/USB2_OCB_4
P_F16/USB2_OCB_5
GP
GP
P_F17/USB2_OCB_6
P_F18/USB2_OCB_7
GP
USB2_COMP
B2_VBUSSENSE
US
RSVD_AB13
GP
US
B2N_1
B2P_1
US
US
B2N_2
B2P_2
US
USB2N_3
B2P_3
US
USB2N_4
B2P_4
US
USB2N_5
US
B2P_5
USB2N_6
US
B2P_6
USB2N_7
US
B2P_7
B2N_8
US
US
B2P_8
B2N_9
US
US
B2P_9
B2N_10
US
B2P_10
US
B2N_11
US
B2P_11
US
B2N_12
US
B2P_12
US
US
B2N_13
B2P_13
US
US
B2N_14
B2P_14
US
US
D7/RSVD
B2_ID
AF5
AG7
AD5
AD7
AG8
AG10
AE1
AE2
AC2
AC3
AF2
AF3
AB3
AB2
AL8
AL7
AA1
AA2
AJ8
AJ7
W2
W3
AD3
AD2
V2
V1
Ch
ange DGPU_PRSNT# to GPU_EVENT#_20141203
AJ11
AJ13
AD43
B_OC0#
US
AD42
B_OC1#
US
AD39
US
B_OC2#
AC44
B_OC3#
US
Y43
US
B_OC4#
Y41
B_OC5#
US
W44
B_OC6#
US
W43
US
B_OC7#
AG3
B2_COMP
US
AD10
AB13
AG2
BD14
BP0- 36
US
US
BP0+ 36
US
BP1- 36
US
BP1+ 36
BP4- 36
US
US
BP4+ 36
US
BP6- 34
US
BP6+ 34
US
BP7- 29
BP7+ 29
US
US
BP8- 29
USBP8+ 29
US
BP9- 36
BP9+ 36
US
B_OC0# 36
US
B_OC1# 36
US
US
B_OC2# 36
41 113/F_4
R6
R4
85 1K_4
42 1K_4
R6
MB USB3.0
USB3.0
MB
DB USB2.0
BT
Touch Screen
CCD
Card reader
Port1
Port2
Port5
US
US
US
US
US
US
US
US
B_OC0#
B_OC1#
B_OC2#
B_OC3#
B_OC4#
B_OC5#
B_OC6#
B_OC7#
R7
6110K_4
R7
6010K_4
R7
5910K_4
8210K_4
R7
R7
5810K_4
R78110K_4
R7
8010K_4
R7
5710K_4
V_DEEP_SUS
+3
09
V
-H_PCH
B B
US
B3_TXN136
US
B3_TXP136
B3_RXN136
USB3.0 (M/B-2)
USB3.0 (M/B-1)
A A
5
US
US
B3_RXP136
US
B3_TXN036
US
B3_TXP036
B3_RXN036
US
USB3_RXP036
4
U45F
C11
B3_1_TXN
US
B11
US
B3_1_TXP
B7
B3_1_RXN
US
A7
US
B3_1_RXP
B12
USB3_2_TXN/SSIC_1_TXN
A12
B3_2_TXP/SSIC_1_TXP
US
C8
USB3_2_RXN/SSIC_1_RXN
B8
B3_2_RXP/SSIC_1_RXP
US
B15
US
B3_6_TXN
C15
USB3_6_TXP
K15
US
B3_6_RXN
K13
USB3_6_RXP
B14
USB3_5_TXN
C14
USB3_5_TXP
G13
USB3_5_RXN
H13
USB3_5_RXP
D13
USB3_3_TXP/SSIC_2_TXP
C13
USB3_3_TXN/SSIC_2_TXN
A9
USB3_3_RXP/SSIC_2_RXP
B10
USB3_3_RXN/SSIC_2_RXN
B13
USB3_4_TXP
A14
USB3_4_TXN
G11
USB3_4_RXP
E11
USB3_4_RXN
SPT_PCH_H
SPT
LPC/eSPI
US
B
SATA
OF 12
6
GP
P_A1/LAD0/ESPI_IO0
P_A2/LAD1/ESPI_IO1
GP
GP
P_A3/LAD2/ESPI_IO2
P_A4/LAD3/ESPI_IO3
GP
P_A5/LFRAME#/ESPI_CS0#
GP
GPP_A6/SERIRQ/ESPI_CS1#
P_A7/PIRQA#/ESPI_ALERT0#
GP
GPP_A0/RCIN#/ESPI_ALERT1#
GP
P_A14/SUS_STAT#/ESPI_RESET#
GPP_A9/CLKOUT_LPC0/ESPI_CLK
GPP_A10/CLKOUT_LPC1
GPP_G19/SMI#
GPP_G18/NMI#
GPP_E6/DEVSLP2
GPP_E5/DEVSLP1
GPP_E4/DEVSLP0
GPP_F9/DEVSLP7
GPP_F8/DEVSLP6
GPP_F7/DEVSLP5
GPP_F6/DEVSLP4
GPP_F5/DEVSLP3
3
Add board ID_20141 20 3
AT22
AV22
AT19
BD16
BE16
BA17
IR
Q_SERIRQ
AW17
BO
ARD_ID8
AT17
BC18
BC17
K_PCI_EC_R
CL
AV19
CL
K_PCI_LPC_R
M45
N43
AE45
AG43
AG42
AB39
AB36
AB43
AB42
AB41
SI
DE
VSLP2
VSLP1
DE
DE
VSLP0
LP
C_LAD0 33,34,37
LP
C_LAD1 33,34,37
LP
C_LAD2 33,34,37
C_LAD3 33,34,37
LP
LPC_LFRAME# 33,34,37
O_EXT_SMI# 12,37
TP
105
DE
VSLP0 33,34
IR
Q_SERIRQ 33,37
O_RCIN# 37
SI
_RST# 37
ESPI
88 22/F_4
R6
R2
52 22/F_4
R2
53 22/F_4
EC
19 18P/50V_4
EC
5 18P/50V_4
2
EC6
18P/50V_4
K_PCI_EC 37
CL
CL
K_PCI_LPC 34
EMI(near PCH)
LK_TPM 33
PC
EM
I(near PCH)
IR
Q_SERIRQ
SI
O_RCIN#
SI
O_EXT_SMI#
VSLP0
DE
DE
VSLP1
VSLP2
DE
+3V_DEEP_SUS10,12,13,14,16,17
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Cu
Cu
Cu
stom
stom
stom
PC
PC
PC
Date: Sheet
Date: Sheet
Date: Sheet
54 10K_4
R2
R784 *10K_4
63 *10K_4
R7
R762 *10K_4
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
H 1/6 (DMI/FDI/VIDEO)
H 1/6 (DMI/FDI/VIDEO)
H 1/6 (DMI/FDI/VIDEO)
1
+3
+3
V
R2
5010K_4
R7
5610K_4
1A
1A
1A
of
of
of
949Tuesday, August 25, 2015
949Tuesday, August 25, 2015
949Tuesday, August 25, 2015
76 2.2K_4
R7
R7
50 2.2K_4
R7
90 2.2K_4
R7
89 2.2K_4
79 2.2K_4
R7
77 2.2K_4
R7
R6
79 10K_4
92 *10K_4
R6
96 *10K_4
R6
V
+3
+3V
5
C8
R6
70 33_4
R659 33_4
R6
62 33_4
R6
B_ME0_CLK
SM
B_ME0_DAT
SM
SM
B_ME1_CLK
SM
B_ME1_DAT
SM
B_PCH_CLK
B_PCH_DAT
SM
PC
H_BATLOW#
SU
SWARN#
SACK#
SU
C6
08 *220P/50V_4
C884 *220P/50V_4
2N
2N
R3
46 4.7K_4
R355 4.7K_4
VPCU
+3
58 *33P/50V_4
Z_BCLK
AC
AC
Z_RST#
AC
Z_SDOUT
AC
Z_SYNC
66 33_4
R6
67
*1M_4
+3
V_S5
R8
28
8
Q2
*2.2K_4
5
43
2
6
1
*2N7002DW
D_MBCLK
R3
R3
D_MBDATA
Q2
4 3
1
2N7002KDW
On SKL voltage at VCCRTC does not exceed 3.2V
R6
58
*SHORT_4
40 *SHORT_4
51 *SHORT_4
9
1B-1
1 3
12
BT
1
B_ME1_CLK
SM
SM
B_ME1_DAT
V
+3
5
2
6
R671 1K_4
VC
CRTC_3
0
Q6
MMBT3904
2
+3
V_DEEP_SUS
R6
64
*4.7K_4
Z_SDOUT
AC
D_AZACPU_SDO3
AU
D_AZACPU_SDI3
AU
D_AZACPU_SCLK3
AU
DM
DM
MRST#37
RS
SM
BALERT#12
L0ALERT#12
SM
SM
B1ALERT#12,35
R8
31
*2.2K_4
B_ME1_CLK
SM
B_ME1_DAT
SM
SM
B_PCH_DAT
SM
B_PCH_CLK
D3
+3
V_RTC_2
+3V_RTC_1
BAT54C
V_RTC_[0:2]
+3
Trace width = 20 mils
20M
IL
R9
63 4.7K_4
IC_DATA032
IC_CLK032
To
XDP
DDR3-L
CPU heat pipe loca l thermal sensor
DDR thermal sensor
+3
V_RTC
0
VC
CRTC_4
HDA
Bus(CLG)
PC
H_AZ_CODEC_BITCLK32
PC
H_AZ_CODEC_RST#32
H_AZ_CODEC_SDOUT32
PC
H_AZ_CODEC_SYNC32
PC
V_DEEP_SUS
+3
D D
C C
B B
Add PU _20141212
RS
MRST#
EC
_PWROK
D_MBCLK22, 37
2N
2ND_MBDATA22, 37
SM
B_RUN_DAT5,16,17,18,35
B_RUN_CLK5,16,17,18,35
SM
RT
C Circuitry (RTC)
ME
_WR#12,37
H_AZ_CODEC_SDIN032
PC
SYS_
PWROK
R2
BALERT#
SM
SM
L0ALERT#
TP
49
VG
A
EC
uch Pa d
+3V_RTC
Trace width = 30 mils
R6
39
20K/F_4
57
R6
20K/F_4
C8
56
1u/6.3V_4
R9
65 4.7K_4
4
30 30_4
R6
R6
31 *SHORT_4
R6
46 30_4
R7
64 *33_4
06 *33_4
R3
R2
42 *0_4
33 *SHORT_4
54
C8
1u/6.3V_4
C8
55
1u/6.3V_4
V_S5
+5
R9
62
68.1K/F_4
R964
150K/F_4
= *Enable security in the Flash
0
AC
R6
Z_SDOUT
D_AZACPU_SDO_R
AU
D_AZACPU_SDI_R
AU
AU
D_AZACPU_SCLK_R
PC
DS
WROK_EC_R
SM
B_PCH_CLK
SM
B_PCH_DAT
SM
B_ME0_CLK
B_ME0_DAT
SM
SM
B1ALERT#
B_ME1_CLK
SM
SM
B_ME1_DAT
651K_4
AC
AC
AC
AC
DM
DM
RT
SRTC_RST#
EC
_PWROK_R
H_RSMRST#
Z_BCLK
Z_RST#
Z_SDOUT
Z_SYNC
IC_DATA0_R
IC_CLK0_R
C_RST#
Description (iPD 20K)
1 = Disable Flash Descriptor Security (Override)
U45D
BA9
HDA_BCLK
BD8
_RST#
HDA
BE7
_SDI0
HDA
BC8
HDA
_SDI1
BB7
HDA
_SDO
BD9
_SYNC
HDA
BD1
VD_BD1
RS
BE2
RS
VD_BE2
DIO
AM1
AN2
AM2
AL42
AN42
AM43
AJ33
AH44
AJ35
AJ38
AJ42
BC10
BB10
AW11
BA11
AV11
BB41
AW44
BB43
BA40
AY44
BB39
AT27
AW42
AW45
Sy
AU
SPA_SDO
DI
SPA_SDI
DI
SPA_BCLK
DI
GP
P_D8/I2S0_SCLK
P_D7/I2S0_RXD
GP
GPP_D6/I2S0_TXD
P_D5/I2S0_SFRM
GP
GP
P_D20/DMIC_DATA0
GP
P_D19/DMIC_CLK0
GPP_D18/DMIC_DATA1
GP
P_D17/DMIC_CLK1
RT
CRST#
SR
TCRST#
PC
H_PWROK
MRST#
RS
DS
W_PWROK
P_C2/SMBALERT#
GP
P_C0/SMBCLK
GP
P_C1/SMBDATA
GP
GP
P_C5/SML0ALERT#
GP
P_C3/SML0CLK
GPP_C4/SML0DATA
P_B23/SML1ALERT#/P CHHOT#
GP
P_C6/SML1CLK
GP
GP
P_C7/SML1DATA
SPT_PCH_H
stem PWR_OK(CLG)
SPWOK
SY
PWROK16
SYS_
SYS_
EC_PWROK_R
SYS_
PWROK_R
PWROK
SPT
-H_PCH
SM
BUS
For HWPG Sequence
For HWPG Sequence
.0V
+1
19
R8
4
4
U5
*TC7SH08FU
R9
+1
+3
V_S5
70 0_4
*15K/F_4
.0V_PWRGD_G1
95
C8
*0.1U/16V_4
C821 0.1u/16V_4
2
1
3 5
R8
*100K_4
SU
SU
C_RST#
RT
12
J1
*J
RE
->SLP_S4# assertion to
VDDQ(+1.35VSUS) ramp
down start(SUSON)
RTC_RST# 16
UMP
SR
TC_RST#
V:E tPLT15(max 200us)
SUSON
SUSON40,41 VRON42
3
GPP_A12/BMBUSY#/ISH_GP 6/SX_EXIT_HOLDOFF#
JT
AG
OF 12
4
+3
4
3
U4
*TC7SH08FU
R6
20 *0_4
19 *SHORT_4
R6
Non Deep Sx
R243 *SHORT_4
22 *0_4
R6
+5
2
20
SC#
SON_EC
P_A8/CLKRUN#
GP
GP
D11/LANPHYPC
GP
D9/SLP_WLAN#
DRA
P_B2/VRALERT#
GP
P_G17/ADR_COMPLETE
GP
SY
GP
P_B12/SLP_S0#
GP
GP
D4/SLP_S3#
GP
D5/SLP_S4#
GPD10/SLP_S5#
D8/SUSCLK
GP
GP
D0/BATLOW#
GP
P_A15/SUSACK#
GP
P_A13/SUSWARN#/SUSP WRDNACK
GP
D2/LAN_WAKE#
D1/ACPRESENT
GP
GP
D3/PWRBTN#
SY
P_B14/SPKR
GP
PR
IT
V_S5
C8
51 *0.1u/16V_4
2
_PWROK
EC
1
3 5
EC
R6
_PWROK
36*0_4
V_S5
08
R8
*100K_4
2
.0V_PWRGD_G2
+1
9
Q4
*METR3904-G
1 3
SU
SON_EC 37
M_RESET#
GP
GP
GP
S_PWROK
D6/SLP_A#
SLP_LAN#
SL
P_SUS#
S_RESET#
OCPWRGD
P_PMODE
AG_TMS
JT
AG_TDO
JT
JT
AG_TDI
JT
AG_TCK
+3V_S5
3
1
BB17
AW22
AR15
AV13
BC14
DRA
BD23
GP
AL27
P_B1
AR27
P_B0
N44
AN24
P_B11
AY1
SYS_
BC13
WA
KE#
BC15
AV15
BC26
AW15
BD15
BA13
AN15
SU
BD13
PC
BB19
SU
BD19
SU
BD11
PC
BB15
AC
BB13
SLP_SUS#_EC
AT13
DNB
AW1
SYS_
BD26
AC
AM3
PR
AT2
AR3
JTAGX
AR2
JT
AG_TMS_PCH
AP1
AG_TDO_PCH
JT
AP2
JT
AG_TDI_PCH
AN3
JT
AG_TCK_PCH
EC
_PWROK 37
IM
VP_PWRGD_3V 2
R6
25
*10K_4
PC
H_PWROK 2,37
R8
22
*10K_4
HW
PG_R
8
Q4
R806
*2N7002K
*100K_4
REV:E tPLT17(max
200us) ->SLP_S3#
assertion to IMVP
VR_ON(VRON) deassert ion
SYS_RESET#
P_B2
GP
CL
KRUN#
LA
N_DISABLE
M_RESET#
P_B2
PWROK_R
PC
IE_WAKE#
PC
H_SLP_S0_N
SCLK
H_BATLOW#
SACK#
SWARN#
IE_LAN_WAKE#
PRESENT
SWON#
RESET#
Z_SPKR
OCPWRGD
R8
09 *0_4
R6
511K_4
R6
R210 10K_4
R7
16 10K_4
TP
TP
35 *SHORT_4
TP
R645 *10K_4
+1
+3
4
6
U5
*TC7SH08FU
R9
72 0_4
+3
KRUN# 33,37
CL
43
37
SYS_
PWROK
PC
SL
PC
SU
SU
SL
SU
102
97*0_4
R6
93*0_4
R6
91*SHORT_4
SU
R6
AC
V_S5
AGX_PCH 2,16
JT
JTAG_TMS_PCH 16
AG_TDO_PCH 16
JT
JT
AG_TDI_PCH 16
JT
AG_TCK_PCH 16
PG 2,37
HW
V_S5
C831 0.1u/16V_4
2
1
VR
3 5
2
V
+1
IE_WAKE# 31,34
P_A# 16
H_SLP_S0_N 16,37
SB# 2,16,37,39
SC# 16,37
P_S5# 16
Ad
SCLK 34
SACK#_EC 37
SU
SU
SWARN#_EC 37
SWARN#
IE_LAN_WAKE# 31
PC
PRESENT 37
AC
SL
P_SUS#_EC 37
DNB
SWON# 37
SYS_
RESET# 16
Z_SPKR 12,32
OCPWRGD 2
PR
V_S5
+3
V_S5
+3
V
+3
SB#
SU
ON_EC
.2VSUS
12
R6
81
DRA
470_4
R6
82 *short_4
d SSD _20141 210
For DS3 Sequence
For DS3 -->Ra
Non-DS3 -->Rb
H_RSMRST#
PC
WROK_C37
DP
Add PU _20141212
78 1K_4
R6
R6
80 10K_4
89 10K_4
R6
62 *10K_4
R2
R2
67 10K_4
PC
H_RSMRST#
R2
32 10K_4
WROK_C
25 100K_4
DP
R2
SYS_
R2
PWROK_R
09 10K_4
VR
ON_EC 37
MRST
12
*0.1u/16V_4
+1
R6
23
*SHORT_4
34
R6
*210/F_4
R6
50
*100/F_4
Rb
R2
23 *SHORT_4
R2
24 *0_4
Ra
IE_LAN_WAKE#
PC
PC
IE_WAKE#
AC
PRESENT
KRUN#
CL
REV:E tPLT18(max 200 us)
->SLP_S3# assertion to
VCCIO VR(MAIND for +1 V_S5
to +VCCIO) disabled
MAINON41,45
1
10
_DRAMRST# 17,18
DDR3
68
C8
+V
.0V
CCSTPLL
R6
21
*0_4
33
32
R6
R6
*210/F_4
51_4
JT
AG_TMS_PCH
JTAG_TDI_PCH
JT
AG_TDO_PCH
AG_TCK_PCH
JT
R6
R6
R6
*100/F_4
49
48
*100/F_4
DS
WROK_EC_R
4
5
U5
*TC7SH08FU
R9
*51_4
V_S5
+3
3 5
71 0_4
47
C824 0.1u/16V_4
2
1
MA
SB#
SU
INON_EC
MA
INON_EC 37
A A
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
PCH 2/6 (SATA/HDA/ SPI)
PCH 2/6 (SATA/HDA/ SPI)
PCH 2/6 (SATA/HDA/ SPI)
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
1A
1A
1A
10 49Monday, September 07, 2015
10 49Monday, September 07, 2015
10 49Monday, September 07, 2015
of
of
of
5
D D
PEG_TXP11_L134
PEG
_TXN11_L134
PEG
_RXP11_L134
PEG
_RXN11_L134
_TXP12_L334
PEG
_TXN12_L334
PEG
PEG_RXP12_L334
PEG
C C
100
TP
C8
6512P/50V_4
1
2
R6
HZ +-30PPM
24M
TP
B B
73
1M_4
Y4
4
3
6212P/50V_4
C8
99
+1.0V_DEEP_SUS change to +1V_S5
Add XC LK_RNIAS# po rt_20 141205
C Clock 32.768KHz
RT
A A
61 18P/5 0V_4
C8
32.
C864 18P /50V_4
Y3
768KHz
C_X1
RT
12
75
R6
10M_4
RTC_X2
5
24M X'tral--->R2602 (Ra) Un-Install
XT
AL24_IN
Green CLK--->R2602 (Ra) Install
AL24_OUT
XT
K_PEGA_REQ#19
CL
IE_CLKREQ_WLAN#34
PC
CL
K_PCIE_LAN_REQ#31
PCIE_CLKREQ_NGFF1#34
_RXN12_L334
+1
V_S5
24 *SHORT_4
R3
76 *SHORT_4
R2
R724 *SHORT_4
58 *SHORT_4
R4
CL
K_DPLL_NSCCLKP2
CL
K_DPLL_NSCCLKN2
CL
CL
R6
68 2.7K/F_4
K_CPU_BCLKP2
K_CPU_BCLKN2
4
PEG
_TXP11_L1
_TXN11_L1
PEG
_RXP11_L1
PEG
_RXN11_L1
PEG
PEG
_TXP12_L3
PEG
_TXN12_L3
PEG
_RXP12_L3
_RXN12_L3
PEG
XTAL24_OUT
XT
XC
LK_RBIAS
RT
C_X1
C_X2
RT
IE_CLKREQ0#
PC
PCIE_CLKREQ1#
PC
IE_CLKREQ2#
PCIE_CLKREQ3#
IE_CLKREQ4#
PC
IE_CLKREQ5#
PC
PC
IE_CLKREQ6#
IE_CLKREQ7#
PC
PC
IE_CLKREQ8#
IE_CLKREQ9#
PC
PC
IE_CLKREQ10#
PC
IE_CLKREQ11#
PC
IE_CLKREQ12#
PC
IE_CLKREQ13#
PCIE_CLKREQ14#
IE_CLKREQ15#
PC
4
AL24_IN
U45C
AV2
_CLK
CL
AV3
CL
_DATA
AW2
CL
_RST#
R44
G
PP_G8/FAN_PWM_0
R43
PP_G9/FAN_PWM_1
G
U39
G
PP_G10/FAN_PWM_2
N42
G
PP_G11/FAN_PWM_3
U43
G
PP_G0/FAN_TACH_0
U42
G
PP_G1/FAN_TACH_1
U41
PP_G2/FAN_TACH_2
G
M44
PP_G3/FAN_TACH_3
G
U36
G
PP_G4/FAN_TACH_4
P44
PP_G5/FAN_TACH_5
G
T45
G
PP_G6/FAN_TACH_6
T44
PP_G7/FAN_TACH_7
G
B33
PC
IE11_TXP
C33
PCIE11_TXN
K31
IE11_RXP
PC
L31
PC
IE11_RXN
AB33
PP_F10/SCLOCK
G
AB35
G
PP_F11/SLOAD
AA44
PP_F13/SDATAOUT0
G
AA45
G
PP_F12/SDATAOUT1
B38
IE14_TXN/SATA1B_T XN
PC
C38
PC
IE14_TXP/SATA1B_T XP
D39
PC
IE14_RXN/SATA1B_RXN
E37
IE14_RXP/SATA1B_RXP
PC
C36
PC
IE13_TXN/SATA0B_T XN
B36
IE13_TXP/SATA0B_T XP
PC
G35
PC
IE13_RXN/SATA0B_RXN
E35
IE13_RXP/SATA0B_RXP
PC
A35
PC
IE12_TXP
B35
IE12_TXN
PC
H33
PC
IE12_RXP
G33
PC
IE12_RXN
J45
IE20_TXP/SATA7_T XP
PC
K44
PC
IE20_TXN/SATA7_T XN
N38
IE20_RXP/SATA7_RXP
PC
N39
PC
IE20_RXN/SATA7_RXN
H44
PC
IE19_TXP/SATA6_T XP
H43
IE19_TXN/SATA6_T XN
PC
L39
PC
IE19_RXP/SATA6_RXP
L37
PCIE19_RXN/SATA6_RXN
SPT_PCH_H
AR17
GP
G1
CL
F1
CL
G2
CL
H2
CL
A5
XT
A6
XT
E1
XC
BC9
RT
BD10
RT
BC24
GP
AW24
GPP_B6/SRCCLKREQ1#
AT24
GP
BD25
GP
BB24
GP
BE25
GP
AT33
GP
AR31
GP
BD32
GPP_H2/SRCCLKREQ8#
BC32
GP
BB31
GP
BC33
GP
BA33
GP
AW33
GP
BB33
GP
BD33
GPP_H9/SRCCLKREQ15#
R13
CL
R11
CL
P1
CL
R2
CL
W7
CL
Y5
CL
U2
CL
U3
CL
U45G
P_A16/CLKOUT_48
KOUT_CPUNSSC_P
KOUT_CPUNSSC
KOUT_CPUBCLK_P
KOUT_CPUBCLK
AL24_OUT
AL24_IN
LK_BIASREF
CX1
CX2
P_B5/SRCCLKREQ0#
P_B7/SRCCLKREQ2#
P_B8/SRCCLKREQ3#
P_B9/SRCCLKREQ4#
P_B10/SRCCLKREQ5#
P_H0/SRCCLKREQ6#
P_H1/SRCCLKREQ7#
P_H3/SRCCLKREQ9#
P_H4/SRCCLKREQ10#
P_H5/SRCCLKREQ11#
P_H6/SRCCLKREQ12#
P_H7/SRCCLKREQ13#
P_H8/SRCCLKREQ14#
KOUT_PCIE_N15
KOUT_PCIE_P15
KOUT_PCIE_N14
KOUT_PCIE_P14
KOUT_PCIE_N13
KOUT_PCIE_P13
KOUT_PCIE_N12
KOUT_PCIE_P12
SPT_PCH_H
3
SPT-H_PCH
G31
SAT
CL
INK
FAN
-H_PCH
SPT
7
PC
Ie/SATA
ST
HO
3 OF 12
CL
KOUT_CPUPCIBCLK_P
CL
OF 12
GP
GP
GP
G
G
G
G
G
CL
KOUT_CPUPCIBCLK
CL
CLKOUT_PCIE_P10
CL
CLKOUT_PCIE_P11
PC
IE9_RXN/SATA0A_RXN
PC
IE9_RXP/SATA0A_RXP
IE9_TXN/SATA0A_T XN
PC
PC
IE9_TXP/SATA0A_T XP
PC
IE10_RXN/SATA1A_RXN
PC
IE10_RXP/SATA1A_RXP
IE10_TXN/SATA1A_T XN
PC
PC
IE10_TXP/SATA1A_T XP
IE15_RXN/SATA2_RXN
PC
IE15_RXP/SATA2_RXP
PC
PC
IE15_TXN/SATA2_T XN
IE15_TXP/SATA2_T XP
PC
IE16_RXN/SATA3_RXN
PC
IE16_RXP/SATA3_RXP
PC
PC
IE16_TXN/SATA3_T XN
PCIE16_TXP/SATA3_T XP
PC
IE17_RXN/SATA4_RXN
PC
IE17_RXP/SATA4_RXP
IE17_TXN/SATA4_T XN
PC
PC
IE17_TXP/SATA4_T XP
PC
IE18_RXN/SATA5_RXN
PC
IE18_RXP/SATA5_RXP
IE18_TXN/SATA5_T XN
PC
PC
IE18_TXP/SATA5_T XP
P_E8/SATALED#
GP
P_E0/SATAXPCIE0/SATAGP0
P_E1/SATAXPCIE1/SATAGP1
P_E2/SATAXPCIE2/SATAGP2
PP_F0/SATAXPCIE3/SATAGP3
PP_F1/SATAXPCIE4/SATAGP4
PP_F2/SATAXPCIE5/SATAGP5
PP_F3/SATAXPCIE6/SATAGP6
PP_F4/SATAXPCIE7/SATAGP7
G
PP_F21/EDP_BKLTCTL
PP_F20/EDP_BKLTEN
G
G
PP_F19/EDP_VDDEN
TH
ERMTRIP#
_SYNC
PM
PL
TRST_PROC#
PM_DOWN
L1
KOUT_ITPXDP
CL
KOUT_ITPXDP_P
KOUT_PCIE_N0
CL
KOUT_PCIE_P0
CL
KOUT_PCIE_N1
CL
CL
KOUT_PCIE_P1
KOUT_PCIE_N2
CL
CL
KOUT_PCIE_P2
CL
KOUT_PCIE_N3
CLKOUT_PCIE_P3
KOUT_PCIE_N4
CL
KOUT_PCIE_P4
CL
CL
KOUT_PCIE_N5
KOUT_PCIE_P5
CL
CL
KOUT_PCIE_N6
KOUT_PCIE_P6
CL
CL
KOUT_PCIE_N7
CL
KOUT_PCIE_P7
CLKOUT_PCIE_N8
CL
KOUT_PCIE_P8
KOUT_PCIE_N9
CL
CL
KOUT_PCIE_P9
KOUT_PCIE_N10
KOUT_PCIE_N11
L2
J1
J2
N7
N8
L7
L5
D3
F2
E5
G4
D5
E6
D8
D7
R8
R7
U5
U7
W10
W11
N3
N2
P3
P2
R3
R4
H31
C31
B31
G29
E29
C32
B32
F41
E41
B39
A39
D43
E42
A41
A40
H42
H40
E45
F45
K37
G37
G45
G44
AD44
AG36
AG35
AG39
AD35
AD31
AD38
AC43
AB44
W36
W35
W42
AJ3
AL3
PEC
I
AJ4
AK2
AH2
_XDP_N_R
CK
_XDP_P_R
CK
A_RXN3/PEG_RXN9_L0
SATA_RXP3/PEG_RXP9_L0
SAT
A_TXN3/PEG_TXN9_L0
SAT
A_TXP3/PEG_TXP9_L0
A_RXN1/PEG_RXN10_L2
SAT
SAT
A_RXP1/PEG_RXP10_L2
A_TXN1/PEG_TXN10_L2
SAT
A_TXP1/PEG_TXP10_L2
SAT
SAT
A_LED#
83 10K_4
R7
IO37
GP
IO34
GP
GPIO35
GPIO36
PCH_THRMTRIP_R#
PM_SYNC_R
H_
PM_DOWN
61 *short_4
R6
56 *short_4
R6
CP
CP
TP
TP
CL
CL
CL
CL
TP
TP40
TP44
TP
TP
TP
CL
CL
R643 30_4
R6
28 *SHORT_4
U_PCI_BCLKN 2
U_PCI_BCLKP 2
K_PCIE_VGA# 19
CL
K_PCIE_VGA 19
CL
47
42
K_PCIE_WLA NN 34
K_PCIE_WLA NP 34
K_PCIE_LANN 31
K_PCIE_LANP 31
39
41
69
68
K_PCIE_NGFF1_N 34
K_PCIE_NGFF1_P 34
TP
110
52
TP
PC
H_BRIGHT 29
PC
H_BLON 29
ED
P_VDD_EN 29
R627 620_ 4
_XDP_N
CK
_XDP_P
CK
WL
LAN
SAT
SAT
SAT
SAT
+3
V
6 0_4
R8
5 *0_4
R8
R461 *0_4
R4
59 *0_4
_SYNC 2
PM
U_PLTRST#R 2
CP
PM_DOWN 2
H_
CK
CK
A
VG
AN
FF SSD
NG
A_RXN3/PEG_RXN9_L0 34
SAT
A_RXP3/PEG_RXP9_L0 34
SAT
A_TXN3/PEG_TXN9_L0 34
SAT
A_TXP3/PEG_TXP9_L0 34
SAT
SAT
A_RXN1/PEG_RXN10_L2 34
SAT
A_RXP1/PEG_RXP10_L2 34
SAT
A_TXN1/PEG_TXN10_L2 34
SAT
A_TXP1/PEG_TXP10_L2 34
A_RXN0 33
A_RXP0 33
A_TXN0 33
A_TXP0 33
_THRMTRIP# 2,5,17,18
PM
_XDP_N 1 6
_XDP_P 16
2
M.2.SSD
HDD (SATA0 6Gb/s)
FF3_DET 34
NG
H_PECI 2
PC
R6
44
*10K_4
PC
IE_CLKREQ4#
PCIE_CLKREQ1#
PCIE_CLKREQ0#
IE_CLKREQ2#
PC
IE_CLKREQ3#
PC
IE_CLKREQ5#
PC
PC
IE_CLKREQ6#
PC
IE_CLKREQ7#
IE_CLKREQ8#
PC
IE_CLKREQ9#
PC
PC
IE_CLKREQ10#
PC
IE_CLKREQ11#
PC
IE_CLKREQ12#
PCIE_CLKREQ13#
PCIE_CLKREQ14#
IE_CLKREQ15#
PC
GP
IO37
IO34
GP
IO35
GP
IO36
GP
0821*10K_4
R1
R7
R275 *10K_4
R718 10K_4
R2
R7
R7
R3
R3
R7
R7
R7
R7
R3
R316 *10K_4
R7
R7
0818*10K_4
0819*10K_4
0820*10K_4
R1
R1
R1
19 *10K_4
78 10K_4
23 10K_4
21 *10K_4
18 *10K_4
17 10K_4
36 *10K_4
35 *10K_4
31 *10K_4
39 *10K_4
15 *10K_4
38 *10K_4
34 *10K_4
R1
0814 10K _4
0816 10K _4
R1
0817 10K _4
R1
0815 10K _4
R1
+3
V
1
11
+3
V
Change from I to NI(For SCH List) _20141212
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Cu
Cu
Cu
stom
stom
stom
PC
PC
PC
H 3/6 (PCIE/USB/CLK)
H 3/6 (PCIE/USB/CLK)
H 3/6 (PCIE/USB/CLK)
Date: Sheet
Date: Sheet
3
2
Date: Sheet
1
1A
1A
1A
of
of
of
11 49Tuesday, Augu st 25, 2015
11 49Tuesday, Augu st 25, 2015
11 49Tuesday, Augu st 25, 2015
5
TRST# Buffer
PL
TRST#(CLG)
PL
-H_PCH
D D
SI
O_EXT_SMI#9,37
C C
SP@
socket P/N: DFHS08FS023 only for A-TEST
SPI
ROM
ylake
Sk
3.3V
B B
Skylake
3.3V
A A
TP103
PCH_SPI_SI
PC
H_SPI_SO
H_SPI_CS0#
PC
H_SPI_CLK
PC
PCH_SPI_CS1#
PC
H_SPI_IO2
H_SPI_IO3
PC
O_EXT_SMI#
SI
Ve
nder Siz e Quanta P/N Vender P/N
EO
N
D
WN
PC
H_SPI_CLK_EC37
PCH_SPI_SI_EC37
H_SPI_SO_EC37
PC
SPI_CS0#_UR_ME37
V_PCH_ME
+3
16M
8M
8M
8M
AKE3
AKE2
AKE3EZN0Q01
AKE3DZN0N01
R6
94 10K_4
EFP0N07
EZN0Q00
R774 *4M@33_4
48 *4M@33_4
R7
R6
98 *4M@33_4
07 *SHORT_4
R7
R7
11 *4M@0_4
5
AG15
AG14
AF17
AE17
AR19
AN17
BB29
BE30
BD31
BC31
AW31
BC29
BD30
AT31
AN36
AL39
AN41
AN38
AH43
AG44
W2
GD
EN
25QH64-104HIP
W2
SPI_CS0#_UR_ME
GPP_A11/PM E#
RSVD
RSVD
RSVD
RSVD
TP2
TP1
SPI0_MOSI
SPI0_MISO
SPI0_CS0#
SPI0_CLK
SPI0_CS1#
SPI0_IO2
SPI0_IO3
SPI0_CS2#
GPP_D1/SPI1_C LK
GPP_D0/SPI1_C S#
GPP_D3/SPI1_M OSI
GPP_D2/SPI1_M ISO
GPP_D22/SPI1_ IO3
GPP_D21/SPI1_ IO2
SPT_PCH_H
5Q64FVSSIQWND
25B64CSIGRGGD
5Q128FVSIQ
H_SPI_CLK_R
PC
PC
H_SPI_SI_R
PC
H_SPI_SO_R
PC
H_SPI_CS0#
PC
H_SPI_CS1#
U45A
BD17
PCI_PME#
SPT
H_SPI_SO
PC
PCH_SPI_SO_EC
only 0ohm option
GPP_B13/PL TRST#
GPP_G16/GSXCL K
GPP_G12/GSXDOU T
GPP_G13/GSXS LOAD
GPP_G14/GSXDIN
GPP_G15/GSXS RESET#
GPP_E3/CPU_ GP0
GPP_E7/CPU_ GP1
GPP_B3/CPU_ GP2
GPP_B4/CPU_ GP3
GPP_H18/SML 4ALERT#
GPP_H17/SML 4DATA
GPP_H16/SML 4CLK
GPP_H15/SML 3ALERT#
GPP_H14/SML 3DATA
GPP_H13/SML 3CLK
GPP_H12/SML 2ALERT#
GPP_H11/SML 2DATA
GPP_H10/SML 2CLK
1
INTRUDER #
OF 12
H SPI ROM(8M+4M)
PC
15ohm CS01502JB12
33ohm CS03302JB29
PC
H_SPI_CS0#
1A-13
08 8M4M@15_4
R7
09 8M@0_4
R7
+3
V_PCH_ME
3.
3K is original and for no
support fast read function
PC
H_SPI_CS1#
PC
H_SPI_CLK
PCH_SPI_SI
PCH_SPI_SO
76 *22p/50V_4
C8
+3
R710 1K_4
R7
47 *4M@33_4
R7
75 *4M@33_4
R712 *4M@33_4
PC
H_SPI_CLK_R
PCH_SPI_SI_R
PCH_SPI_SO_R
V_PCH_ME
1A-3 2013/10/16 Add U34 flash 4M ROM reserve for ZQ0D.
BB27
P43
R39
R36
R42
R41
AF41
AE44
BC23
BD24
BC36
BE34
BD39
BB36
BA35
BC35
BD35
AW35
BD34
BE11
PCI_PLTRST#
DG
SML4ALERT#
SM
B_ME4_DAT
B_ME4_CLK
SM
L3ALERT#
SM
SMB_ME3_DAT
SMB_ME3_CLK
SM
L2ALERT#
B_ME2_DAT
SM
B_ME2_CLK
SM
SM_INTRUDER#
_SO_8M
SPI
H_SPI_IO2
PC
PCH_SPI_IO3
R7
03 *1K_4
4
PU_PW_CTRL#
+3V_S5
1
2
3
4
SPI_WP_IO2_ME
4
2
1
R3
05 *0_4
DGPU_PW_CTRL# 13
TP107
R6771M_4
R7
54 *SHORT_6
U47
VCC
CS#
IO3/HOLD #
IO1/DO
CLK
IO2/W P#
IO0/DI
GND
W25Q64FW -- 8MB
H_SPI_CLK_EC
PC
PC
H_SPI_SI_EC
R713 *4M@33_4
R702 8M4M@15_4
R7
46 *4M@33_4
R7
73 8M4M@15_4
U46
1
CE#
VDD
6
SCK
5
SI
2
SO
HOLD#
3
WP#
VSS
*4M@ROM-4M_EC
SPI
_WP_IO2_EC
+3
V
C518 0.1u/16V_4
U2
4
3 5
TC7SH08FU
V_RTC
+3
8
7
SPI
6
SPI_CLK_8M
5
SPI
R7
44 8M@15_4
R7
45 8M@15_4
SPI_HOLD_IO3_ME
8
7
SPI_HOLD_IO3_EC
4
3
4
+3V_PCH_ME
_HOLD_IO3_ME
_SI_8M
SPI_WP_IO2_EC
_WP_IO2_ME
SPI
SPI
_HOLD_IO3_EC
PL
TRST# 2,16,19,31,33,34,37
07
R3
100K_4
C873 0.1u/16V_4
43 1K_4
R7
R770 8M4M@15_4
R7
71 8M4M@15_4
reserve for SPI fast read
+3V_PCH_ME
R772 *1K_4 R729
C8
74
*4M@0.1u/16V_4
V_PCH_ME
+3
PCH_SPI_CLK
H_SPI_SI
PC
C875
*22p/50V_4
SM
SMB_ME4_DAT
SM
SM
SMB_ME2_CLK
SM
R7
B_ME4_CLK
B_ME3_CLK
B_ME3_DAT
B_ME2_DAT
49 499/F_4
37 499/F_4
R7
R741 499/F_4
26 499/F_4
R3
R742 499/F_4
R3
25 499/F_4
TLS CONFIDENTIALITY ENABLED
HIGH:T Enable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (with confidentiality). (CRB)
LOW: Disable Intel ME Crypto Transport Layer Security
(TLS) cipher suite (no confidentiality). (Default)
BALERT#10
SM
3
+3V_DEEP_SUS
Ad
d PCH Strap Pin_20141203
TOP SWAP OVERRIDE STRAP
HIGH:TOP SWAP ENABLED (CRB)
LOW:TOP SWAP DISABLED(DEFAULT)
AC
Z_SPKR10,32
NO
REBOOT IF SAMPLED HIGH
HIGH:TOP SWAP ENABLED (CRB)
LOW: Disable "No Reboot" mode. (Default)
BBS_
V_DEEP_SUS
+3
R333
4.7K_4
32
R3
*20K/F_4
BIT1
BBS_
BIT113
SMBALERT#
Ch
ange R2725 from I to N_20141212
+3V
R7
*150K/F_4
+3
V
BOOT SELE CT STRAP
HIGH:LPC
LOW: SPI. (Default)
27
R722
*20K/F_4
ESPI
HIGH:eSPI Is selected for EC.
LOW: LPC Is selected for EC. (Default)
R337
4.7K_4
SML0ALERT#10
R336
*20K/F_4
RESERVED
This strap should sample HIGH.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
GPIO13
S_
/LPC SELECT STRAP
SM
L0ALERT#
+3
PCH_SPI_SI
S_GPIO
V_DEEP_SUS
*20K/F_4
28
R7
*4.7K_4
2
+3V_DEEP_SUS
R766
*4.7K_4
R767
*20K/F_4
+3
V_DEEP_SUS
R335
*4.7K_4
R334
4.7K/F_4
CONFIDENTIALITY ENABLED
TLS
HIGH: Flash Descriptor Security (override). This
strap should only be asserted high using external
pull-up in manufacturing/debug environments ONLY.(CRB)
LOW: security measures defined in the Flash
Descriptor. (Default)
2
RESERVED
This strap should sample HIGH.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
PC
H_SPI_SO
RESERVED
This strap should sample LOW.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
SM
SERVED
SERVED
ME
+3
_WR#
B1ALERT#
H_SPI_IO2
PC
PCH_SPI_IO3
V_DEEP_SUS
R6
40
*1K_4
B1ALERT#10,35
SM
RE
This strap should sample HIGH.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
RE
This strap should sample HIGH.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
ME
_WR#10,37
R653
*1K_4
+3
+3
V_DEEP_SUS
1
V_DEEP_SUS
R3
*20K/F_4
R2
*4.7K_4
R2
*4.7K_4
R2
*20K/F_4
+3V_DEEP_SUS
*20K/F_4
R726
*4.7K_4
+3
*20K/F_4
ESPI
01
98
92
94
30
R7
V_DEEP_SUS
R733
R7
32
*100_4
FLASH SHARING MODE
HIGH:SLAVE ATTACEHD FLASH SHARING
LOW: 0: MASTER ATTACHED FLASH SHARING
This strap should sample LOW.
There should NOT be any on-board device
driving it to opposite direction during
strap sampling.
DFX TEST MODE QUALIFIER FOR OTHER DFX STRAP
WHEN SAMPLED LOW
PGDMON15
X TEST MODE
DF
XTAL INPUT IS SINGLE ENDED IF
SAMPLED LOW ELSE DIFFERENTIAL
PU_PWROK13,21
DG
RING OSCILLATOR BYPASS
PU_HOLD_RST#13,19
DG
DG
PU_PWR_EN13,47
XTAL INPUT FREQUENCY[1]
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Cu
Cu
Cu
stom
stom
stom
H 4/6 (GPIO/MISC)
H 4/6 (GPIO/MISC)
H 4/6 (GPIO/MISC)
PC
PC
PC
Date: Sheet of
Date: Sheet of
Date: Sheet of
1
SML2ALERT#
DMON
PG
DG
PU_PWROK
DGPU_HOLD_RST#
DGPU_PWR_EN
+3V_DEEP_SUS
V_DEEP_SUS
+3
+3
V_DEEP_SUS
R2
*10K_4
12
R751
*4.7K_4
R740
*20K/F_4
66
R2
*1K_4
R264
*1K_4
R2
81
*10K_4
93
R2
*10K_4
R2
*10K_4
88
12 49Monday , S ept ember 07, 201 5
12 49Monday , S ept ember 07, 201 5
12 49Monday , S ept ember 07, 201 5
87
1A
1A
1A
5
+3
V
I_SERR#
PC
R7
88*10K_4
V_S5
1
R7
GP
U Control PU/PD
96EV@10K_4
83*10K_4
DG
R3
09*10K_4
DG
PU_PW_CTRL#
DG
DG
PU_PWROK
CRT_HPD
ED
37100K_4
V
+3
2
2N7002K
78 *0_4
VG
PU_EN
PU_PWR_EN
6_FB_EN
GC
PU_HOLD_RST#
P_HPD
24 *10K/F_4
R6
+3
R7
Q4
69TPD@10K_4
3
6
R7
R2
TP
D_INT#_D
15 *IV@1K_4
86 *10K_4
+3
S5
R2
01*IV@10K_4
82*100K_4
R2
R3
13*10K_4
+3
V
V
+3V_DEEP_SUS
ED
P_HPD29
uchpad INT
To
D_INT#_D
TP
TP
D_INT#35,37
+3
V
V
+3
DG
PU_PW_CTRL#12
S5
20131015 For GC6 NV DG GC6_FB_EN PD.1A-1
R274 10K_4
high UMA Only
low
R7
14 EV@100K_4
R1
R2
GPU power is control by PCH
GPIO (Discrete, SG or Optimize)
D D
C C
DGPU_PWROK PD on GPU side
R652100K_4
R6
100k pull-down on PCH side
ylake-H Strapping Table
Sk
B B
A A
n Name Strap description
Pi
GP
P_B14 (SPKR)
GPP_B18
(GSPI0_MOSI)
GPP_C2
(SMBALERT#)
GPP_B22
(GSPI1_MOSI)
GPP_C5
(SML0ALERT#)
SPI0_MOSI
SPI0_MISO
GPP_B23
(SML1ALERT#
/PCHHOT#)
SPI0_IO2
SPI0_IO3
HDA_SDO /
I2S_TXD0
GPP_E19
(DDPB_CTRLDATA)
GPP_E21
(DDPC_CTRLDATA)
Top-Block Swap override PCH_PWROK
No reboot PCH_PWROK
TLS Confidentiality
Boot BIOS Strap Bit (BBS)
eSPI or LPC
Reserved
Reserved
Reserved
Reserved
Reserved
F
lash Descriptor Security
Override / Intel ME Debug Mode
splay Port B Detected
Di
Display Port C Detected
Sa
mpled
RSMRST#
PCH_PWROK
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
RSMRST#
PCH_PWROK
PCH_PWROK
PCH_PWROK
0 = *Disable Top Swap (iPD 20K)
1 = Enable Top Swap Mode
0 = *Disable No Reboot (iPD 20K)
1 = Enable No Reboot Mode
0 = *Disable Intel ME Cryp to TLS(iPD 20K)
1 = Enable Intel ME Cryp to TLS
0 = *SPI (iPD 20K)
1 = LPC
0 = *LPC is selected for EC (iPD 20K)
1 = eSPI selected for EC
0 = *Enable security in the Flash
Description (iPD 20K)
1 = Disable Flash Descriptor Security (Override)
0 = *Port B is not detected (iPD 20K)
1 =Port B is detected
0 = *Port C is not detected (iPD 20K)
1 =Port C is detected
4
Ad
d G PU Pow er C on tro l Si gan ls
TP
BBS_
_EXTTS#017
PM
EXT
GPIO12
S_
I_SERR#
To
uch Screen
To
PC
uch PAD
waiting for define!
30 10K_4
P_HPD
ED
AW4
GP
AY2
CRT
_HPD
GP
AV4
GP
BA4
GPP_I3/DDPE_HPD3
BD7
GP
T_HDMI_HPD30
IN
CRT
_HPD28
38
TP
SI
O_EXT_SCI#37
R2
figuration note
Con
(iPU 15 ~ 40K)
(iPU 15 ~ 40K)
(iPD 20K)
(iPU 15 ~ 40K)
(iPU 15 ~ 40K)
DG
PU_HOLD_RST#12,19
DG
147
BIT112
_INT_PCH29
TP
CEL_INTA#35
AC
TS#117
87 *100_4
R7
I2
C1_SCL29
C1_SDA29
I2
C0_SCL35
I2
I2
C0_SDA35
U45E
P_I0/DDPB_HPD0
P_I1/DDPC_HPD1
P_I2/DDPD_HPD2
P_I4/EDP_HPD
SPT_PCH_H
V
+3
+3
V
3
2
V_DEEP_SUS9,10,12,14,16,17
+3
1
13
-H_PCH
U45K
AT29
GS
PI1_MOSI
GP
P_B22/GSPI1_MOSI
GS
PI0_MOSI
D_INT#_D
TP
RT2_CTS
UA
UA
RT2_RTS
UA
RT2_TXD
RT2_RXD
UA
GPP_I7/DDPC_CTRLCLK
P_I8/DDPC_CTRLDATA
GP
P_I5/DDPB_CTRLCLK
GP
GP
P_I6/DDPB_CTRLDAT A
GPP_I9/DDPD_CTRLCLK
GP
P_I10/DDPD_CTRLDATA
GS
GS
PI1_MOSI
AR29
GPP_B21/GSPI1_MISO
AV29
GP
BC27
GP
BD28
GP
BD27
GP
AW27
GP
AR24
GP
AV44
GP
BA41
GP
AU44
GP
AV43
GP
AU41
GP
AT44
GP
AT43
GP
AU43
GPP_C12/UART1_RXD/IS H_UART1_RXD
AN43
GP
AN44
GP
AR39
GP
AR45
GP
AR41
GP
AR44
GP
AR38
GP
AT42
GP
AM44
GP
AJ44
GP
BB3
BD6
BA5
BC4
BE5
BE6
Y44
P_F14
GP
V44
P_F23
GP
W39
GP
P_F22
L43
P_G23
GP
L44
P_G22
GP
U35
GP
P_G21
R35
GP
P_G20
BD36
GP
P_H23
PI0_MOSI
P_B20/GSPI1_CLK
P_B19/GSPI1_CS#
P_B18/GSPI0_MOSI
P_B17/GSPI0_MISO
P_B16/GSPI0_CLK
P_B15/GSPI0_CS#
P_C9/UART0_TXD
P_C8/UART0_RXD
P_C11/UART0_CTS#
P_C10/UART0_RTS#
P_C15/UART1_CTS#/IS H_UART1_CTS#
P_C14/UART1_RTS#/IS H_UART1_RTS#
P_C13/UART1_TXD/IS H_UART1_TXD
P_C23/UART2_CTS#
P_C22/UART2_RTS#
P_C21/UART2_TXD
P_C20/UART2_RXD
P_C19/I2C1_SCL
P_C18/I2C1_SDA
P_C17/I2C0_SCL
P_C16/I2C0_SDA
P_D4/ISH_I2C2_SDA/ISH_I 2C3_SDA
P_D23/ISH_I2C2_SCL/ISH_I2C 3_SCL
SPT_PCH_H
PU_EVENT#22
GC
6_FB_EN19,22
DGPU_PWROK12,21
DG
PU_PWR_EN12,47
VG
PU_EN46
OD
D_PRSNT#
BBS_BIT1
68 *0_4
R7
AC
CEL_INTA#
TP
112
C1_SCL
I2
I2
C1_SDA
I2
C0_SCL
I2C0_SDA
SPT
-H_PCH
OF 12
5
25 *1K_4
R7
17 *1K_4
R7
SPT
P_D14/ISH_UART0_TXD /SML0BCLK/I2C2_SCL
GP
P_D13/ISH_UART0_RXD/S ML0BDATA/I2C2_SDA
GP
11
_CLK
CRT
CRT
_DATA
OCC_N_R
SKT
Ne
w CN to CPU_201412 03
CRT
_CLK
R2
_DATA
CRT
R6
OF 12
I_DDCCLK_SW 30
HDM
HDM
I_DDCDATA_SW 30
TP
50
TP
36
SKT
OCC_N_R 2
11 2.2K_4
38 2.2K_4
GP
P_D16/ISH_UART0_CTS #
GP
P_D15/ISH_UART0_RTS #
P_H20/ISH_I2C0_SCL
GP
GP
P_H19/ISH_I2C0_SDA
GPP_H22/ISH_I2C1_SCL
GP
P_H21/ISH_I2C1_SDA
GP
P_A23/ISH_GP5
GP
P_A22/ISH_GP4
P_A21/ISH_GP3
GP
GP
P_A20/ISH_GP2
P_A19/ISH_GP1
GP
GP
P_A18/ISH_GP0
GP
P_A17/ISH_GP7
V
+3
GP
GP
GP
GPP_D9
P_D10
P_D11
P_D12
Bo
ard_ID4 29
Low
VRAM 2GB VRAM 4GB
Reserved
(Default)
TPM
No touch panel
ard ID
R7
94 10K_4
R3
20 10K_4
23 10K_4
R3
63 *10K_4
R2
04 10K_4
R7
R7
00 *10K_4
R6
99 *10K_4
91 *10K_4
R9
86 10K_4
R9
R7
65 *IV@10K_4
High
Reserve
G-sensor No G-sensor
No TPM
touch panel
RA
RA
RA
Board_ID0
Bo
Bo
Bo
Board_ID4
Bo
Bo
M_ID1
M_ID2
M_ID3
ard_ID1
ard_ID2
ard_ID3
ard_ID5
ard_ID6
SKU
_ID0
R7
86 EV@10K_4
UMA Only
dGPU Only
AL44
_ID0
SKU
AL36
M_ID3
RA
AL35
M_ID2
RA
AJ39
M_ID1
RA
AJ43
AL43
AK44
AK45
BC38
BB38
BD38
BE39
BC22
ARD_ID6
BO
BD18
BOARD_ID5
BE21
ARD_ID4
BO
BD22
BO
ARD_ID3
BD21
BO
ARD_ID2
BB22
BOARD_ID1
BC19
BO
ARD_ID0
Bo
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
R7
85 *10K_4
R3
22 *10K_4
27 *10K_4
R3
61 10K_4
R2
05 *10K_4
R7
R7
01 10K_4
R7
06 10K_4
R695 10K_4
90 10K_4
R9
87 *10K_4
R9
SKU_ID0
0
1
+3
V_DEEP_SUS
+3
V_DEEP_SUS
VGA H/W
Signal
UMA
GPU
Setup
Menu
Hidden
Hidden
UMA boot
GPU boot
HighLow
Reserved
BOARD_ID5
BOARD_ID6
Reserve UART FFC connect or for Win 7 debug
UA
RT2_RXD
UART2_TXD
UART2_RTS
RT2_CTS
UA
RT2_RXD
UA
RT2_TXD
UA
UART2_RTS
UA
RT2_CTS
(Before C1)
(Default)
R8
02 *49.9K/F_4
R799 *49.9K/F_4
R7
98 *49.9K/F_4
95 *49.9K/F_4
R7
+5V
4
CN1
1
2
3
7
4 8
5
6
*UART Function
Reserved
(After C2)
ReserveReserved
+3
V_S5
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Size Document Number Rev
Size Document Number Rev
Size Document Number Rev
Custom
Custom
Custom
PCH 4/6 (GPIO/MISC )
PCH 4/6 (GPIO/MISC )
PCH 4/6 (GPIO/MISC )
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
1
1A
1A
1A
13 49Tuesday, September 08, 2015
13 49Tuesday, September 08, 2015
13 49Tuesday, September 08, 2015
of
of
of
5
4
3
2
1
14
SPT
-H_PCH
CORE
MPHY
USB
8
VCCGPIO
OF 12
CPRIM_1P0
VC
VC
CDSW_3P3
VC
VC
CPGPPBCH
VC
CPGPPBCH
CPGPPEF
VC
CPGPPEF
VC
VC
CPGPPG
VCCPRIM_3P3
VC
CPRIM_1P0
CRTCPRIM_3P3
VC
CPRIM_1P0
VC
VC
CPRIM_1P0
VC
CPRIM_1P0
CPRIM_1P0
VC
VCCPGPPD
CPGPPD
VC
VC
CPGPPD
VC
CPGPPD
CPRIM_3P3
VC
VC
CPRIM_3P3
VC
CPRIM_3P3
CPGPPA
CATS
VC
VC
CRTC
DCP
RTC
VC
CSPI
CSPI
VC
CSPI
VC
AL22
BA24
BA31
BC42
BD40
AJ41
AL41
AD41
AN5
AD15
AD13
BA20
BA22
BA26
AJ20
AJ21
AJ23
AJ25
BE41
BE43
BE42
BC44
BA45
BC45
BB45
BD3
BE3
BE4
0.0908A
0.403A
0.0879A
0.27262A
0.14107A
0.1318A
0.2875A
+VCCPRI
+VCCAT
+VCCRT
DCPRT
+VCCPRI
0.0121A
0.081A
M_1.0V_AL22
+VCCPRI
+VCCPG
+VCCPG
+VCCPRI
C4
73 *0.1U/16V_4
M_1.0V_AJ20_AD15
0.0066A
S
0.
CPRIM_3.3V
C5
C
09 0.1U/16V_4
M_1.0V_AJ20
92 0.1U/16V_4
C4
+VCCSPI
PPD
+VCCPG
PPA
PPEF
M_3P3
002A
C4
67 *1U/6.3V_4
R2
45 *SHORT_6
44 *SHORT_6
R2
57 *SHORT_6
R2
**L
60*SHORT _6
R2
C5
C4
C5
C8
21*SHORT _6
R2
R2
77*SHORT _6
081U/6.3V_4
+VCCDSW
93*1U /6.3V_4
+VCCPG
29*0.1U/16 V_4
79*0.1U/16 V_4
+VCCPG
+3V_DEEP_SUS
+3V_DEEP_SUS
+3V_DEEP_SUS
+3V_RT
C
+1V_S5
PPBCH
+1V_S5
+1V_S5
PPG
3P3
+VCCPG
PPEF
R3
14*SHORT_6
28*SHORT_6
R3
R7
R7
96*SHORT_6
+VCCPG
ayout Note: +VCCPRIM_1P0 total :5.5167A**
R7
53*SHORT _6
52*SHORT_6
R7
+3V_DEEP_SUS
+3V_DEEP_SUS
+3V_DEEP_SUS
+3V_DEEP_SUS
+3V_DEEP_SUS
+3V_DEEP_SUS
93 *SHORT_6
+3V_DEEP_SUS
PPEF
C8
77
0.1U/16V_4
D D
d R 2689 for NI to +1.0 V_DE EP_S US_20 1412 24
Ad
+1V_S5 +VCCDSW
+1V_S5
C4
45
22U/6.3V_6
C C
+3V_S5
C4
46
22U/6.3V_6
46 *SHORT_4
R2
R2
+V3.
3DX_1.5DX_ADO
+1V_S5
91*0_6
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
+1V_S5
_1.0V
C4
C4
03 *SHORT_6
R3
+VCCDSW
_1.0V
R2
97 *SHORT_6
R3
21 *SHORT_6
R3
30 *SHORT_6
02 *SHORT_6
R3
20 *SHORT_6
R2
R2
22 *SHORT_6
R2
56 *SHORT_6
72 1U/6.3V_4
79 *1U/6.3V_4
04 1U/6.3V_4
C5
R2
17*SHORT _6
R2
59*SHORT _6
R2
19*SHORT _6
18*SHORT _6
R2
R2
16*SHORT _6
M_1.0V_AJ20_AA23
+VCCPRI
91 *1U/6.3V_4
C4
0454A
0.
0.0348A
0.0237A
0.0237A
0.0327A
C4
57 *1U/6.3V_4
+VCCAM
94 1U/6.3V_4
C4
89 22U/6.3V_6
C4
0.0248A
+VCCAM
C5
31 1U/6.3V_4
0.0248A
+VCCPCI
C539 1U/6.3V_4
83 1U/6.3V_4
C4
0.095A
+VCCAPLLEBB
0.533A
+VCCPRI
0.01A
+VCCUSB2PLL_1P0
0.01A
+VCCHDAPLL_1P0
0.075A
+VCCDSW
+VCCCLK1
+VCCCLK3
+VCCCLK4
+VCCCLK2
+VCCCLK5
PHY_1P0
PHYPLL_1P0
E3PLL_1P0
M_1.0V_AC17
3P3
Change C2364 from NI to I _20141212
AA23
AA26
AA28
AC23
AC26
AC28
AE23
AE26
BA29
AC17
AN19
BA15
W15
Y23
Y25
N17
R19
U20
V17
R17
U21
U23
U25
U26
V26
A43
B43
C44
C45
V28
AJ5
AL5
K2
K3
U45H
VC
CPRIM_1P0
CPRIM_1P0
VC
CPRIM_1P0
VC
VC
CPRIM_1P0
VC
CPRIM_1P0
CPRIM_1P0
VC
CPRIM_1P0
VC
VC
CPRIM_1P0
VC
CPRIM_1P0
CPRIM_1P0
VC
DSW_1P0
DCP
VCCCLK1
CCLK3
VC
VC
CCLK4
VC
CCLK2
CCLK2
VC
VC
CCLK5
VC
CCLK5
CMPHY_1P0
VC
VC
CMPHY_1P0
VC
CMPHY_1P0
CMPHY_1P0
VC
CMPHY_1P0
VC
VC
CMPHYPLL_1P0
VC
CMPHYPLL_1P0
CPCIE3PLL_1P0
VC
CPCIE3PLL_1P0
VC
VCCAPLLEBB_1P0
CPRIM_1P0
VC
VC
CUSB2PLL_1P0
VC
CUSB2PLL_1P0
CHDAPLL_1P0
VC
VC
CHDA
VC
CDSW_3P3
SPT_PCH_H
+3V_RT
C
CPRIM_3.3V
+VCCRT
C4
1U/6.3V_4
80
81
C4
0.1U/16V_4
47*0_4
R2
3DX_1.5DX_ADO
+V3.
C4
1U/6.3V_4
C4
87
88
0.1U/16V_4
5V
+1.
B B
+3V
+VCCAT
S
C4
69
1U/6.3V_4
for DS3
R2
96*SHO RT_4
64
50
R3
100K_4
P_SUS_ON37
SL
A A
5
4
C5
1U/6.3V_4
55
C5
*10P/50V _4
R3
47
1 2
*short_6
7
U2
5
IN
4
IN
3
ON
/OFF
*IC(5P) G524 3AT11U-Lay
3
OU
GN
+3V_DEEP_SUS+3V_S5
+3V_DEEP_SUS
1
T
2
D
C5
48
0.1U/10V_4
9,10,12,13,16,17
2
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
Si
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
A3
A3
A3
PCH 5/6 (POWER)
PCH 5/6 (POWER)
PCH 5/6 (POWER)
Date: Sheet
Date: Sheet
Date: Sheet
1
1A
1A
1A
of
of
of
14
14
14
49Tuesday, August 25, 2015
49Tuesday, August 25, 2015
49Tuesday, August 25, 2015
5
4
3
2
1
15
U45I
-H_PCH
SPT
18
AC
VSS
AN4
VSS
10
AN
VSS
BE14
D D
C C
B B
BE1
BE23
BE2
BE32
BE3
BE4
BE9
M3
M4
AA1
AA1
AA2
AA2
AA25
AA2
AA4
AA4
AB10
C1
C2
C3
K1
K2
K3
K3
K4
K4
L12
L13
L15
L41
N1
N1
N1
N22
N2
N35
N3
N4
P1
P19
P2
P4
R1
R1
R2
R2
R3
R3
Y1
Y2
Y2
Y2
Y2
Y2
A1
A2
A3
A3
C2
J7
K4
L4
L8
N4
N5
R5
T1
T2
T4
8
8
7
0
0
8
7
0
7
3
6
2
3
5
2
0
5
9
4
6
1
7
2
5
0
4
2
9
3
8
8
0
1
6
8
9
8
5
2
7
7
8
0
1
9
2
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SPT_PCH_H
9
OF 12
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
AR
AR7
U1
AL4
AE2
AE4
AE4
AF18
AF
AF
AF
AF
AF
AF
AF
AG
AG
AG
AG
AG
AG
AG
AH
AH
AH
AH
AH
AH
AH
AH
AH
AH
AH
AJ
AJ14
AJ
AJ17
AJ
AJ26
AJ
AJ29
AJ
AJ32
AJ
AK4
AK4
AU
AV1
AV2
AV2
AV3
AV3
AV6
AW
AW
AW
AW
AW
AY3
AY4
B2
B3
B3
B4
B6
BA1
BB1
BB1
BB2
BB25
BB3
BB34
BC
BD43
5
5
9
2
20
21
23
25
26
28
29
11
13
31
32
33
38
4
1
17
18
20
21
23
25
26
28
29
45
10
15
18
28
31
36
2
7
7
4
7
1
3
13
19
29
37
9
8
5
5
7
0
1
6
1
0
2
C42
D1
D12
D1
D16
D1
D19
D2
D2
D2
D2
D2
D3
D3
D3
D3
D3
E1
E1
E3
E3
G4
H1
H1
H2
H2
H2
H2
H3
U10
U1
U14
U1
U1
U2
U2
U3
U3
U3
U3
V1
V2
V2
V2
V2
V2
V4
W1
W3
W3
W3
W3
Y1
F4
F8
G9
H3
J10
J1
J3
J3
J5
T4
U4
U8
V3
W4
W8
0
5
7
1
4
5
7
9
0
1
3
5
6
3
5
1
3
4
2
7
9
2
4
7
9
5
1
9
2
1
7
8
8
9
1
2
3
8
8
0
1
3
5
9
5
4
1
2
3
8
7
SPT
U45L
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
SPT_PCH_H
-H_PCH
U45J
AB11
VSS
AB7
VSS
AB14
VSS
1
AB3
VSS
AB32
VSS
8
AB3
VSS
AB4
VSS
AB5
VSS
1
AC
VSS
20
AC
VSS
21
AC
VSS
25
AC
VSS
29
AC
VSS
45
AC
VSS
AB8
VSS
11
AD
VSS
14
AD
VSS
5
AB1
VSS
AD
32
VSS
33
AD
VSS
AD
36
VSS
4
AD
VSS
AD
8
VSS
8
AE1
VSS
AE2
0
VSS
1
AE2
VSS
AE2
5
VSS
8
AE2
VSS
10
AL
VSS
11
AL
VSS
13
AL
VSS
17
AL
VSS
19
AL
VSS
AL24
VSS
29
AL
VSS
AL32
VSS
33
AL
VSS
AL38
VSS
15
AM
VSS
AM17
VSS
19
AM
VSS
AM22
VSS
24
AM
VSS
27
AM
VSS
29
AM
VSS
45
AM
VSS
11
AN
VSS
22
AN
VSS
27
AN
VSS
31
AN
VSS
39
AN
VSS
7
AN
VSS
8
AN
VSS
AP1
1
VSS
AP4
VSS
AR
33
VSS
34
AR
VSS
AR
42
VSS
9
AR
VSS
AT
10
VSS
15
AT
VSS
AT
36
VSS
9
AT
VSS
1
AU
VSS
35
AU
VSS
36
AU
VSS
39
AU
VSS
45
AU
VSS
C4
VSS
OF 12
12
BD
BD45
BD
BE44
BC
D4
A42
B4
B4
BB1
A4
2
44
5
5
4
A4
A3
B2
A2
B1
1
4
C1
D1
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
RS
VD
VD
RS
SPT_PCH_H
-H_PCH
SPT
AR22
PG
VD
RS
W13
RSVD
U13
RS
VD
P31
RSVD
N31
RS
VD
P27
RS
VD
R27
VD
RS
N29
RS
VD
P29
VD
RS
AN29
RS
VD
R24
VD
RS
P24
VD
RS
AT3
EQ#
PR
AT4
DY#
PR
AY5
U_TRST#
CP
H_TRIGOUT
H_TRIGIN
PC
H_2_CPU_TRIG
AL2
AK1
PC
PC
OF 12
10
PC
H_2_CPU_TRIG8
DMON
H_2_CPU_TRIG_R
PC
R62930_4
PC
H_2_CPU_TRIG_R
PG
DMON 12
XDP_PREQ# 2,16
P_PRDY# 2,16
XD
XD
P_TRST# 2,16
U_2_PCH_TRIG 8
CP
A A
VPCU5,10,29,31,32,34,35,37,38,39,46,47
+3
PROJECT :ZRY
PROJECT :ZRY
PROJECT :ZRY
Quanta Computer Inc.
Quanta Computer Inc.
Quanta Computer Inc.
ze Document Number Rev
Size Document Number Rev
Size Document Number Rev
Si
Cu
Cu
Cu
stom
stom
stom
Date: Sheet
Date: Sheet
5
4
3
2
Date: Sheet
H 6/6 (GND)
H 6/6 (GND)
H 6/6 (GND)
PC
PC
PC
1
1A
1A
1A
of
of
of
15 49Tuesday, August 25, 2015
15 49Tuesday, August 25, 2015
15 49Tuesday, August 25, 2015
Loading...