ZILOG Z8E00110HEC, Z8E00110HSC, Z8E00110PEC, Z8E00110PSC, Z8E00110SEC Datasheet

DS97Z8X1300

P R E L I M I N A R Y

1

1

P

RELIMINARY

P

RODUCT

S

PECIFICATION

Z8E001

1

CMOS OTP M

ICROCONTROLLER

FEATURES

Microcontroller Core Features

■

All Instructions Execute in one 1 µ s Instruction
Cycle with 10 MHz Crystal

■

1K x 8 On-Chip OTP EPROM Memory

■

64 x 8 General-Purpose Registers (SRAM)

■

Six Vectored Interrupts with Fixed Priority

■

Operating Speed: DC - 10 MHz

■

Six Addressing Modes: R, IR, X, D, RA, & IM

Peripheral Features

■

13 Total Input/Output Pins

■

One 8-Bit I/O Port (Port A)
– I/O Bit Programmable
– Each Bit Programmable as Push-Pull or Open-

Drain

■

One 5-Bit I/O Port (Port B)
– I/O Bit Programmable
– Includes Special Functionality:

Stop-Mode Recovery Input
Comparator Inputs
Selectable Edge Interrupts
Timer Output

■

One Analog Comparator

■

16-Bit Programmable Watch-Dog Timer (WDT)

■

Software Programmable Timers Configurable as:
– Two 8-Bit Standard Timers and One 16-Bit

Standard Timer or

– One 16-Bit Standard Timer and One 16-Bit Pulse

Width Modulator (PWM) Timer

Additional Features

■

On-Chip Oscillator that Accepts XTAL, Ceramic
Resonator, LC, or External Clock

■

Programmable Options:
– EPROM Protect

■

Power Reduction Modes:
– HALT Mode with Peripheral Units Active
– STOP Mode with all Functionality Shut Down

CMOS/Technology Features

■

Low-Power Consumption

■

3.0V to 5.5V Operating Range @ 0 ° C to +70 ° C

4.5V to 5.5V Operating Range @ -40 ° C to +105 ° C

■

18-Pin DIP,SOIC, and 20-Pin SSOP Packages.

Part ROM RAM* Speed
Number (KB) (Bytes) (MHz)

Z8E001 1 64 10

* General-Purpose

Z8E001
CMOS OTP Microcontroller Zilog

2

P R E L I M I N A R Y

DS97Z8X1300

GENERAL DESCRIPTION

Zilog's Z8E001 Microcontroller (MCU) is a One-Time Pro­grammable (OTP) member of Zilog’s single-chip Z8

Plus

MCU family that allows easy software development, de­bug, prototyping, and small production runs not economi­cally desirable with masked ROM versions.

For applications demanding powerful I/O capabilities, the
Z8E001's dedicated input and output lines are grouped
into two ports, and are configurable under software con­trol.

Both 8-bit and 16-bit on-chip timers, with a large number of
user selectable modes, offload the system of administer­ing real-time tasks such as counting/timing and I/O data
communications.

Note: All signals with a preceding front slash, “/”, are

active Low. For example, B//W (WORD is active Low);
/B/W (BYTE is active Low, only).

Power connections follow conventional descriptions be­low:

Connection Circuit Device

Power

V

CC

V

DD

Ground GND

V

SS

Figure 1. Functional Block Diagram

One 16-bit
Std. Timer

Interrupt

Control

One Analog
Comparator

ALU

FLAG

Register

Pointer

RAM

Register File

Machine Timing

& Inst. Control

OTP

Prg. Memory

Program

Counter

VCC

GND XTAL

Port A

Port B

I/O

Two 8-bit Timers

or
One 16-bit PWM
Timer

I/O

/RESET

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300

P R E L I M I N A R Y

3

Figure 2. EPROM Programming Mode Block Diagram

Z8E001

PORT

A

DATA
MUX

EPROM

ROM PROT

Z8E001 MCU

ADDRESS
GENERATOR

PGM + TEST
MODE LOGIC

ADDRESS
MUX

D7-0

D7-0

AD9 - 0

AD9 - 0

AD9 -0

D7 - 0

ADCLR/VPP/PGM

ADCLK

XTAL1

OPTION BIT

Z8E001
CMOS OTP Microcontroller Zilog

4

P R E L I M I N A R Y

DS97Z8X1300

PIN DESCRIPTION

Figure 3. 18-Pin DIP/SOIC Pin Identification/EPROM Programming Mode

/PGM

GND
GND
GND

ADCLR/VPP

D7
D6
D5
D4

ADCLK
XTAL1
NC
GND
VDD
D0
D1
D2
D3

18

DIP 18 - Pin

1

910

Table 1. 18-Pin DIP/SOIC Pin Assignments/EPROM Programming Mode

EPROM Programming Mode
Pin # Symbol Function Direction

1 /PGM Prog Mode Input
2-4 GND Ground
5 ADCLR/V

PP

Clear Clk./Prog Volt. Input

6-9 D7-D4 Data 7,6,5,4 In/Output
10-13 D3-D0 Data 3,2,1,0 In/Output
14 V

DD

Power Supply

15 GND Ground
16 NC No Connection
17 XTAL1 1MHz Clock Input
18 ADCLK Address Clock Input

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300

P R E L I M I N A R Y

5

Figure 4. 18-Pin DIP/SOIC Pin Identification

PB1
PB2
PB3
PB4

/RST

PA7
PA6
PA5
PA4

PBO
XTAL1
XTAL2
VSS
VCC
PA0
PA1
PA2
PA3

18

DIP 18 - Pin

1

910

Table 2. 18-Pin DIP/SOIC Pin Assignments

Standard Mode
Pin # Symbol Function Direction

1–4 PB1–PB4 Port B, Pins 1,2,3,4 In/Output
5 /RESET Reset Input
6-9 PA7-PA4 Port A, Pins 7,6,5,4 In/Output
10-13 PA3-PA0 Port A, Pins 3,2,1,0 In/Output
14 V

CC

Power Supply

15 V

SS

Ground

16 XTAL2 Crystal Osc. Clock Output
17 XTAL1 Crystal Osc. Clock Input
18 PB0 Port B, Pin 0 In/Output

Z8E001
CMOS OTP Microcontroller Zilog

6

P R E L I M I N A R Y

DS97Z8X1300

PIN DESCRIPTION (Continued)

Figure 5. 20-Pin SSOP Pin Identification

PB1
PB2
PB3
PB4

/RESET

NC
PA7
PA6
PA5
PA4

PBO
XTAL1
XTAL2
VSS
VCC
NC
PA0
PA1
PA2
PA3

20

SSOP 20 - Pin

1

10 11

Table 3. 20-Pin SSOP Pin Assignments

Standard Mode
Pin # Symbol Function Direction

1–4 PB1–PB4 Port B, Pins 1,2,3,4 In/Output
5 /RESET Reset Input
6 NC No Connection
7-10 PA7-PA4 Port A, Pins 7,6,5,4 In/Output
11-14 PA3-PA0 Port A, Pins 3,2,1,0 In/Output
15 NC No Connection
16 V

CC

Power Supply

17 V

SS

Ground

18 XTAL2 Crystal Osc. Clock Output
19 XTAL1 Crystal Osc. Clock Input
20 PB0 Port B, Pin 0 In/Output

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300

P R E L I M I N A R Y

7

Figure 6. 20-Pin SSOP Pin Identification/EPROM Programming Mode

/PGM

GND
GND
GND

ADCLR/VPP

NC

D7
D6
D5
D4

ADCLK
XTAL1
NC
GND
NC
VDD
NC
D1
D2
D3

20

SSOP 20 - Pin

1

10 11

Table 4. 20-Pin SSOP Pin Assignments/EPROM Programming Mode

EPROM Programming Mode
Pin # Symbol Function Direction

1 /PGM Prog Mode Input
2-4 GND Ground
5 ADCLR/V

PP

Clear Clk./Prog Volt. Input

6 NC No Connection
7-10 D7-D4 Data 7,6,5,4 In/Output
11-14 D3-D0 Data 3,2,1,0 In/Output
15 NC No Connection
16 V

DD

Power Supply

17 GND Ground
18 NC No Connection
19 XTAL1 1MHz Clock Input
20 ADCLK Address Clock Input

Z8E001
CMOS OTP Microcontroller Zilog

8

P R E L I M I N A R Y

DS97Z8X1300

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under Absolute Maxi­mum Ratings may cause permanent damage to the de­vice. This is a stress rating only; functional operation of the
device at any condition above those indicated in the oper­ational sections of these specifications is not implied. Ex­posure to absolute maximum rating conditions for an ex­tended period may affect device reliability. Total power
dissipation should not exceed 880 mW for the package.
Power dissipation is calculated as follows:

Parameter Min Max Units Note

Ambient Temperature under Bias –40 +105 C
Storage Temperature –65 +150 C
Voltage on any Pin with Respect to V

SS

–0.6 +7 V 1

Voltage on V

DD

Pin with Respect to V

SS

–0.3 +7 V

Voltage on /RESET Pin with Respect to V

SS

–0.6 V

DD

+1 V 2

Total Power Dissipation 880 mW
Maximum Allowable Current out of V

SS

80 mA

Maximum Allowable Current into V

DD

80 mA

Maximum Allowable Current into an Input Pin –600 +600

µ

A3

Maximum Allowable Current into an Open-Drain Pin –600 +600

µ

A4
Maximum Allowable Output Current Sunk by Any I/O Pin 25 mA
Maximum Allowable Output Current Sourced by Any I/O Pin 25 mA
Maximum Allowable Output Current Sunk by Port A 40 mA
Maximum Allowable Output Current Sourced by Port A 40 mA
Maximum Allowable Output Current Sunk by Port B 40 mA
Maximum Allowable Output Current Sourced by Port B 40 mA

Notes:

1. This applies to all pins except the /RESET pin and where otherwise noted.

2. There is no input protection diode from pin to V

DD

.

3. This excludes XTAL pins.

4. Device pin is not at an output Low state.

Total Power Dissipation = V

DD

x [I

DD

- (sum of I

OH

)]

+ sum of [(V

DD

- V

OH

) x I

OH

]

+ sum of (V

0L

x I

0L

)

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300

P R E L I M I N A R Y

9

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin (Fig­ure 7).

CAPACITANCE

T

A

= 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.

Figure 7. Test Load Diagram

From Output

Under Test

150 pF

Parameter Min Max

Input capacitance 0 12 pF
Output capacitance 0 12 pF
I/O capacitance 0 12 pF

Z8E001
CMOS OTP Microcontroller Zilog

10 P R E L I M I N A R Y DS97Z8X1300

DC ELECTRICAL CHARACTERISTICS

TA = 0°C to +70 °C

Typical [1]

Sym Parameter

V

CC

[3]

Min Max @ 25°C Units Conditions Notes

V

CH

Clock Input High
Voltage

3.0V 0.7V

CCVCC

+0.3 1.3 V Driven by External

Clock Generator

5.5V 0.7V

CCVCC

+0.3 2.5 V Driven by External

Clock Generator

V

CL

Clock Input Low
Voltage

3.0V VSS–0.3 0.2V

CC

0.7 V Driven by External
Clock Generator

5.5V VSS–0.3 0.2V

CC

1.5 V Driven by External
Clock Generator

V

IH

Input High Voltage 3.0V

5.5V

0.7V

CC

0.7V

CC

VCC+0.3
V

CC

+0.3

1.3

2.5

V
V

V

IL

Input Low Voltage 3.0V

5.5V

VSS–0.3
VSS–0.3

0.2V

CC

0.2V

CC

0.7

1.5

V
V

V

OH

Output High Voltage 3.0V VCC–0.4 3.1 V IOH = –2.0 mA

5.5V VCC–0.4 4.8 V IOH = –2.0 mA

V

OL1

Output Low Voltage 3.0V 0.6 0.2 V IOL = +4.0 mA

5.5V 0.4 0.1 V IOL = +4.0 mA

V

OL2

Output Low Voltage 3.0V 1.2 0.5 V IOL = +6 mA,

5.5V 1.2 0.5 V IOL = +12 mA,

V

RH

Reset Input High Voltage 3.0V 0.5V

CC

V

CC

1.1 V

5.5V 0.5V

CC

V

CC

2.2 V

V

RL

Reset Input Low Voltage 3.0V VSS–0.3 0.2V

CC

0.9 V

5.5V VSS–0.3 0.2V

CC

1.4 V

V

OFFSET

Comparator Input Offset
Voltage

3.0V 25.0 10.0 mV

5.5V 25.0 10.0 mV

I

IL

Input Leakage 3.0V –1.0 2.0 0.064 µAVIN = 0V, V

CC

5.5V –1.0 2.0 0.064 µAVIN = 0V, V

CC

I

OL

Output Leakage 3.0V –1.0 2.0 0.114 µAVIN = 0V, V

CC

5.5V –1.0 2.0 0.114 µAVIN = 0V, V

CC

V

ICR

Comparator Input
Common Mode
Voltage Range

3.0V VSS–0.3 V

CC

–1.0 V 7

5.5V VSS–0.3 V

CC

–1.0 V 7

I

IR

Reset Input Current 3.0V -10 -60 -30 µA

5.5V -20 -180 -100 µA

I

CC

Supply Current 3.0V 2.5 2.0 mA @ 10 MHz 4,5

5.5V 6.0 4.0 mA @ 10 MHz 4,5

I

CC1

Standby Current 3.0V 2.0 1.0 mA HALT Mode VIN = 0V,VCC

@ 10 MHz

4,5

5.5V 2.0 1.0 mA HALT Mode VIN = 0V,VCC
@ 10 MHz

4,5

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 11

T

A

= 0 ° C to
+70 °C

Typical

[1]

Sym Parameter

V

CC

[3]

Min Max @ 25°C Units Conditions Notes

I

CC2

Standby Current 3.0V 500 150 nA STOP Mode VIN = 0V, V

CC

6

5.5V 500 250 nA STOP Mode V

IN

= 0V,VCC 6

Notes:

1. Typical values are measured at V

CC

= 3.3V and VCC = 5.0V.

2. V

SS

= 0V = GND

3. The V

CC

voltage specification of 3.0 V guarantees 3.3 V +/- 0.3 V and the VCC voltage specification of 5.5 V guarantees

5.0 V +/- 0.5 V.

4. All outputs unloaded, I/O pins floating, and all inputs are at V

CC

or VSS level.

5. CL1 = CL2 = 22 pF.

6. Same as note [4] except inputs at V

CC

.

7. For analog comparator input when analog comparator is enabled.

Z8E001
CMOS OTP Microcontroller Zilog

12 P R E L I M I N A R Y DS97Z8X1300

DC ELECTRICAL CHARACTERISTICS (Continued)

TA = -40°C to

+105°C Typical [1]

Sym Parameter

V

CC

[3]

Min Max @ 25°C Units Conditions Notes

V

CH

Clock Input High
Voltage

4.5V 0.7 VCCVCC+0.3 2.5 V Driven by External Clock
Generator

5.5V 0.7 VCCVCC+0.3 2.5 V Driven by External Clock
Generator

V

CL

Clock Input Low
Voltage

4.5V VSS–0.3 0.2 V

CC

1.5 V Driven by External Clock
Generator

5.5V VSS–0.3 0.2 V

CC

1.5 V Driven by External Clock
Generator

V

IH

Input High Voltage 4.5V 0.7 VCCVCC+0.3 2.5 V

5.5V 0.7 VCCVCC+0.3 2.5 V

V

IL

Input Low Voltage 4.5V VSS–0.3 0.2 V

CC

1.5 V

5.5V VSS–0.3 0.2 V

CC

1.5 V

V

OH

Output High Voltage 4.5V VCC–0.4 4.8 V IOH = –2.0 mA

5.5V VCC–0.4 4.8 V IOH = –2.0 mA

V

OL1

Output Low Voltage 4.5V 0.4 0.1 V IOL = +4.0 mA

5.5V 0.4 0.1 V IOL = +4.0 mA

V

OL2

Output Low Voltage 4.5V 1.2 0.5 V IOL = +12 mA,

5.5V 1.2 0.5 V IOL = +12 mA,

V

RH

Reset Input High
Voltage

4.5V 0.5V

CC

V

CC

1.1 V

5.5V 0.5V

CC

V

CC

2.2 V

V

OFFSET

Comparator Input
Offset V oltage

4.5V 25.0 10.0 mV

5.5V 25.0 10.0 mV

I

IL

Input Leakage 4.5V -1.0 2.0 <1.0 µAVIN = 0V, V

CC

5.5V -1.0 2.0 <1.0 µAVIN = 0V, V

CC

I

OL

Output Leakage 4.5V -1.0 2.0 <1.0 µAVIN = 0V, V

CC

5.5V -1.0 2.0 <1.0 µAVIN = 0V, V

CC

V

ICR

Comparator Input
Common Mode
Voltage Range

4.5V 0 VCC –1.5V V 7

5.5V 0 VCC –1.5V V 7

I

IR

Reset Input Current 4.5V -18 -180 -112 µA

5.5V -18 -180 -112 µA

I

CC

Supply Current 4.5V 7.0 4.0 mA @ 10 MHz 4,5

5.5V 7.0 4.0 mA @ 10 MHz 4,5

I

CC1

Standby Current 4.5V 2.0 1.0 mA HALT Mode VIN = 0V, VCC

@ 10 MHz

4,5

5.5V 2.0 1.0 mA HALT Mode VIN = 0V, VCC
@ 10 MHz

4,5

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 13

T

A

= -40 °C

to +105 °C

Typical [1]

Sym Parameter VCC[3] Min Max @ 25°C Units Conditions Notes

I

CC2

Standby Current 4.5V 700 250 nA STOP Mode VIN = 0V, VCC 6

5.5V 700 250 nA STOP Mode V

IN

= 0V, VCC 6

Notes:

1. Typical values are measured at V

CC

= 3.3V and VCC = 5.0V.

2. V

SS

= 0V = GND

3. The V

CC

voltage specification of 3.0 V guarantees 3.3 V +/- 0.3 V and the VCC voltage specification of 5.5 V guarantees

5.0 V +/- 0.5 V.

4. All outputs unloaded, I/O pins floating, and all inputs are at V

CC

or VSS level.

5. CL1 = CL2 = 22 pF.

6. Same as note [4] except inputs at V

CC

.

7. For analog comparator input when analog comparator is enabled.

Z8E001
CMOS OTP Microcontroller Zilog

14 P R E L I M I N A R Y DS97Z8X1300

AC ELECTRICAL CHARACTERISTICS

Additional Table

Figure 8. AC Electrical Timing Diagram

13

3

2

2

CLOCK

IRQ

N

4

5

TA= 0 °C to +70 °C

10 MHz

No Symbol Parameter

V

CC

[2] Min Max Units Notes

1 TpC Input Clock Period 3.0V 100 DC ns 1

5.5V 100 DC ns 1

2 TrC,TfC Clock Input Rise and Fall Times 3.0V 15 ns 1

5.5V 15 ns 1

3 TwC Input Clock Width 3.0V 50 ns 1

5.5V 50 ns 1

4 TwIL Int. Request Input Low Time 3.0V 70 ns 1

5.5V 70 ns 1

5 TwIH Int. Request Input High Time 3.0V 5TpC 1

5.5V 5TpC 1

6 Twsm STOP Mode Recovery Width Spec. 3.0V 12 ns

5.5V 12 ns

7 Tost

Oscillator Start-Up Time 3.0V 5TpC

5.5V 5TpC

Notes:

1. Timing Reference uses 0.7 V

CC

for a logic 1 and 0.2 VCC for a logic 0.

2. The V

DD

voltage specification of 3.0V guarantees 3.3V +/- 0.3V. The VDD voltage specification of 5.5V guarantees 5.0V +/- 0.5V.

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 15

T

A

= –40 °C to +105 °C

10 MHz

No Symbol Parameter

V

CC

[2] Min Max Units Notes

1 TpC Input Clock Period 4.5V 100 DC ns 1

5.5V 100 DC ns 1

2 TrC,TfC Clock Input Rise

and Fall Times

4.5V 15 ns 1

5.5V 15 ns 1

3 TwC Input Clock Width 4.5V 50 ns 1

5.5V 50 ns 1

4 TwIL Int. Request Input

Low Time

4.5V 70 ns 1

5.5V 70 ns 1

5 TwIH Int. Request Input

High Time

4.5V 5TpC 1

5.5V 5TpC 1

6 Twsm STOP Mode Recovery

Width Spec.

4.5V 12 ns

5.5V 12 ns

7 Tost

Oscillator Start-Up Time 4.5V 5TpC

5.5V 5TpC

Notes:

1. Timing Reference uses 0.7 V

CC

for a logic 1 and 0.2 VCC for a logic 0.

2. The V

DD

voltage specification of 3.0V guarantees 3.3V +/- 0.3V. The VDD voltage specification of 5.5V guarantees 5.0V +/- 0.5V.

Z8E001
CMOS OTP Microcontroller Zilog

16 P R E L I M I N A R Y DS97Z8X1300

Z8

PLUS

CORE

The Z8E001 is based on the Zilog Z8

Plus

Core Architec­ture. This core is capable of addressing up to 64KBytes of
program memory and 4KBytes of RAM. Register RAM is
accessed as either 8 or 16 bit registers using a combina­tion of 4, 8, and 12 bit addressing modes. The architecture

supports up to 15 vectored interrupts from external and in­ternal sources. The processor decodes 44 CISC instruc­tions using six addressing modes. See the Z8

Plus

User’s

Manual (UM97Z8X0300) for more information.

RESET

This section describes the Z8E001 reset conditions, reset
timing, and register initialization procedures. Reset is gen­erated by the Reset Pin, Watch-Dog Timer (WDT), and
Stop-Mode Recovery (SMR).

A system reset overrides all other operating conditions and
puts the Z8E001 into a known state. To initialize the chip’s
internal logic, the /RESET input must be held Low for at
least 30 XTAL clock cycles. The control registers and ports
are reset to their default conditions after a reset from the

/RESET pin. The control registers and ports are not reset
to their default conditions after wakeup from Stop Mode or
WDT timeout.

During RESET, the program counter is loaded with 0020H.
I/O ports and control registers are configured to their de­fault reset state. Resetting the Z8E001 does not effect the
contents of the general-purpose registers.

RESET PIN OPERATION

The Z8E001 hardware /RESET pin initializes the control
and peripheral registers, as shown in Table 4. Specific re­set values are shown by 1 or 0, while bits whose states are
unchanged are indicated by the letter U.

/RESET must be held low until the oscillator stabilizes,
then for an additional 30 XTAL clock cycles to be sure that
the internal reset is complete. The /RESET pin has a
Schmitt-Trigger input with a trip point. There is no high side
protection diode. The user should place an external diode
from /RESET to VCC. A pull-up resistor on the /RESET pin
is approximately 500 K-ohms, typical.

Program execution starts 10 XTAL clock cycles after /RE­SET has returned High. The initial instruction fetch is from
location 0020H. Figure 7 shows reset timing.

After a reset, the first routine executed must be one that
initializes the TCTLHI control register to the required sys­tem configuration, followed by initialization of the remain­ing control registers.

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 17

* The SMR and WDT flags are set indicating the source of
the RESET.

Table 5. Control and Peripheral Register Reset Values

Register Register Bits

(HEX) Name 765432 1 0 Comments

FF Stack Pointer 0 0 U U U U U U Stack pointer is not affected by RESET
FE Reserved
FD Register Pointer UUUU00 0 0 Register pointer is not affected by RESET
FC Flags UUUUUU**Only WDT & SMR flags are affected by RESET
FB Interrupt Mask 000000 0 0 All interrupts masked by RESET
FA Interrupt Request 000000 0 0 All interrupt requests cleared by RESET

F9-F0 Reserved
EF-E0 Virtual Copy Virtual Copy of the Current Working Register Set
DF-D8 Reserved

D7 PortB Spec. Func. 000000 0 0 Deactivates all port special functions after RESET
D6 PortB Control 000000 0 0 Defines all bits as inputs in PortB after RESET
D5 PortB Output UUUUUU U U Output register not affected by RESET
D4 PortB Input UUUUUU U U Current sample of the input pin following RESET
D3 PortA Spec. Func. 000000 0 0 Deactivates all port special functions after RESET
D2 PortA Control 000000 0 0 Defines all bits as inputs in PortA after RESET
D1 PortA Output UUUUUU U U Output register not affected by RESET
D0 PortA Input UUUUUU U U Current sample of the input pin following RESET
CF Reserved

CE Reserved
CD T1VAL UUUUUUUU
CC T0VAL UUUUUUUU
CB T3VAL UUUUUUUU
CA T2VAL UUUUUUUU

C9 T3AR UUUUUUUU

C8 T2AR UUUUUUUU

C7 T1ARHI UUUUUUUU

C6 T0ARHI UUUUUUUU

C5 T1ARLO UUUUUUUU

C4 T0ARLO UUUUUUUU

C3 WDTHI 11111111

C2 WDTLO 11111111

C1 TCTLHI 111110 0 0 WDT Enabled in HALT Mode, WDT timeout at

maximum value, STOP Mode disabled

C0 TCTLLO 000000 0 0 All standard timers are disabled

D1 D0 Reset Source

0 0 /RESET Pin
0 1 SMR Recovery
1 0 WDT Reset
1 1 Reserved

Z8E001
CMOS OTP Microcontroller Zilog

18 P R E L I M I N A R Y DS97Z8X1300

Figure 9. Reset Timing

First Machine Cycle

Clock

/RESET

First Instruction Fetch

Hold Low For 30 XTAL

Periods (Minimum)

10 XTAL CLOCK CYCLES

Figure 10. Example of External Power-On Reset

Circuit

1 µF

100 KΩ

/RESET

1KΩ

VCC

Z8E001

VCC

500 KΩ

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 19

Figure 11. Z8E001 Reset Circuitry with WDT and SMR

XTAL

/64

TCTLHI

D6,D5,D4

3

WDT TAP SELECT

SMR
RECOVERY

SMR

(PB0)

/WDTRST

16-

BIT TIMER

WDT Tap Select

/WDTRST

WatchDog Timer

Z8E001
CMOS OTP Microcontroller Zilog

20 P R E L I M I N A R Y DS97Z8X1300

Z8E001 WATCH-DOG TIMER (WDT)

The WDT is a retriggerable one-shot 16-bit timer that re­sets the Z8E001 if it reaches its terminal count. The WDT
is driven by the XTAL2 clock pin. In order to provide the
longer timeout periods desired in applications, the watch­dog timer is only updated every 64th clock cycle. When op­erating in the RUN or HALT Modes, a WDT timeout reset
is functionally equivalent to an interrupt vectoring the PC
to 0020H and setting the WDT flag to a one state. Coming
out of RESET, the WDT will be fully enabled with its time­out value set at the maximum value, unless otherwise pro­grammed during the first instruction. Subsequent execu­tions of the WDT instruction reinitialize the watchdog timer
registers, C2H and C3H, to their initial values as defined by
bits D6, D5, and D4 of the TCTLHI register. The WDT can­not be disabled except on the first cycle after RESET, and
if the device enters Stop mode.

The WDT instruction should be executed often enough to
provide some margin before allowing the WDT registers to
get near 0. Because the WDT timeout periods are relative­ly long, a WDT reset will occur in the unlikely event that
the WDT times out on exactly the same cycle that the WDT
instruction is executed.

The WDT and SMR flags are the only flags that are affect­ed by the external RESET pin. /RESET clears both the
WDT and SMR flags. A WDT timeout sets the WDT flag.
The STOP instruction sets the SMR flag. This behavior en­ables software to determine whether a pin RESET oc­curred, or whether a WDT timeout occurred, or whether a
return from STOP Mode occurred. Reading the WDT flag
does not reset it to zero, the user must clear it via software.
Failure to clear the flag may result in undefined behavior.

Note: The WDT can only be disabled via software if the
first instruction out of RESET performs this function. Logic
within the Z8E001 will detect that it is in the process of
executing the first instruction after the part leaves RESET.

During the execution of this instruction, the upper five bits
of the TCTLHI register can be written. After this first
instruction, hardware will not allow the upper five bits of
this register to be written.

Figure 12. Z8E001 TCTLHI Register for Control of WDT

D7 D6 D5 D4 D3 D2 D1 D0

0C1

TCTLHI

RESERVED (MUST BE 0)

0 = STOP MODE ENABLED
1 = STOP MODE DISABLED*

D6 D5 D4 WDT TIMEOUT VALUE

---- --- ---- -------------------------------­ 0 0 0 DISABLED
0 0 1 65,536 TpC
0 1 0 131,072 TpC
0 1 1 262,144 TpC
1 0 0 524,288 TpC
1 0 1 1,048,576 TpC
1 1 0 2,097,152 TpC
1 1 1 4,194,304 TpC*

(XTAL CLOCKS TO TIMEOUT)

1 = WDT ENABLED IN HALT MODE*
0 = WDT DISABLED IN HALT MODE

* Designates Default Value after RESET

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 21

The TCTLHI bits for control of the WDT are described be­low:

WDT Time Select (D6, D5, D4). Bits 6, 5, and 4 determine
the time-out period. Figure 11 shows the range of timeout
values that can be obtained. The default values of D6, D5,
and D4 are all 1, thus setting the WDT to its maximum tim­eout period when coming out of RESET.

WDT During HALT (D7). This bit determines whether or
not the WDT is active during HALT Mode. A 1 indicates ac­tive during HALT. A 0 prevents the WDT from resetting the
part while halted.Coming out of reset, the WDT will be en­abled during HALT Mode.

STOP MODE (D3). Coming out of RESET, the Z8E001 will
have STOP Mode disabled. If an application desires to use
STOP Mode, bit D3 must be cleared immediately upon
leaving RESET. If bit D3 is set, the STOP instruction will
execute as a NOP. If bit D3 is cleared, the STOP instruc­tion will enter Stop Mode. Whenever the Z8E001 wakes up
after having been in STOP Mode, the STOP Mode will,
once again, be disabled.

Bits 2, 1 and 0. These bits are reserved and must be 0.

POWER-DOWN MODES

In addition to the standard RUN mode, the Z8E001 MCU
supports two Power-Down modes to minimize device cur-

rent consumption. The two modes supported are HALT
and STOP.

HALT MODE OPERATION

The HALT Mode suspends instruction execution and turns
off the internal CPU clock. The on-chip oscillator circuit re­mains active so the internal clock continues to run and is
applied to the timers and interrupt logic.

To enter the HALT Mode, the Z8E001 only needs to exe­cute a HALT instruction. It is NOT necessary to execute a
NOP instruction immediately before the HALT instruction.

The HALT Mode may be exited by servicing an interrupt,
either externally or internally generated. Upon completion
of the interrupt service routine, the user program continues
from the instruction after the HALT instruction.

The HALT Mode may also be exited via a /RESET activa­tion or a Watch-Dog Timer (WDT) timeout. In these cases,
program execution will restart at the reset restart address
0020H.

Figure 13. Time-Out Period of the WDT

Crystal

Clocks to

Time-Out

Using a

D6 D5 D4 Timeout 10 MHZ Crystal

0 0 0 Disabled Disabled
0 0 1 65,536 TpC 6.55 ms
0 1 0 131,072 TpC 13.11 ms
0 1 1 262,144 TpC 26.21 ms
1 0 0 524,288 TpC 52.43 ms
1 0 1 1,048,576 TpC 104.86 ms
1 1 0 2,097,152 TpC 209.72 ms
1 1 1 4,194,304 TpC 419.43 ms

Notes:

TpC = XTAL clock cycle
The default on reset is D6 = D5 = D4 = 1.

7F HALT ;enter HALT Mode

Z8E001
CMOS OTP Microcontroller Zilog

22 P R E L I M I N A R Y DS97Z8X1300

STOP MODE OPERATION

The STOP Mode provides the lowest possible device
standby current. This instruction turns off the on-chip oscil­lator and internal system clock.

To enter the STOP Mode, the Z8E001 only needs to exe­cute a STOP instruction. It is NOT necessary to execute a
NOP instruction immediately before the STOP instruction.,

The STOP Mode is exited by any one of the following re­sets: /RESET pin or a STOP-Mode Recovery source.
Upon reset generation, the processor will always restart
the application program at address 0020H and the STOP
Mode Flag will be set. Reading this flag does not clear it,
the user must clear this flag with software. Failure to clear
this flag may result in undefined behavior.

The Z8E001 provides a dedicated STOP-Mode Recov­ery (SMR) circuit. In this case, a low level applied to input
pin PB0 will trigger a SMR. To use this mode, pin PB0 (I/O
Port B, bit 0) must be configured as an input before the
STOP Mode is entered. The low level on PB0 must be held
for a minimum pulse width T

WSM

.

Note: Use of the PB0 input for the stop mode recovery
does not initialize the control registers.

Note: The STOP Mode current (I

CC2

) will be minimized

when:

■ V

CC

is at the low end of the devices operating range.

■ Output current sourcing is minimized.

■ All inputs (digital and analog) are at the low or high rail

voltages.

CLOCK

The Z8E001 MCU derives its timing from on-board clock
circuitry connected to pins XTAL1 and XTAL2. The clock
circuitry consists of an oscillator, a glitch filter, a divide-by­two shaping circuit, a divide-by-four shaping circuit, and a
divide-by-eight shaping circuit. Figure 12 illustrates the
clock circuitry. The oscillator’s input is XTAL1 and its out­put is XTAL2. The clock can be driven by a crystal, a ce­ramic resonator, LC clock, or an external clock source.

6F STOP ;enter STOP Mode

Figure 14. Z8E001 Clock Circuit

÷2

XTAL2

XTAL1

Glitch
Filter

÷4

÷8

WDT
Clock

Timer
Clock

Machine
Clock
(5 cycles
per in­struction)

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 23

OSCILLATOR OPERATION

The Z8E001 MCU uses a Pierce oscillator with an internal
feedback (Figure 13). The advantages of this circuit are
low cost, large output signal, low-power level in the crystal,
stability with respect to VCC and temperature, and low im­pedances (not disturbed by stray effects).

One draw back is the need for high gain in the amplifier to
compensate for feedback path losses. The oscillator am­plifies its own noise at start-up until it settles at the frequen­cy that satisfies the gain/phase requirements A x B = 1,
where A = V0/Vi is the gain of the amplifier and B = Vi/V0 is
the gain of the feedback element. The total phase shift
around the loop is forced to zero (360 degrees). Since VIN
must be in phase with itself, the amplifier/inverter provides
180 degree phase shift and the feedback element is forced
to provide the other 180 degrees of phase shift.

R1 is a resistive component placed from output to input of
the amplifier. The purpose of this feedback is to bias the
amplifier in its linear region and to provide the start-up tran­sition.

Capacitor C

2

combined with the amplifier output resistance
provides a small phase shift. It will also provide some at­tenuation of overtones.

Capacitor C1 combined with the crystal resistance pro­vides additional phase shift.

C1 and C2 can affect the start-up time if they increase dra­matically in size. As C1 and C2 increase, the start-up time
increases until the oscillator reaches a point where it does
not start up any more.

It is recommended for fast and reliable oscillator start-up
(over the manufacturing process range) that the load ca­pacitors be sized as low as possible without resulting in
overtone operation.

Layout

Traces connecting crystal, caps, and the Z8E001 oscillator
pins should be as short and wide as possible. This reduces
parasitic inductance and resistance. The components
(caps, crystal, resistors) should be placed as close as pos­sible to the oscillator pins of the Z8E001.

The traces from the oscillator pins of the IC and the ground
side of the lead caps should be guarded from all other trac­es (clock, V

CC

, address/data lines, system ground) to re­duce cross talk and noise injection. This is usually accom­plished by keeping other traces and system ground trace
planes away from the oscillator circuit and by placing a
Z8E001 device VSS ground ring around the traces/compo­nents. The ground side of the oscillator lead caps should
be connected to a single trace to the Z8E001 VSS (GND)
pin. It should not be shared with any other system ground
trace or components except at the Z8E001 device VSS pin.
This is to prevent differential system ground noise injection
into the oscillator (Figure 14).

Figure 15. Pierce Oscillator with Internal Feedback

Circuit

XTAL2

Z8E001

V

SS

XTAL1

C1

C2

RI

V

1

A

V

0

Z8E001
CMOS OTP Microcontroller Zilog

24 P R E L I M I N A R Y DS97Z8X1300

Indications of an Unreliable Design

There are two major indicators that are used in working de­signs to determine their reliability over full lot and temper­ature variations. They are:

Start-up Time. If start -up time is excessive, or varies wide­ly from unit to unit, there is probably a gain problem. C1/C2
needs to be reduced; the amplifier gain is not adequate at
frequency, or crystal Rs is too large.

Output Level. The signal at the amplifier output should
swing from ground to VCC. This indicates there is adequate
gain in the amplifier. As the oscillator starts up, the signal
amplitude grows until clipping occurs, at which point the
loop gain is effectively reduced to unity and constant oscil­lation is achieved. A signal of less than 2.5 volts peak-to­peak is an indication that low gain may be a problem. Ei­ther C

1

or C2 should be made smaller or a low-resistance

crystal should be used.

Circuit Board Design Rules

The following circuit board design rules are suggested:

■ To prevent induced noise the crystal and load capacitors

should be physically located as close to the Z8E001 as
possible.

■ Signal lines should not run parallel to the clock oscillator

inputs. In particular, the crystal input circuitry and the
internal system clock output should be separated as
much as possible.

■ V

CC

power lines should be separated from the clock

oscillator input circuitry.

■ Resistivity between XTAL1 or XTAL2 and the other pins

should be greater than 10 Mohms.

Figure 16. Circuit Board Design Rules

XTAL2

V

SS

XTAL1

Board Design Example

V

SS

Z8E001

Z8E001

Z8E001

C1

C2

Clock Generator Circuit

Signals A B

Signal C

(Parallel Traces

Must Be Avoided)

(Top View)

17

16

15

17

16

XTAL1

XTAL2

X1

X2

PB0

V

CC

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 25

Crystals and Resonators

Crystals and ceramic resonators (Figure 15) should have
the following characteristics to ensure proper oscillator op­eration:

Depending on operation frequency, the oscillator may re­quire the addition of capacitors C1 and C2 (shown in Fig­ures 15 and16). The capacitance values are dependent on
the manufacturer’s crystal specifications.

In most cases, the RD is 0 Ohms and RF is infinite. It is de­termined and specified by the crystal/ceramic resonator
manufacturer. The RD can be increased to decrease the
amount of drive from the oscillator output to the crystal. It
can also be used as an adjustment to avoid clipping of the
oscillator signal to reduce noise. The RF can be used to im­prove the start-up of the crystal/ceramic resonator. The
Z8E001 oscillator already has an internal shunt resistor in
parallel to the crystal/ceramic resonator.

It is recommended in Figures 14, 15, and 16 to connect the
load capacitor ground trace directly to the V

SS

(GND) pin
of the Z8E001. This ensures that no system noise is inject­ed into the Z8E001 clock. This trace should not be shared
with any other components except at the VSS pin of the
Z8E001.

Please note that a parallel resonant crystal or resonator
data sheet will specify a load capacitor value that is the se­ries combination of C1 and C2, including all parasitics (PCB
and holder).

Crystal Cut AT (crystal only)
Mode Parallel, Fundamental Mode
Crystal Capacitance <7pF
Load Capacitance 10pF < CL < 220 pF,

15 typical

Resistance 100 ohms max

Figure 17. Crystal/Ceramic Resonator Oscillator

Figure 18. LC Clock

XTAL2

Z8E001

V

SS

XTAL1

C1

C2

RF

R

D

XTAL2

Z8E001

V

SS

XTAL1

C1

C2

L

Figure 19. External Clock

XTAL2

Z8E001

V

SS

XTAL1

N/C

Z8E001
CMOS OTP Microcontroller Zilog

26 P R E L I M I N A R Y DS97Z8X1300

LC OSCILLATOR

The Z8E001 oscillator can use a LC network to generate a
XTAL clock (Figure 16).

The frequency stays stable over VCC and temperature. The
oscillation frequency is determined by the equation:

where L is the total inductance including parasitics and C

T

is the total series capacitance including the parasitics.

Simple series capacitance is calculated using the following
equation:

Sample calculation of capacitance C1 and C2 for 5.83 MHz
frequency and inductance value of 27 uH:

TIMERS

For the Z8E001, 8-bit timers T0 and T1 are available to
function as a pair of independent 8-bit standard timers, or
they can be cascaded to function as a 16-bit PWM timer.
In addition, 8-bit timers T2 and T3 are provided but they
can only operate in cascade to function as a 16-bit stan­dard timer.

1

Frequency =

2π (LCT)

1/2

1/ C

T

If C

1

1/CT

C

1

= 1/C

1

+ 1/C2

= C

2

= 2 C

1

= 2C

T

5.83 (10^6) = 1
2π [2.7 (10-6) CT] 1/2

CT = 27.6 pf

Thus C1 = 55.2 pf and C2 = 55.2 pf.

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 27

Figure 20. Timers Block Diagram

T2VALT2ART3AR

T3VAL

Internal Data Bus

16-bit DOWN COUNTER

IRQ5 (T23)

Internal Data Bus

T0VALT0ARLOT0ARHI

8-bit
Counter

Down

IRQ0 (T0)

16-bit DOWN COUNTER16-bit INITIALIZATION REGISTER

IRQ0
IRQ2

T1ARHI

T1ARLO

T1VAL

8-bit
Down
Counter

IRQ2 (T1)

Internal Data Bus

OSC
/8

OSC
/8

OSC
/8

ENABLE TCTLLO (D5)

ENABLE TCTLL0 (D2-D0)

ENABLE TCTLLO (D2-D0)

16-bit Standard Timer

16-bit PWM Timer

8-bit Standard Timer

8-bit Standard Timer

Z8E001
CMOS OTP Microcontroller Zilog

28 P R E L I M I N A R Y DS97Z8X1300

Figure 21. TCTLLO Register

D7 D6 D5 D4 D3 D2 D1 D0

0C0

TCTLLO

TIMER STATUS
D2 D1 D0 T0 T1 T01

---- ---- --- ------------ ------------ --------------­ 0 0 0 DISAB. DISAB.
0 0 1 ENAB. DISAB.
0 1 0 DISAB. ENAB.
0 1 1 ENAB. ENAB.
1 0 0 ENAB.(*)
1 0 1 ENAB.(*) DISAB.
1 1 0 DISAB. ENAB.(*)
1 1 1 ENAB.(*) ENAB.(*)

(NOTE: (*) INDICATES AUTO-RELOAD
IS ACTIVE.)

RESERVED (MUST BE 0)

1 = T23 16-BIT TIMER ENABLED WITH
AUTO-RELOAD ACTIVE
0 = T2 AND T3 TIMERS DISABLED

RESERVED (MUST BE 0 )

NOTE: TIMER T01 IS A 16-BIT PWM TIMER FORMED BY CASCADING 8-BIT TIMERS
T1 (MSB) AND T0 (LSB). TIMER T23 IS A STANDARD 16-BIT TIMER FORMED
BY CASCADING 8-BIT TIMERS T3(MSB) AND T2(LSB).

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 29

Each 8-bit timer is given a pair of registers, which are both
readable and writable. One of the registers is defined to
contain the auto-initialization value for the timer, while the
second register contains the current value for the timer.
When a timer is enabled, the timer will decrement whatev­er value is currently held in its count register, and will then
continue decrementing until it reaches 0, at which time an
interrupt will be generated and the contents of the auto-ini­tialization register are optionally copied into the count val­ue register. If auto-initialization is not enabled, the timer
will stop counting upon reaching 0 and control logic will
clear the appropriate control register bit to disable the tim­er.This is referred to as "single-shot" operation. If auto-ini­tialization is enabled, the timer will continue counting from
the initialization value. Software should not attempt to use
registers that are defined as having timer functionality.

Software is allowed to write to any register at any time, but
care should be taken if timer registers be updated while the
timer is enabled. If software updates the count value while
the timer is in operation, the timer will continue counting
based upon the software-updated value. This can produce
strange behavior if the software update occurred at exactly
the point that the timer was reaching 0 to trigger an inter­rupt and/or reload.

Similarly, if software updates the initialization value regis­ter while the timer is active, the next time that the timer
reaches 0, it will be initialized using the updated value.
Again, strange behavior could result if the initialization val­ue register is being written while the timer is in the process
of being initialized. Whether initialization is done with the
new or old value is a function of the exact timing of the
write operation. In all cases, the Z8E001 will prioritize the
software write above that of a decrementer writeback.
However, when hardware clears a control register bit for a
timer that is configured for single-shot operation; the clear­ing of the control bit will override a software write. Reading
either register can be done at any time, and will have no
effect on the functionality of the timer.

If a timer pair is defined to operate as a single 16-bit entity,
the entire 16-bit value must reach 0 before an interrupt is
generated. In this case, a single interrupt will be generat­ed, and the interrupt will correspond to the even 8-bit timer.
For example, timers T2 and T3 are cascaded to form a sin­gle 16-bit timer, so the interrupt for the combined timer will
be defined to be that of timer T2 rather than T3. When a
timer pair is specified to act as a single 16-bit timer, the
even timer registers in the pair (timer T0 or T2) will be de­fined to hold the timer’s least significant byte; while the odd
timer in the pair will hold the timer’s most significant byte.

In parallel with the posting of the interrupt request, the in­terrupting timer’s count value will be initialized by copying
the contents of the auto-initialization value register to the
count value register. It should be noted that any time that
a timer pair is defined to act as a single 16-bit timer, that

the auto-reload function will be performed automatically.
All 16-bit timers will continue counting while their interrupt
requests are active, and will operate in a free-running man­ner.

If interrupts are disabled for a long period of time, it is pos­sible for the timer to decrement to 0 again before its initial
interrupt has been responded to. This is a degenerate
case, and hardware is not required to detect this condition.

When the timer control register is written, all timers that are
enabled by the write will begin counting using the value
that is held in their count register. An auto-initialization is
not performed. All timers can receive an internal clock
source only. Each timer that is enabled will be updated ev­ery 8th XTAL clock cycle.

If T0 and T1 are defined to work independently, then each
will work as an 8-bit timer with a single auto-initialization
register; T0ARLO for T0, and T1ARLO for T1. Each timer
will assert its predefined interrupt when it times out, and
will optionally perform the auto-initialization function. If T0
and T1 are cascaded to form a single 16-bit timer, then the
single 16-bit timer will be capable of performing as a Pulse­Width Modulator (PWM). This timer is referred to as T01 to
distinguish it as having special functionality that is not
available when T0 and T1 act independently.

When T01 is enabled, it can use a pair of 16-bit auto-initial­ization registers. In this mode, one 16-bit auto-initialization
value is composed of the concatenation of T1ARLO and
T0ARLO, and the second auto-initialization value is com­posed of the concatenation of T1ARHI and T0ARHI. When
T01 times out, it will alternately initialize its count value us­ing the LO auto-init pair followed by the HI auto-init pair.
This functionality corresponds to a PWM where the T1 in­terrupt will define the end of the HI section of the wave­form, and the T0 interrupt will mark the end of the LO por­tion of the PWM waveform.

To use the cascaded timers as a PWM, one must initialize
the T0 and T1 count registers to work in conjunction with
the port pin. The user should initialize the T0 and T1 count
registers to the PWM_HI auto-init value to obtain the de­sired PWM behavior. The PWM is arbitrarily defined to use
the LO autoreload registers first. This implies that it had
just timed out after beginning in the HI portion of the PWM
waveform. As such, the PWM is defined to assert the T1
interrupt after the first timeout interval.

After the auto-initialization has been completed, decre­menting occurs for the number of counts defined by the
PWM_LO registers. When decrementing again reaches 0,
the T0 interrupt is asserted; and auto-init using the
PWM_HI registers occurs. Decrementing occurs for the
number of counts defined by the PWM_HI registers until
reaching 0, at which time the the T1 interrupt is asserted,
and the cycle begins again.

Z8E001
CMOS OTP Microcontroller Zilog

30 P R E L I M I N A R Y DS97Z8X1300

The internal timers can be used to trigger external events
by toggling the PB1 output when generating an interrupt.
This functionality can only be achieved in conjunction with
the port unit defining the appropriate pin as an output sig­nal with the timer output special function enabled. In this
mode, the appropriate port output will be toggled when the
timer count reaches 0, and will continue toggling each time
that the timer times out.

T

OUT

Mode

The PortB special function register PTBSFR (0D7H) (Fig­ure 20), is used in conjunction with the Port B directional
control register PTBDIR (0D6) (Figure 21) to configure
PB1 for T

OUT

operation for timer0. In order for T

OUT

to func-

tion, PB1 must be defined as an output line by setting PT-

BCTL bit 1 to 1. Configured in this way, PB1 has the capa­bility of being a clock output for timer0, toggling the PB1
output pin on each timer0 timeout.

At end-of-count, the interrupt request line IRQ0 , clocks a
toggle flip-flop. The output of this flip-flop drives the T

OUT

line, PB1. In all cases, when timer0 reaches its end-of­count, T

OUT

toggles to its opposite state (Figure 22). If, for
example, timer0 is in Continuous Counting Mode, Tout will
have a 50 percent duty cycle output. This duty cycle can
easily be controlled by varying the initial values after each
end-of-count.

Figure 22. PortB Special Function Register (T

out

Operation)

D7 D6 D5 D4 D3 D2 D1 D0

0D7

PTBSFR

1 = ENABLE BIT 0 AS SMR INPUT
0 = NO SPECIAL FUNCTIONALITY

1 = ENABLE BIT 1 AS TIMER0 OUTPUT
0 = NO SPECIAL FUNCTIONALITY

1 = ENABLE BIT 2 AS INT1 INPUT
0 = NO SPECIAL FUNCTIONALITY

D4 D3 COMPAR. INTERRUPTS

--- --- -------------- -------------------

0 0 DISABLED DISABLED
0 1 ENABLED DISABLED

1 0 DISABLED ENABLED
1 1 ENABLED ENABLED

BIT 3: COMP. REF. INPUT
BIT 4: COMP. SIGNAL INPUT/
INT0/INT2
RESERVED (MUST BE 0)

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 31

Figure 23. PortB Directional Control Register

D7 D6 D5 D4 D3 D2 D1 D0

0D6

PTBDIR

RESERVED (MUST BE 0)

1 = BIT N SET AS OUTPUT
0 = BIT N SET AS INPUT

Figure 24. Timer T0 Output Through T

OUT

T

OUT

PB1

IRQ0
(T0
End-of-Count)

÷2

Z8E001
CMOS OTP Microcontroller Zilog

32 P R E L I M I N A R Y DS97Z8X1300

RESET CONDITIONS

After a hardware RESET, the timers are disabled. See Ta­ble 4 for timer control, value, and auto-initialization register
status after RESET.

I/O PORTS

The Z8E001 has 13 lines dedicated to input and output.
These lines are grouped into two ports known as Port A
and Port B. Port A is an 8-bit port, bit programmable as
either inputs or outputs. Port B can be programmed to pro­vide standard input/output or the following special func­tions: timer0 output, comparator input, SMR input, and
external interrupt inputs.

All ports have push-pull CMOS outputs. In addition, the
outputs of Port A on a bit-wise basis may be configured for
open-drain operation.The ports operate on a bit-wise ba­sis. As such, the register values for/at a given bit position
only affect the bit in question.

Each port is defined by a set of four control registers. See
Figure 25, below.

Directional Control and Special Function
Registers

Each port on the Z8E001 has an associated, dedicated Di­rectional Control Register that determines on a bit-wise
basis whether a given port bit will operate as an input or as
an output.

Each port on the Z8E001 has a Special Function Register
that in conjunction with the directional control register im­plements, on a bit-wise basis, any special functionality
that may be defined for each particular port bit.

Input and Output Value Registers

Each port has an Output Value Register and an Input Val­ue Register. For port bits configured as an input by means
of the Directional Control Register, the Input Value Regis­ter for that bit position will contain the current synchronized
input value.

For port bits configured as an output by means of the Di­rectional Control Register, the value held in the corre­sponding bit of the Output Value Register is driven directly
onto the output pin. The opposite register bit for a given pin
(the output register bit for an input pin and the input regis­ter bit for an output pin) will hold their previous value. They
will not be changed by hardware nor will they have any ef­fect on the hardware.

Figure 25. Z8E001 I/O Ports Registers

REGISTER

ADDRESS

IDENTIFIER

0D7H
0D6H
0D5H

PTBSFR

PTBDIR

PTBOUT

Port A SPECIAL FUNCTION

Port A DIRECTION CONTROL

Port A OUTPUT VALUE
Port A INPUT VALUE

0D3H
0D2H

0D1H

0D0H

PTASFR

PTADIR

PTAOUT

PTAIN

0D4H

Port B SPECIAL FUNCTION

Port B DIRECTION CONTROL

Port B OUTPUT VALUE

Port B INPUT VALUE

PTBIN

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Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 33

READ/WRITE OPERATIONS

The control for each port is done on a bit-wise basis. All
bits are capable of operating as inputs or outputs, depend­ing upon the setting of the port’s directional control regis­ter. If configured as an input, each bit is given a Schmitt­trigger. The output of the Schmitt-trigger is latched twice to
perform a synchronization function, and the output of the
synchronizer is fed to the port input register, which can be
read by software.

A write to a port input register has the effect of updating the
contents of the input register, but subsequent reads will not
necessarily return the same value that was written. If the
bit in question is defined as an input, the input register for
that bit position will contain the current synchronized input
value. Thus, writes to that bit position will be overwritten on
the next clock cycle with the newly sampled input data.
However, if the particular port bit is programmed as an out­put, the input register for that bit will retain the software-up­dated value since the port bits that are programmed as
outputs do not sample the value being driven out.

Any bit in either port can be defined as an output by setting
the appropriate bit in the directional control register. If this
is the case, the value held in the appropriate bit of the port
output register is driven directly onto the output pin. Note,
however, that this does not necessarily reflect the actual
output value. If an external error is holding an output pin

either high or low against the output driver, the software
read will return the DESIRED value, not the actual state
caused by the contention. When a bit is defined as an out­put , the Schmitt-trigger on the input will be disabled to
save power.

Updates to the output register will take effect based upon
the timing of the internal instruction pipeline, but will be ref­erenced to the rising edge of the clock. The output register
can be read at any time, and will return the current output
value that is held. No restrictions are placed on the timing
of reads and/or writes to any of the port registers with re­spect to the others, but care should be taken when updat­ing the directional control and special function registers.

When updating a directional control register, the special
function register should first be disabled. If this precaution
is not taken, spurious events could take place as a result
of the change in port I/O status. This is especially impor­tant when defining changes in Port B, since the spurious
event referred to above could be one or more interrupts.
Clearing of the SFR register should be the first step in con­figuring the port, and setting the SFR register should be
the last step in the port configuration process. To ensure
deterministic behavior, the SFR register should not be writ­ten until the pins are being driven appropriately and all ini­tialization has been completed.

PORT A

Port A is a general-purpose port. Figure 25 shows a block
diagram of Port A. Each of its lines can be independently
programmed as input or output via the Port A Directional
Control Register (PTADIR at 0D2H) as seen in Figure 24.
A bit set to a 1 in PTADIR configures the corresponding
bit in Port A as an output, while a bit cleared to 0 config­ures the corresponding bit in Port A as an input.

The input buffers are Schmitt-triggered. Bits programmed
as outputs may be individually programmed as either
push-pull or open drain by setting the corresponding bit in
the Special Function Register (PTASFR, Figure 29.)

Figure 26. Port A Directional Control Register

D7 D6 D5 D4 D3 D2 D1 D0

0 = Input

1 = Output

PTADIR Register

Register 0D2H

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CMOS OTP Microcontroller Zilog

34 P R E L I M I N A R Y DS97Z8X1300

Figure 27. Port A Configuration with Open-Drain Capability and Schmitt-Trigger

PIN

PA0-PA7

PTAIN.bitN
N = 0...7

PTAOUT.bitN
N = 0...7

PTASF.bitN
N = 0...7

PTADIR.bitN
N = 0...7

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Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 35

Port A Register Diagrams

Port A Input Value Register

Port A Output Value Register

Figure 28. Port A Input Value Register

D7 D6 D5 D4 D3 D2 D1 D0

Register 0D0H

PTAIN

PORT A BIT N CURRENT INPUT
VALUE
(only updated for pins in
input mode)

Figure 29. Port A Output Value Register

D7 D6 D5 D4 D3 D2 D1 D0

Register 0D1H

PTAOUT

PORT A BIT N CURRENT
OUTPUT V ALUE

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CMOS OTP Microcontroller Zilog

36 P R E L I M I N A R Y DS97Z8X1300

Port A Directional Control Register

Port A Special Function Register

Figure 30. Port A Directional Control Register

D7 D6 D5 D4 D3 D2 D1 D0

Register 0D2H

PTADIR

1 = BIT N SET AS AN OUTPUT
0 = BIT N SET AS AN INPUT

Figure 31. Port A Special Function Register

D7 D6 D5 D4 D3 D2 D1 D0

Register 0D3H

PTASFR

1 = BIT N IN OPEN-DRAIN MODE
0 = BIT N IN PUSH-PULL MODE

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Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 37

PORT B
Port B Description

Port B is a 5-bit, bidirectional, CMOS-compatible I/O port.
These five I/O lines can be configured under software con­trol to be an input or output, independently. Input buffers
are Schmitt-triggered. See Figures 31 through 34 for dia­grams of all five Port B pins.

In addition to standard input/output capability on all five
pins of Port B, each pin provides special functionality as
shown in the following table:

Special functionality is invoked via the Port B Special
Function Register. See Figure 30 for the arrangement and
control conventions for this register.

Table 6. Port B Special Functions

Port Pin

Input Special

Function

Output Special

Function

PB0 Stop Mode Recovery

Input

None

PB1 None Timer0 Output
PB2 Interrupt1 None
PB3 Comparator

Reference Input

None

PB4 Comparator Signal

Input/Interrupt0/

Interrupt2

None

Figure 32. Port B Special Function Register

D7 D6 D5 D4 D3 D2 D1 D0

Register 0D7H

PTBSFR

1 = ENABLE PB0 AS SMR INPUT
0 = NO SPECIAL FUNCTIONALITY

1 = ENABLE PB1 AS TIMER0 OUTPUT
0 = NO SPECIAL FUNCTIONALITY

1 = ENABLE PB2 AS INT1 INPUT
0 = NO SPECIAL FUNCTIONALITY

RESERVED (MUST BE 0)

1 = Analog Comparator on PB3 & PB4
0 = Digital Inputs on PB3 & PB4

1 = PB4 Interrupts Enabled
0 = PB4 Interrupts Disabled

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CMOS OTP Microcontroller Zilog

38 P R E L I M I N A R Y DS97Z8X1300

PORT B - PIN 0 CONFIGURATION

Figure 33. Port B Pin 0 Diagram

PIN

PB0

PTBOUT.bit0

PTBSF.bit0

PTBDIR.bit0

PTBDIR.bit0

PTBIN.bit0

SMR

SMR Flag

RESET

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Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 39

PORT B - PIN 1 CONFIGURATION

Figure 34. Port B Pin 1 Diagram

PIN

PB1

TIMER0

PTBOUT.bit1

PTBSF.bit1

PTBDIR.bit1

PTBDIR.bit1

PTBIN.bit1

Output

M

U

X

Z8E001
CMOS OTP Microcontroller Zilog

40 P R E L I M I N A R Y DS97Z8X1300

PORT B - PIN 2 CONFIGURATION

Figure 35. Port B Pin 2 Diagram

PIN

PB2

PTBOUT.bit2

PTBSF.bit2

PTBDIR.bit2

PTBDIR.bit2

PTBIN.bit2

EDGE DETECT LOGIC

INT1

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Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 41

PORT B - PINS 3 AND 4 CONFIGURATION

Figure 36. Port B Pins 3 and 4 Diagram

PIN

PB3

PTBOUT.bit3

PTBSF.bit3

PTBDIR.bit3

PTBDIR.bit4

PTBIN.bit4

EDGE DETECT LOGIC

INT0

-

INT2

+

AN IN

REF

PTBDIR.bit3

PTBIN.bit3

PIN

PB4

PTBOUT.bit4

PTBDIR.bit4

PTBSF.bit4

M
U

X

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CMOS OTP Microcontroller Zilog

42 P R E L I M I N A R Y DS97Z8X1300

PORT B CONTROL REGISTERS

Figure 37. Port B Input Value Register

D7 D6 D5 D4 D3 D2 D1 D0

Register 0D4H

PTBIN

PORT B BIT N CURRENT INPUT
VALUE

RESERVED (MUST BE 0)

(only updated for pins in
input mode)

Figure 38. Port B Output Value Register

D7 D6 D5 D4 D3 D2 D1 D0

Register 0D5H

PTBOUT

PORT B BIT N CURRENT
OUTPUT V ALUE

RESERVED (MUST BE 0)

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Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 43

Figure 39. Port B Directional Control Register

D7 D6 D5 D4 D3 D2 D1 D0

Register 0D6H

PTBDIR

RESERVED (MUST BE 0)

1 = BIT N SET AS OUTPUT
0 = BIT N SET AS INPUT

Figure 40. Port B Special Function Register

D7 D6 D5 D4 D3 D2 D1 D0

Register 0D7H

PTBSFR

1 = ENABLE PB0 AS SMR INPUT
0 = NO SPECIAL FUNCTIONALITY

1 = ENABLE PB1 AS TIMER0 OUTPUT
0 = NO SPECIAL FUNCTIONALITY

1 = ENABLE PB2 AS INT1 INPUT
0 = NO SPECIAL FUNCTIONALITY

RESERVED (MUST BE 0)

1 = Analog Comparator on PB3 & PB4
0 = Digital Inputs on PB3 & PB4

1 = PB4 Interrupts Enabled
0 = PB4 Interrupts Disabled

Z8E001
CMOS OTP Microcontroller Zilog

44 P R E L I M I N A R Y DS97Z8X1300

I/O PORT RESET CONDITIONS
Full Reset

Port A and Port B output value registers are not affected
by RESET.

On RESET, the Port A and Port B directional control reg­isters will be cleared to all zeros, which will define all pins
in both ports as inputs.

On RESET, since the directional control registers have re­defined all pins as inputs, the Port A and Port B input value

registers will have the previously held data overwritten with
the current sample of the input pins.

On RESET, the Port A and Port B special function regis­ters will be cleared to all zeros, which will deactivate all
port special functions.

Note: The SMR and WDT timeout events are NOT full
device resets. None of the port control registers is effected
by either of these events.

ANALOG COMPARATOR

The Z8E001 includes one on-chip analog comparator.
Pin PB4 has a comparator front end. The comparator ref­erence voltage is on pin PB3.

Comparator Description

The on-chip comparator can process an analog signal on
PB4 with reference to the voltage on PB3. The analog
function is enabled by programming the Port B Special
Function Register bits 3 and 4.

When the analog comparator function is enabled, bit 4 of
the input register will be defined as holding the synchro­nized output of the comparator, while bit 3 will retain a syn­chronized sample of the reference input.

If the interrupts for PB4 are enabled when the comparator
special function is selected, the output of the comparator
will generate interrupts.

COMPARATOR OPERATION

The comparator output reflects the relationship between
the analog input to the reference input. If the voltage on
the analog input is higher than the voltage on the refer­ence input, then the comparator output will be at a high
state. If the voltage on the analog input is lower than the
voltage on the reference input, then the analog output will
be at a Low state.

Comparator Definitions

V

ICR

The usable voltage range for the positive input and the ref­erence input is called the common mode voltage range (V

I-

CR

). The comparator is not guaranteed to work if the input

is outside of the V

ICR

range.

V

offset

The absolute value of the voltage between the positive in­put and the reference input required to make the compar­ator output voltage switch is the input offset voltage (V

off-

set

).

I

IO

For the CMOS voltage comparator input, the input offset
current (IIO) is the leakage current of the CMOS input gate.

HALT Mode

The analog comparator is functional during HALT Mode. If
the interrupts are enabled, an interrupt generated by the
comparator will cause a return from HALT Mode.

STOP Mode

The analog comparator is disabled during STOP Mode.
The comparator is powered down to prevent it from draw­ing any current.

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Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 45

INPUT PROTECTION

All I/O pins on the Z8E001 have diode input protection.
There is a diode from the I/O pad to VCC and to VSS. See
Figure 41.

However, on the Z8E001, the /RESET pin has only the in­put protection diode from pad to VSS. See Figure 42.

The high-side input protection diode was removed on this
pin to allow the application of high voltage during the OTP
programming mode.

For better noise immunity in applications that are exposed
to system EMI, a clamping diode to V

CC

from this pin may
be required to prevent entering the OTP programming
mode or to prevent high voltage from damaging this pin.

Figure 41. I/O Pin Diode Input Protection

PIN

V

CC

V

SS

Figure 42. /RESET Pin Input Protection

PIN

V

SS

/RESET

Z8E001
CMOS OTP Microcontroller Zilog

46 P R E L I M I N A R Y DS97Z8X1300

PACKAGE INFORMATION

Figure 43. 18-Pin DIP Package Diagram

Figure 44. 18-Pin SOIC Package Diagram

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 47

Figure 45. 20-Pin SSOP Package Diagram

Z8E001
CMOS OTP Microcontroller Zilog

48 P R E L I M I N A R Y DS97Z8X1300

ORDERING INFORMATION

For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired.

CODES
Preferred Package

P = Plastic DIP

Longer Lead Time

S = SOIC
H = SSOP

Preferred Temperature

S = 0°C to +70°C
E = –40°C to +105°C

Speed

10 = 10 MHz

Environmental

C = Plastic Standard

Standard T emperature
18-Pin DIP 18-Pin SOIC 20-Pin SSOP

Z8E00110PSC Z8E00110SSC Z8E00110HSC

Extended Temperature
18-Pin DIP 18-Pin SOIC 20-Pin SSOP

Z8E00110PEC Z8E00110SEC Z8E00110HEC

Example:
Z 8E001 10 P S C is a Z86E001, 10 MHz, DIP, 0° to +70°C, Plastic Standard Flow

Environmental Flow

Temperature
Package
Speed
Product Number
Zilog Prefix

Z8E001

Zilog CMOS OTP Microcontroller

DS97Z8X1300 P R E L I M I N A R Y 49

Pre-Characterization Product:

The product represented by this CPS is newly introduced
and Zilog has not completed the full characterization of the
product. The CPS states what Zilog knows about this
product at this time, but additional features or non­conformance with some aspects of the CPS may be found,

either by Zilog or its customers in the course of further
application and characterization work. In addition, Zilog
cautions that delivery may be uncertain at times, due to
start-up yield issues.

Low Margin:

Customer is advised that this product does not meet
Zilog's internal guardbanded test policies for the
specification requested and is supplied on an exception
basis. Customer is cautioned that delivery may be
uncertain and that, in addition to all other limitations on

Zilog liability stated on the front and back of the
acknowledgement, Zilog makes no claim as to quality and
reliability under the CPS. The product remains subject to
standard warranty for replacement due to defects in
materials and workmanship.

© 1998 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change with­out notice. Devices sold by Zilog, Inc. are covered by war­ranty and patent indemnification provisions appearing in
Zilog, Inc. Terms and Conditions of Sale only.

ZILOG, INC. MAKES NO WARRANTY, EXPRESS,
STATUTORY, IMPLIED OR BY DESCRIPTION,
REGARDING THE INFORMATION SET FORTH HEREIN
OR REGARDING THE FREEDOM OF THE DESCRIBED
DEVICES FROM INTELLECTUAL PROPERTY
INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY
OF MERCHANTABILITY OR FITNESS FOR ANY
PURPOSE.

Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.

Zilog’s products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.

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Campbell, CA 95008-6600
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