1
0 °
P
RELIMINARY
P
RODUCT
S
PECIFICATION
FEATURES
ROM
Device
Z86L04 1K 125 8 Optional Optional
Z86L08 2K 125 8 Optional Optional
Note: *General-Purpose
■
18-Pin DIP and SOIC Packages
■
■
2.0V to 3.9V Operating Range
■
14 Input / Output Lines
■
Five Vectored, Prioritized Interrupts from Five Different
Sources
■
Two On-Board Comparators
■
Software Enabled Watch-Dog Timer (WDT)
■
Programmable Interrupt Polarity
■
Two Standby Modes: STOP and HALT
■
Low-Voltage Protection
(KB)
C to + 70 ° C Standard Temperature
RAM*
(Bytes)
Speed
(MHz)
Auto
Latch
Permanent
WDT
Z86L04/L08
Z8 8-B
M
ICROCONTROLLERS
■
■
■
■
■
■
■
■
IT
C
OST
-E
FFECTIVE
ROM Mask/OTP Options:
– ROM Protect
– Auto Latch Disable
– Permanent Watch-Dog Timer (WDT)
– RC Oscillator
– 32 kHz Crystal Operation
– Low EMI
– WDT Clock Source (Z86L04 only)
Two Programmable 8-Bit Counter/Timers with
6-Bit Programmable Prescalers
Power-On Reset (POR) Timer
On-Chip Oscillator that Accepts RC, Crystal, Ceramic
Resonator, LC, or External Clock Drive
Clock-Free WDT Reset
Low-Power Consumption (40 mw)
Fast Instruction Pointer (1.5 µ s @ 8 MHz)
Fourteen Digital Inputs at CMOS Levels;
Schmitt-Triggered
1
GENERAL DESCRIPTION
Zilog's Z86L04/L08 microcontrollers (MCUs) are members
of the Z8 single-chip MCU family, which offer easy software/hardware system expansion.
For applications demanding powerful I/O capabilities, the
MCU's dedicated input and output lines are grouped into
three ports, and are configurable under software control to
provide timing, status signals, or parallel I/O.
DS97LVO0901
P R E L I M I N A R Y
One on-chip counter/timer, with a large number of user-selectable modes, off-load the system of administering realtime tasks such as counting/timing and I/O data communications. Additionally, two on-board comparators process
analog signals with a common reference voltage (Figure
1).
1
2
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers Zilog
GENERAL DESCRIPTION (Continued)
Note: All Signals with a preceding front slash, "/", are ac-
tive Low, e.g.: B//W (WORD is active Low); /B/W (BYTE is
active Low, only).
Input
Vcc GND
Port 3
Counter/
Timer
Interrupt
Control
T wo Analog
Comparators
General-Purpose
Register File
Power connections follow conventional descriptions below:
Connection Circuit Device
Power V
CC
Ground GND V
XTAL
Machine
Timing & Inst.
Control
ALU
FLAG
Register
Pointer
Program
Memory
Program
Counter
V
DD
SS
Port 2
I/O
(Bit Programmable)
Figure 1. Z86L04/L08 Functional Block Diagram
Port 0
I/O
P R E L I M I N A R Y
DS97LVO0901
1
Zilog Z8 8-Bit Cost-Effective Microcontrollers
D7-D0
Z8 MCU
A10-A0
A10-A0
Z86L04/L08
Clear
P00
Clock
P01
Address
Counter
A10-A0
3 Bits
PGM
Mode Logic
EPM
P32
/PGM
/CE
P02
XT1
Figure 2. EPROM Programming Mode Block Diagram
Address MUX
EPROM
Option Bits
VPP
P33
D7-D0
Data MUX
D7-D0
Z8 PORT2
/OE
P31
DS97LVO0901
P R E L I M I N A R Y
3
4
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers Zilog
PIN DESCRIPTIONS
P24
P25
P26
P27
VCC
XTAL2
XTAL1
P31
P32
1
DIP 18 - Pin
910
18
P23
P22
P21
P20
GND
P02
P01
P00
P33
Figure 3. 18-Pin Standard Mode Configuration
Table 1. 18-Pin Standard Mode Identification
Pin # Symbol Function Direction
1-4 P24-P27 Port 2, Pins 4, 5, 6, 7In/Output
5V
CC
6 XTAL2 Crystal Oscillator
Power Supply
Output
Clock
7 XTAL1 Crystal Oscillator
Input
Clock
8 P31 Port 3, Pin 1, AN1 Input
9 P32 Port 3, Pin 2, AN2 Input
10 P33 Port 3, Pin 3, REF Input
11-13 P00-P02 Port 0, Pins 0, 1, 2 In/Output
14 GND Ground
15-18 P20-P23 Port 2, Pins 0, 1, 2, 3In/Output
P24
P25
P26
P27
VCC
XTAL2
XTAL1
P31
P32
1
SOIC 18 - Pin
910
18
P23
P22
P21
P20
GND
P02
P01
P00
P33
Figure 4. 18-Pin SOIC Configuration
Table 2. 18-Pin SOIC Pin Identification
Pin # Symbol Function Direction
1-4 P24-P27 Port 2, Pins 4,5,6,7 In/Output
5V
CC
Power Supply
6 XTAL2 Crystal Osc. Clock Output
7 XTAL1 Crystal Osc. Clock Input
8 P31 Port 3, Pin 1, AN1 Input
9 P32 Port 3, Pin 2, AN2 Input
10 P33 Port 3, Pin 3, REF Input
11-13 P00-P02 Port 0, Pins 0,1,2 In/Output
14 GND Ground
15-18 P20-P23 Port 2, Pins 0,1,2,3 In/Output
P R E L I M I N A R Y
DS97LVO0901
1
µ
°
°
µ
Z86L04/L08
Zilog Z8 8-Bit Cost-Effective Microcontrollers
ABSOLUTE MAXIMUM RATINGS
Parameter Min Max Units
Ambient Temperature under Bias –40 +105
Storage Temperature –65 +150
Voltage on any Pin with Respect to V
Voltage on V
Pin with Respect to V
DD
Voltage on Pin 7 with Respect to V
Voltage on Pin 7,8,9,10 with Respect to V
[Note 1] –0.7 +12 V
SS
SS
[Note 2] (Z86C02/L02) –0.7 V
SS
[Note 2] (Z86E02) –0.7 V
SS
–0.3 +7 V
+1 V
DD
+1 V
DD
Total Power Dissipation 462 mW
Maximum Allowed Current out of V
Maximum Allowed Current into V
DD
SS
300 mA
270 mA
Maximum Allowed Current into an Input Pin [Note 3] –600 +600
Maximum Allowed Current into an Open-Drain Pin [Note 4] –600 +600
Maximum Allowed Output Current Sinked by Any I/O Pin 20 mA
Maximum Allowed Output Current Sourced by Any I/O Pin 20 mA
Maximum Allowed Output Current Sinked by Port 2, Port 0 80 mA
Maximum Allowed Output Current Sourced by Port 2, Port 0 80 mA
C
C
A
A
Notes:
Stresses greater than those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. This is a stress rating only; functional operation of
the device at any condition above those indicated in the
operational sections of these specifications is not implied.
Exposure to absolute maximum rating conditions for an
extended period may affect device reliability.
Total power dissipation should not exceed 462 mW for the
package. Power dissipation is calculated as follows:
Total Power dissipation = V
DD
x [I
– (sum of I
DD
)] + sum of [(V
OH
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin (Figure 5).
1. This applies to all pins except where otherwise noted.
2. Maximum current into pin must be ± 600 µ A.
There is no input protection diode from pin to V
DD
.
3. This excludes Pin 6 and Pin 7.
4. Device pin is not at an output Low state.
– V
) x I
DD
OH
From Output
Under T est
] + sum of (V
OH
0L
x I
0L
)
150 pF
T
= 25 ° C, V
A
= GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.
CC
Parameter Min Max
Input capacitance 0 15 pF
Output capacitance 0 20 pF
I/O capacitance 0 25 pF
DS97LVO0901
P R E L I M I N A R Y
Figure 5. Test Load Diagram
Capacitance
5
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers Zilog
DC CHARACTERISTICS
Z86L04/L08
T
Sym. Parameter
V
Clock Input High
CH
Voltage
V
Clock Input Low
CL
Voltage
V
V
V
V
V
V
OFFSET
Input High Voltage 2.0V 0.9 V
IH
Input Low Voltage 2.0V VSS–0.3 0.1 V
IL
Output High Voltage 2.0V VCC–0.4 3.0 V IOH = – 500 µA 4,5
OH
Output Low Voltage 2.0V 0.8 0.2 V IOL = +1.0 mA 4,5
OL1
Output Low Voltage 2.0V 1.0 0.8 V IOL = + 3.0 mA 4,5
OL2
Comparator Input
Offset V oltage
V
VCC Low Voltage
LV
Auto Reset
I
Input Leakage
IL
(Input Bias Current
of Comparator)
I
V
Output Leakage 2.0V –1.0 1.0 µAVIN = 0V, V
OL
Comparator Input
ICR
Common Mode
Voltage Range
= 0 ° C to +70 °C
VCC [3]
2.0V 0.9 V
3.9V 0.9 V
2.0V VSS–0.3 0.1 V
3.9V VSS–0.3 0.1 V
3.9V 0.9 V
3.9V V
3.9V V
A
Min Max @ 25 °C Units Conditions Notes
CC
CC
CC
CC
–0.3 0.1 V
SS
–0.4 3.0 V IOH = – 500 µA 4,5
CC
VCC+0.3 V Driven by External
VCC+0.3 V Driven by External
CC
CC
VCC+0.3 V 1
VCC+0.3 V 1
CC
CC
3.9V 0.4 0.1 V I
3.9V 0.8 0.3 V I
2.0V 25 10 mV
3.9V 25 10 mV
1.4 2.15 V
2.0V –1.0 1.0 µAVIN = 0V, V
3.9V –1.0 1.0 µAVIN = 0V, V
3.9V –1.0 1.0 µAVIN = 0V, V
2.0
3.9
0
0
V
–1.0
CC
V
–1.0
CC
Typical
Clock Generator
Clock Generator
V Driven by External
Clock Generator
V Driven by External
Clock Generator
V1
V1
= +1.0 mA 4,5
OL
= + 3.0 mA 4,5
OL
CC
CC
CC
CC
V
V
6
P R E L I M I N A R Y
DS97LVO0901
Z86L04/L08
1
Zilog Z8 8-Bit Cost-Effective Microcontrollers
Sym Parameter
I
Supply Current 2.0V 3.3 mA @ 2 MHz 5,6
CC
I
Standby Current (Halt Mode) 2.0V 2.3 mA @ 2 MHz 5,6,7
CC1
I
Standby Current (Stop Mode) 2.0V 10 1.0 µA 6,7
CC2
I
Auto Latch Low Current 2.0V 12 3.0 µA 0V < VIN < V
ALL
I
Auto Latch High Current 2.0V –8 -1.5 µA 0V < VIN < V
ALH
Notes:
1. Port 0, 2, and 3 only.
2. V
3. V
4. Standard Mode (not Low EMI mode).
5. Inputs at V
6. WDT is not running.
7. Comparator inputs at V
= 0V = GND. The device operates down to VLV. The minimum operational VCC is determined by the value of the voltage V
SS
at the ambient temperature.
= 2.0V to 3.9V, typical values measured at VCC = 3.3 V.
CC
or VSS, outputs are unloaded.
CC
.
CC
TA = 0 °C to +70 °C
V
CC
[3]
Min Max @ 25 °C Units Conditions Notes
Typical
3.9V 6.8 mA @ 2 MHz 5,6
2.0V 6.0 mA @ 8 MHz 5,6
3.9V 9.0 mA @ 8 MHz 5,6
3.9V 3.8 mA @ 2 MHz 5,6,7
2.0V 3.8 mA @ 8 MHz 5,6,7
3.9V 4.8 mA @ 8 MHz 5,6,7
3.9V 10 1.0 µA 6,7
CC
3.9V 32 16 µA 0V < VIN < V
CC
CC
3.9V –16 -8.0 µA
LV
DS97LVO0901 P R E L I M I N A R Y 7
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers Zilog
AC ELECTRICAL CHARACTERISTICS
Clock
T
IN
IRQ
3
7 7
4
1
2 2 3
5
6
N
8
9
Figure 6. AC Electrical Timing Diagram
8 P R E L I M I N A R Y DS97LVO0901
Z86L04/L08
1
Zilog Z8 8-Bit Cost-Effective Microcontrollers
AC ELECTRICAL CHARACTERISTICS
Timing Table (Standard Mode for SCLK/TCLK = XTAL/2)
TA= 0 °C to +70 °C
8 MHz
No. Symbol Parameter
1 TpC Input Clock Period 2.0V 125 DC ns 1
2 TrC,TfC Clock Input Rise and Fall Times 2.0V 25 ns 1
3 TwC Input Clock Width 2.0V 62 ns 1
4 TwTinL Timer Input Low Width 2.0V 70 ns 1
5 TwTinH Timer Input High Width 2.0V 5TpC 1
6 TpTin Timer Input Period 2.0V 8TpC 1
7 TrTin,
TtTin
8 TwIL Int. Request Input Low Time 2.0V 70 ns 1,2,3
9 TwIH Int. Request Input High Time 3.0V 5TpC 1,2,3
10 Twdt Watch-Dog Timer Delay Time Before Time-Out 2.0V 25 ms
11 Tpor Power-On Reset Time
Notes:
1. Timing Reference uses 0.7 V
2. Interrupt request through Port 3 (P33-P31).
3. IRQ 0,1,2 only.
4. For Z86L08 using internal RC oscillator.
5. For Z86L04 using internal RC oscillator.
Precaution: Maximum frequency in Low EMI mode is 1 MHz.
Timer Input Rise and Fall Time 2.0V 100 ns 1
for a logic 1 and 0.2 VCC for a logic 0.
CC
V
CC
3.9V 125 DC ns 1
3.9V 25 ns 1
3.9V 62 ns 1
.39V 70 ns 1
3.9V 5TpC 1
3.9V 8TpC 1
3.9V 100 ns 1
3.9V 70 ns 1,2,3
3.9V 5TpC 1,2,3
3.9V 10 ms
2.0V 70 ms 4
3.9V 50 ms 4
2.0V 20 ms 5
3.9V 6 ms 5
Min Max Units Notes
DS97LVO0901 P R E L I M I N A R Y 9
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers Zilog
PIN FUNCTIONS
XTAL1, XTAL2 Crystal In, Crystal Out (time-based input
and output, respectively). These pins connect a parallelresonant crystal, LC, RC, or an external single-phase
clock (8 MHz max) to the on-chip clock oscillator and buffer.
Port 0, P02-P00. Port 0 is a 3-bit bidirectional, Schmitt-triggered CMOS compatible I/O port. These three I/O lines
can be globally configured under software control to be inputs or outputs (Figure 7).
Z8
Auto Latch. The Auto Latch puts valid CMOS levels on all
CMOS inputs (except P33, P32, P31) that are not externally driven. A valid CMOS level, rather than a floating node,
reduces excessive supply current flow in the input buffer.
On Power-up and Reset, the Auto Latch will set the ports
to an undetermined state of 0 or 1. Default condition is
Auto Latches enabled.
Port 0 (I/O)
Open
Out
In
PAD
Auto Latch Option
R 500 kΩ
Figure 7. Port 0 Configuration
10 P R E L I M I N A R Y DS97LVO0901
Z86L04/L08
1
Zilog Z8 8-Bit Cost-Effective Microcontrollers
Port 2, P27-P20. Port 2 is an 8-bit, bit-programmable, bi-
directional, Schmitt-triggered, CMOS, compatible I/O port.
These eight I/O lines can be configured under software
Z8
Port 2
control to be inputs or outputs, independently. Bits programmed as outputs can be globally programmed as either push-pull or open-drain (Figure 8).
Port 2 (I/O)
Open-Drain
Open
Out
In
1.5 2.3 Hysteresis
Figure 8. Port 2 Configuration
PAD
VCC @ 5.0V
Auto Latch Option
R 500 kΩ
DS97LVO0901 P R E L I M I N A R Y 11
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers Zilog
PIN FUNCTIONS (Continued)
Port 3, P33-P31. Port 3 is a 3-bit, CMOS, compatible port
with three fixed input (P33-P31) lines. These three input
lines can be configured under software control as digital
Schmitt-trigger inputs or analog inputs.
Z8
0 = Digital
1 = Analog
D1
DIG.
AN.
PAD
P31 (AN1)
R247 = P3M
+
-
These three input lines are also used as the interrupt
sources IRQ0-IRQ3 and as the timer input signal TIN (Figure 9).
Port 3
TIN
P31 Data Latch
IRQ2
PAD
PAD
P32 (AN2)
P33 (REF)
IRQ3
P32 Data Latch
IRQ0
+
-
P33 Data Latch
V
cc
IRQ1
IRQ 0,1,2 = Falling Edge Detection
IRQ3 = Rising Edge Detection
Figure 9. Port 3 Configuration
12 P R E L I M I N A R Y DS97LVO0901
Z86L04/L08
1
Zilog Z8 8-Bit Cost-Effective Microcontrollers
Comparator Inputs. Two analog comparators are added
to input of Port 3, P31 and P32, for interface flexibility. The
comparators reference voltage P33 (REF) is common to
both comparators.
Typical applications for the on-board comparators; Zero
crossing detection, A/D conversion, voltage scaling, and
threshold detection. In analog mode, P33 input functions
serve as a reference voltage to the comparators.
FUNCTIONAL DESCRIPTION
The following special functions have been incorporated
into the Z86L04/L08 devices to enhance the standard Z8
core architecture to provide the user with increased design
flexibility.
INT OSC
POR
(Cold Start)
Delay Line
T
POR
P27
(Stop Mode)
The dual comparator (common inverting terminal) features
a single power supply which discontinues power in STOP
mode. The common voltage range is 0-4V when the V
is 5.0V; the power supply and common mode rejection ratios are 90 dB and 60 dB, respectively.
Interrupts are generated on either edge of Comparator 2's
output, or on the falling edge of Comparator 1's output.
The comparator output is used for interrupt generation,
Port 3 data inputs, or TIN through P31. Alternatively, the
comparators can be disabled, freeing the reference input
(P33) for use as IRQ1 and/or P33 input.
RESET. This function is accomplished by means of a Power-On Reset or a Watch-Dog Timer Reset. Upon powerup, the Power-On Reset circuit waits for T
POR
clock cycles, then starts program execution at address
000C (Hex) (Figure 10). The control registers' reset values
are shown in Table 3.
XTAL OSC
ms
18 CLK
Reset Filter
Chip
Reset
CC
ms, plus 18
Figure 10. Internal Reset Configuration
DS97LVO0901 P R E L I M I N A R Y 13
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers Zilog
Power-On Reset (POR). A timer circuit clocked by a ded-
icated on-board RC oscillator is used for a POR timer function. The POR time allows V
and the oscillator circuit to
CC
stabilize before instruction execution begins. The POR
timer circuit is a one-shot timer triggered by one of the five
following conditions:
■ Power bad to power good status
■ Stop-Mode Recovery
■ WDT time-out
■ WDT time-out (in HALT Mode)
■ WDT time-out (in STOP Mode)
Watch-Dog Timer Reset. The WDT is a retriggerable
one-shot timer that resets the Z8 if it reaches its terminal
count. The WDT is initially enabled by executing the WDT
instruction and is retriggered on subsequent execution of
the WDT instruction. The timer circuit is driven by an onboard RC oscillator. If the permanent WDT option is selected then the WDT is enabled after reset and operates in
RUN Mode, HALT mode, STOP mode and cannot be disabled. If the permanent WDT option is not selected then
the WDT, when enabled by the user's software, does not
operate in STOP Mode, but it can operate in HALT Mode
by using a WDH instruction.
Table 3. Control Register Reset Values
Reset Condition
Addr Reg. D7 D6 D5 D4 D3 D2 D1 D0 Comments
FF SPL 00000000
FE GPR 00000000
FDRP 00000000
FC FLAGSUUUUUUUU
FB IMR 0UUUUUUU
FA IRQ UU000000IRQ3 is used
for positive
edge
detection
F9 IPR UUUUUUUU
F8* P01M U U U 0 U U 0 1
F7*P3M UUUUUU0 0P2 open-drain
F6*P2M 11111111Inputs after
reset
F5 PRE0 UUUUUUU0
F4 T0 UUUUUUUU
F3 PRE1 UUUUUU00
F2 T1 UUUUUUUU
F1 TMR 00000000
Notes:
*Registers are not reset after a STOP-Mode Recovery using P27
pin. A subsequent reset will cause these control registers to be
reconfigured as shown in Table 4 and the user must avoid bus
contention on the port pins or it may affect device reliability.
14 P R E L I M I N A R Y DS97LVO0901
Z86L04/L08
1
Zilog Z8 8-Bit Cost-Effective Microcontrollers
Program Memory. The Z8 addresses up to 1024,2048
bytes of internal program memory (Figure 11). The first 12
bytes of program memory are reserved for the interrupt
vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. Bytes
0-1023/0-2047 are on-chip mask programmable ROM.
1024/2047
Location of
First Byte of
On-Chip
ROM
Instruction
Executed
After RESET
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
12
11
10
IRQ5
IRQ5
9
8
7
6
5
4
3
2
1
0
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
Figure 11. Program Memory Map
Register File. The Register File consists of three I/O port
registers, 61 general-purpose registers, and 12 control
and status registers R0-R3, R4-R127 and R241-R255, respectively (Figure 12). General-purpose registers occupy
the 04H to 7FH address space. I/O ports are mapped as
per the existing CMOS Z8. The instructions can access
registers directly or indirectly through an 8-bit address
field. This allows short 4-bit register addressing using the
Register Pointer. In the 4-bit mode, the register file is divided into eight working register groups, each occupying 16
continuous locations. The Register Pointer (Figure 13) addresses the starting location of the active working-register
group.
255
254
253
252
251
250
249
248
247
246
245
244
243
242
241
240
128
127
IndentifiersLocation
Stack Pointer (Bits 7-0)
General Purpose GPR
Register Pointer
Program Control Flags
Interrupt Mask Register
Interrupt Request Register
Interrupt Priority Register
Ports 0-1 Mode
Port 3 Mode
Port 2 Mode
To Prescaler
Timer/Counter0
T1 Prescaler
Timer/Counter1
Timer Mode
Not Implemented
General Purpose
4
3
2
1
0
Registers
Port 3
Port 2
Reserved
Port 0
SPL
RP
Flags
IMR
IRQ
IPR
P01M
P3M
P2M
PRE0
T0
PRE1
T1
TMR
P3
P2
P1
P0
Figure 12. Register File
DS97LVO0901 P R E L I M I N A R Y 15
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers Zilog
FUNCTIONAL DESCRIPTION (Continued)
General-Purpose Registers (GPR). These registers are
undefined after the device is powered up. The registers
keep their last value after any reset, as long as the reset
r7 r6 r5 r4 R253
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
FF
F0
Register Group F
r3 r2 r1 r0
(Register Pointer)
R15 to R0
occurs in the V
Register R254 has been designated as a general-purpose
register. But is set to 00Hex after any reset.
Counter/Timer. There are two 8-bit programmable
counter/timers (T0 and T1), each driven by its 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources. (Figure 14).
voltage-specified operating range. Note:
CC
7F
70
6F
60
5F
50
4F
40
3F
30
2F
20
1F
10
0F
00
Specified Working
Register Group
Register Group 1
Register Group 0
I/O Ports
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
R15 to R0
R15 to R4
R3 to R0
Figure 13. Register Pointer
Stack Pointer. The Z8 has an 8-bit Stack Pointer (R255)
used for the internal stack that resides within the 60 general-purpose registers. It is set to 00Hex after any reset.
The 6-bit prescaler divide the input frequency of the clock
source by any integer number from 1 to 64. Each prescaler
drives its counter, which decrements the value (1 to 256)
that has been loaded into the counter. When both counter
and prescaler reach the end of count, a timer interrupt request IRQ5 (T1 or IRQ4 (T0) is generated.
The counter can be programmed to start, stop, restart to
continue, or restart from the initial value. The counters are
also programmed to stop upon reaching zero (Single-Pass
mode) or to automatically reload the initial value and continue counting (Modulo-N Continuous Mode).
The counters, but not the prescaler, are read at any time
without disturbing their value or count mode. The clock
source for T1 is user-definable and is either the internal microprocessor clock divided by four, or an external signal input through Port 3. The Timer Mode register configures the
external timer input (P31) as an external clock, a trigger input that is retriggerable or non-retriggerable, or used as a
gate input for the internal clock.
16 P R E L I M I N A R Y DS97LVO0901
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Zilog Z8 8-Bit Cost-Effective Microcontrollers
Internal Data Bus
OSC
÷ 2
Clock
Logic
TIN P31
Internal Clock
External Clock
÷ 4
Internal Clock
Gated Clock
Triggered Clock
Write Write Read
PRE0
Initial Value
Register
6-Bit
÷ 4
Write Write Read
Down
Counter
6-Bit
Down
Counter
PRE1
Initial Value
Register
T0
Initial Value
Register
8-bit
Down
Counter
8-Bit
Down
Counter
T1
Initial Value
Register
T0
Current Value
Register
IRQ4
IRQ5
T1
Current Value
Register
Internal Data Bus
Figure 14. Counter/Timers Block Diagram
DS97LVO0901 P R E L I M I N A R Y 17
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers Zilog
FUNCTIONAL DESCRIPTION (Continued)
Interrupts. The Z8 has five interrupts from four different
sources. These interrupts are maskable and prioritized
(Figure 15). The sources are divided as follows: the falling
edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge
of P32 (AN2), and one counter/timer. The Interrupt Mask
Register globally or individually enables or disables the
five interrupt requests (Table 4).
When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. All Z8 interrupts are
vectored through locations in program memory. When an
Interrupt machine cycle is activated, an Interrupt Request
is granted. This disables all subsequent interrupts, saves
the Program Counter and Status Flags, and then branches
to the program memory vector location reserved for that interrupt. This memory location and the next byte contain the
16-bit starting address of the interrupt service routine for
that particular interrupt request.
To accommodate polled interrupt systems, interrupt inputs
are masked and the interrupt request register is polled to
determine which of the interrupt requests needs service.
User must select any Z86E08 mode in Zilog's C12 ICEBOX™ emulator. The rising edge interrupt is not directly
supported on the Z86CCP00ZEM emulator.
Table 4. Interrupt Types, Sources, and Vectors
Vector
Name Source Location Comments
IRQ0 AN2(P32) 0,1 External (F)Edge
IRQ1 REF(P33) 2,3 External (F)Edge
IRQ2 AN1(P31) 4,5 External (F)Edge
IRQ3 AN2(P32) 6,7 External (R)Edge
IRQ4 T0 8,9 Internal
IRQ5 T1 10,11 Internal
Note:
F = Falling edge triggered
R = Rising edge triggered
Interrupt
Request
IRQ0 - IRQ5
IRQ
IMR
Global
Interrupt
Enable
IPR
Priority
Logic
Vector Select
Figure 15. Interrupt Block Diagram
6
18 P R E L I M I N A R Y DS97LVO0901
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Zilog Z8 8-Bit Cost-Effective Microcontrollers
Clock. The Z8 on-chip oscillator has a high-gain, parallel-
resonant amplifier for connection to a crystal, ceramic resonator, or any suitable external clock source (XTAL1 = INPUT, XTAL2 = OUTPUT). The crystal should be AT cut,
8 MHz max, with a series resistance (RS) of less than or
equal to 100 Ohms.
XTAL1
C1
C1
**
C2
Ceramic
Resonator
or Crystal †
† Note: If 32 KHz oscillator is selected then an external 10 Megohm resistor must be connected between XTAL1 and
XTAL2 pins.
XTAL2
C2
Vss *Vss *
LC Clock
XTAL1
L
XTAL2
=Device Ground Pin
*
The crystal or ceramic resonator should be connected
across XTAL1 and XTAL2 using the vendors crystal or ceramic resonator recommended capacitors from each pin
directly to device ground pin 14 (Figure 16). Note that the
crystal capacitor loads should be connected to VSS, Pin 14
to reduce Ground noise injection.
XTAL1
XTAL2
External Clock
C
Vss *
RC Clock
XTAL1
R
XTAL2
Figure 16. Oscillator Configuration
DS97LVO0901 P R E L I M I N A R Y 19
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers Zilog
FUNCTIONAL DESCRIPTION (Continued)
HALT Mode. This instruction turns off the internal CPU
clock but not the crystal oscillation. The counter/timer and
external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain active. The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT mode. After the interrupt
service routine, the program continues from the instruction
after the HALT.
STOP Mode. This instruction turns off the internal clock
and external crystal oscillation and reduces the standby
current to 10 µA. The STOP mode is released by a RESET
through a Stop-Mode Recovery (pin P27). A Low condition
on pin P27 releases the STOP mode even if P27 is an output. Program execution begins at location 000C(Hex).
However, when P27 is used to release the STOP mode,
the I/O port mode registers are not reconfigured to their default power-on conditions. This prevents any I/O, configured as output when the STOP instruction was executed,
from glitching to an unknown state. To use the P27 release
approach with STOP mode, use the following instruction:
LD P2M, #1XXX XXXXB
NOP
STOP
Notes:
X = Dependent on user’s application.
Stop-Mode Recovery pin P27 is not edge triggered.
In order to enter STOP or HALT mode, it is necessary to
first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user executes a
NOP (opcode=FFH) immediately before the appropriate
SLEEP instruction, such as:
FF NOP ; clear the pipeline
6F STOP ; enter STOP mode
or
FF NOP ; clear the pipeline
7F HALT ; enter HALT mode
Watch-Dog Timer (WDT). The Watch-Dog Timer is enabled by instruction WDT. When the WDT is enabled, it
cannot be stopped by the instruction. With the WDT instruction, the WDT is refreshed when it is enabled within
every 1 Twdt period; otherwise, the controller resets itself,
The WDT instruction affects the flags accordingly; Z=1,
S=0, V=0. WDT = 5F (Hex)
Opcode WDT (5FH). The first time opcode 5FH is executed, the WDT is enabled and subsequent execution clears
the WDT counter. This must be done at least every T
WDT
otherwise, the WDT times out and generates a reset. The
generated reset is the same as a power-on reset of T
POR
plus 18 XTAL clock cycles. The internal RC driven WDT
does not run in stop mode, unless the permanent WDT enable option is selected. The WDT does not run in halt
mode unless WDH instruction is executed or permanent
WDT enable option is selected.
Opcode WDH (4FH). When this instruction is executed it
enables the WDT during HALT. If not, the WDT stops
when entering HALT. This instruction does not clear the
counters, it just makes it possible to have the WDT running
during HALT mode. A WDH instruction executed without
executing WDT (5FH) has no effect.
Note: Opcode WDH and permanently enabled WDT is
not directly supported by the Z86CCP00ZEM.
WDT Clock Source. The WDT clock source option selects
the clock source for the WDT. It can be the internal onboard RC oscillator or the internal system clock (SCLK). If
the SCLK is selected, then the WDT time out (T
130,416 x SCLK and the T
is 16,362 x SCLK. Also, if
POR
WDT
) is
the permanent WDT option is selected in this case; the
WDT will not run in STOP mode. (Z86L04 only)
Auto Reset Voltage (VLV). The Z8 has an auto-reset built-
in. The auto-reset circuit resets the Z8 when it detects the
VCC below VLV. Figure 17 shows the Auto Reset Voltage
versus temperature.
;
,
20 P R E L I M I N A R Y DS97LVO0901
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Zilog Z8 8-Bit Cost-Effective Microcontrollers
Vcc
(Volts)
3.2
3.1
3.0
2.9
2.8
2.7
2.6
2.5
2.4
2.3
2.2
2.1
2.0
1.9
1.8
1.7
1.6
–20°C0°C20°C
–40°C
40°C
60°C80°C
100°C
Temp
Figure 17. Typical Auto Reset Voltage (V
OPTIONS
ROM protect, Low Noise, Auto Latch Disable, RC Oscillator, 32 kHz Crystal and Permanent WDT enable features
as options and must be selected at the time of ROM code
submissions.
ROM Protect. ROM Protect fully protects the Z8 ROM
code from being read externally. When ROM Protect is selected, the instructions LDC and LDCI are supported.
(However, instructions LDE and LDEI are not supported.)
Auto Latch Disable. Auto Latch Disable option when Selected will globally disable all Auto Latches.
RC. RC Oscillator option when selected will allow using a
resistor (R) and a capacitor (C) as a clock source.
WDT Clock Source. This selects the clock source of the
WDT and POR counter chain to be driven by either the internal system clock or the internal on-board RC oscillator.
(Z86L04 only).
) vs. Temperature
LV
WDT Enable. WDT Enable option bit when selected will
have the WDT permanently enabled in all modes and can
not be stopped in HALT or STOP Mode, if the internal RC
oscillator is selected as the clock source. If the system
clock (SCLK) is the clock source, the WDT will be stopped
in STOP mode.
Please note that when using the device in a noisy environment, it is suggested that the voltages on the EPM and CE
pins be clamped to V
through a diode to VCC to prevent
CC
accidentally entering the OTP mode. The VPP requires
both a diode and a 100 pF capacitor.
32 kHz Crystal. This disables the internal feedback resistor on the crystal oscillator circuit (not for RC oscillator circuit) so that a 32 kHz crystal can be connected to the
XTAL1 and XTAL2 pins.
Low EMI. The Low EMI (Low noise) mode by passes the
divide by two clock circuit (SCLK = XTAL/1) and lowers the
output sink and drive currents by 75 percent. The maximum oscillator frequency at XTAL pins is 1MHz.
DS97LVO0901 P R E L I M I N A R Y 21
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers Zilog
Z8 CONTROL REGISTERS
R241 TMR
D7 D6 D5 D4 D3 D2 D1 D0
R247 P3M
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
(Must be 0)
0 Disable T Count
1 Enable T Count
0 No Function
1 Load T
0 Disable T Count
1 Enable T Count
T Modes
IN
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
Reserved (Must be 0.)
0
0
1
1
1
Figure 18. Timer Mode Register (F1H: Read/Write)
R242 T1
D7 D6 D5 D4 D3 D2 D1 D0
T Initial Value
1
(When Written)
(Range 1-256 Decimal
01-00 HEX)
T Current Value
1
(When READ)
Figure 19. Counter Timer 1 Register (f2H:Read/Write)
R243 PRE1
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode
0 T Single Pass
1
1 T Modulo
1
Clock Source
1 T Internal
1
0 T External Timing Input
1
(T ) Mode
IN
Prescaler Modulo
(Range: 1-64 Decimal
01-00 HEX)
0 Port 2 Open-Drain
1 Port 2 Push-pull
Port 3 Inputs
0 Digital Mode
1 Analog Mode
Reserved (Must be 0)
Figure 22. Port 3 Mode Register (F7H: Write Only)
R248 P01M
D7 D6 D5 D4 D3 D2 D1 D0
P03-P00 Mode
00 = Output
01 = Input
Reserved (Must be 1.)
Reserved (Must be 0.)
Figure 23. Port 0 and 1 Mode Register
: Write Only)
(F8
H
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
IRQ0, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
Reserved (Must be 0.)
Figure 24. Interrupt Priority Register
(F9
: Write Only)
H
Figure 20. Prescaler1 Register (F3H: Write Only)
R246 P2M
D7 D6 D5 D4 D3 D2 D1 D0
P2 - P2 I/O Definition
70
0 Defines Bit as OUTPUT
1 Defines Bit as INPUT
Figure 21. Port 2 Mode Register (F6
: Write Only)
H
22 P R E L I M I N A R Y DS97LVO0901
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Zilog Z8 8-Bit Cost-Effective Microcontrollers
R250 IRQ
D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 = P32 Input ↓
IRQ1 = P33 Input ↓
IRQ2 = P31 Input ↓
IRQ3 = P32 Input ↑
IRQ4 = Reserved
IRQ5 = T1
Reserved (Must be 0.)
Figure 25. Interrupt Request Register
(FAH: Read/Write)
R251 IMR
D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ5-IRQ0
(D = IRQ0)
Reserved (Must be 0.)
1 Enables Interrupts
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0.)
Register Pointer
Figure 28. Register Pointer FDH: Read/Write)
R255 SPL
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Lower
Byte (SP - SP )
Figure 29. Stack Pointer (FF
0
: Read/Write)
H
7 0
Figure 26. Interrupt Mask Register (FB
R252 Flags
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
Figure 27. Flag Register (FCH: Read/Write)
: Read/Write)
H
DS97LVO0901 P R E L I M I N A R Y 23
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers Zilog
PACKAGE INFORMATION
Figure 30. 18-Pin DIP Package Diagram
Figure 31. 18-Pin SOIC Package Diagram
24 P R E L I M I N A R Y DS97LVO0901
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Zilog Z8 8-Bit Cost-Effective Microcontrollers
ORDERING INFORMATION
Standard T emperature
18-Pin DIP 18-Pin SOIC
Z86L0408PSC Z86L0408SSC
Z86L0808PSC Z86L0808SSC
For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired.
CODES
Preferred Package
P = Plastic DIP
Longer Lead Time
S = SOIC
Preferred Temperature
S = 0 °C to +70 °C
Example:
Z 86L08 08 P S C is a Z86L08, 08 MHz, Plastic DIP, 0 °C to +70 °C, Plastic Standard Flow
Speed
08 = 8 MHz
Environmental
C = Plastic Standard
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
© 1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc.
makes no warranty, express, statutory, implied or by
description, regarding the information set forth herein or
regarding the freedom of the described devices from
intellectual property infringement. Zilog, Inc. makes no
warranty of merchantability or fitness for any purpose.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
DS97LVO0901 P R E L I M I N A R Y 25
Zilog’s products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com
Z86L04/L08
Z8 8-Bit Cost-Effective Microcontrollers Zilog
26 P R E L I M I N A R Y DS97LVO0901
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