ZiLOG Z86E30, Z86E31, Z86E40 PRODUCT SPECIFICATION
1
Z8
FEATURES
ROM
Device
Z86E30 4 237 24 16
Z86E31 2 125 24 16
Z86E40 4 236 32 16
Note: *General-Purpose
■
Standard Temperature (V
■
Extended Temperature (V
■
Available Packages:
28-Pin DIP/SOIC/PLCC OTP (Z86E30/31 only)
40-Pin DIP OTP (Z86E40 only)
44-Pin PLCC/QFP OTP (Z86E40 only)
(KB)
RAM*
(Bytes)
= 3.5V to 5.5V)
CC
= 4.5V to 5.5V)
CC
I/O
Lines
Speed
(MHz)
P
RELIMINARY
P
RODUCT
Z86E30/E31/E40
4K OTP M
■
Programmable OTP Options:
RC Oscillator
EPROM Protect
Auto Latch Disable
Permanently Enabled WDT
Crystal Oscillator Feedback Resistor Disable
RAM Protect
■
Low-Power Consumption: 60 mW
Fast Instruction Pointer: 0.75 µ s
■
■
Two Standby Modes: STOP and HALT
■
Digital Inputs CMOS Levels, Schmitt-Triggered
■
Software Programmable Low EMI Mode
ICROCONTROLLER
S
PECIFICATION
1
■
Software Enabled Watch-Dog Timer (WDT)
■
Push-Pull/Open-Drain Programmable on
Port 0, Port 1, and Port 2
■
24/32 Input/Output Lines
■
Auto Latches
■
Auto Power-On Reset (POR)
GENERAL DESCRIPTION
The Z86E30/E31/E40 8-Bit One-Time Programmable
(OTP) Microcontrollers are members of Zilog's single-chip
®
Z8
MCU family featuring enhanced wake-up circuitry,
programmable Watch-Dog Timers, Low Noise EMI options, and easy hardware/software system expansion capability.
Four basic address spaces support a wide range of memory configurations. The designer has access to three additional control registers that allow easy access to register
mapped peripheral and I/O circuits.
■
Two Programmable 8-Bit Counter/Timers Each
with a 6-Bit Programmable Prescaler
■
Six Vectored, Priority Interrupts from Six
Different Sources
■
Two Comparators
■
On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC, RC, or External Clock Drive
For applications demanding powerful I/O capabilities, the
Z86E30/E31 have 24 pins, and the Z86E40 has 32 pins of
dedicated input and output. These lines are grouped into
four ports, eight lines per port, and are configurable under
software control to provide timing, status signals, and parallel I/O with or without handshake, and address/data bus
for interfacing external memory.
Notes: All signals with a preceding front slash, “/”, are
active Low. For example, B/W
(BYTE is active Low, only).
(WORD is active Low); B/W
DS97Z8X0502
P R E L I M I N A R Y
1
2
Z86E30/E31/E40
Z8 4K OTP Microcontroller Zilog
Power connections follow conventional descriptions below:
Connection Circuit Device
Power V
CC
Ground GND V
V
DD
SS
(E40 Only)
Output Input
Port 3
Counter/
Timers (2)
Interrupt
Control
T wo Analog
Comparators
V
CC
ALU
FLAGS
Register
Pointer
Register File
GND
XTAL
AS DS R/W RESET
Machine Timing
Instruction Control
RESET
WDT, POR
OTP
Program
Counter
&
Port 2
I/O
(Bit Programmable)
Figure 1. Z86E30/E31/E40 Functional Block Diagram
Port 0
44
Address or I/O
(Nibble Programmable)
P R E L I M I N A R Y
Port 1
8
Address/Data or I/O
(Byte Programmable)
(E40 Only)
DS97Z8X0502
1
Z86E30/E31/E40
Zilog Z8 4K OTP Microcontroller
D7 - 0
AD 11- 0
Z8 MCU
AD 11- 0
MSN
Port 3
Z8
Port 0
AD 11- 0
PGM + Test
Mode Logic
EPM
P32
CE
XT1
PGM
P30
Address
MUX
EPROM
TEST ROM
OTP
Options
V
PP
P33
D7 - 0
Data
MUX
D7 - 0
Z8
Port 2
OE
P31
Figure 2. EPROM Programming Block Diagram
DS97Z8X0502
P R E L I M I N A R Y
3
4
Z86E30/E31/E40
Z8 4K OTP Microcontroller Zilog
PIN IDENTIFICATION
Table 1. 40-Pin DIP Pin Identification
Standard Mode
R/W
P25
P26
P27
P04
P05
P06
P14
P15
P07
V
P16
P17
XTAL2
XTAL1
P31
P32
P33
P34
Figure 3. 40-Pin DIP Pin Configuration
1
40-Pin DIP
CC
20 21
AS
Standard Mode
40
DS
P24
P23
P22
P21
P20
P03
P13
P12
GND
P02
P11
P10
P01
P00
P30
P36
P37
P35
RESET
Pin # Symbol Function Direction
1 R/W
Read/Write Output
2–4 P25–P27 Port 2, Pins 5,6,7 In/Output
5–7 P04–P06 Port 0, Pins 4,5,6 In/Output
8–9 P14–P15 Port 1, Pins 4,5 In/Output
10 P07 Port 0, Pin 7 In/Output
11 V
CC
Power Supply
12–13 P16–P17 Port 1, Pins 6,7 In/Output
14 XTAL2 Crystal Oscillator Output
15 XTAL1 Crystal Oscillator Input
16–18 P31–P33 Port 3, Pins 1,2,3 Input
19 P34 Port 3, Pin 4 Output
20 AS Address Strobe Output
21 RESET Reset Input
22 P35 Port 3, Pin 5 Output
23 P37 Port 3, Pin 7 Output
24 P36 Port 3, Pin 6 Output
25 P30 Port 3, Pin 0 Input
26–27 P00–P01 Port 0, Pins 0,1 In/Output
28–29 P10–P11 Port 1, Pins 0,1 In/Output
30 P02 Port 0, Pin 2 In/Output
31 GND Ground
32–33 P12–P13 Port 1, Pins 2,3 In/Output
34 P03 Port 0, Pin 3 In/Output
35–39 P20–P24 Port 2, Pins 0,1,2,3,4 In/Output
40 DS Data Strobe Output
P R E L I M I N A R Y
DS97Z8X0502
1
Z86E30/E31/E40
Zilog Z8 4K OTP Microcontroller
P20
P03
P13
P12
GND
GND
P02
P11
P10
P01
P21
P22
P23
P24
DS
NC
R/W
P25
P26
P27
P04
7
17
6
P05
P06
P14
1
44-Pin PLCC
CCVCC
P15
P07
V
P16
40
29
2818
P17
XTAL2
Figure 4. 44-Pin PLCC Pin Configuration
Standard Mode
P00
39
XTAL1
P30
P36
P37
P35
RESET
R/RL
AS
P34
P33
P32
P31
Table 2. 44-Pin PLCC Pin Identification
Pin # Symbol Function Direction
1–2 GND Ground
3–4 P12–P13 Port 1, Pins 2,3 In/Output
5 P03 Port 0, Pin 3 In/Output
6–10 P20–P24 Port 2, Pins 0,1,2,3,4 In/Output
11 DS
Data Strobe Output
12 NC No Connection
13 R/W Read/Write Output
14–16 P25–P27 Port 2, Pins 5,6,7 In/Output
17–19 P04–P06 Port 0, Pins 4,5,6 In/Output
20–21 P14–P15 Port 1, Pins 4,5 In/Output
22 P07 Port 0, Pin 7 In/Output
23–24 V
CC
Power Supply
25–26 P16–P17 Port 1, Pins 6,7 In/Output
27 XTAL2 Crystal Oscillator Output
28 XTAL1 Crystal Oscillator Input
29–31 P31–P33 Port 3, Pins 1,2,3 Input
32 P34 Port 3, Pin 4 Output
Table 2. 44-Pin PLCC Pin Identification
Pin # Symbol Function Direction
33 AS Address Strobe Output
34 R/RL ROM/ROMless select Input
35 RESET Reset Input
36 P35 Port 3, Pin 5 Output
37 P37 Port 3, Pin 7 Output
38 P36 Port 3, Pin 6 Output
39 P30 Port 3, Pin 0 Input
40–41 P00–P01 Port 0, Pins 0,1 In/Output
42–43 P10–P11 Port 1, Pins 0,1 In/Output
44 P02 Port 0, Pin 2 In/Output
DS97Z8X0502
P R E L I M I N A R Y
5
6
Z86E30/E31/E40
Z8 4K OTP Microcontroller Zilog
PIN IDENTIFICATION (Continued)
P20
P03
P13
P12
GND
GND
P02
P11
P10
P01
P00
2333
11
22
12
P30
P36
P37
P35
RESET
R/RL
AS
P34
P33
P32
P31
P21
P22
P23
P24
DS
NC
R/W
P25
P26
P27
P04
34
44-Pin QFP
44
1
P05
P06
P14
Figure 5. 44-Pin QFP Pin Configuration
Standard Mode
Table 3. 44-Pin QFP Pin Identification
Pin # Symbol Function Direction
1–2 P05–P06 Port 0, Pins 5,6 In/Output
3–4 P14–P15 Port 1, Pins 4,5 In/Output
5 P07 Port 0, Pin 7 In/Output
6–7 V
CC
Power Supply
8–9 P16–P17 Port 1, Pins 6,7 In/Output
10 XTAL2 Crystal Oscillator Output
11 XTAL1 Crystal Oscillator Input
12–14 P31–P33 Port 3, Pins 1,2,3 Input
15 P34 Port 3, Pin 4 Output
16 AS
Address Strobe Output
17 R/RL ROM/ROMless select Input
18 RESET Reset Input
19 P35 Port 3, Pin 5 Output
20 P37 Port 3, Pin 7 Output
21 P36 Port 3, Pin 6 Output
22 P30 Port 3, Pin 0 Input
23–24 P00–P01 Port 0, Pin 0,1 In/Output
25–26 P10–P11 Port 1, Pins 0,1 In/Output
P15
CCVCC
P07
P16
V
P17
XTAL2
XTAL1
Table 3. 44-Pin QFP Pin Identification
Pin # Symbol Function Direction
27 P02 Port 0, Pin 2 In/Output
28–29 GND Ground
30–31 P12–P13 Port 1, Pins 2,3 In/Output
32 P03 Port 0, Pin 3 In/Output
33–37 P20–4 Port 2, Pins 0,1,2,3,4 In/Output
38 DS Data Strobe Output
39 NC No Connection
40 R/W Read/Write Output
41–43 P25–P27 Port 2, Pins 5,6,7 In/Output
44 P04 Port 0, Pin 4 In/Output
P R E L I M I N A R Y
DS97Z8X0502
1
Z86E30/E31/E40
Zilog Z8 4K OTP Microcontroller
Table 4. 40-Pin DIP Package Pin Identification
EPROM Mode
1
NC
D5
D6
D7
A4
A5
A6
NC
NC
A7
V
CC
NC
NC
NC
CE
OE
EPM
V
PP
A8
NC
40-Pin DIP
20 21
40
NC
D4
D3
D2
D1
D0
A3
NC
NC
GND
A2
NC
NC
A1
A0
PGM
A10
A11
A9
NC
Pin # Symbol Function Direction
1 NC No Connection
2–4 D5–D7 Data 5,6,7 In/Output
5–7 A4–A6 Address 4,5,6 Input
8–9 NC No Connection
10 A7 Address 7 Input
11 V
CC
Power Supply
12–14 NC No Connection
15 CE Chip Select Input
16 OE Output Enable Input
17 EPM EPROM Prog. Mode Input
18 V
PP
Prog. Voltage Input
19 A8 Address 8 Input
20–21 NC No Connection
22 A9 Address 9 Input
23 A11 Address 11 Input
24 A10 Address 10 Input
Figure 6. 40-Pin DIP Pin Configuration
EPROM Mode
25 PGM
26–27 A0–A1 Address 0,1 Input
28–29 NC No Connection
Prog. Mode Input
30 A2 Address 2 Input
31 GND Ground
32–33 NC No Connection
34 A3 Address 3 Input
35–39 D0–D4 Data 0,1,2,3,4 In/Output
40 NC No Connection
DS97Z8X0502
P R E L I M I N A R Y
7
8
Z86E30/E31/E40
Z8 4K OTP Microcontroller Zilog
PIN IDENTIFICATION (Continued)
D1
D2
D3
D4
NC
NC
NC
D5
D6
D7
A4
D0A3NCNCGND
6
7
17
A5
A6
NC
GNDA2NCNCA1
1
44-Pin PLCC
CCVCC
A7
NC
V
40
2818
NCNCNC
A0
39
29
CE
Figure 7. 44-Pin PLCC Pin Configuration
EPROM Programming Mode
PGM
A10
A11
A9
NC
NC
NC
A8
V
PP
EPM
OE
Table 5. 44-Pin PLCC Pin Configuration
EPROM Programming Mode
Pin # Symbol Function Direction
1–2 GND Ground
3–4 NC No Connection
5 A3 Address 3 Input
6–10 D0–D4 Data 0,1,2,3,4 In/Output
11–13 NC No Connection
14–16 D5–D7 Data 5,6,7 In/Output
17–19 A4–A6 Address 4,5,6 Input
20–21 NC No Connection
22 A7 Address 7 Input
23–24 V
CC
Power Supply
25–27 NC No Connection
28 CE
Chip Select Input
29 OE Output Enable Input
30 EPM EPROM Prog.
Input
Mode
Table 5. 44-Pin PLCC Pin Configuration
EPROM Programming Mode
Pin # Symbol Function Direction
31 V
PP
Prog. Voltage Input
32 A8 Address 8 Input
33–35 NC No Connection
36 A9 Address 9 Input
37 A11 Address 11 Input
38 A10 Address 10 Input
39 PGM
Prog. Mode Input
40–41 A0,A1 Address 0,1 Input
42–43 NC No Connection
44 A2 Address 2 Input
P R E L I M I N A R Y
DS97Z8X0502
1
Z86E30/E31/E40
Zilog Z8 4K OTP Microcontroller
D1
D2
D3
D4
NC
NC
NC
D5
D6
D7
A4
D0A3NCNCGND
34
44
1
A5
A6
NCNCNC
44 -Pin QFP
GNDA2NCNCA1
CCVCC
A7
NC
V
2333
12
11
NC
Figure 8. 44-Pin QFP Pin Configuration
EPROM Programming Mode
A0
22
CE
PGM
A10
A11
A9
NC
NC
NC
A8
V
PP
EPM
OE
Table 6. 44-Pin QFP Pin Identification
EPROM Programming Mode
Pin # Symbol Function Direction
1–2 A5–A6 Address 5,6 Input
3–4 NC No Connection
5 A7 Address 7 Input
6–7 V
CC
Power Supply
8–10 NC No Connection
11 CE
Chip Select Input
12 OE Output Enable Input
13 EPM EPROM Prog.
Input
Mode
14 V
PP
Prog. Voltage Input
15 A8 Address 8 Input
16–18 NC No Connection
19 A9 Address 9 Input
20 A11 Address 11 Input
21 A10 Address 10 Input
22 PGM
Prog. Mode Input
Table 6. 44-Pin QFP Pin Identification
EPROM Programming Mode
Pin # Symbol Function Direction
23–24 A0,A1 Address 0,1 Input
25–26 NC No Connection
27 A2 Address 2 Input
28–29 GND Ground
30–31 NC No Connection
32 A3 Address 3 Input
33–37 D0–D4 Data 0,1,2,3,4 In/Output
38–40 NC No Connection
41–43 D5–D7 Data 5,6,7 In/Output
44 A4 Address 4 Input
DS97Z8X0502
P R E L I M I N A R Y
9
Z86E30/E31/E40
D5
D6
D7
A4
A5
A6
A7
V
CC
NC
CE
OE
EPM
V
PP
A8
D4
D3
D2
D1
D0
A3
V
SS
A2
A1
A0
PGM
A10
A11
A9
28
28-Pin DIP
1
14 15
25
19
5
11
18
12
264
28-Pin PLCC
1
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
XXX
P21
P20
P03
V
SS
P02
P01
P00
P05
P06
P07
V
CC
XT2
XT1
P31
P04
P27
P26
P25
P24
P23
P22
P32
P33
P34
P35
P37
P36
P30
Z8 4K OTP Microcontroller Zilog
PIN IDENTIFICATION (Continued)
P25
P26
P27
P04
P05
P06
P07
V
XTAL2
XTAL1
P31
P32
P33
P34
28-Pin DIP/SOIC Pin Configuration
1
28-Pin DIP
CC
14 15
Figure 9. Standard Mode
28
P24
P23
P22
P21
P20
P03
V
SS
P02
P01
P00
P30
P36
P37
P35
Figure 10. EPROM Programming Mode
28-Pin DIP/SOIC Pin Configuration
Table 7. 28-Pin DIP/SOIC/PLCC
Pin Identification*
Pin # Symbol Function Direction
1–3 P25–P27 Port 2, Pins 5,6, In/Output
4–7 P04–P07 Port 0, Pins 4,5,6,7 In/Output
8VCCPower Supply
9 XTAL2 Crystal Oscillator Output
10 XTAL1 Crystal Oscillator Input
11–13 P31–P33 Port 3, Pins 1,2,3 Input
14–15 P34–P35 Port 3, Pins 4,5 Output
16 P37 Port 3, Pin 7 Output
17 P36 Port 3, Pin 6 Output
18 P30 Port 3, Pin 0 Input
19–21 P00–P02 Port 0, Pins 0,1,2 In/Output
22 V
23 P03 Port 0, Pin 3 In/Output
24–28 P20–P24 Port 2, Pins
10 P R E L I M I N A R Y DS97Z8X0502
SS
Ground
0,1,2,3,4
In/Output
Figure 11. Standard Mode
28-Pin PLCC Pin Configuration
Z86E30/E31/E40
1
Zilog Z8 4K OTP Microcontroller
Table 8. 28-Pin EPROM
Pin Identification
Pin # Symbol Function Direction
1–3 D5–D7 Data 5,6,7 In/Output
4–7 A4–A7 Address 4,5,6,7 Input
8VCCPower Supply
9 NC No connection
10 CE
Chip Select Input
11 OE Output Enable Input
12 EPM EPROM Prog.
Input
Mode
13 V
PP
Prog. Voltage Input
14–15 A8–A9 Address 8,9 Input
16 A11 Address 11 Input
17 A10 Address 10 Input
18 PGM
Prog. Mode Input
XXX
A5
XXX
A6
XXX
A7
XXX
VCC
XXX
NC
XXX
CE
XXX
OE
A4D7D6D5D4D3D2
1
5
28-Pin PLCC
11
12
PP
A8
A9
V
EPM
A11
264
18
A10
25
19
PGM
XXX
D1
XXX
D0
XXX
A3
XXX
V
SS
XXX
A2
XXX
A1
XXX
A0
19–21 A0–A2 Address 0,1,2 Input
Figure 12. EPROM Programming Mode
28-Pin PLCC Pin Configuration
22 V
SS
Ground
23 A3 Address 3 Input
24–28 D0–D4 Data 0,1,2,3,4 In/Output
DS97Z8X0502 P R E L I M I N A R Y 11
Z86E30/E31/E40
Z8 4K OTP Microcontroller Zilog
ABSOLUTE MAXIMUM RATINGS
Parameter Min Max Units
Ambient Temperature under Bias –40 +105 C
Storage Temperature –65 +150 C
Voltage on any Pin with Respect to V
Voltage on V
Voltage on XTAL1 and RESET
Pin with Respect to V
DD
Pins with Respect to VSS [Note 2] –0.6 VDD+1 V
Total Power Dissipation 1.21 W
Maximum Allowable Current out of V
Maximum Allowable Current into V
Maximum Allowable Current into an Input Pin [Note 3] –600 +600 µA
Maximum Allowable Current into an Open-Drain Pin [Note 4] –600 +600 µA
Maximum Allowable Output Current Sinked by Any I/O Pin 25 mA
Maximum Allowable Output Current Sourced by Any I/O Pin 25 mA
Maximum Allowable Output Current Sinked by RESET
Notes:
1. This applies to all pins except XTAL pins and where otherwise noted.
2. There is no input protection diode from pin to V
3. This excludes XTAL pins.
4. Device pin is not at an output Low state.
[Note 1] –0.6 +7 V
SS
SS
SS
DD
–0.3 +7 V
220 mA
180 mA
Pin 3 mA
.
DD
Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the
device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin
(Test Load).
Total power dissipation should not exceed 1.2 W for the
package. Power dissipation is calculated as follows:
Total Power Dissipation = VDD x [ IDD – (sum of IOH) ]
+ sum of [ (VDD – VOH) x IOH ]
+ sum of (V0L x I0L)
From Output
Under Test
150 pF
Figure 13. Test Load Diagram
12 P R E L I M I N A R Y DS97Z8X0502
Z86E30/E31/E40
1
Zilog Z8 4K OTP Microcontroller
CAPACITANCE
TA = 25°C, VCC = GND = 0V, f = 1.0 MHz; unmeasured pins returned to GND.
Parameter Min Max
Input capacitance 0 12 pF
Output capacitance 0 12 pF
I/O capacitance 0 12 pF
DC ELECTRICAL CHARACTERISTICS
V
CC
Sym Parameter
V
CH
V
CL
V
IH
V
IL
V
OH
Clock Input High Voltage 3.5V
Clock Input Low Voltage 3.5V
Input High Voltage 3.5V
Input Low Voltage 3.5V
Output High Voltage
Low EMI Mode
V
V
OH1
OL
Output High Voltage 3.5V
Output Low Voltage
Low EMI Mode
V
V
V
OL1
OL2
RH
Output Low Voltage 3.5V
Output Low Voltage 3.5V
Reset Input High
Voltage
V
V
RL
OLR
Reset Input Low Voltage 3.5V
Reset Output Low
Voltage
V
OFFSET
Comparator Input
Offset Voltage
V
ICR
Input Common Mode
Voltage Range
I
IL
I
OL
I
IR
Input Leakage 3.5V
Output Leakage 3.5V
Reset Input Current 3.5V
Note [3] Min Max
5.5V
4.5V
5.5V
5.5V
3.5V
5.5V
5.5V
3.5V
4.5V
4.5V
4.5V
3.5V
5.5V
5.5V
3.5V
5.5V
3.5V
4.5V
3.5V
5.5V
4.5V
4.5V
4.5V
TA= 0 °C to +70 °C
0.7 V
CC
0.7 V
CC
GND -0.3
GND -0.3
0.7 V
CC
0.7 V
CC
GND -0.3
GND -0.3
VCC+0.3
V
CC
0.2 V
0.2 V
VCC+0.3
V
CC
0.2 V
0.2 V
VCC -0.4
V
-0.4
CC
VCC -0.4
V
-0.4
CC
.8 V
CC
.8 V
CC
GND -0.3
GND -0.3
0
0
0.2 V
0.2 V
VCC -1.0V
V
CC
-1
-1
-1
-1
-20
-20
+0.3
+0.3
0.4
0.4
0.4
0.4
1.2
1.2
V
CC
V
CC
0.6
0.6
25
25
-1.0V
2
2
2
2
-130
-180
Typical
@ 25°C Units Conditions Notes
CC
CC
CC
CC
1.8
2.5
0.9
1.5
2.5
2.5
1.5
1.5
3.3
VVDriven by External
Clock Generator
VVDriven by External
Clock Generator
V
V
V
V
VVI
= – 0.5 mA
OH
4.8
= -2.0 mA
OH
I
= -2.0 mA
OH
I
= 1.0 mA
OL
I
= + 4.0 mA
OL
I
= + 12 mA
OL
I
= 1.0 mA
OL
CC
CC
3.3
4.8
0.2
0.2
0.1
0.1
0.5
0.5
1.7
2.1
1.3
1.7
0.3
0.2
10
10
VVI
VVIOL = 1.0 mA
VVIOL = + 4.0 mA
VVIOL = + 12 mA
V
V
V
V
VVIOL = 1.0 mA
mV
mV
V
V
0.032
0.032
0.032
0.032
-65
-112
µAµAVIN = 0V, V
VIN = 0V, V
µAµAVIN = 0V, V
VIN = 0V, V
µA
µA
CC
CC
CC
CC
8
8
8
8
13
10
10
DS97Z8X0502 P R E L I M I N A R Y 13
Z86E30/E31/E40
Z8 4K OTP Microcontroller Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
TA= 0 °C to +70 °C
V
CC
Sym Parameter
I
CC
Supply Current 3.5V
Note [3] Min Max
5.5V
I
CC1
Standby Current
Halt Mode
3.5V
5.5V
3.5V
5.5V
I
CC2
Standby Current
Stop Mode
3.5V
5.5V
3.5V
5.5V
I
ALL
I
ALH
T
POR
V
LV
Notes:
1. Device does function down to the Auto Reset voltage.
2. GND=0V
3. The V
4. All outputs unloaded, I/O pins floating, inputs at rail.
5. CL1= CL2 = 22 pF
6. Same as note [4] except inputs at V
7. Max. temperature is 70°C.
8. STD Mode (not Low EMI Mode)
9. Auto Latch (mask option) selected
10. For analog comparator inputs when analog comparators are
11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2
12. Typicals are at V
13. Z86E40 only
14. WDT running
Auto Latch
Low Current
Auto Latch
High Current
Power On Reset 3.5V
3.5V
5.5V
3.5V
5.5V
5.5V
0.7
1.4
-0.6
-1
3.0
2.0
Auto Reset Voltage 2.3 3.1 2.9 V 1,7
voltage specification of 5.5V guarantees 5.0V ± 0.5V and
CC
the V
enabled.
is floating.
voltage specification of 3.5V guarantees only 3.5V.
CC
CC.
= 5.0V and VCC = 3.5V
CC
20
25
8
8
7.0
7.0
10
10
800
800
8
15
-5
-8
24
13
Typical
@ 25°C Units Conditions Notes
7
20
3.7
3.7
2.9
2.9
2
3
600
600
mAmA@ 16 MHz
@ 16 MHz
mAmAVIN = 0V, VCC
@ 16 MHz
mAmAClock Divide by
16 @ 16 MHz
µA
VIN = 0V, VCC
µA
V
= 0V, V
µA
µA
IN
VIN = 0V, V
VIN = 0V, V
CC
CC
CC
4,5
4,5
4,5
4,5
4,5
4,5
6,11
6,11
6,11,1
4
6,11,1
4
2.4
4.7
-1.8
-3.8
7
4
µAµA0V <VIN<V
0V <VIN<V
µAµA0V<VIN<V
0V<VIN<V
ms
ms
CC
CC
CC
CC
9
9
9
9
14 P R E L I M I N A R Y DS97Z8X0502
Z86E30/E31/E40
1
Zilog Z8 4K OTP Microcontroller
TA=–40 °C to +105 °C
Sym Parameter
V
CH
Clock Input High
Voltage
V
CL
Clock Input Low
Voltage
V
IH
V
IL
V
OH
Input High Voltage 4.5V
Input Low Voltage 4.5V
Output High
Voltage Low EMI
Mode
V
V
OH1
OL
Output High Voltage 4.5V
Output Low Voltage
Low EMI Mode
V
V
V
OL1
OL2
RH
Output Low Voltage 4.5V
Output Low Voltage 4.5V
Reset Input High
Voltage
V
OLR
Reset Output Low
Voltage
V
OFFSET
Comparator Input
Offset V oltage
V
ICR
Input Common
Mode V oltage
Range
I
IL
I
OL
I
IR
I
CC
I
CC1
Input Leakage 4.5V
Output Leakage 4.5V
Reset Input Current 4.5V
Supply Current 4.5V
Standby Current
Halt Mode
V
CC
Note [3] Min Max
4.5V
5.5V
4.5V
5.5V
5.5V
5.5V
4.5V
5.5V
0.7 V
CC
0.7 V
CC
GND-0.3
GND-0.3
0.7 V
CC
0.7 V
CC
GND-0.3
GND-0.3
VCC -0.4
V
-0.4
CC
VCC+0.3
V
+0.3
CC
0.2 V
0.2 V
VCC+0.3
V
+0.3
CC
0.2 V
0.2 V
VCC -0.4
4.5V
4.5V
5.5V
V
-0.4
CC
0.4
0.4
0.4
5.5V
0.4
1.2
5.5V
3.5V
5.5V
3.5V
5.5V
4.5V
5.5V
4.5V
5.5V
5.5V
5.5V
5.5V
.8 V
.8 V
-18
-18
CC
CC
0
0
-1
-1
-1
-1
1.2
V
CC
V
CC
0.6
0.6
25
25
VCC-1.5V
V
-1.5V
CC
2
2
2
2
-180
-180
25
5.5V
4.5V
5.5V
25
8
8
CC
CC
CC
CC
Typical
@ 25°C Units Conditions Notes
2.5
2.5
1.5
1.5
2.5
2.5
1.5
1.5
4.8
4.8
4.8
4.8
0.2
0.2
0.1
0.1
0.5
0.5
1.7
2.1
0.3
0.2
10
10
<1
<1
<1
<1
-112
-112
20
20
3.7
VVDriven by External
Clock Generator
VVDriven by External
Clock Generator
V
V
V
V
VVI
VVI
= – 0.5 mA
OH
I
= – 0.5 mA
OH
= -2.0 mA
OH
I
= -2.0 mA
OH
VVIOL = 1.0 mA
I
= 1.0 mA
OL
VVIOL = + 4.0 mA
I
= +4.0 mA
OL
VVIOL = + 12 mA
I
= + 12 mA
OL
V
V
VVIOL = 1.0 mA
I
= 1.0 mA
OL
mV
mV
V
V
µAµAVIN = 0V, V
VIN = 0V, V
µAµAVIN = 0V, V
VIN = 0V, V
CC
CC
CC
CC
µA
µA
mAmA@ 16 MHz
@ 16 MHz
mAmAVIN = 0V, VCC
13
13
13
13
10
10
4,5
4,5
4,5
@ 16 MHz
3.7
V
= 0V, VCC
IN
4,5
8
8
8
8
8
8
8
8
@ 16 MHz
I
CC2
I
ALL
Standby Current
(Stop Mode)
Auto Latch Low
Current
4.5V
5.5V
4.5V
5.5V
1.4
1.4
10
10
20
20
2
3
4.7
4.7
µAµAVIN = 0V, VCC
V
= 0V, V
IN
µAµA0V < VIN < V
0V < VIN < V
CC
CC
CC
6,11,14
6,11,14
9
9
DS97Z8X0502 P R E L I M I N A R Y 15
Z86E30/E31/E40
Z8 4K OTP Microcontroller Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
TA=–40 °C to +105 °C
V
CC
Sym Parameter
I
ALH
Auto Latch High
Current
T
POR
V
LV
1. Device does function down to the Auto Reset voltage.
2. GND=0V
3. The V
4. All outputs unloaded, I/O pins floating, inputs at rail.
5. CL1= CL2 = 22 pF
6. Same as note [4] except inputs at VCC.
7. Maximum temperature is 70°C
8. STD Mode (not Low EMI Mode)
9. Auto Latch (mask option) selected
10. For analog comparator inputs when analog comparators are
11. Clock must be forced Low, when XTAL1 is clock driven and XTAL2
12. Typicals are at V
13. Z86E40 only
14. WDT is not running.
Power On Reset 4.5V
Auto Reset Voltage 2.0 3.3 2.9 V 1
voltage specification of 5.5V guarantees 5.0V ± 0.5V.
CC
enabled.
is floating.
= 5.0V
CC
Note [3] Min Max
4.5V
5.5V
5.5V
-1.0
-1.0
2.0
2.0
-10
-10
14
14
Typical
@ 25°C Units Conditions Notes
-3.8
-3.8
4
4
µAµA0V < VIN < V
0V < VIN < V
mS
mS
CC
CC
9
9
16 P R E L I M I N A R Y DS97Z8X0502
Z86E30/E31/E40
1
Zilog Z8 4K OTP Microcontroller
R/W , DM
Port 0
Port 1
AS
DS
(Read)
Port1
12
18 3
A7 - A0 D7 - D0 IN
21
4
5
17
13
19
16
8 11
6
20
9
10
D7 - D0 OUTA7 - A0
DS
(Write)
14
7
Figure 14. External I/O or Memory Read/Write Timing
Z86E40 Only
15
DS97Z8X0502 P R E L I M I N A R Y 17
Z86E30/E31/E40
Z8 4K OTP Microcontroller Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
TA = 0°C to 70°C
16 MHz
Note [3]
No Symbol Parameter
1 TdA(AS) Address Valid to AS Rise
Delay
2 TdAS(A) AS Rise to Address Float
Delay
3 TdAS(DR) AS Rise to Read Data Req’d
V alid
4 TwAS AS Low Width 3.5V
5 TdAS(DS) Address Float to DS Fall 3.5V
6 TwDSR DS (Read) Low Width 3.5V
7 TwDSW DS (Write) Low Width 3.5V
8 TdDSR(DR) DS Fall to Read Data Req’d
Valid
9 ThDR(DS) Read Data to DS Rise Hold
Time
10 TdDS(A) DS Rise to Address Active
Delay
11 TdDS(AS) DS Rise to AS Fall Delay 3.5V
12 TdR/W(AS) R/W Valid to AS Rise Delay 3.5V
13 TdDS(R/W) DS Rise to R/W Not Valid 3.5V
14 TdDW(DSW) Write Data Valid to DS Fall
(Write) Delay
15 TdDS(DW) DS Rise to Write Data Not
Valid Delay
16 TdA(DR) Address Valid to Read Data
Req’d Valid
17 TdAS(DS) AS Rise to DS Fall Delay 3.5V
18 TdDM(AS) DM Valid to AS Fall Delay 3.5V
20 ThDS(AS) DS Valid to Address Valid
Hold Time
Notes:
1. When using extended memory timing, add 2 TpC.
2. Timing numbers given are for minimum TpC.
3. The V
the V
Standard Test Load
All timing references use 0.7 V
For Standard Mode (not Low-EMI Mode for outputs) with SMR D1 = 0, D0 = 0.
voltage specification of 5.5V guarantees 5.0V ±0.5V and
CC
voltage specification of 3.5V guarantees only 3.5V
CC
for a logic 1 and 0.2 VCC for a logic 0.
CC
V
CC
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
5.5V
5.5V
5.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
5.5V
5.5V
5.5V
3.5V
5.5V
3.5V
5.5V
3.5V
5.5V
5.5V
5.5V
3.5V
5.5V
Min Max Units Notes
25
25
35
35
40
40
0
0
135
135
80
80
0
0
50
50
35
35
25
25
35
35
55
55
35
35
45
45
30
30
35
35
180
180
75
75
25
25
230
230
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
1,2
2
1,2
1,2
1,2
2
2
2
2
2
2
2
1,2
2
2
18 P R E L I M I N A R Y DS97Z8X0502
Z86E30/E31/E40
1
Zilog Z8 4K OTP Microcontroller
TA = -40°C to 105°C
16 MHz
Note [3]
No Symbol Parameter
1 TdA(AS) Address Valid to AS Rise
Delay
2 TdAS(A) ASAS Rise to Address Float
Delay
3 TdAS(DR) AS Rise to Read Data Req’d
V alid
4 TwAS AS Low Width 4.5V
5 TdAS(DS) Address Float to DS Fall 4.5V
6 TwDSR DS (Read) Low Width 4.5V
7 TwDSW DS (Write) Low Width 4.5V
8 TdDSR(DR) DS Fall to Read Data Req’d
Valid
9 ThDR(DS) Read Data to DS Rise Hold
Time
10 TdDS(A) DS Rise to Address Active
Delay
11 TdDS(AS) DS Rise to AS Fall Delay 4.5V
12 TdR/W(AS) R/W Valid to AS Rise Delay 4.5V
13 TdDS(R/W) DS Rise to R/W Not Valid 4.5V
14 TdDW(DSW) Write Data Valid to DS Fall
(Write) Delay
15 TdDS(DW) DS Rise to Write Data Not
Valid Delay
16 TdA(DR) Address Valid to Read Data
Req’d Valid
17 TdAS(DS) AS Rise to DS Fall Delay 4.5V
18 TdDM(AS) /DM Valid to AS Fall Delay 4.5V
20 ThDS(AS) DS Valid to Address Valid
Hold Time
Notes:
1. When using extended memory timing, add 2 TpC.
2. Timing numbers given are for minimum TpC.
3. The V
the V
Standard Test Load
All timing references use 0.7 V
For Standard Mode (not Low-EMI Mode for outputs) with SMR, D1 = 0, D0 = 0.
voltage specification of 5.5V guarantees 5.0V ±0.5V and
CC
voltage specification of 3.5V guarantees only 3.5V
CC
for a logic 1 and 0.2 VCC for a logic 0.
CC
V
CC
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
5.5V
5.5V
5.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
5.5V
5.5V
5.5V
4.5V
5.5V
4.5V
5.5V
4.5V
5.5V
5.5V
5.5V
4.5V
5.5V
Min Max Units Notes
25
25
35
35
40
40
0
0
135
135
80
80
0
0
50
50
35
35
25
25
35
35
55
55
35
35
45
45
30
30
35
35
180
180
75
75
25
25
230
230
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2
2
1,2
2
1,2
1,2
1,2
2
2
2
2
2
2
2
1,2
2
2
DS97Z8X0502 P R E L I M I N A R Y 19
Z86E30/E31/E40
Z8 4K OTP Microcontroller Zilog
DC ELECTRICAL CHARACTERISTICS (Continued)
Clock
TIN
IRQN
Clock
Setup
Stop
Mode
Recovery
Source
7 7
8
1
2 2 3
4
5
6
9
10
3
11
Figure 15. Additional Timing Diagram
20 P R E L I M I N A R Y DS97Z8X0502
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