Datasheet Z86E2116PSC, Z86E2116VEC, Z86E2116VSC, Z86E2112FEC, Z86E2112FSC Datasheet (ZILOG)

1

C

USTOMER

P

ROCUREMENT

S

PECIFICA TION

Z86E21

CMOS Z8® OTP
MICROCONTROLLER

GENERAL DESCRIPTION

The Z86E21 microcontroller (MCU) introduces the next
level of sophistication to single-chip architecture. The
Z86E21 is a member of the Z8 single-chip microcontroller
family with 8 Kbytes of EPROM and 236 bytes of general
purpose RAM.

The Z86E21 is a pin compatible, One-Time-Programmable
(OTP) version of the Z86C21. The Z86E21 contains 8
Kbytes of EPROM memory in place of the 8 Kbyte of ROM
on the Z86C21.

The MCU is housed in a 40-pin DIP, 44-pin Leaded Chip­Carrier, or a 44-pin Quad Flat Pack, and is manufactured
in CMOS technology. The ROMless pin option is available
on the 44-pin versions only. The MCU can address both
external memory and preprogrammed ROM which en­ables this Z8 microcomputer to be used in high volume
applications or where code flexibility is required.

Zilog’s CMOS microcontroller offers fast execution, effi­cient use of memory, sophisticated interrupts, input/output
bit manipulation capabilities, and easy hardware/software
system expansion along with low cost and low power
consumption.

The Z86E21 architecture is based on Zilog’s 8-bit
microcontroller core. The device offers a flexible I/O
scheme, an efficient register and address space structure,
multiplexed capabilities between address/data, I/O, and a
number of ancillary features that are useful in many indus­trial and advanced scientific applications.

The device applications demand powerful I/O capabilities.
The Z86E21 fulfills this with 32-pin dedicated to input and
output. These lines are grouped into four ports. Each port
consists of eight lines, and is configurable under software
control to provide timing, status signals, serial or parallel
I/O with or without handshake, and an address/data bus
for interfacing external memory.

There are three basic address spaces available to support
this wide range of configuration: Program Memory, Data
Memory and 236 General-Purpose registers.

To unburden the program from coping with real-time
problems such as counting/timing and serial data commu­nication, the Z86E21 offers two on-chip counter/timers with
a large number of user selectable modes, and an asyn­chronous receiver/transmitter (UART) (see Functional Block
Description).

In ROM Protect Mode, the instructions LDC, LDCI, LDE
and LDEI are disabled when reading address locations
%0000 to %1FFF.

Notes:

All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).

Power connections follow conventional descriptions below:

Connection Circuit Device

Power V

CC

V

DD

Ground GND V

SS

DC-2964-10

PRODUCT RECOMMENDATIONS

Zilog recommends the following programming equipment for use with this One-Time-Programmable product:

Recommended Revision Level

Device Zilog Support Tool Hardware Software

Z86E21 Z86C1200ZEM ICEBOX™ Emulator* (*Does not support 4K/8K option.) B 1.5
Z86E21 Data I/O 3900 Programmer* (*Does not support option bits.) 1.1
Z86E21 Data I/O Unisite Programmer* (*Does not support option bits.) 3.7

Some non-Zilog programmers may have different pro­gramming waveforms, voltages and timings and not all
programmers may meet the programming requirements of
Zilog's One-Time-Programmable products.

If difficulty is encountered in programming a Zilog OTP
product, please contact your local Zilog sales office.

2

GENERAL DESCRIPTION (Continued)

Port 3

UART

Counter/

Timers

(2)

Interrupt

Control

Port 2

I/O

(Bit Programmable)

ALU

FLAGS

Register

Pointer

Register File

256 x 8-Bit

Machine Timing and

Instruction Control

Prg. Memory

8192 x 8-Bit

Program

Counter

Vcc GND XTAL

44

Port 0

Output Input

Address or I/O

(Nibble Programmable)

8

Port 1

Address/Data or I/O

(Byte Programmable)

/AS /DS R//W /RESET

Functional Block Diagram

3

PIN DESCRIPTION

Standard Mode

40-Lead DIP Pin Assignments

40-Lead DIP Pin Identification

Pin # Symbol Function Direction

1VCCPower Supply Input
2 XTAL2 Crystal, Oscillator Clock Output
3 XTAL1 Crystal, Oscillator Clock Input
4 P37 Port 3 pin 7 Output
5 P30 Port 3 pin 0 Input

6 /RESET Reset Input
7 R//W Read/Write Output
8 /DS Data Strobe Output
9 /AS Address Strobe Output
10 P35 Port 3 pin 5 Output

Pin # Symbol Function Direction

11 GND Ground, GND Input
12 P32 Port 3 pin 2 Input
13-20 P00-P07 Port 0 pin 0,1,2,3,4,5,6,7 In/Output
21-28 P10-P17 Port 1 pin 0,1,2,3,4,5,6,7 In/Output
29 P34 Port 3 pin 4 Output

30 P33 Port 3 pin 3 Input
31-38 P20-P27 Port 2 pin 0,1,2,3,4,5,6,7 In/Output
39 P31 Port 3 pin 1 Input
40 P36 Port 3 pin 6 Output

1
2

9

3
4
5
6
7
8

40
39
38
37
36
35
34
33
32

P36
P31

P21

P27
P26
P25
P24
P23
P22

VCC

XTAL2

P37
P30

/RESET

R//W

/DS

31
30
29
28
2714

10
11
12
13

XTAL1

GND

P32
P00
P01

P20
P33
P34
P17
P16

Z86E21

DIP

15

26
25
24
23
22
21

20

16
17
18
19

/AS
P35

P02
P03

P06
P07

P05

P04 P13

P15
P14

P12
P11
P10

4

PIN DESCRIPTION (Continued)
Standard Mode

N/C

P30

P37

XTAL1

XTAL2

VCC

P36

P31

P27

P26

P25

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

N/C

N/C
P24
P23
P22
P21
P20
P33
P34
P17
P16
P15

/RESET

R//W

/DS

/AS

P35

GND

P32
P00
P01
P02

R//RL

7
8

9
10
11
12
13
14
15
16
17

38
37
36
35
34
33
32
31
30
29

39

Z86E21

PLCC

6543214443424140

18 19 20 21 22 23 24 25 26 27 28

Pin # Symbol Function Direction

14-16 P00-P02 Port 0 pin 0,1,2 In/Output
17 R//RL ROM/ROMless control Input
18-22 P03-P07 Port 0 pin 3,4,5,6,7 In/Output
23-27 P10-P14 Port 1 pin 0,1,2,3,4 In/Output

28 N/C Not Connected Input
29-31 P15-P17 Port 1 pin 5,6,7 In/Output
32 P34 Port 3 pin 4 Output
33 P33 Port 3 pin 3 Input

34-38 P20-P24 Port 2 pin 0,1,2,3,4 In/Output
39 N/C Not Connected Input
40-42 P25-P27 Port 2 pin 5,6,7 In/Output
43 P31 Port 3 pin 1 Input
44 P36 Port 3 pin 6 Output

Pin # Symbol Function Direction

1VCCPower Supply Input
2 XTAL2 Crystal, Oscillator Clock Output
3 XTAL1 Crystal, Oscillator Clock Input
4 P37 Port 3 pin 7 Output

5 P30 Port 3 pin 0 Input
6 N/C Not Connected Input
7 /RESET Reset Input
8 R//W Read/Write Output

9 /DS Data Strobe Output
10 /AS Address Strobe Output
11 P35 Port 3 pin 5 Output
12 GND Ground, GND Input
13 P32 Port 3 pin 2 Input

44-Lead PLCC Pin Assignments

44-Lead PLCC Pin Identification

5

34
35
36
37
38
39
40
41
42
43
44

21
20
19
18
17
16
15
14
13
12

22

33 32 31 30 29 28 27 26 25 24 23

1234567891011

GND

P30

P37

XTAL1

XTAL2

VCC

P36

P31

P27

P26

P25

/RESET

R//W

/DS

/AS

P35

GND

P32
P00
P01
P02

R//RL

GND
P24
P23
P22
P21
P20
P33
P34
P17
P16
P15

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

GND

Z86E21

QFP

44-Lead QFP Pin Identification

Pin # Symbol Function Direction

1-5 P03-P07 Port 0 pin 3,4,5,6,7 In/Output
6 GND Ground, GND Input
7-14 P10-P17 Port 1 pin 0,1,2,3,4,5,6,7 In/Output
15 P34 Port 3 pin 4 Output

16 P33 Port 3 pin 3 Input
17-21 P20-P24 Port 2 pin 0,1,2,3,4 In/Output
22 GND Ground, GND Input
23-25 P25-P27 Port 2 pin 5,6,7 In/Output

26 P31 Port 3 pin 1 Input
27 P36 Port 3 pin 6 Output
28 GND Ground, GND Input
29 V

CC

Power Supply Input

30 XTAL2 Crystal, Oscillator Clock Output

Pin # Symbol Function Direction

31 XTAL1 Crystal, Oscillator Clock Input
32 P37 Port 3 pin 7 Output
33 P30 Port 3 pin 0 Input
34 /RESET Reset Input

35 R//W Read/Write Output
36 /DS Data Strobe Output
37 /AS Address Strobe Output
38 P35 Port 3 pin 5 Output

39 GND Ground, GND Input
40 P32 Port 3 pin 2 Input
41-43 P00-P02 Port 0 pin 0,1,2 In/Output
44 R//RL ROM/ROMless control Input

44-Lead QFP Pin Assignments

6

Stresses greater than those listed under Absolute Maxi­mum Ratings may cause permanent damage to the de­vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational
sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for an extended pe­riod may affect device reliability.

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Test Load
Diagram).

ABSOLUTE MAXIMUM RATINGS

Symbol Description Min Max Units

V

CC

Supply Voltage* -0.3 +7.0 V

T

STG

Storage Temp -65 +150 C

T

A

Oper Ambient Temp † C

Notes:

* Voltages on all pins with respect to GND.

13.0 V Maximum on P30-P33.
† See Ordering Information

+5V

From Output

Under Test

9.1 kΩ

2.1 kΩ

150 pF

Test Load Diagram

7

DC CHARACTERISTICS

TA = 0°CT

A

= -40°C

to +70°C to +105°C Typical

Sym. Parameter Min Max Min Max @ 25°C Units Conditions

Max Input Voltage 7 7 V IIN 250 µA
Max Input Voltage 13 13 V P30-P33 Only

V

CH

Clock Input High Voltage 3.8 V

CC

3.8 V

CC

V Driven by External Clock Generator

V

CL

Clock Input Low Voltage -0.03 0.8 -0.03 0.8 V Driven by External Clock Generator

V

IH

Input High Voltage 2.0 V

CC

2.0 V

CC

V

V

IL

Input Low Voltage -0.3 0.8 -0.3 0.8 V

V

OH

Output High Voltage 2.4 2.4 V IOH = -2.0 mA

V

OL

Output Low Voltage 0.4 0.4 V IOL = +2.0 mA

V

RH

Reset Input High Voltage 3.8 V

CC

3.8 V

CC

V

V

Rl

Reset Input Low Voltage -0.03 0.8 -0.03 0.8 V

I

IL

Input Leakage -10 10 -10 10 µA 0V VIN +5.25V

I

OL

Output Leakage -10 10 -10 10 µA 0V VIN +5.25V

I

IR

Reset Input Current -50 -50 µAVCC= +5.25V, VRL = 0V

I

CC

Supply Current 50 50 25 mA @ 12 MHz

60 60 35 mA @ 16 MHz

I

CC1

Standby Current 15 15 5 mA HALT Mode VIN = OV, V

CC

@ 12 MHz

20 20 10 mA HALT Mode VIN = OV, V

CC

@ 16 MHz

I

CC2

Standby Current 20 20 5 µA STOP Mode VIN = OV, V

CC

@ 12 MHz

20 20 5 µA STOP Mode VIN = OV, V

CC

@ 16 MHz

Notes:

I

CC2

requires loading TMR (%F1H) with any value prior to STOP execution.

Use this sequence:

LD TMR,#00
NOP

8

R//W

9

12

19

3

16

13

4

5

8 18 11

6

17

10

15

7

14

21

Port 0, /DM

Port 1

/AS

/DS

(Read)

Port 1

/DS

(Write)

A - A

07

D - D IN

07

D - D OUT

07

A - A

07

External I/O or Memory Read/Write Timing

AC CHARACTERISTICS

External I/O or Memory Read or Write Timing Diagram

9

AC CHARACTERISTICS

External I/O or Memory Read and Write Timing Table

TA = 0°C to 70°CT

A

= -40°C to 105°C

12 MHz 16 MHz 12 MHz 16 MHz

No Symbol Parameter Max Min Max Min Max Min Max Min Units Notes

1 TdA(AS) Address Valid to /AS Rise Delay 35 20 35 25 ns [2,3]
2 TdAS(A) /AS Rise to Address Float Delay 45 30 45 35 ns [2,3]
3 TdAS(DR) /AS Rise to Read Data Req’d Valid 220 180 250 180 ns [1,2,3]
4 TwAS /AS Low Width 55 35 55 40 ns [2,3]

5 TdAZ(DS) Address Float to /DS Fall 0000ns
6 TwDSR /DS (Read) Low Width 185 135 185 135 ns [1,2,3]
7 TwDSW /DS (Write) Low Width 110 80 110 80 ns [1,2,3]
8 TdDSR(DR) /DS Fall to Read Data Req’d Valid 130 75 130 75 ns [1,2,3]

9 ThDR(DS) Read Data to /DS Rise Hold Time 0000ns[2,3]
10 TdDS(A) /DS Rise to Address Active Delay 45 35 65 50 ns [2,3]
11 TdDS(AS) /DS Rise to /AS Fall Delay 55 30 45 35 ns [2,3]
12 TdR/W(AS) R//W Valid to /AS Rise Delay 30 20 33 25 ns [2,3]

13 TdDS(R/W) /DS Rise to R//W Not Valid 35 30 50 35 ns [2,3]
14 TdDW(DSW) Write Data Valid to /DS Fall (Write) Delay 35 25 35 25 ns [2,3]
15 TdDS(DW) /DS Rise to Write Data Not Valid Delay 35 30 55 35 ns [2,3]
16 TdA(DR) Address Valid to Read Data Req’d Valid 255 200 310 230 ns [1,2,3]

17 TdAS(DS) /AS Rise to /DS Fall Delay 55 40 65 45 ns [2,3]
18 TdDI(DS) Data Input Setup to /DS Rise 75 60 75 60 ns [1,2,3]
19 TdDM(AS) /DM Valid to /AS Fall Delay 50 30 50 30 ns [2,3]

Clock Dependent Formulas

Number Symbol Equation

1 TdA(AS) 0.40TpC + 0.32
2 TdAS(A) 0.59TpC - 3.25
3 TdAS(DR) 2.38TpC + 6.14
4 TwAS 0.66TpC - 1.65

6 TwDSR 2.33TpC - 10.56
7 TwDSW 1.27TpC + 1.67
8 TdDSR(DR) 1.97TpC - 42.5
10 TdDS(A) 0.8TpC

11 TdDS(AS) 0.59TpC - 3.14
12 TdR/W(AS) 0.4TpC
13 TdDS(R/W) 0.8TpC - 15
14 TdDW(DSW) 0.4TpC

15 TdDS(DW) 0.88TpC - 19
16 TdA(DR) 4TpC - 20
17 TdAS(DS) 0.91TpC - 10.7
18 TsDI(DS) 0.8TpC - 10
19 TdDM(AS) 0.9TpC - 26.3

Notes:

[1] When using extended memory timing add 2 TpC.
[2] Timing numbers given are for minimum TpC.
[3] See clock cycle dependent characteristics table.

Standard Test Load

All timing references use 2.0V for a logic 1 and 0.8V for a logic 0.

10

AC CHARACTERISTICS

Additional Timing Diagram

Clock

1

3

4

5

2 2 3

T

IRQ

IN

N

Additional Timing

AC CHARACTERISTICS

Additional Timing Table

TA = 0°C to 70°CT

A

= -40°C to 105°C

12 MHz 16 MHz 12 MHz 16 MHz

No Symbol Parameter Max Min Max Min Max Min Max Min Units Notes

1 TpC Input Clock Period 83 1000 62.5 1000 83 1000 62.5 1000 ns [1]
2 TrC,TfC Clock Input Rise & Fall Times 15 10 15 10 ns [1]
3 TwC Input Clock Width 37 21 37 21 ns [1]
4 TwTinL Timer Input Low Width 75 50 75 50 ns [2]

5 TwTinH Timer Input High Width 3TpC 3TpC 3TpC 3TpC [2]
6 TpTin Timer Input Period 8TpC 8TpC 8TpC 8TpC [2]
7 TrTin,TfTin Timer Input Rise & Fall Times 100 100 100 100 ns [2]

8A TwIL Interrupt Request Input Low Times 70 50 70 50 ns [2,4]
8B TwIL Interrupt Request Input Low Times 3TpC 3TpC 3TpC 3TpC [2,5]
9 TwIH Interrupt Request Input High Times 3TpC 3TpC 3TpC 3TpC [2,3]

Notes:

[1] Clock timing references use 3.8V for a logic 1 and 0.8V for a logic 0.
[2] Timing references use 2.0V for a logic 1 and 0.8V for a logic 0.
[3] Interrupt references request via Port 3.
[4] Interrupt request via Port 3 (P31-P33).
[5] Interrupt request via Port 30.

11

AC CHARACTERISTICS

Handshake Timing Diagrams

Data In

1 2

3

4 5 6

/DAV

(Input)

RDY

(Output)

Next Data In Valid

Delayed RDY

Delayed DAV

Data In Valid

Input Handshake Timing

Data Out

/DAV

(Output)

RDY

(Input)

Next Data Out Valid

Delayed RDY

Delayed DAV

Data Out Valid

7

8 9

10

11

Output Handshake Timing

12

AC CHARACTERISTICS

Handshake Timing Table

TA = 0°C to 70°CT

A

= -40°C to 105°C

12 MHz 16 MHz 12 MHz 16 MHz Data

No Symbol Parameter Max Min Max Min Max Min Max Min Direction

1 TsDI(DAV) Data In Setup Time 0 0 0 0 IN
2 ThDI(DAV) Data In Hold Time 145 145 145 145 IN
3 TwDAV Data Available Width 110 110 110 110 IN
4 TdDAVI(RDY) DAV Fall to RDY Fall Delay 115 115 115 115 IN

5 TdDAVId(RDY) DAV Rise to RDY Rise Delay 115 115 115 115 IN
6 TdDO(DAV) RDY Rise to DAV Fall Delay 0 0 0 0 IN
7 TcLDAV0(RDY) Data Out to DAV Fall Delay TpC TpC TpC TpC OUT
8 TcLDAV0(RDY) DAV Fall to RDY Fall Delay 0 0 0 0 OUT

9 TdRDY0(DAV) RDY Fall to DAV Rise Delay 115 115 115 115 OUT
10 TwRDY RDY Width 110 110 110 110 OUT
11 TdRDY0d(DAV) RDY Rise to DAV Fall Delay 115 115 115 115 OUT

Zilog’s products are not authorized for use as critical compo­nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.

Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone [phone]
Telex 910-338-7621
FAX [phone]
Internet: http://www.zilog.com

© 1995 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer­chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.