ZiLOG Z86E04, Z86E08 PROCUREMENT SPECIFICATION

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RELIMINARY

RODUCT

PECIFICATION

Z86E04/E08

CMOS Z8 OTP M

PRODUCT DEVICES

Part Oscillator Operating Operating ROM Number Type

Z86E0412PEC Crystal 4.5V–5.5V –40 ° C/105 ° C 1 18-Pin DIP Z86E0412PSC1866 Crystal 4.5V–5.5V 0 ° C/70 ° C 1 18-Pin DIP Z86E0412PSC1903 RC 4.5V–5.5V 0 ° C/70 ° C 1 18-Pin DIP Z86E0412PEC1903 RC 4.5V–5.5V –40 ° C/105 ° C 1 18-Pin DIP Z86E0412SEC Crystal 4.5V–5.5V –40 ° C/105 ° C 1 18-Pin SOIC Z86E0412SSC1866 Crystal 4.5V–5.5V 0 ° C/70 ° C 1 18-Pin SOIC Z86E0412SSC1903 RC 4.5V–5.5V 0 ° C/70 ° C 1 18-Pin SOIC Z86E0412SEC1903 RC 4.5V–5.5V –40 ° C/105 ° C 1 18-Pin SOIC Z86E0812PEC Crystal 4.5V–5.5V –40 ° C/105 ° C 2 18-Pin DIP Z86E0812PSC1866 Crystal 4.5V–5.5V 0 ° C/70 ° C 2 18-Pin DIP Z86E0812PSC1903 RC 4.5V–5.5V 0 ° C/70 ° C 2 18-Pin DIP Z86E0812PEC1903 RC 4.5V–5.5V –40 ° C/105 ° C 2 18-Pin DIP Z86E0812SEC Crystal 4.5V–5.5V –40 ° C/105 ° C 2 18-Pin SOIC Z86E0812SSC1866 Crystal 4.5V–5.5V 0 ° C/70 ° C 2 18-Pin SOIC Z86E0812SSC1903 RC 4.5V–5.5V 0 ° C/70 ° C 2 18-Pin SOIC Z86E0812SEC1903 RC 4.5V–5.5V –40 ° C/105 ° C 2 18-Pin SOIC

Temperature (KB) Package

ICROCONTROLLERS

Several key product features of the extensive family of Zilog Z86E04/E08 CMOS OTP microcontrollers are presented in the above table. This table enables the user to identify which of the E04/E08 product variants most closely match the user’s application requirements.

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

FEATURES

■

14 Input/Output Lines Six Vectored, Prioritized Interrupts

■

(3 falling edge, 1 rising edge, 2 timers)

■

Two Analog Comparators

■

Program Options: – Low Noise

– ROM Protect – Auto Latch – Watch-Dog Timer (WDT) – EPROM/Test Mode Disable

GENERAL DESCRIPTION

Zilog's Z86E04/E08 Microcontrollers (MCU) are One-Time Programmable (OTP) members of Zilog’s single-chip Z8 MCU family that allow easy software development, debug, prototyping, and small production runs not economically desirable with masked ROM versions.

For applications demanding powerful I/O capabilities, the Z86E04/E08's dedicated input and output lines are grouped into three ports, and are configurable under software control to provide timing, status signals, or parallel I/O.

■

Two Programmable 8-Bit Counter/Timers, Each with 6-Bit Programmable Prescaler

■

WDT/ Power-On Reset (POR)

■

On-Chip Oscillator that Accepts XTAL, Ceramic Resonance, LC, RC, or External Clock

■

Clock-Free WDT Reset Low-Power Consumption (50 mw typical)

■

Fast Instruction Pointer (1 µ s @ 12 MHz)

■

RAM Bytes (125)

Note: All Signals with an overline, “

example: B/W

(WORD is active Low); B/W (BYTE is active

”, are active Low, for

Low, only). Power connections follow conventional descriptions be-

low:

Connection Circuit Device

Power

Ground GND

Two on-chip counter/timers, with a large number of user selectable modes, offload the system of administering real-time tasks such as counting/timing and I/O data communications.

P R E L I M I N A R Y

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers

Input

Port 3

Counter/

Timers (2)

Interrupt

Control

T wo Analog

Comparators

Vcc GND

ALU

FLAG

Pointer

General-Purpose

XTAL

Machine

Timing & Inst.

Control

OTP

Program

Counter

Port 2

I/O

(Bit Programmable)

Port 0

I/O

Figure 1. Functional Block Diagram

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

GENERAL DESCRIPTION (Continued)

D7–0

AD 10–0

Z8 MCU

Address

MUX

AD 10–0

Clear

P00

Clock

P01

Address Counter

PGM

Mode Logic

EPM

P32

XT1

D7–0

AD 10–0

3 bits

PGM

P30

EPROM

ROM PROT

Low Noise

VPP P33

Figure 2. EPROM Programming Mode Block Diagram

Data MUX

D7–0

Port 2

P31

P R E L I M I N A R Y

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P24 P25 P26 P27

XTAL2 XTAL1

P31 P32

P23 P22 P21 P20 GND P02 P01 P00 P33

910

Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers

PIN DESCRIPTION

D4 D5 D6 D7

EPM

910

D3 D2 D1 D0 GND PGM CLOCK CLEAR V

Figure 3. 18-Pin EPROM Mode Conﬁguration

Table 1. 18-Pin DIP Pin Identiﬁcation

EPROM Programming Mode Pin # Symbol Function Direction

1–4 D4–D7 Data 4, 5, 6, 7 In/Output 5V

Power Supply

6 NC No Connection 7CE

Chip Enable Input 8OEOutput Enable Input 9 EPM EPROM Prog Mode Input 10 V

Prog V oltage Input

11 Clear Clear Clock Input 12 Clock Address Input 13 PGM

Prog Mode Input 14 GND Ground 15–18 D0–D3 Data 0,1, 2, 3 In/Output

Figure 4. 18-Pin DIP/SOIC Mode Conﬁguration

Table 2. 18-Pin DIP/SOIC Pin Identiﬁcation

Standard Mode Pin # Symbol Function Direction

1–4 P24–P27 Port 2, Pins 4,5,6,7 In/Output 5V

Power Supply

6 XTAL2 Crystal Osc. Clock Output 7 XTAL1 Crystal Osc. Clock Input 8 P31 Port 3, Pin 1, AN1 Input 9 P32 Port 3, Pin 2, AN2 Input 10 P33 Port 3, Pin 3, REF Input 11–13 P00–P02 Port 0, Pins 0,1,2 In/Output 14 GND Ground 15–18 P20–P23 Port 2, Pins 0,1,2,3 In/Output

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the de-

dissipation should not exceed 462 mW for the package.

Power dissipation is calculated as follows: vice. This is a stress rating only; functional operation of the device at any condition above those indicated in the operational sections of these specifications is not implied. Exposure to absolute maximum rating conditions for an extended period may affect device reliability. Total power

Total Power Dissipation = V

x [I

–(sum of I

+ sum of [(V + sum of (V

)]

–V

) x I

x I

]

Parameter Min Max Units Note

Ambient Temperature under Bias –40 +105 C Storage Temperature –65 +150 C Voltage on any Pin with Respect to V

Voltage on V

Pin with Respect to V

SS SS

Voltage on Pins 7, 8, 9, 10 with Respect to V

–0.6 V

–0.7 +12 V 1 –0.3 +7 V

+1 V 2

Total Power Dissipation 1.65 W Maximum Allowable Current out of V

Maximum Allowable Current into V

300 mA 220 mA

Maximum Allowable Current into an Input Pin –600 +600 µA3 Maximum Allowable Current into an Open-Drain Pin –600 +600 µA4 Maximum Allowable Output Current Sinked by Any I/O Pin 25 mA Maximum Allowable Output Current Sourced by Any I/O Pin 25 mA Total Maximum Output Current Sinked by a Port 60 mA Total Maximum Output Current Sourced by a Port 45 mA

Notes:

1. This applies to all pins except where otherwise noted. Maximum current into pin must be ± 600 µA.

2. There is no input protection diode from pin to V

3. This excludes Pin 6 and Pin 7.

4. Device pin is not at an output Low state.

(not applicable to EPROM Mode).

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Z86E04/E08

From Output

Under Test

150 pF

Zilog CMOS Z8 OTP Microcontrollers

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test conditions as noted. All voltages are referenced to Ground. Positive current flows into the referenced pin (Figure 5).

Figure 5. Test Load Diagram

CAPACITANCE

= 25°C, VCC = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.

Parameter Min Max

Input capacitance 0 10 pF Output capacitance 0 20 pF I/O capacitance 0 25 pF

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DC ELECTRICAL CHARACTERISTICS

Standard Temperature

Sym Parameter

INMAX

Max Input Voltage 4.5V 12 V IIn<250 µA 1

Clock Input High Voltage

Clock Input Low Voltage

OL1

OL2

OFFSET

Input High Voltage 4.5V

Input Low Voltage 4.5V

Output High Voltage 4.5V VCC–0.4 4.8 V IOH = –2.0 mA 5

Output Low Voltage 4.5V 0.8 0.1 V IOL = +4.0 mA 5

Output Low Voltage 4.5V 0.8 0.8 V IOL = +12 mA, 5

Comparator Input Offset V oltage

VCC Low Voltage Auto Reset

Input Leakage (Input Bias Current of Comparator)

TA = 0°C to +70°C

[4]

Min Max @ 25°C Units Conditions Notes

Typical

5.5V 12 V IIn<250 µA 1

4.5V 0.8 V

VCC+0.3 2.8 V Driven by External

Clock Generator

5.5V 0.8 V

VCC+0.3 2.8 V Driven by External

Clock Generator

4.5V VSS–0.3 0.2 V

1.7 V Driven by External Clock Generator

5.5V VSS–0.3 0.2 V

1.7 V Driven by External Clock Generator

5.5V

0.7 V

VSS–0.3 VSS–0.3

CC CC

VCC+0.3 VCC+0.3

0.2 V

2.8

1.5

V V

5.5V VCC–0.4 4.8 V IOH = –2.0 mA 5

4.5V VCC–0.4 4.8 V Low Noise @ IOH = –0.5 mA

5.5V VCC–0.4 4.8 V Low Noise @ IOH = –0.5 mA

5.5V 0.4 0.1 V IOL = +4.0 mA 5

4.5V 0.4 0.1 V Low Noise @ IOL = 1.0 mA

5.5V 0.4 0.1 V Low Noise @ I

= 1.0 mA

5.5V 0.8 0.8 V IOL = +12 mA, 5

4.5V 25.0 10.0 mV

5.5V 25.0 10.0 mV

2.2 3.0 2.8 V @ 6 MHz Max. Int. CLK Freq.

4.5V –1.0 1.0 µAVIN = 0V, V

5.5V –1.0 1.0 µAVIN = 0V, V

CC CC

ICR

Output Leakage 4.5V –1.0 1.0 µAVIN = 0V, V

5.5V –1.0 1.0 µAVIN = 0V, V

Comparator Input

–1.0 V

CC CC

Common Mode Voltage Range

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Z86E04/E08

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Sym Parameter

CC1

Supply Current 4.5V 11.0 6.8 mA All Output and I/O Pins

Standby Current 4.5V 4.0 2.5 mA HALT Mode VIN = 0V,

Supply Current (Low Noise Mode)

TA = 0°C to +70°C

[4]

Min Max @ 25°C Units Conditions Notes

Typical

Floating @ 2 MHz

5.5V 11.0 6.8 mA All Output and I/O Pins Floating @ 2 MHz

4.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 8 MHz

5.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 8 MHz

4.5V 20.0 12.0 mA All Output and I/O Pins Floating @ 12 MHz

5.5V 20.0 12.0 mA All Output and I/O Pins Floating @ 12 MHz

VCC @ 2 MHz

5.5V 4.0 2.5 mA HALT Mode VIN = 0V, VCC @ 2 MHz

4.5V 5.0 3.0 mA HALT Mode VIN = 0V, VCC @ 8 MHz

5.5V 5.0 3.0 mA HALT Mode VIN = 0V, VCC @ 8 MHz

4.5V 7.0 4.0 mA HALT Mode VIN = 0V, VCC @ 12 MHz

5.5V 7.0 4.0 mA HALT Mode V

= 0V,

VCC @ 12 MHz

4.5V 11.0 6.8 mA All Output and I/O Pins Floating @ 1 MHz

5.5V 11.0 6.8 mA All Output and I/O Pins Floating @ 1 MHz

4.5V 13.0 7.5 mA All Output and I/O Pins Floating @ 2 MHz

5.5V 13.0 7.5 mA All Output and I/O Pins Floating @ 2 MHz

4.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 4 MHz

5.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 4 MHz

5,7

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DC ELECTRICAL CHARACTERISTICS (Continued)

Sym Parameter

Standby Current

CC1

TA = 0°C to +70°C

[4]

Min Max @ 25°C Units Conditions Notes

4.5V 4.0 2.5 mA HALT Mode V

Typical

(Low Noise Mode)

5.5V 4.0 2.5 mA HALT Mode VIN = 0V,

4.5V 4.5 2.8 mA HALT Mode VIN = 0V,

5.5V 4.5 2.8 mA HALT Mode VIN = 0V,

4.5V 5.0 3.0 mA HALT Mode VIN = 0V,

5.5V 5.0 3.0 mA HALT Mode VIN = 0V,

Standby Current 4.5V 10.0 1.0 µA STOP Mode VIN = 0V, V

CC2

5.5V 10.0 1.0 µA STOP Mode VIN = 0V,VCC

Auto Latch Low

ALL

Current

Auto Latch High

ALH

Current

Notes:

1. Port 2 and Port 0 only

2. V

= 0V = GND

3. The device operates down to V the voltage VLV at the ambient temperature. The VLV increases as the temperature decreases.

4. V

= 4.5 to 5.5V, typical values measured at VCC = 5.0V.

The V

5. Standard Mode (not Low EMI Mode)

6. Z86E08 only

7. All outputs unloaded and all inputs are at V

8. If analog comparator is selected, then the comparator inputs must be at V

voltage specification of 5.5 V guarantees 5.0 V ± 0.5V with typical values measured at VCC = 5.0V.

4.5V 32.0 16 µA 0V < VIN < V

5.5V 32.0 16 µA 0V < VIN < V

4.5V –16.0 –8.0 µA 0V < VIN < V

5.5V –16.0 –8.0 µA 0V < VIN < V

of the specified frequency for VLV . The minimum operational VCC is determined on the value of

or VSS level.

level.

= 0V,

@ 1 MHz

VCC @ 1 MHz

VCC @ 2 MHz

VCC @ 4 MHz

WDT is not Running

CC CC CC CC

7,8

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers

DC ELECTRICAL CHARACTERISTICS

Extended Temperature

Sym Parameter

INMAX

Max Input Voltage 4.5V 12.0 V IIN < 250 µA1

Clock Input High Voltage

Clock Input Low Voltage

OL1

OL2

OFFSET

Input High Voltage 4.5V 0.7 V

Input Low Voltage 4.5V VSS–0.3 0.2 V

Output High Voltage 4.5V VCC–0.4 4.8 V IOH = –2.0 mA 5

Output Low Voltage 4.5V 0.4 0.1 V IOL = +4.0 mA 5

Output Low Voltage 4.5V 1.0 0.3 V IOL = +12 mA, 5

Comparator Input Offset V oltage

VCC Low Voltage Auto Reset

Input Leakage (Input Bias Current of Comparator)

ICR

Output Leakage 4.5V –1.0 1.0 µAVIN = 0V, V

Comparator Input Common Mode Voltage Range

TA = –40°C to

+105°C Typical

[4]

Min Max @ 25°C Units Conditions Notes

5.5V 12.0 V IIN < 250 µA1

4.5V 0.8 V

CCVCC

+0.3 2.8 V Driven by External

Clock Generator

5.5V 0.8 V

CCVCC

+0.3 2.8 V Driven by External

Clock Generator

4.5V VSS–0.3 0.2 V

1.7 V Driven by External Clock Generator

5.5V VSS–0.3 0.2 V

1.7 V Driven by External Clock Generator

CCVCC

5.5V 0.7 V

CCVCC

5.5V VSS–0.3 0.2 V

+0.3 2.8 V +0.3 2.8 V

CC CC

1.5 V

5.5V VCC–0.4 4.8 V IOH = –2.0 mA 5

4.5V VCC–0.4 V Low Noise @ IOH = –0.5 mA

5.5V VCC–0.4 V Low Noise @ IOH = –0.5 mA

5.5V 0.4 0.1 V I

= +4.0 mA 5

4.5V 0.4 0.1 V Low Noise @ IOL = 1.0 mA

5.5V 0.4 0.1 V Low Noise @ IOL = 1.0 mA

5.5V 1.0 0.3 V IOL = +12 mA, 5

4.5V 25.0 10.0 mV

5.5V 25.0 10.0 mV

1.8 3.8 2.8 V @ 6 MHz Max. Int.

CLK Freq.

4.5V –1.0 1.0 µAVIN = 0V, V

5.5V –1.0 1.0 µAVIN = 0V, V

CC CC

0 VCC –1.5 V

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

DC ELECTRICAL CHARACTERISTICS (Continued)

= –40°C to

+105°C Typical

Sym Parameter

CC1

Supply Current 4.5V 11.0 6.8 mA All Output and I/O Pins

Standby Current 4.5V 5.0 2.5 mA HALT Mode VIN = 0V,

Supply Current (Low Noise Mode)

[4]

Min Max @ 25°C Units Conditions Notes

Floating @ 2 MHz

5.5V 11.0 6.8 mA All Output and I/O Pins Floating @ 2 MHz

4.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 8 MHz

5.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 8 MHz

4.5V 20.0 12.0 mA All Output and I/O Pins Floating @ 12 MHz

5.5V 20.0 12.0 mA All Output and I/O Pins Floating @ 12 MHz

VCC @ 2 MHz

5.5V 5.0 2.5 mA HALT Mode VIN = 0V, VCC @ 2 MHz

4.5V 5.0 3.0 mA HALT Mode VIN = 0V, VCC @ 8 MHz

5.5V 5.0 3.0 mA HALT Mode VIN = 0V, VCC @ 8 MHz

4.5V 7.0 4.0 mA HALT Mode VIN = 0V, VCC @ 12 MHz

5.5V 7.0 4.0 mA HALT Mode VIN = 0V,

@ 12 MHz

4.5V 11.0 6.8 mA All Output and I/O Pins Floating @ 1 MHz

5.5V 11.0 6.8 mA All Output and I/O Pins Floating @ 1 MHz

4.5V 13.0 7.5 mA All Output and I/O Pins Floating @ 2 MHz

5.5V 13.0 7.5 mA All Output and I/O Pins Floating @ 2 MHz

4.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 4 MHz

5.5V 15.0 8.2 mA All Output and I/O Pins Floating @ 4 MHz

5,7

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers

Sym Parameter

CC1

Standby Current (Low Noise Mode)

TA = –40°C to +105°C

VCC [4]

Min Max @ 25°C Units Conditions Notes

4.5V 4.0 2.5 mA HALT Mode V

Typical

@ 1 MHz

= 0V,

5.5V 4.0 2.5 mA HALT Mode VIN = 0V, VCC @ 1 MHz

4.5V 4.5 2.8 mA HALT Mode VIN = 0V, VCC @ 2 MHz

5.5V 4.5 2.8 mA HALT Mode VIN = 0V, VCC @ 2 MHz

4.5V 5.0 3.0 mA HALT Mode VIN = 0V, VCC @ 4 MHz

5.5V 5.0 3.0 mA HALT Mode VIN = 0V, VCC @ 4 MHz

CC2

Standby Current 4.5V 20 1.0 µA STOP Mode VIN = 0V, VCC

7,8

WDT is not Running

5.5V 20 1.0 µA STOP Mode VIN = 0V, VCC

7,8

WDT is not Running

ALL

ALH

Notes:

1. Port 2 and Port 0 only

2. V

3. The device operates down to VLV of the specified frequency for VLV . The minimum operational VCC is determined on the value of

4. V

5. Standard Mode (not Low EMI Mode)

6. Z86E08 only

7. All outputs unloaded and all inputs are at V

8. If analog comparator is selected, then the comparator inputs must be at V

Auto Latch Low Current

Auto Latch High Current

= 0V = GND

the voltage V

= 4.5V to 5.5V, typical values measured at VCC = 5.0V

at the ambient temperature. The VLV increases as the temperature decreases.

4.5V 40 16 µA 0V < VIN < V

5.5V 40 16 µA 0V < VIN < V

4.5V –20.0 –8.0 µA 0V < VIN < V

5.5V –20.0 –8.0 µA 0V < VIN < V

or VSS level.

CC CC CC CC

level.

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

AC ELECTRICAL CHARACTERISTICS

Clock

IRQ

Figure 6. AC Electrical Timing Diagram

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers

AC ELECTRICAL CHARACTERISTICS

Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) Standard Temperature

8 MHz 12 MHz

No Symbol Parameter

1 TpC Input Clock Period 4.5V 125 DC 83 DC ns 1

2 TrC,TfC Clock Input Rise

and Fall Times

3 TwC Input Clock Width 4.5V 62 41 ns 1

4 TwTinL Timer Input Low Width 4.5V 100 100 ns 1

5 TwTinH Timer Input High Width 4.5V 5TpC 5TpC 1

6 TpTin Timer Input Period 4.5V 8TpC 8TpC 1

7 TrTin,

TtTin

8 TwIL Int. Request Input

9 TwIH Int. Request Input

10 Twdt Watch-Dog Timer

11 Tpor

Notes:

1. Timing Reference uses 0.7 V

2. Interrupt request through Port 3 (P33–P31).

Timer Input Rise and Fall Time

Low Time

High Time

Delay Time for Timeout Power-On Reset Time 4.5V 20 80 20 80 ms 1

for a logic 1 and 0.2 VCC for a logic 0.

5.5V 125 DC 83 DC ns 1

4.5V 25 15 ns 1

5.5V 25 15 ns 1

5.5V 62 41 ns 1

5.5V 70 70 ns 1

5.5V 5TpC 5TpC 1

5.5V 8TpC 8TpC 1

4.5V 100 100 ns 1

5.5V 100 100 ns 1

4.5V 70 70 ns 1,2

5.5V 70 70 ns 1,2

4.5V 5TpC 5TpC 1,2

5.5V 5TpC 5TpC 1,2

4.5V 12 12 ms 1

5.5V 12 12 ms 1

5.5V 20 80 20 80 ms 1

TA= 0 °C to +70 °C

Min Max Min Max Units Notes

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AC ELECTRICAL CHARACTERISTICS

Timing Table (Standard Mode for SCLK/TCLK = XTAL/2) Extended Temperature

TA= –40 °C to +105 °C

8 MHz 12 MHz

No Symbol Parameter

1 TpC Input Clock Period 4.5V 125 DC 83 DC ns 1

5.5V 125 DC 83 DC ns 1

2 TrC,TfC Clock Input Rise

and Fall Times

4.5V 25 15 ns 1

5.5V 25 15 ns 1

3 TwC Input Clock Width 4.5V 62 41 ns 1

5.5V 62 41 ns 1

4 TwTinL Timer Input Low Width 4.5V 70 70 ns 1

5.5V 70 70 ns 1

5 TwTinH Timer Input High Width 4.5V 5TpC 5TpC 1

5.5V 5TpC 5TpC 1

6 TpTin Timer Input Period 4.5V 8TpC 8TpC 1

5.5V 8TpC 8TpC 1

7 TrTin,

TtTin

8 TwIL Int. Request Input

9 TwIH Int. Request Input

10 T wdt Watch-Dog Timer

11 Tpor

Notes:

1. Timing Reference uses 0.7 V

2. Interrupt request made through Port 3 (P33–P31).

Timer Input Rise and Fall Time

4.5V 100 100 ns 1

5.5V 100 100 ns 1

4.5V 70 70 ns 1,2

Low Time

5.5V 70 70 ns 1,2

4.5V 5TpC 5TpC 1,2

High Time

5.5V 5TpC 5TpC 1,2

4.5V 10 10 ms 1

Delay Time for Timeout

5.5V 10 10 ms 1

Power-On Reset Time 4.5V 12 100 12 100 ms 1

5.5V 12 100 12 100 ms 1

for a logic 1 and 0.2 VCC for a logic 0.

Min Max Min Max Units Notes

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers

AC ELECTRICAL CHARACTERISTICS

Low Noise Mode, Standard Temperature

TA= 0 °C to +70 °C

1 MHz 4 MHz

No Symbol Parameter

1 TPC Input Clock Period 4.5V 1000 DC 250 DC ns 1

2TrC

TfC

3 TwC Input Clock Width 4.5V 500 125 ns 1

4. TwTinL Timer Input Low Width 4.5V 70 70 ns 1

5 TwTinH Timer Input High Width 4.5V 2.5TpC 2.5TpC 1

6 TpTin Timer Input Period 4.5V 4TpC 4TpC 1

7 TrTin,

TtTin

8 TwIL

Low Time

9 TwIH

High Time

10 T wdt Watch-Dog Timer

Notes:

1. Timing Reference uses 0.7 V

2. Interrupt request through Port 3 (P33–P31).

Clock Input Rise and Fall Times

Timer Input Rise and Fall Time

Int. Request Input 4.5V 70 70 ns 1,2

Int. Request Input 4.5V 2.5TpC 2.5TpC 1,2

Delay Time for Timeout

for a logic 1 and 0.2 VCC for a logic 0.

5.5V 1000 DC 250 DC ns 1

4.5V 25 25 ns 1

5.5V 25 25 ns 1

5.5V 500 125 ns 1

5.5V 70 70 ns 1

5.5V 2.5TpC 2.5TpC 1

5.5V 4TpC 4TpC 1

4.5V 100 100 ns 1

5.5V 100 100 ns 1

5.5V 70 70 ns 1,2

5.5V 2.5TpC 2.5TpC 1,2

4.5V 12 12 ms 1

5.5V 12 12 ms 1

Min Max Min Max Units Notes

DS97Z8X1104 P R E L I M I N A R Y 17

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

AC ELECTRICAL CHARACTERISTICS (Continued)

Low Noise Mode, Extended Temperature

TA= –40 °C to +105 °C

1 MHz 4 MHz

No Symbol Parameter

1 TPC Input Clock Period 4.5V 1000 DC 250 DC ns 1

2TrC

TfC

Clock Input Rise and Fall Times

3 TwC Input Clock Width 4.5V 500 125 ns 1

4. TwTinL Timer Input Low Width 4.5V 70 70 ns 1

5 TwTinH Timer Input High Width 4.5V 2.5TpC 2.5TpC 1

6 TpTin Timer Input Period 4.5V 4TpC 4TpC 1

7 TrTin,

TtTin

Timer Input Rise and Fall Time

8 TwIL Int. Request Input

Low Time

9 TwIH Int. Request Input

High Time

10 T wdt Watch-Dog Timer

Delay Time for Timeout

Notes:

1. Timing Reference uses 0.7 V

2. Interrupt request through Port 3 (P33–P31).

for a logic 1 and 0.2 VCC for a logic 0.

Min Max Min Max Units Notes

5.5V 1000 DC 250 DC ns 1

4.5V 25 25 ns 1

5.5V 25 25 ns 1

5.5V 500 125 ns 1

5.5V 70 70 ns 1

5.5V 2.5TpC 2.5TpC 1

5.5V 4TpC 4TpC 1

4.5V 100 100 ns 1

5.5V 100 100 ns 1

4.5V 70 70 ns 1,2

5.5V 70 70 ns 1,2

4.5V 2.5TpC 2.5TpC 1,2

5.5V 2.5TpC 2.5TpC 1,2

4.5V 10 10 ms 1

5.5V 10 10 ms 1

18 P R E L I M I N A R Y DS97Z8X1104

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers

LOW NOISE VERSION Low EMI Emission

The Z86E04/E08 can be programmed to operate in a Low EMI Emission Mode by means of a mask ROM bit option. Use of this feature results in:

■ All pre-driver slew rates reduced to 10 ns typical.

■ Internal SCLK/TCLK operation limited to a maximum of

4 MHz–250 ns cycle time.

PIN FUNCTIONS OTP Programming Mode

D7–D0

EPROM through this data bus.

VCC

Mode and 6.4V during the other modes (Program, Program Verify, and so on).

EPROM Read Mode, Program Mode, and Program Verify Mode.

OE Bus direction. When this pin is Low, the Data Bus is output. When High, the Data Bus is input.

EPM ent EPROM Program Modes by applying different voltages.

Data Bus.

Power Supply.

Chip Enable

Output Enable

Data can be read from, or written to, the

It is typically 5V during EPROM Read

(active Low). This pin is active during

(active Low). This pin drives the Data

EPROM Program Mode.

This pin controls the differ-

■ Output drivers have resistances of 500 Ohms (typical).

■ Oscillator divide-by-two circuitry eliminated.

The Low EMI Mode is mask-programmable to be selected by the customer at the time the ROM code is submitted.

Clock

Address Clock.

address counter increases by one with one clock cycle. PGM

Program Mode

programs the data to the EPROM through the Data Bus.

This pin is a clock input. The internal

(active Low). A Low level at this pin

Application Precaution

The production test-mode environment may be enabled accidentally during normal operation if surges above VCC occur on the XTAL1 pin.

In addition, processor operation of Z8 OTP devices may be affected by OE pins while the microcontroller is in Standard Mode.

Recommendations for dampening voltage surges in both test and OTP Mode include the following:

■ Using a clamping diode to V

excessive noise

surges on the VPP, CE, EPM,

excessive noise

Program Voltage.

age. Clear

Clear

(active High). This pin resets the internal ad-

dress counter at the High Level.

This pin supplies the program volt-

■ Adding a capacitor to the affected pin.

Note: Programming the EPROM/Test Mode Disable option will prevent accidental entry into EPROM Mode or Test Mode.

DS97Z8X1104 P R E L I M I N A R Y 19

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

PIN FUNCTIONS (Continued)

XTAL1, XTAL2

and output, respectively). These pins connect a parallelresonant crystal, LC, or an external single-phase clock (8 MHz or 12 MHz max) to the on-chip clock oscillator and buffer.

Port 0, P02–P00. Port 0 is a 3-bit bidirectional, Schmitttriggered CMOS-compatible I/O port. These three I/O lines can be globally configured under software control to be inputs or outputs (Figure 7).

Crystal In, Crystal Out

(time-based input

Auto Latch. The Auto Latch puts valid CMOS levels on all CMOS inputs (except P33, P32, P31) that are not externally driven. A valid CMOS level, rather than a floating node, reduces excessive supply current flow in the input buffer. On Power-up and Reset, the Auto Latch will set the ports to an undetermined state of 0 or 1. Default condition is Auto Latches enabled.

Port 0 (I/O)

Out

1.5 2.3 Hysteresis

Figure 7. Port 0 Conﬁguration

V @ 5.0V

R 500 kΩ

PAD

Auto Latch Option

20 P R E L I M I N A R Y DS97Z8X1104

Page 21

Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers Port 2, P27–P20. Port 2 is an 8-bit, bit programmable, bi-

directional, Schmitt-triggered CMOS-compatible I/O port. These eight I/O lines can be configured under software

control to be inputs or outputs, independently. Bits programmed as outputs can be globally programmed as either push-pull or open-drain (Figure 8).

Port 2 (I/O)

Open-Drain

/OE

Out

1.5 2.3 Hysteresis

Figure 8. Port 2 Conﬁguration

PAD

VCC @ 5.0V

Auto Latch Option

R 500 kΩ

DS97Z8X1104 P R E L I M I N A R Y 21

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

PIN FUNCTIONS (Continued)

Port 3, P33–P31. Port 3 is a 3-bit, CMOS-compatible port

with three fixed input (P33–P31) lines. These three input lines can be configured under software control as digital Schmitt-trigger inputs or analog inputs.

Z86E04

and

Z86E08

R247 = P3M

0 = Digital 1 = Analog

These three input lines are also used as the interrupt sources IRQ0–IRQ3, and as the timer input signal TIN (Figure 9).

Port 3

PAD

P31 (AN1)

P32 (AN2)

P33 (REF)

TIN

DIG.

P31 Data Latch IRQ2

AN.

IRQ3

P32 Data Latch IRQ0

P33 Data Latch

IRQ1

IRQ 0,1,2 = Falling Edge Detection IRQ3 = Rising Edge Detection

Figure 9. Port 3 Conﬁguration

22 P R E L I M I N A R Y DS97Z8X1104

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers Comparator Inputs. Two analog comparators are added

to input of Port 3, P31, and P32, for interface flexibility. The comparators reference voltage P33 (REF) is common to both comparators.

Typical applications for the on-board comparators; Zero crossing detection, A/D conversion, voltage scaling, and threshold detection. In Analog Mode, P33 input functions serve as a reference voltage to the comparators.

The dual comparator (common inverting terminal) features a single power supply which discontinues power in STOP

FUNCTIONAL DESCRIPTION

The following special functions have been incorporated into the Z8 devices to enhance the standard Z8 core architecture to provide the user with increased design flexibility.

INT OSC XTAL OSC

Mode. The common voltage range is 0–4 V when the V

is 5.0V; the power supply and common mode rejection ratios are 90 dB and 60 dB, respectively.

Interrupts are generated on either edge of Comparator 2's output, or on the falling edge of Comparator 1's output. The comparator output is used for interrupt generation, Port 3 data inputs, or TIN through P31. Alternatively, the comparators can be disabled, freeing the reference input (P33) for use as IRQ1 and/or P33 input.

RESET. This function is accomplished by means of a Power-On Reset or a Watch-Dog Timer Reset. Upon powerup, the Power-On Reset circuit waits for T

ms, plus 18

POR

clock cycles, then starts program execution at address 000C (Hex) (Figure 10). The Z8 control registers' reset value is shown in Table 3.

POR

(Cold Start)

Delay Line

TPOR msec

P27

(Stop Mode)

Figure 10. Internal Reset Conﬁguration

Power-On Reset (POR). A timer circuit clocked by a ded-

icated on-board RC oscillator is used for a POR timer function. The POR time allows VCC and the oscillator circuit to stabilize before instruction execution begins. The POR timer circuit is a one-shot timer triggered by one of the four following conditions:

■ Power-bad to power-good status

■ Stop-Mode Recovery

■ WDT time-out

18 CLK

Reset Filiter

Chip Reset

Watch-Dog Timer Reset. The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its terminal count. The WDT is initially enabled by executing the WDT instruction and is retriggered on subsequent execution of the WDT instruction. The timer circuit is driven by an onboard RC oscillator.

■ WDH time-out

DS97Z8X1104 P R E L I M I N A R Y 23

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

FUNCTIONAL DESCRIPTION (Continued)

Table 3. Control Registers

Reset Condition

Addr. Reg. D7 D6 D5 D4 D3 D2 D1 D0 Comments

FF SPL 0 0 0 0 0 0 0 0 FD RP 0 0 0 0 0 0 0 0 FC FLAGS U U U U U U U U FB IMR 0 U U U U U U U FA IRQ U U 0 0 0 0 0 0 IRQ3 is used for positive edge

detection F9 IPR U U U U U U U U F8* P01M U U U 0 U U 0 1 F7* P3M U U U U U U 0 0 F6* P2M 1 1 1 1 1 1 1 1 Inputs after reset F5 PRE0 U U U U U U U 0 F4 T0 U U U U U U U U F3 PRE1 U U U U U U 0 0 F2 T1 U U U U U U U U F1 TMR 0 0 0 0 0 0 0 0

Note: *Registers are not reset after a STOP-Mode Recovery using P27 pin. A subsequent reset will cause these control registers to be reconfigured as shown in Table 4 and the user must avoid bus contention on the port pins or it may affect device reliability.

24 P R E L I M I N A R Y DS97Z8X1104

Page 25

Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers Program Memory. The Z86E04/E08 addresses up to

1K/2KB of Internal Program Memory (Figure 11). The first 12 bytes of program memory are reserved for the interrupt vectors. These locations contain six 16-bit vectors that correspond to the six available interrupts. Bytes 0–1024/2048 are on-chip one-time programmable ROM.

1023/2047

Location of

First Byte of

Instruction

Executed

After RESET

Interrupt

Vector

(Lower Byte)

Interrupt

Vector

(Upper Byte)

On-Chip

ROM

9 8

7 6

5 4

3 2

1 0

IRQ5 IRQ5 IRQ4 IRQ4 IRQ3 IRQ3 IRQ2 IRQ2 IRQ1 IRQ1 IRQ0 IRQ0

Identifiers

3FH/7FFH

3FFH/7FFH

0CH 0BH

0AH

09H 08H

07H 06H

05H 04H

03H 02H

01H 00H

Register File. The Register File consists of three I/O port registers, 124 general-purpose registers, and 14 control and status registers R0–R3, R4–R127 and R241–R255, respectively (Figure 12). General-purpose registers occupy the 04H to 7FH address space. I/O ports are mapped as per the existing CMOS Z8.

Location

255 (FFH) 254 (FE) 253 (FD)

252 (FC) 251 (FB)

250 (FA) 249 (F9)

248 (F8) 247 (F7)

246 (F6) 245 (F5) 244 (F4) 243 (F3) 242 (F2)

241 (F1H)

General-Purpose Register

Program Control Flags

Interrupt Mask Register

Interrupt Request Register

Interrupt Priority Register

Ports 0-1 Mode

Port 3 Mode Port 2 Mode

T0 Prescaler

Timer/Counter 0

T1 Prescaler

Timer/Counter 1

Timer Mode

Identifiers SPLStack Pointer (Bits 7-0)

GPR RP FLAGS

IMR IRQ IPR P01M P3M P2M PRE0 T0 PRE1 T1 TMR

Figure 11. Program Memory Map

128

127 (7FH)

4 3 2 1

0 (00H)

Not Implemented

General-Purpose

Registers

Port 3 Port 2

Reserved

Port 0

Figure 12. Register File

P3 P2 P1 P0

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

FUNCTIONAL DESCRIPTION (Continued)

The Z8 instructions can access registers directly or indirectly through an 8-bit address field. This allows short 4-bit register addressing using the Register Pointer.

In the 4-bit mode, the register file is divided into eight working register groups, each occupying 16 continuous locations. The Register Pointer (Figure 13) addresses the starting location of the active working-register group.

r7 r6 r5 r4 R253

The upper nibble of the register file address provided by the register pointer specifies the active working-register group.

70 6F

60 5F

50 4F

40 3F

30 2F

20 1F

10 0F

*Expanded Register Group (0) is selected in this figure by handling bits D3 to D0 as "0" in Register R253(RP).

Specified Working

I/O Ports

r3 r2 r1 r0

(Register Pointer)

R15 to R0

The lower nibble of the register file address provided by the instruction points to the specified register.

R15 to R0

R15 to R4* R3 to R0

Stack Pointer. The Z8 has an 8-bit Stack Pointer (R255) used for the internal stack that resides within the 124 general-purpose registers.

General-Purpose Registers (GPR). These registers are undefined after the device is powered up. The registers keep their last value after any reset, as long as the reset occurs in the VCC voltage-specified operating range. Note: Register R254 has been designated as a general-purpose register and is set to 00 Hex after any reset or Stop-Mode Recovery.

Counter/Timer. There are two 8-bit programmable counter/timers (T0 and T1), each driven by its own 6-bit programmable prescaler. The T1 prescaler is driven by internal or external clock sources; however, the T0 can be driven by the internal clock source only (Figure 14).

The 6-bit prescalers divide the input frequency of the clock source by any integer number from 1 to 64. Each prescaler drives its counter, which decrements the value (1 to 256) that has been loaded into the counter. When both counter and prescaler reach the end of count, a timer interrupt request IRQ4 (T0) or IRQ5 (T1) is generated.

The counter can be programmed to start, stop, restart to continue, or restart from the initial value. The counters are also programmed to stop upon reaching zero (Single-Pass Mode) or to automatically reload the initial value and continue counting (Modulo-N Continuous Mode).

The counters, but not the prescalers, are read at any time without disturbing their value or count mode. The clock source for T1 is user-definable and is either the internal microprocessor clock divided by four, or an external signal input through Port 3. The Timer Mode register configures the external timer input (P31) as an external clock, a trigger input that is retriggerable or non-retriggerable, or used as a gate input for the internal clock.

Figure 13. Register Pointer

26 P R E L I M I N A R Y DS97Z8X1104

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers

Internal Data Bus

OSC

÷ 2

Clock Logic

TIN P31

Internal Clock

External Clock

÷ 4

Internal Clock Gated Clock Triggered Clock

Write Write Read

PRE0

Initial Value

6-Bit

÷ 4

Write Write Read

Down

Counter

6-Bit

Down

Counter

PRE1

Initial Value

8-bit

Down

Counter

8-Bit

Down

Counter

Initial Value

Current Value

IRQ4

IRQ5

Current Value

* Note: By passed, if Low EMI Mode is selected.

Figure 14. Counter/Timers Block Diagram

Internal Data Bus

DS97Z8X1104 P R E L I M I N A R Y 27

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

FUNCTIONAL DESCRIPTION (Continued)

Interrupts. The Z8 has six interrupts from six different

sources. These interrupts are maskable and prioritized (Figure 15). The sources are divided as follows: the falling edge of P31 (AN1), P32 (AN2), P33 (REF), the rising edge of P32 (AN2), and two counter/timers. The Interrupt Mask Register globally or individually enables or disables the six interrupt requests (Table 4).

When more than one interrupt is pending, priorities are resolved by a programmable priority encoder that is controlled by the Interrupt Priority register. All Z8 interrupts are vectored through locations in program memory. When an Interrupt machine cycle is activated, an Interrupt Request is granted. This disables all subsequent interrupts, saves the Program Counter and Status Flags, and then branches to the program memory vector location reserved for that interrupt. This memory location and the next byte contain the 16-bit starting address of the interrupt service routine for that particular interrupt request.

To accommodate polled interrupt systems, interrupt inputs are masked and the interrupt request register is polled to determine which of the interrupt requests needs service.

Note: User must select any Z86E08 mode in Zilog's C12 ICEBOX™ emulator. The rising edge interrupt is not supported on the CCP emulator (a hardware/software workaround must be employed).

Table 4. Interrupt Types, Sources, and Vectors

Vector

Name Source Location Comments

IRQ0 AN2(P32) 0,1 External (F)Edge IRQ1 REF(P33) 2,3 External (F)Edge IRQ2 AN1(P31) 4,5 External (F)Edge IRQ3 AN2(P32) 6,7 External (R)Edge IRQ4 T0 8,9 Internal IRQ5 T1 10,11 Internal

Notes:

F = Falling edge triggered R = Rising edge triggered

Interrupt

Request

Global

Interrupt

Enable

IRQ0 - IRQ5

IRQ

IMR

IPR

PRIORITY

LOGIC

Vector Select

Figure 15. Interrupt Block Diagram

28 P R E L I M I N A R Y DS97Z8X1104

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers Clock. The Z8 on-chip oscillator has a high-gain, parallel-

resonant amplifier for connection to a crystal, LC, RC, ceramic resonator, or any suitable external clock source (XTAL1 = INPUT, XTAL2 = OUTPUT). The crystal should be AT cut, up to 12 MHz max., with a series resistance (RS) of less than or equal to 100 Ohms.

XTAL1

XTAL2

Ceramic Resonator or Crystal C1, C2 = 47 pF TYP * F = 8 MHz

XTAL1

XTAL2

The crystal should be connected across XTAL1 and XTAL2 using the vendors crystal recommended capacitors from each pin directly to device ground pin 14 (Figure 16). Note that the crystal capacitor loads should be connected to VSS, Pin 14 to reduce Ground noise injection.

XTAL1

XTAL2

External Clock

RC @ 5V Vcc (TYP)

C1 = 100 pF R = 2K F = 6 MHz

XTAL1

XTAL2

* Typical value including pin parasitics

Figure 16. Oscillator Conﬁguration

DS97Z8X1104 P R E L I M I N A R Y 29

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

FUNCTIONAL DESCRIPTION (Continued)

Table 5. Typical Frequency vs. RC Values

VCC = 5.0V @ 25°C

Load Capacitor

33 pFd 56 pFd 100 pFd 0.00 1µFd

Resistor (R)

1.0M 33K 31K 20K 20K 12K 11K 1.4K 1.4K 560K 56K 52K 34K 32K 20K 19K 2.5K 2.4K 220K 144K 130K 84K 78K 48K 45K 6K 6K 100K 315K 270K 182K 164K 100K 95K 12K 12K 56K 552K 480K 330K 300K 185K 170K 23K 22K 20K 1.4M 1M 884K 740K 500K 450K 65K 61K 10K 2.6M 2M 1.6M 1.3M 980K 820K 130K 123K 5K 4.4M 3M 2.8M 2M 1.7K 1.3M 245K 225K 2K 8M 5M 6M 4M 3.8K 2.7M 600K 536K 1K 12M 7M 8.8M 6M 6.3K 4.2M 1.0M 950K

Notes:

A = STD Mode Frequency. B = Low EMI Mode Frequency.

A(Hz) B(Hz) A(Hz) B(Hz) A(Hz) B(Hz) A(Hz) B(Hz)

Table 6. Typical Frequency vs. RC Values

= 3.3V @ 25°C

Load Capacitor

Resistor (R) 33 pFd 56 pFd 100 pFd 0.00 1µFd

A(Hz) B(Hz) A(Hz) B(Hz) A(Hz) B(Hz) A(Hz) B(Hz)

1.0M 18K 18K 12K 12K 7.4K 7.7K 1K 1K 560K 30K 30K 20K 20K 12K 12K 1.6K 1.6K 220K 70K 70K 47K 47K 30K 30K 4K 4K 100K 150K 148K 97K 96K 60K 60K 8K 8K 56K 268K 250K 176K 170K 100K 100K 15K 15K 20K 690M 600K 463K 416K 286K 266K 40K 40K 10K 1.2M 1M 860K 730K 540K 480K 80K 76K 5K 2M 1.7M 1.5M 1.2M 950K 820K 151K 138K 2K 4.6M 3M 3.3M 2.4M 2.2M 1.6M 360K 316K 1K 7M 4.6M 5M 3.6M 3.6K 2.6M 660K 565K

Notes:

A = STD Mode Frequency. B = Low EMI Mode Frequency.

30 P R E L I M I N A R Y DS97Z8X1104

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers HALT Mode. This instruction turns off the internal CPU

clock but not the crystal oscillation. The counter/timers and external interrupts IRQ0, IRQ1, IRQ2 and IRQ3 remain active. The device is recovered by interrupts, either externally or internally generated. An interrupt request must be executed (enabled) to exit HALT Mode. After the interrupt service routine, the program continues from the instruction after the HALT.

Note: On the C12 ICEBOX, the IRQ3 does not wake the device out of HALT Mode.

STOP Mode. This instruction turns off the internal clock and external crystal oscillation and reduces the standby current to 10 µA. The STOP Mode is released by a RESET through a Stop-Mode Recovery (pin P27). A Low input condition on P27 releases the STOP Mode. Program execution begins at location 000C(Hex). However, when P27 is used to release the STOP Mode, the I/O port Mode registers are not reconfigured to their default power-on conditions. This prevents any I/O, configured as output when the STOP instruction was executed, from glitching to an unknown state. To use the P27 release approach with STOP Mode, use the following instruction:

Watch-Dog Timer (WDT). The Watch-Dog Timer is enabled by instruction WDT. When the WDT is enabled, it cannot be stopped by the instruction. With the WDT instruction, the WDT is refreshed when it is enabled within every 1 Twdt period; otherwise, the controller resets itself, The WDT instruction affects the flags accordingly; Z=1, S=0, V=0.

WDT = 5F (Hex)

Opcode WDT (5FH). The first time Opcode 5FH is executed, the WDT is enabled and subsequent execution clears the WDT counter. This must be done at least every T otherwise, the WDT times out and generates a reset. The generated reset is the same as a power-on reset of T plus 18 XTAL clock cycles. The software enabled WDT does not run in STOP Mode.

Opcode WDH (4FH). When this instruction is executed it enables the WDT during HALT. If not, the WDT stops when entering HALT. This instruction does not clear the counters, it just makes it possible to have the WDT running during HALT Mode. A WDH instruction executed without executing WDT (5FH) has no effect.

WDT

POR

; ,

LD P2M, #1XXX XXXXB NOP STOP

X = Dependent on user's application.

Note: A low level detected on P27 pin will take the device out of STOP Mode even if configured as an output.

In order to enter STOP or HALT Mode, it is necessary to first flush the instruction pipeline to avoid suspending execution in mid-instruction. To do this, the user executes a NOP (opcode=FFH) immediately before the appropriate SLEEP instruction, such as:

FF NOP ; clear the pipeline 6F STOP ; enter STOP Mode

or FF NOP ; clear the pipeline 7F HALT ; enter HALT Mode

Permanent WDT. Selecting the hardware enabled Permanent WDT option, will automatically enable the WDT upon exiting reset. The permanent WDT will always run in HALT Mode and STOP Mode, and it cannot be disabled.

Auto Reset Voltage (VLV). The Z8 has an auto-reset built- in. The auto-reset circuit resets the Z8 when it detects the VCC below VLV.

Figure 17 shows the Auto Reset Voltage versus temperature. If the VCC drops below the VCC operating voltage range, the Z8 will function down to the VLV unless the internal clock frequency is higher than the specified maximum VLV frequency.

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

FUNCTIONAL DESCRIPTION (Continued)

Vcc

(Volts)

2.9

2.8

2.7

2.6

2.5

2.4

2.3

–40°C

–20°C0°C20°C

Figure 17. Typical Auto Reset Voltage

(VLV) vs. Temperature

40°C

60°C80°C

Temp

100°C

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers

Low EMI Emission

The Z8 can be programmed to operate in a low EMI Emission (Low Noise) Mode by means of an EPROM programmable bit option. Use of this feature results in:

■ Less than 1 mA consumed during HALT Mode.

■ All drivers slew rates reduced to 10 ns (typical).

■ Internal SCLK/TCLK = XTAL operation limited to a

maximum of 4 MHz–250 ns cycle time.

■ Output drivers have resistances of 500 ohms (typical).

■ Oscillator divide-by-two circuitry eliminated.

In addition to VDD and GND (VSS), the Z8 changes all its pin functions in the EPROM Mode. XTAL2 has no function, XTAL1 functions as CE tions as EPM, P33 functions as VPP, and P02 functions as PGM.

, P31 functions as OE, P32 func-

ROM Protect. ROM Protect fully protects the Z8 ROM code from being read externally. When ROM Protect is selected, the instructions LDC and LDCI are supported (Z86E04/E08 and Z86C04/C08 do not support the instructions of LDE and LDEI). When the device is programmed for ROM Protect, the Low Noise feature will not automatically be enabled.

Please note that when using the device in a noisy environment, it is suggested that the voltages on the EPM and CE pins be clamped to VCC through a diode to VCC to prevent accidentally entering the OTP Mode. The VPP requires both a diode and a 100 pF capacitor.

Auto Latch Disable. Auto Latch Disable option bit when programmed will globally disable all Auto Latches.

WDT Enable. The WDT Enable option bit, when programmed, will have the hardware enabled Permanent WDT enabled after exiting reset and can not be stopped in Halt or Stop Mode.

EPROM/Test Mode Disable. The EPROM/Test Mode Disable option bit, when programmed, will disable the EPROM Mode and the Factory Test Mode. Reading, verifying, and programming the Z8 will be disabled. To fully verify that this mode is disabled, the device must be power cycled.

Table 7. OTP Programming Table

Programming Modes

EPM CE OE PGM ADDR DATA

EPROM READ NU V PROGRAM V PROGRAM VERIFY V EPROM PROTECT V LOW NOISE SELECT V AUTO LATCH DISABLE V WDT ENABLE V EPROM/TEST MODE V

Notes:

1. V

=12.75V ± 0.25 VDC .

2. V

= As per specific Z8 DC specification.

3. V

= As per specific Z8 DC specification.

4. X = Not used, but must be set to V

5. NU = Not used, but must be set to either V

6. I

during programming = 40 mA maximum.

7. I

during programming, verify, or read = 40 mA maximum.

8. * V

has a tolerance of ±0.25V.

H H H H H H H

or VIH level.

or VIL level.

User Modes. Table 7 shows the programming voltage of each mode.

ADDR Out 5.0V ADDR In 6.4V ADDR Out 6.4V

NU NU 6.4V NU NU 6.4V NU NU 6.4V NU NU 6.4V NU NU 6.4V

VCC*

DS97Z8X1104 P R E L I M I N A R Y 33

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

FUNCTIONAL DESCRIPTION (Continued)

Internal Address Counter. The address of Z8 is generat-

ed internally with a counter clocked through pin P01 (Clock). Each clock signal increases the address by one

Programming Waveform. Figures 19, 20, 21 and 22 show the programming waveforms of each mode. Table 8

shows the timing of programming waveforms. and the “high” level of pin P00 (Clear) will reset the address to zero. Figure 18 shows the setup time of the serial address input.

Programming Algorithm. Figure 23 shows the flow chart

of the Z8 programming algorithm.

Table 8. Timing of Programming Waveforms

Parameters Name Min Max Units

1 Address Setup Time 2 µs 2 Data Setup Time 2 µs 3V

Setup 2 µs

Setup Time 2 µs

5 Chip Enable Setup Time 2 µs 6 Program Pulse Width 0.95 ms 7 Data Hold Time 2 µs 8OE Setup Time 2 µs

9 Data Access Time 188 ns 10 Data Output Float Time 100 ns 11 Overprogram Pulse Width 2.85 ms 12 EPM Setup Time 2 µs 13 PGM Setup Time 2 µs 14 Address to OE Setup Time 2 µs 15 Option Program Pulse Width 78 ms 16 OE Width 250 ns 17 Address Valid to OE Low 125 ns

34 P R E L I M I N A R Y DS97Z8X1104

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers

P0 1 = C lock

P0 0 = C lear

Vp p/ EPM

Interna l

Ad dr es s

Data

Vih

Vil

Invalid Valid

0 Min

Invalid V alid

Legend: T1 Reset Clock Width

T2 Input Clock High T3 Input Clock Period

T4 Input Clock Low T5 C l oc k t o Ad dr es s Counter Out Delay T6 Epm/ Vpp Set up Time

Figure 18. Z86E04/E08 Address Counter Waveform

30 ns Min 100 ns Min

200 ns Min 100 ns Min

15 ns Max 40 µs Min

DS97Z8X1104 P R E L I M I N A R Y 35

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

FUNCTIONAL DESCRIPTION (Continued)

VIH

Ad dr es s

Data

EP M

VIL

VIH

VIL

VI H

VI L

5. 0V

VI H

VI L

Ad dres s Stable

Ad dres s Sta bl e

Invalid Valid Invalid Valid

PG M

VI H

VI L

VI H

VI L

16 16

Figure 19. Z86E04/E08 Programming Waveform

(EPROM Read)

36 P R E L I M I N A R Y DS97Z8X1104

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers

Address

Data

VIL

Data

Stable

2 109

Address

Stable

Data Out

Valid

VPP

VIH

EPM

VIL

VCC

5.0V

PGM

VIH

VIL

VIH

VIL VIH

VIL

6 8

Program

Cycle

Figure 20. Z86E04/E08 Programming Waveform

(Program and Verify)

Verify Cycle

DS97Z8X1104 P R E L I M I N A R Y 37

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

FUNCTIONAL DESCRIPTION (Continued)

Address

Data

5.0V

EPM

PGM

12 13

EPROM Protect

12 13

Low Noise Program

Figure 21. Z86E04/E08 Programming Options Waveform

(EPROM Protect and Low Noise Program)

38 P R E L I M I N A R Y DS97Z8X1104

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers

Address

Data

VPP

5.0V

12 12

13 13

EPM

PGM

12 13

Auto Latch WDT

12 13

1515

EPROM/Test Mode Disabl e

Figure 22. Z86E04/E08 Programming Options Waveform

(Auto Latch Disable, Permanent WDT Enable and

EPROM/Test Mode Disable)

DS97Z8X1104 P R E L I M I N A R Y 39

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

FUNCTIONAL DESCRIPTION (Continued)

Start

Addr =

First Location

V = 6.4V

V = 13.0V

N = 0

Program

1 ms Pulse

Increment N

Increment

Address

Fail

One Byte

Pass

Prog. One Pulse 3xN ms Duration

Last Addr ? Yes

V = V = 5.0V

Pass

N = 25 ?

Verify

Verify All

Bytes

Yes

Fail

Verify

Byte

Device

Failed

Fail

Pass

Device

Passed

Figure 23. Z86E04/E08 Programming Algorithm

40 P R E L I M I N A R Y DS97Z8X1104

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers

Z8 CONTROL REGISTERS

R241 TMR

D7 D6 D5 D4 D3 D2 D1 D0

0 No Function 1 Load T0

0 Disable T0 Count 1 Enable T0 Count

0 No Function 1 Load T1

0 Disable T1 Count 1 Enable T1 Count

TIN Modes 00 External Clock Input 01 Gate Input 10 Trigger Input (Non-retriggerable) 11 Trigger Input (Retriggerable)

Reserved (Must be 0)

Figure 24. Timer Mode Register (F1H: Read/Write)

R242 T1

D7 D6 D5 D4 D3 D2 D1 D0

R244 T0

D7 D6 D5 D4 D3 D2 D1 D0

Figure 27. Counter/Timer 0 Register

(F4H: Read/Write)

R245 PRE0

D7 D6 D5 D4 D3 D2 D1 D0

T Initial Value

(When Written) (Range: 1-256 Decimal 01-00 HEX)

T Current Value

(When READ)

Count Mode 0 T0 Single Pass 1 T0 Modulo N

Reserved (Must be 0)

Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)

T Initial Value

(When Written) (Range 1-256 Decimal

01-00 HEX) T Current Value

(When READ)

Figure 25. Counter Timer 1 Register (F2H: Read/Write)

R243 PRE1

D7 D6 D5 D4 D3 D2 D1 D0

Count Mode

0 = T Single Pass

1 = T Modulo N

Clock Source

1 = T Internal

0 = T External Timing Input

(T ) Mode

Prescaler Modulo (Range: 1-64 Decimal 01-00 HEX)

Figure 26. Prescaler 1 Register (F3H: Write Only)

Figure 28. Prescaler 0 Register (F5

R246 P2M

D7 D6 D5 D4 D3 D2 D1 D0

P2 - P2 I/O Definition 0 Defines Bit as OUTPUT

1 Defines Bit as INPUT

Figure 29. Port 2 Mode Register (F6

R247 P3M

D7 D6 D5 D4 D3 D2 D1 D0

0 Port 2 Open-Drain 1 Port 2 Push-pull

Port 3 Inputs 0 Digital Mode

1 Analog Mode

Reserved (Must be 0)

: Write Only)

Figure 30. Port 3 Mode Register (F7H: Write Only)

DS97Z8X1104 P R E L I M I N A R Y 41

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Z86E04/E08

)

CMOS Z8 OTP Microcontrollers Zilog

Z8 CONTROL REGISTERS (Continued)

R248 P01M

D7 D6 D5 D4 D3 D2 D1 D0

Figure 31. Port 0 and 1 Mode Register

(F8H: Write Only)

R249 IPR

D7 D6 D5 D4 D3 D2 D1 D0

Interrupt Group Priority

IRQ1, IRQ4 Priority (Group C)

IRQ0, IRQ2 Priority (Group B)

IRQ3, IRQ5 Priority (Group A)

Reserved (Must be 0.

P02-P00 Mode 00 = Output 01 = Input

Reserved (Must be 1.) Reserved (Must be 0.)

Reserved = 000 C > A > B = 001 A > B > C = 010 A > C > B = 011 B > C > A = 100 C > B > A = 101 B > A > C = 110 Reserved = 111

0 = IRQ1 > IRQ4 1 = IRQ4 > IRQ1

0 = IRQ2 > IRQ0 1 = IRQ0 > IRQ2

0 = IRQ5 > IRQ3 1 = IRQ3 > IRQ5

R251 IMR

D7 D6 D5 D4 D3 D2 D1 D0

Figure 34. Interrupt Mask Register

(FBH: Read/Write)

R252 Flags

D7 D6 D5 D4 D3 D2 D1 D0

Figure 35. Flag Register

(FCH: Read/Write)

R253 RP

D7 D6 D5 D4 D3 D2 D1 D0

1 Enables IRQ0-IRQ5 (D = IRQ0)

Reserved (Must be 0.)

1 Enables Interrupts

User Flag F1 User Flag F2

Half Carry Flag Decimal Adjust Flag Overflow Flag Sign Flag

Zero Flag Carry Flag

Figure 32. Interrupt Priority Register

(F9H: Write Only)

R250 IRQ

D7 D6 D5 D4 D3 D2 D1 D0

IRQ0 = P32 Input IRQ1 = P33 Input IRQ2 = P31 Input IRQ3 = P32 Input IRQ4 = T0 IRQ5 = T1

Reserved (Must be 0)

Default After Reset = 00H

Figure 36. Register Pointer

(FDH: Read/Write)

R255 SPL

D7 D6 D5 D4 D3 D2 D1 D0

Expanded Register File Working Register Pointer

Stack Pointer Lowe Byte (SP - SP )

Figure 33. Interrupt Request Register

(FAH: Read/Write)

Figure 37. Stack Pointer

(FFH: Read/Write)

42 P R E L I M I N A R Y DS97Z8X1104

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Z86E04/E08

Zilog CMOS Z8 OTP Microcontrollers

PACKAGE INFORMATION

18-Pin DIP Package Diagram

18-Pin SOIC Package Diagram

DS97Z8X1104 P R E L I M I N A R Y 43

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Z86E04/E08 CMOS Z8 OTP Microcontrollers Zilog

ORDERING INFORMATION

Z86E04 Z86E08

Standard T emperature

18-Pin DIP 18-Pin SOIC

Z86E0412PSC Z86E0412SSC Z86E0412PEC Z86E0412SEC

For fast results, contact your local Zilog sales office for assistance in ordering the part(s) desired.

18-Pin DIP 18-Pin SOIC

Z86E0812PSC Z86E0812SSC Z86E0812PEC Z86E0812SEC

Standard T emperature

Codes

Preferred Package

P = Plastic DIP

Longer Lead Time

S = SOIC

Preferred Temperature

S = 0°C to +70°C E = –40°C to +105°C

Speeds

12 =12 MHz

Environmental

C = Plastic Standard

Example:

Z 86E04 12 P S C

is a Z86E04, 12 MHz, DIP, 0°C to +70°C, Plastic Standard Flow Environmental Flow

Temperature Package Speed Product Number Zilog Prefix

© 1998 by Zilog, Inc. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Zilog, Inc. The information in this document is subject to change without notice. Devices sold by Zilog, Inc. are covered by warranty and patent indemnification provisions appearing in Zilog, Inc. Terms and Conditions of Sale only.

ZILOG, INC. MAKES NO WARRANTY, EXPRESS, STATUTORY, IMPLIED OR BY DESCRIPTION, REGARDING THE INFORMATION SET FORTH HEREIN OR REGARDING THE FREEDOM OF THE DESCRIBED DEVICES FROM INTELLECTUAL PROPERTY INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PURPOSE.

44 P R E L I M I N A R Y DS97Z8X1104

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Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Zilog prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustains life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user.

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