Zilog Z86193 User Manual
Z8 Family of Microcontrollers
Z8® CPU
User Manual
UM001604-0108
Copyright ©2008 by Zilog®, Inc. All rights reserved.
www.zilog.com
Z8® CPU
User Manual
ii
Warning:
LIFE SUPPORT POLICY
DO NOT USE IN LIFE SUPPORT
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.
Document Disclaimer
©2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT.
ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this
document has been verified according to the general principles of electrical and mechanical engineering.
Z8 is the registered trademark of Zilog, Inc. All other product or service names are the property of their
respective owners.
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Revision History
Each instance in Revision History reflects a change to this document from its previous
revision. For more details, refer to the corresponding pages and appropriate links in the
table below.
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User Manual
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Date Revision
Level
January
2008
February
2007
September
2004
04 Updated Zilog logo, Zilog text, Disclaimer section,
03 Changed the OP code to B0 and B1 in Instruction
02 Formatted to current publication standards. All pages
Description Page No
All
and implemented Style Guide.
167
Description.
UM001604-0108 Revision History
Table of Contents
Z8® CPU Product Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Key Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Development Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
®
Z8
CPU Standard Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
General-Purpose Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
RAM Protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Working Register Groups . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Z8 Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
®
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Control and Peripheral Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Standard Z8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Expanded Z8 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
External Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
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Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Z8® CPU
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Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Frequency Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Clock Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
SCLK ÷ TCLK Divide-By-16 Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
External Clock Divide-By-Two . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Oscillator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Indications of an Unreliable Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Circuit Board Design Rules . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Crystals and Resonators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
LC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
RC Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Reset Pin, Internal POR Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
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Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Mode Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Input and Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Port 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
General I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Read/Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Handshake Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Port 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
General I/O Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Read/Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Handshake Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Port 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
General Port I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Read/Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Handshake Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Port 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
General Port I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Read/Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Special Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Port Handshake . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
I/O Port Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Full Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Comparator Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Comparator Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Comparator Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Comparator Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Run Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Open-Drain Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Low EMI Emission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Input Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
®
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CMOS Autolatches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Autolatch Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
v
Counters and Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Prescalers and Counter/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Counter/Timer Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Load and Enable Count Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
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Prescaler Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
T
Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
OUT
Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
T
IN
External Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Gated Internal Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Triggered Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Retriggerable Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Cascading Counter/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
External Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Internal Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Interrupt Request Register Logic and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Interrupt Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Interrupt Priority Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Interrupt Mask Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Interrupt Request Register Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
IRQ Software Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Vectored Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Vectored Interrupt Cycle Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Nesting of Vectored Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Polled Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
vi
Power-Down Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Halt Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Stop Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Stop Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Serial Input/Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
UART Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
UART Bit-Rate Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
UART Receiver Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Receiver Shift Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Overwrites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Framing Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Transmitter Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Overwrites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
UART Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
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Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
SPI Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SPI Compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
SPI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Receive Character Available and Overrun . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
External Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
External Addressing Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
External Stacks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Address Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Data Strobe . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Extended Bus Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Instruction Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
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Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
vii
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Processor Flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Zero Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Sign Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Overflow Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Decimal Adjust Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Half Carry Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Notation and Binary Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
®
Z8
Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Instruction Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
UM001604-0108 Table of Contents
Z8® CPU Product Overview
Zilog’s Z8® microcontroller (MCU) product line continues to expand with new product
introductions. Zilog MCU products are targeted for cost-sensitive, high-volume applications including consumer, automotive, security, and HVAC. It includes ROM-based products geared for high-volume production (where software is stable) and one-time
programmable (OTP) equivalents for prototyping as well as volume production where
time to market or code flexibility is critical (see Tab l e 1 on page 3). A variety of packaging
options are available including plastic DIP, SOIC, PLCC, and QFP.
A generalized Z8 CPU block diagram is displayed in Figure 1 on page 2. The same onchip peripherals are used across the MCU product line with the primary differences being
the amount of ROM/RAM, number of I/O lines present, and packaging/temperature
ranges available. This allows code written for one MCU device to be easily ported to
another family member.
Z8® CPU
User Manual
1
Key Features
The key features include:
General-Purpose Register File—Every RAM register acts like an accumulator, speeding
instruction execution and maximizing coding efficiency. Working register groups allow
fast context switching.
Flexible I/O—I/O byte, nibble, and/or bit programmable as inputs or outputs. Outputs are
software programmable as open-drain or push–pull on a port basis. Inputs are SchmittTriggered with autolatches to hold unused inputs at a known voltage state.
Analog Inputs—Three input pins are software programmable as digital or analog inputs.
When in analog mode, two comparator inputs are provided with a common reference
input. These inputs are ideal for a variety of common functions, including threshold level
detection, analog-to-digital conversion, and short circuit detection. Each analog input provides a unique maskable interrupt input.
Timer/Counter—The Timer/Counter (T/C) consists of a programmable 6-bit prescaler and
8-bit downcounter, with maskable interrupt upon end-of-count. Software controls T/C
load/start/stop, countdown read (at any time on the fly), and maskable end-of-count interrupt. Special functions available include T
or external trigger input) and T
clock). These special functions allow accurate hardware input pulse measurement and output waveform generation.
Interrupts—There are six vectored interrupt sources with software-programmable enable
and priority for each of the six sources.
(external counter input, external gate input,
IN
(external access to timer output or the internal system
OUT
Watchdog Timer—An internal Watchdog Timer (WDT) circuit is included as a fail-safe
mechanism so that if software strays outside the bounds of normal operation, the WDT is
used to time-out and reset the MCU. To maximize circuit robustness and reliability, the
UM001604-0108 Z8® CPU Product Overview
Z8® CPU
User Manual
default WDT clock source is an internal RC circuit (isolated from the device clock
source).
Auto Reset/Low-Voltage Protection—All family devices have internal Power-On Reset.
ROM devices add low-voltage protection. Low-voltage protection ensures the MCU is in
a known state at all times (in active RUN or RESET modes) without external hardware (or
a device reset pin).
Low-EMI Operation—Mode is programmable via software or as a mask option. This new
option provides for reduced radiated emission via clock and output drive circuit changes.
Low-Power—CMOS with two standby modes; STOP and HALT.
Full Z8® Instruction Set—Forty-eight basic instructions, supported by six addressing
modes with the ability to operate on bits, nibbles, bytes, and words.
2
Output
Port 3
Counter/
Timers (2)
Interrupt
Control
Analog
Comparators
(2)
Port 2
Input
CC
ALU
FLAG
Register
Pointer
Port 0
GND
V
Register File
256 x 8-Bit
XTAL
AS DS
Machine Timing
& Instruction Control
RESET, WDT,
Prg. Memory
512/K x 8-Bit
Program
R/W RESET
POR
Counter
Port 1
8
)
I/O
(
Bit Programmable)
44
Address or I/O
(
Nibble
Programmable)
Address/Data or I/O
(
Byte Programmable
Figure 1. Z8 CPU Block Diagram
UM001604-0108 Z8® CPU Product Overview
Product Development Support
The Z8® MCU product line is fully supported with a range of cross assemblers, C compilers, ICEBOX emulators, single and gang OTP/EPROM programmers, and software simulators.
The
Z86CCP01ZEM low-cost Z8 CCP real-time emulator/programmer kit is designed
specifically to support all the products outlined in Tab l e 1 on page 3.
Table 1. Zilog General-Purpose Microcontroller Product Family
Z8® CPU
User Manual
3
RC
Speed
(MHz)
ROM/
Product
Z86C03 512/60 14 1 2 6 F Y Y Y 8 18
Z86E03 512/60 14 1 2 6 F Y N Y 8 18
Z86C04 1K/124 14 2 2 6 F Y Y Y 8 18
Z86E04 1K/124 14 2 2 6 F Y N Y 8 18
Z86C06 1K/124 14 2 2 6 P Y Y Y 12 18
Z86E06 1K/124 14 2 2 6 P Y N Y 12 18
Z86C08 2K/124 14 2 2 6 F Y Y Y 12 18
Z86E08 2K/124 14 2 2 6 F Y N Y 12 18
Z86C30 4K/236 24 2 2 6 P Y Y Y 12 28
Z86E30 4K/236 24 2 2 6 P Y N Y 12 28
Z86C31 2K/124 24 2 2 6 P Y Y Y 8 28
Z86E31 2K/124 24 2 2 6 P Y N Y 8 28
Z86C40 4K/236 32 2 2 6 P Y Y Y 16 40/44
Z86E40 4K/236 32 2 2 6 P Y N Y 16 40/44
Note:
RAM I/O T/C AN INT WDT POR V
Z86Cxx signify ROM devices; 86xx signify EPROM devices; F = fixed; P = programmable.
BO
Pin
Count
The Z86CCP01ZEM kit includes:
•
Z8 CCP evaluation board
•
Z8 CCP power cable
•
Zilog Developer Studio (ZDS) CD-ROM, Including Windows-Based GUI Host Software
•
1999 Zilog Technical Library
•
Z8 CCP User Manual
UM001604-0108 Z8® CPU Product Overview
Z8® CPU
User Manual
A Z8 CCP Emulator Accessory Kit (Z8CCP00ZAC) is also available and provides an RS232 cable and power cable along with the 28- and 40- pin ZIF sockets and 28- and 40-pin
target connector cables required to emulate/program 28-/40-pin devices.
4
UM001604-0108 Z8® CPU Product Overview
Address Space
Introduction
Z8® CPU includes the following four address spaces:
•
The Z8 Standard Register File contains addresses for peripheral, control, all generalpurpose, and all I/O port registers. This is the default register file specification.
•
The Z8 Expanded Register File (ERF) contains addresses for control and data registers for additional peripherals/features.
•
Z8 external Program Memory contains addresses for all memory locations having
executable code and/or data.
•
Z8 external data memory contains addresses for all memory locations that hold data
only, whether internal or external.
Z8® CPU
User Manual
5
Z8® CPU Standard Register File
The Z8 Standard Register File totals up to 256 consecutive bytes (Registers). The register
file consists of 4 I/O ports (
control registers (
names, locations, and identifiers.
Table 2. Z8 Standard Register File
Hex Address
FF SPL Stack Pointer Low Byte
FE SPH Stack Pointer High Byte
FD RP Register Pointer
FC FLAGS Program Control Flags
FB IMR Interrupt Mask Register
FA IRQ Interrupt Request Register
F9 IPR Interrupt Priority Register
F8 P01M Port 0–1 Mode Register
F7 P3M Port 3 Mode Register
F0h–FFh). Table 2 lists the layout of the register file, including register
Register
Identifier Register Description
00h–03h), 236 General-Purpose Registers (04h–EFh), and 16
F6 P2M Port 2 Mode Register
F5 PRE0 T0 Prescaler
UM001604-0108 Address Space
Table 2. Z8 Standard Register File (Continued)
Register
Hex Address
F4 T0 Timer/Counter 0
F3 PRE1 T1 Prescaler
F2 T1 Timer/Counter 1
F1 TMR Timer Mode
F0 SIO Serial I/O
EF R239
General-Purpose Registers (GPR)
04 R4
Identifier Register Description
Z8® CPU
User Manual
6
03 P3 Port 3
02 P2 Port 2
01 P1 Port 1
00 P0 Port 0
Registers can be accessed as either 8-bit or 16-bit registers using Direct, Indirect, or
Indexed Addressing. All 236 general-purpose registers can be referenced or modified by
any instruction that accesses an 8-bit register, without the requirement for special instructions. Registers accessed as 16 bits are treated as even-odd register pairs (there are 118
valid pairs). In this case, the data’s most significant byte (MSB) is stored in the even numbered register, while the least significant byte (LSB) goes into the next higher odd numbered register. See Figure 2.
MSB
Rn Rn+1
n = Even Address
Figure 2. 16-Bit Register Addressing
LSB
By using a logical instruction and a mask, individual bits within registers can be accessed
for bit set, bit clear, bit complement, or bit test operations. For example, the instruction
AND R15, MASK performs a bit clear operation, Figure 3 on page 7 displays this
example.
UM001604-0108 Address Space
Z8® CPU
User Manual
7
0 1 1 1 0 0 0 0
1 1 0 1 1 1 1 1
AND R15, DFh ;Clear Bit 5 of Working Register 15
0 1 0 1 0 0 0 0
Figure 3. Accessing Individual Bits (Example)
When instructions are executed, registers are read when defined as sources and written
when defined as destinations. All General-Purpose Registers function as accumulators,
address pointers, index registers, stack areas, or scratch pad memory.
General-Purpose Registers
General-Purpose Registers are undefined after the device is powered up. The registers
keep their last value after any reset, as long as the reset occurs in the V
specified operating range. It does not keep its last state from a V
below 1.8 V.
R15
MASK
R15
voltage-
CC
reset if VCC drops
LV
Note:
Registers in Bank
E0-EF may only be accessed through the working register and indirect
addressing modes. Direct access cannot be used because the 4-bit working register address
mode already uses the format
number from
0h to Fh.
RAM Protect
The upper portion of the register file address space 80h to EFh (excluding the control registers) may be protected from reading and writing. The RAM Protect bit option is maskprogrammable and is selected by the customer when the ROM code is submitted. After the
mask option is selected, activate this feature from the internal ROM code to turn OFF/on
the RAM Protect by loading either a 0 or 1 into the IMR register, bit D6. A 1 in D6 enables
RAM Protect. Only devices that use registers
Working Register Groups
Z8® instructions can access 8-bit registers and register pairs (16-bit words) using either
4-bit or 8-bit address fields. 8-bit address fields refer to the actual address of the register.
For example, Register
01011000 (58h).
58h is accessed by calling upon its 8-bit binary equivalent,
[E | dst], where dst represents the working register
80h to EFh offer this feature.
UM001604-0108 Address Space
Z8® CPU
User Manual
With 4-bit addressing, the register file is logically divided into 16 Working Register
Groups of 16 registers each, as listed in Tab le 3. These 16 registers are known as Working
Registers. A Register Pointer (one of the control registers,
FDh) contains the base address
of the active Working Register Group. The high nibble of the Register Pointer determines
the current Working Register Group.
When accessing one of the Working Registers, the 4-bit address of the Working Register is
combined within the upper four bits (high nibble) of the Register Pointer, thus forming the
8-bit actual address. Figure 4 on page 9 displays this operation. Because working registers
are typically specified by short format instructions, there are fewer bytes of code required,
which reduces execution time. In addition, when processing interrupts or changing tasks,
the Register Pointer speeds context switching. A special Set Register Pointer (SRP)
instruction sets the contents of the Register Pointer.
Table 3. Working Register Groups
8
Register Pointer
(FDh) High Nibble
1111b F F0–FF
1110b E E0–EF
1101b D D0–DF
1100b C C0–CF
1011b B B0–BF
1010b A A0–AF
1001b 9 90–9F
1000b 8 80–8F
0111b 7 70–7F
0110b 6 60–6F
0101b 5 50–5F
0100b 4 40–4F
0011b 3 30–3F
0010b 2 20–2F
0001b 1 10–1F
Working Register
Group (Hex)
Actual Registers
(Hex)
0000b 0 00–0F
UM001604-0108 Address Space
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User Manual
9
0 1 1 1 0 0 0 0
1 1 0 1 1 1 1 1
0 1 1 1 0 1 1 0
Figure 4. Working Register Addressing Examples
R7 R6 R5 R4 R3 R2 R1 R0
The upper nibble of the register file address,
provided by the register pointer, specifies
the active working-register group.
FF
F0
EF
80
7F
70
6F
60
5F
50
4F
40
3F
30
2F
20
1F
10
0F
Working Register Group F
Specified Working Register Group
Working Register Group 1
Working Register Group 0
Register Pointer (FDh), Standard Register File
INC R6 (instruction, short format)
Actual register address (76h)
R253
(Register Pointer)
The lower nibble
of the register
file address
(provided by the
instruction) points
to the specified
register.
R15 to R0
R15 to R4
00
*Note: The full register file is shown. Refer to the selected device product specification for actual file
size.
I/O Ports
R3 to R0
Figure 5. Register Pointer
UM001604-0108 Address Space
Error Conditions
Registers in the Z8® Standard Register File must be correctly used because certain conditions produce inconsistent results and should be avoided.
•
Registers F3h and F5h–F9h are write-only registers. If an attempt is made to read
these registers,
•
When register FDh (Register Pointer) is read, the least significant four bits (lower nibble) indicate the current Expanded Register File Bank. (For example,
the Standard Register File, while
•
When Ports 0 and 1 are defined as address outputs, registers 00h and 01h return 1s in
each address bit location when reading.
•
Writing to bits that are defined as timer output, serial output, or handshake output has
no effect.
Z8® CPU
User Manual
10
FFh is returned. Reading any write-only register returns FFh.
0000 indicates
1010 indicates Expanded Register File Bank A.)
•
The Z8 CPU instruction DJNZ uses any general-purpose working register as a counter.
•
Logical instructions such as OR and AND require that the current contents of the
operand be read. They therefore do not function properly on write-only registers.
•
The WDTMR register must be written within the first 60 internal system clocks
(SCLK) of operation after a reset.
Z8 Expanded Register File
The standard register file of the Z8 CPU has been expanded to form 16 Expanded Register
File (ERF) Banks, as displayed in Figure 6 on page 11. Each ERF Bank consists of up to
256 registers (the same amount as in the Standard Register File) that can then be divided
into 16 Working Register Groups. This expansion allows for access to additional feature/
peripheral control and data registers.
UM001604-0108 Address Space
Working Register
Group Pointer
Z8 Register File
FF
F0
7F
0F
00
Register Pointer
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register
Group Pointer
Expanded Register File
Bank (F)
(F) 0F WDTMR
(F) 0E Reserved
(F) 0E Reserved
(F) 0D Reserved
(F) 0C Reserved
(F) 0B SMR
(F) 0A Reserved
(F) 09 Reserved
(F) 08 Reserved
(F) 07 Reserved
(F) 06 Reserved
(F) 05 Reserved
(F) 04 Reserved
(F) 03 Reserved
(F) 02 Reserved
(F) 01 Reserved
(F) 00 PCON
Expanded Register File
Bank (0)
(0) 0F GPR
(0) 0E GPR
(0) 0D GPR
(0) 0C GPR
(0) 0B GPR
(0) 0A GPR
(0) 09 GPR
(0) 08 GPR
(0) 07 GPR
(0) 06 GPR
(0) 05 GPR
(0) 04 GPR
(0) 03 P3
(0) 02 P2
(0) 01 P1
(0) 00 P0
Expanded Register File
Bank (C)
(C) 0F Reserved
(C) 0E Reserved
(C) 0D Reserved
(C) 0C Reserved
(C) 0B Reserved
(C) 0A Reserved
(C) 09 Reserved
(C) 08 Reserved
(C) 07 Reserved
(C) 06 Reserved
(C) 05 Reserved
(C) 04 Reserved
(C) 03 Reserved
(C) 02 SCON
(C) 01 RXBUF
(C) 00 SCOMP
Z8® CPU
User Manual
11
*Note: The fully implemented register file is shown. Refer to the specific product specification for actual register file architecture implemented.
Figure 6. Expanded Register File Architecture
Currently, three out of the possible sixteen Z8 ERF Banks have been implemented. ERF
®
Bank 0, also known as the Z8
played in Figure 7 on page 12. Only Working Register Group 0 (register addresses
Standard Register File, has all 256 bytes defined, as dis-
00h to
0Fh) has been defined for ERF Bank C and ERF Bank F (see Table 4 on page 12). All
other working register groups in ERF Banks C and F, as well as the remaining thirteen
ERF Banks, are not implemented. All are reserved for future use.
UM001604-0108 Address Space
Z8® CPU
User Manual
12
When an ERF Bank is selected, register addresses 00h to 0Fh access those sixteen ERF
Bank registers—in effect replacing the first sixteen locations of the Z8
®
Standard Register
File.
For example, if ERF Bank C is selected, the Z8 Standard Registers
no longer accessible. Registers
00h through 0Fh are now the 16 registers from ERF Bank
00h through 0Fh are
C, Working Register Group 0. No other Z8 Standard Registers are affected because only
Working Register Group 0 is implemented in ERF Bank C.
Access to the ERF is accomplished through the Register Pointer (
FDh). The lower nibble
of the Register Pointer determines the ERF Bank while the upper nibble determines the
Working Register Group within the register file, as displayed in Figure 7.
0 1 1 1
Working
Register
Group
Select ERF Bank Ch
Working Register Group 7h
Figure 7. Register Pointer Example
1 1 0 0
Expanded
Register
Bank
The value of the lower nibble in the Register Pointer (
FDh) corresponds to the ERF Bank
identification. Table 4 lists the lower nibble value and the register file assigned to it.
Table 4. ERF Bank Address
Register Pointer
(FDh) Low Nibble
0000b 0 Z8 Standard Register File*
0001b 1 Expanded Register File Bank 1
0010b 2 Expanded Register File Bank 2
0011b 3 Expanded Register File Bank 3
0100b 4 Expanded Register File Bank 4
0101b 5 Expanded Register File Bank 5
0110b 6 Expanded Register File Bank 6
0111b 7 Expanded Register File Bank 7
1000b 8 Expanded Register File Bank 8
Hex
Register File
UM001604-0108 Address Space
Table 4. ERF Bank Address (Continued)
Register Pointer
(FDh) Low Nibble
1001b 9 Expanded Register File Bank 9
1010b A Expanded Register File Bank A
1011b B Expanded Register File Bank B
1100b C Expanded Register File Bank C
1101b D Expanded Register File Bank D
1110b E Expanded Register File Bank E
1111b F Expanded Register File Bank F
*
The Z8® Standard Register File is equivalent to Expanded Register File
Bank 0.
Hex
Register File
Z8® CPU
User Manual
13
The upper nibble of the register pointer selects which group of 16 bytes in the Register
File, out of the 256 total bytes, is accessed as working registers. Table 5 lists an example.
Table 5. Register Pointer Access Example
R253 RP = 00h ;ERF Bank 0, Working Reg.
Group 0
R0 = Port 0 = 00h
R1 = Port 1 = 01h
R2 = Port 2 = 02h
R3 = Port 3 = 03h
R11 = GPR 0Bh
R15 = GPR 0Fh
If R253 RP = 0Fh ;ERF Bank F, Working Reg.
Group 0
R0 = PCON = 00h
R1 = Reserved = 01h
R2 = Reserved = 02h
R11 = SMR = 0Bh
R15 = WDTMR = 0Fh
UM001604-0108 Address Space
Table 5. Register Pointer Access Example (Continued)
If R253 RP = FFh
;ERF Bank F, Working Reg.
Group F.
00h = PCON
R0 = SI0 01h = Reserved
R1 = TMR 02h = Reserved
...
R2 = T1 0Bh = SMR
...
R15 = SPL 0Fh = WDTMR
Z8® CPU
User Manual
14
Because enabling an ERF Bank (C or F) only changes register addresses 00h to 0Fh, the
working register pointer can be used to access either the selected ERF Bank (Bank C or F,
Working Register Group 0) or the
®
Z8
Standard Register File (ERF Bank 0, Working Reg-
ister Groups 1 through F).
When an ERF Bank other than Bank 0 is enabled, the first 16 bytes of
the Z8 Standard
Register File (I/O ports 0 to 3, Groups 4 to F) are no longer accessible (the selected ERF
Bank, Registers
00h to 0Fh are accessed instead). It is important to re-initialize the Regis-
ter Pointer to enable ERF Bank 0 when these registers are required for use.
The SPI register is mapped into ERF Bank C. Access is easily done using the example in
Table 6.
Table 6. ERF Bank C Access Example
LD RP, #0Ch ;Select ERF Bank C working
;register group 0 for access.
LD R2,#xx ;access SCON
LD R1, #xx ;access RXBUF
LD RP, #00h ;Select ERF Bank 0 so I/O ports
;are again accessible.
UM001604-0108 Address Space
Z8® CPU
User Manual
Table 7. Z8 ERF Bank Layout
ERF Bank ERF
Fh PCON, SMR, WDT, (00h, 0Bh, 0Fh), Working Register Group 0 only
implemented.
Eh Not implemented (reserved)
Dh Not implemented (reserved)
Ch SPI Registers: SCOMP, RXBUF, SCON (00h, 01h, 02h), Working
Register Group 0 only implemented.
Bh Not implemented (reserved)
Ah Not implemented (reserved)
9h Not implemented (reserved)
15
8h Not implemented (reserved)
7h Not implemented (reserved)
6h Not implemented (reserved)
5h Not implemented (reserved)
4h Not implemented (reserved)
3h Not implemented (reserved)
2h Not implemented (reserved)
1h Not implemented (reserved)
0h Z8 Ports 0, 1, 2, 3, and General-Purpose Registers 04h to EFh, and
control registers F0h to FFh.
Refer to the specific product specification to determine the above registers are implemented.
Z8® Control and Peripheral Registers
Standard Z8 Registers
The standard Z8 control registers govern the operation of the CPU. Any instruction which
references the register file can access these control registers. The following control registers are available:
•
Interrupt Priority Register (IPR)
•
Interrupt Mask Register (IMR)
•
Interrupt Request Register (IRQ)
UM001604-0108 Address Space
Z8® CPU
User Manual
•
Program Control Flags (FLAGS)
•
Register Pointer (RP)
•
Stack Pointer High-Byte (SPH)
•
Stack Pointer Low-Byte (SPL)
The Z8
program instructions. The PC is not an addressable register.
Peripheral registers are used to transfer data, configure the operating mode, and control the
operation of the on-chip peripherals. Any instruction that references the register file can
access the peripheral registers. The peripheral registers are:
•
•
®
CPU uses a 16-bit Program Counter (PC) to determine the sequence of current
Serial I/O (SIO)
Timer Mode (TMR)
16
•
Timer/Counter 0 (T0)
•
T0 Prescaler (PRE0)
•
Timer/Counter 1 (T1)
•
T1 Prescaler (PRE1)
•
Port 0–1 Mode (P01M)
•
Port 2 Mode (P2M)
•
Port 3 Mode (P3M)
In addition, the four port registers (P0–P3) are considered to be peripheral registers.
Expanded Z8 Registers
The expanded Z8 control registers govern the operation of additional features or peripherals. Any instruction which references the register file can access these registers.
The ERF contains the control registers for WDT, Port Control, Serial Peripheral Interface
(SPI), and the SMR functions. Figure 6 on page 11 displays the layout of the Register
Banks in the ERF. Register Bank C in the ERF consists of the registers for the SPI. Ta b l e 8
lists the registers within ERF Bank C, Working Register Group 0.
Table 8. ERF Bank C WR Group 0
Register Function Working Register
F Reserved R15
E Reserved R14
D Reserved R13
UM001604-0108 Address Space
Table 8. ERF Bank C WR Group 0 (Continued)
Register Function Working Register
C Reserved R12
B Reserved R11
A Reserved R10
9 Reserved R9
8 Reserved R8
7 Reserved R7
6 Reserved R6
5 Reserved R5
4 Reserved R4
Z8® CPU
User Manual
17
3 Reserved R3
2 SPI Control (SCON) R2
1 SPI Tx/Rx Data (Roxburgh) R1
0 SPI Compare (SCOMP) R0
Working Register Group 0 in ERF Bank 0 consists of the registers for Z8® General-Purpose Registers and ports. Table 9 lists the registers within this group.
Table 9. ERF Bank 0 WR Group 0
Register Function Working Register
F General-Purpose Register R15
E General-Purpose Register R14
D General-Purpose Register R13
C General-Purpose Register R12
B General-Purpose Register R11
A General-Purpose Register R10
9 General-Purpose Register R9
8 General-Purpose Register R8
7 General-Purpose Register R7
6 General-Purpose Register R6
5 General-Purpose Register R5
UM001604-0108 Address Space
Z8® CPU
User Manual
Table 9. ERF Bank 0 WR Group 0 (Continued)
Register Function Working Register
4 General-Purpose Register R4
3Port 3 R3
2Port 2 R2
1Port 1 R1
0Port 0 R0
Working Register Group 0 in ERF Bank F consists of the control registers for STOP mode,
WDT, and port control. Table 10 lists the registers within this group.
Table 10. ERF Bank F WR Group 0
18
Register Function Working Register
F WDTMR R15
E Reserved R14
D Reserved R13
C Reserved R12
BSMR R11
A Reserved R10
9 Reserved R9
8 Reserved R8
7 Reserved R7
6 Reserved R6
5 Reserved R5
4 Reserved R4
3 Reserved R3
2 Reserved R2
1 Reserved R1
0PCON R0
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Program Memory
The first 12 bytes of Program Memory are reserved for the interrupt vectors, as displayed
in Figure 8 on page 20. These locations contain six 16-bit vectors that correspond to the
six available interrupts. Address 12 up to the maximum ROM address consists of on-chip
mask-programmable ROM. Refer to the product data sheet for the exact program, data,
register memory size, and address range available. At addresses outside the internal ROM,
®
the Z8
Address/Data mode for devices with Port 0 and Port 1 featured. Otherwise, the program
counter continues to execute NOPs up to address
to fetch executable code (see Figure 8).
The internal Program Memory is one-time programmable (OTP) or mask programmable
dependent on the specific device. A ROM protect feature prevents dumping of the ROM
contents by inhibiting execution of the LDC, LDCI, LDE, and LDEI instructions to Program Memory in all modes. ROM look-up tables cannot be used with this feature.
CPU executes external Program Memory fetches through Port 0 and Port 1 in
Z8® CPU
User Manual
19
FFFFh, roll over to 0000h, and continue
The ROM Protect option is mask-programmable, to be selected when the ROM code is
submitted. For the OTP ROM, the ROM Protect option is an OTP programming option.
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Location of
First Byte of
Instruction
Executed
After RESET
65535
4096
4095
12
External
ROM and RAM
On–Chip
ROM
Z8® CPU
User Manual
20
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
Figure 8. Z8® Program Memory Map
Z8® External Memory
Z8 CPU, in some cases, has the capability to access external Program Memory with the
16-bit Program Counter. To access external Program Memory the Z8 CPU offers multiplexed address/data lines (AD7–AD0) on Port 1 and address lines (A15–A8) on Port 0.
This feature only applies to devices that offer Port 0 and Port 1. The maximum external
address is
Strobe), DS
Memory starts after the last address of the internal ROM. Figure 9 on page 21 displays an
example of external Program Memory for the Z8 CPU.
FFFF. This memory interface is supported by the control lines AS (Address
(Data Strobe), and R/W (Read/Write). The origin of the external Program
11
10
9
8
7
6
5
4
3
2
0
IRQ
5
IRQ
5
IRQ
4
IRQ
4
IRQ
3
IRQ
3
IRQ
2
IRQ
2
IRQ
1
IRQ
1
1
IRQ
IRQ
0
0
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External Data Memory
The Z8 CPU, in some cases, can address up to 60 KB of external data memory beginning
at location 4096. External data memory (DM
external Program Memory space. DM
appear on pin P34, is used to distinguish between data and Program Memory space. The
state of the DM
opcode references Program Memory (DM
data memory (DM
and D4 for this mode.
signal is controlled by the type of instruction being executed. An LDC
active Low). You must configure Port 3 Mode Register (P3M) bits D3
65535
Z8® CPU
User Manual
21
) can be included with, or separated from, the
, an optional I/O function that can be programmed to
inactive), and an LDE instruction references
External
Memory
4096
4095
Not Addressable
0
*Note: For additional information on using external memory, see Chapter 10 of this
manual. For exact memory addressing options available, see the device product
specification.
Figure 9. External Memory Map
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Z8® Stacks
Stack operations can occur in either the Z8 Standard Register File or external data memory. Under software control, Port 0–1 Mode register (
the General-Purpose Registers can be used for the stack when the internal stack is
selected.
Z8® CPU
User Manual
22
F8h) selects the stack location. Only
The register pair
operations. The stack address is stored with the MSB in
FEh and FFh form the 16-bit Stack Pointer (SP), that is used for all stack
FEh and LSB in FFh, see
Figure 10.
FFh
LOWER Byte
FEh
UPPER Byte
Figure 10. Stack Pointer
Stack Pointer Low
Stack Pointer High
The stack address is decremented prior to a PUSH operation and incremented after a POP
operation. The stack address always points to the data stored on the top of the stack. The
Z8 CPU stack is a return stack for CALL instructions and interrupts, as well as a data
stack.
During a CALL instruction, the contents of the PC are saved on the stack. The PC is
restored during a RETURN instruction. Interrupts cause the contents of the PC and Flag
registers to be saved on the stack. The IRET instruction restores them (see Figure 11 on
page 23).
When the Z8 CPU is configured for an internal stack (using the Z8 Standard Register
File), register
FFh serves as the Stack Pointer. The value in FEh is ignored. FEh can be
used as a general-purpose register in this case only.
An overflow or underflow can occur when the stack address is incremented or decremented during normal stack operations. The programmer must prevent this occurrence, or
unpredictable operation happens.
UM001604-0108 Address Space
PCL
Z8® CPU
User Manual
23
Top of Stack
PCL
PCH
Stack Contents
After a Call
Instruction
Top of Stack
Figure 11. Stack Operations
PCH
FLAGS
Stack Contents
After an
Interrupt Cycle
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