Zilog Z80180 User Manual

Z8018x
Family MPU
User Manual
UM005003-0703
ZiLOG WORLDWIDE HEADQUARTERS • 532 Race Street • SAN JOSE, CA 95126-3432
T
ELEPHONE: 408.558.8500 • FAX: 408.558.8300 • WWW.ZILOG.COM
Z8018x Family MPU User Manual
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© 2003 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use of information, devices, or technology as critical components of life support systems is not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
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MANUAL OBJECTIVES

This user manual describes the features of the Z8018x MPUs.This manual provides basic programming information for the Z80180/Z8S180/ Z8L180. These cores and base peripheral sets are used in a large family of ZiLOG products. Below is a list of ZiLOG products that use this class of processor, along with the associated processor family. This document is also the core user manual for the following products:
Part Family
Z80180 Z80180
Z8S180 Z8S180
Z8L180 Z8L180
Z8018x
Family MPU User Manual
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Z80181 Z80180
Z80182 Z80180, Z8S180*
Z80S183 Z8S180
Z80185/195 Z8S180
Z80189 Z8S180
* Part number-dependant

Intended Audience

This manual is written for those who program the Z8018x.

Manual Organization

The Z8018x User Manual is divided into five sections, seven appendices, and an index.
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Sections

Z8018X MPU Operation
Presents features, a general description, pins descriptions, block diagrams, registers, and details of operating modes for the Z8018x MPUs.
Software Architecture
Provides instruction sets and CPU registers for the Z8018x MPUs.
DC Characteristics
Presents the DC parameters and absolute maximum ratings for the Z8X180 MPUs.
AC Characteristics
Presents the AC parameters for the Z8018x MPUs.
Timing Diagrams
Contains timing diagrams and standard test conditions for the Z8018x MPUs.

Appendices

The appendixes in this manual provide additional information applicable to the Z8018x family of ZiLOG MPUs:
Instruction set
Instruction summary table
Op Code map
Bus Control signal conditions in each machine cycle and interrupt conditions
Operating mode summary
Status signals
I/O registers and ordering information
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Table of Contents

Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Operation Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
CPU Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Wait State Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
HALT and Low Power Operation Modes
(Z80180-Class Processors Only) . . . . . . . . . . . . . . . . . . . . . . . .31
Low Power Modes
(Z8S180/Z8L180 only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Add-On Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
STANDBY Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
STANDBY Mode Exit wiht BUS REQUEST . . . . . . . . . . . . . . . . .38
STANDBY Mode EXit with External Interrupts . . . . . . . . . . . . . . .39
IDLE Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
STANDBY-QUICK RECOVERY Mode . . . . . . . . . . . . . . . . . . . .41
Internal I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
MMU Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Interrupt Acknowledge Cycle Timings . . . . . . . . . . . . . . . . . . . . . .82
Interrupt Sources During RESET . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Dynamic RAM Refresh Control . . . . . . . . . . . . . . . . . . . . . . . . . . .86
DMA Controller (DMAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
Asynchronous Serial Communication Interface (ASCI) . . . . . . . .115
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Baud Rate Generator
(Z8S180/Z8L180-Class Processors Only) . . . . . . . . . . . . . . . 143
Clocked Serial I/O Port (CSI/O) . . . . . . . . . . . . . . . . . . . . . . . . . . 146
CSI/O Registers Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Programmable Reload Timer (PRT) . . . . . . . . . . . . . . . . . . . . . . . 156
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
Z80180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Z8S180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
Z8L180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
AC Characteristics—Z8S180 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Restart Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
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Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .210
Data Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .211
Data Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
Program and Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229
Special Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235
Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237
Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247
Bus Control Signal Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . .251
Bus and Control Signal Condition in each Machine Cycle . . . . . . . . .251
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Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279
Operating Modes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .281
Request Acceptances in Each Operating Mode . . . . . . . . . . . . . . . . . .281
Request Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .282
Operation Mode Transition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283
Other Operation Mode Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .285
Status Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .287
Pin Outputs in Each Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . .287
Pin Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
Internal I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303
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List of Figures

Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1
Figure 1. 64-Pin DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Figure 2. 68-Pin PLCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
Figure 3. 80-Pin QFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Figure 4. Z80180/Z8S180/Z8L180 Block Diagram . . . . . . . . . . . . . . .6
Figure 5. Operation Mode Control Register . . . . . . . . . . . . . . . . . . . .15
Figure 6. M1 Temporary Enable Timing . . . . . . . . . . . . . . . . . . . . . .16
Figure 7. I/O Read and Write Cycles with IOC = 1
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 8. I/O Read and Write cycles with IOC = 0
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Figure 9. Op Code Fetch (without Wait State) Timing Diagram . . . .19
Figure 10. Op Code Fetch (with Wait State) Timing Diagram . . . . . .20
Figure 11. Memory Read/Write (without Wait State)
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Figure 12. Memory Read/Write (with Wait State)
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
Figure 13. I/O Read/Write Timing Diagram . . . . . . . . . . . . . . . . . . . .23
Figure 14. Instruction Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .24
Figure 15. RESET Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Figure 16. Bus Exchange Timing During Memory Read . . . . . . . . . . .26
Figure 17. Bus Exchange Timing During CPU Internal Operation . . .27
Figure 18. WAIT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Figure 19. Memory and I/O Wait State Insertion
(DCNTL – DMA/Wait Control Register) . . . . . . . . . . . . . .29
Figure 20. HALT Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .33
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Figure 21. SLEEP Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 22. I/O Address Relocation . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 23. Logical Address Mapping Examples . . . . . . . . . . . . . . . . . 55
Figure 24. Physical Address Transition . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 25. MMU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 26. I/O Address Translation . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 27. Logical Memory Organization . . . . . . . . . . . . . . . . . . . . . 58
Figure 28. Logical Space Configuration . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 29. Physical Address Generation . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 30. Physical Address Generation 2 . . . . . . . . . . . . . . . . . . . . . 64
Figure 31. Interrupt Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 32. TRAP Timing Diagram -2nd Op Code Undefined . . . . . . 71
Figure 33. TRAP Timing - 3rd Op Code Undefined . . . . . . . . . . . . . 72
Figure 34. NMI Use . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 35. NMI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Figure 36. INT0 Mode 0 Timing Diagram . . . . . . . . . . . . . . . . . . . . . 76
Figure 37. INT0 Mode 1 Interrupt Sequence . . . . . . . . . . . . . . . . . . . 77
Figure 38. INT0 Mode 1 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
Figure 39. INT0 Mode 2 Vector Acquisition . . . . . . . . . . . . . . . . . . . 79
Figure 40. INT0 Interrupt Mode 2 Timing Diagram . . . . . . . . . . . . . 80
Figure 41. INT1, INT2 Vector Acquisition . . . . . . . . . . . . . . . . . . . . 81
Figure 42. RETI Instruction Sequence . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 43. INT1, INT2 and Internal Interrupts Timing Diagram . . . . 86
Figure 44. Refresh Cycle Timing Diagram . . . . . . . . . . . . . . . . . . . . . 87
Figure 45. DMAC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Figure 46. DMA Timing Diagram-CYCLE STEAL Mode . . . . . . . 106
Figure 47. CPU Operation and DMA Operation DREQ0
Figure 48. CPU Operation and DMA Operation DREQ0
is Programmed for Level-Sense . . . . . . . . . . . . . . . . . . . 107
is Programmed for Edge-Sense . . . . . . . . . . . . . . . . . . . . 108
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Figure 49. TEND0 Output Timing Diagram . . . . . . . . . . . . . . . . . . .108
Figure 50. DMA Interrupt Request Generation . . . . . . . . . . . . . . . . .114
Figure 51. NMI and DMA Operation Timing Diagram . . . . . . . . . . .115
Figure 52. ASCI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Figure 53. DCD0 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .139
Figure 54. RTS0 Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .140
Figure 55. ASCI Interrupt Request Circuit Diagram . . . . . . . . . . . . .140
Figure 56. ASCI Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141
Figure 57. CSI/O Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Figure 58. CSI/O Interrupt Request Generation . . . . . . . . . . . . . . . . .151
Figure 59. Transmit Timing Diagram–Internal Clock . . . . . . . . . . . .153
Figure 60. Transmit Timing–External Clock . . . . . . . . . . . . . . . . . . .154
Figure 61. CSI/O Receive Timing–Internal Clock . . . . . . . . . . . . . . .155
Figure 62. CSI/O Receive Timing–External Clock . . . . . . . . . . . . . .156
Figure 63. PRT Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157
Figure 64. Timer Initialization, Count Down, and Reload
Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Figure 65. Timer Output Timing Diagram . . . . . . . . . . . . . . . . . . . . .164
Figure 66. PRT Interrupt Request Generation . . . . . . . . . . . . . . . . . .164
Figure 67. E Clock Timing Diagram (During Read/Write Cycle
and Interrupt Acknowledge Cycle . . . . . . . . . . . . . . . . . .167
Figure 68. E Clock Timing in BUS RELEASE Mode . . . . . . . . . . . .167
Figure 69. E Clock Timing in SLEEP Mode and
SYSTEM STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . .168
Figure 70. External Clock Interface . . . . . . . . . . . . . . . . . . . . . . . . . .169
Figure 71. Clock Generator Circuit . . . . . . . . . . . . . . . . . . . . . . . . . .170
Figure 72. Circuit Board Design Rules . . . . . . . . . . . . . . . . . . . . . . .170
Figure 73. Example of Board Design . . . . . . . . . . . . . . . . . . . . . . . . .171
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Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Figure 74. CPU Register Configurations . . . . . . . . . . . . . . . . . . . . . 176
Figure 75. Register Direct — Bit Field Definitions . . . . . . . . . . . . . 181
Figure 76. Register Indirect Addressing . . . . . . . . . . . . . . . . . . . . . . 181
Figure 77. Indexed Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 78. Extended Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Figure 79. Immediate Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Figure 80. Relative Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 81. AC Timing Diagram 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 82. AC Timing Diagram 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Figure 83. CPU Timing (IOC = 0) (I/O Read Cycle,
I/O Write Cycle) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Figure 84. DMA Control Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . 200
Figure 85. E Clock Timing (Memory R/W Cycle) (I/O R/W Cycle) 201
Figure 86. E Clock Timing (BUS RELEASE Mode, SLEEP Mode, and
SYSTEM STOP Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Figure 87. E Clock Timing (Minimum Timing Example of PWEL and
PWEH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 88. Timer Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Figure 89. SLP Execution Cycle Timing Diagram . . . . . . . . . . . . . . 203
Figure 90. CSI/O Receive/Transmit Timing Diagram . . . . . . . . . . . 204
Figure 91. External Clock Rise Time and Fall Time . . . . . . . . . . . . 204
Figure 92. Input Rise Time and Fall Time
(Except EXTAL, RESET) . . . . . . . . . . . . . . . . . . . . . . . . 204
Figure 93. Test Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
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List of Tables

Z80180, Z8S180, Z8L180 MPU Operation . . . . . . . . . . . . . . . . . . . .1
Table 1. Status Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
Table 2. Multiplexed Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . .12
Table 3. Memory Wait States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Table 4. Wait State Insertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Table 5. Power-Down Modes
(Z8S180/Z8L180-Class Processor Only) . . . . . . . . . . . . . .37
Table 6. I/O Address Map for Z80180-Class Processors Only . . . . .44
Table 7. I/O Address Map
(Z8S180/Z8L180-Class Processors Only) . . . . . . . . . . . . .48
Table 8. State of IEF1 and IEF2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 9. Vector Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 10. RETI Control Signal States . . . . . . . . . . . . . . . . . . . . . . . . .85
Table 11. DRAM Refresh Intervals . . . . . . . . . . . . . . . . . . . . . . . . . .89
Table 12. Channel 0 Destination . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Table 13. Channel 0 Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99
Table 14. Transfer Mode Combinations . . . . . . . . . . . . . . . . . . . . . . .99
Table 15. Channel 1 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . .102
Table 16. DMA Transfer Request . . . . . . . . . . . . . . . . . . . . . . . . . . .110
Table 17. Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131
Table 18. Divide Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134
Table 19. ASCI Baud Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . .142
Table 20. Clock Mode Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . .144
Table 21. 2^ss Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .145
Table 22. CSI/O Baud Rate Selection . . . . . . . . . . . . . . . . . . . . . . . .150
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Table 23. Timer Output Control . . . . . . . . . . . . . . . . . . . . . . . . . . . .163
Table 24. E Clock Timing in Each Condition . . . . . . . . . . . . . . . . . .166
Table 25. Z8X180 Operating Frequencies . . . . . . . . . . . . . . . . . . . .169
Software Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173
Table 26. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . .173
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185
Table 27. Absolute Maximum Rating . . . . . . . . . . . . . . . . . . . . . . . .185
Table 28. Z80180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .186
Table 29. Z8S180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .187
Table 30. Z8L180 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .189
xv
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .193
Table 31. Z8S180 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 193
Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
Table 32. Register Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207
Table 33. Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Table 34. Instruction Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208
Table 35. Address Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Table 36. Flag Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .209
Table 37. Operations Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . .210
Table 38. Arithmetic and Logical Instructions (8-bit) . . . . . . . . . . . .211
Table 39. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . .216
Table 40. Arithmetic Instructions (16-bit) . . . . . . . . . . . . . . . . . . . . .221
Table 41. 8-Bit Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222
Table 42. 16-Bit Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223
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Table 43. Block Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225
Table 44. Stock and Exchange . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227
Table 45. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . 229
Table 46. I/O Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
Table 47. Special Control Instructions . . . . . . . . . . . . . . . . . . . . . . . 235
Op Code Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Table 48. 1st Op Code Map Instruction Format: XX . . . . . . . . . . . 247
Table 49. 2nd Op Code Map Instruction Format: CB XX . . . . . . . 249
Table 50. 2nd Op Code Map Instruction Format: ED XX . . . . . . . 250
Bus Control Signal Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 51. Bus and Control Signal Condition in Each
Machine Cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251
Table 52. Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279
Operating Modes Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281
Table 53. Request Acceptances in Each Operating Mode . . . . . . . . 281
Table 54. The Z80180 Types of Requests . . . . . . . . . . . . . . . . . . . . 282

Status Signals 287

Table 55. Pin Outputs in Each Operating Mode. . . . . . . . . . . . . . . . 287
Table 56. Pin Status During RESET and
LOW POWER OPERATION Modes. . . . . . . . . . . . . . . . 289
I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
Table 57. Internal I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293
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Z80180, Z8S180, Z8L180 MPU Operation

FEATURES

Operating Frequency to 33 MHz
On-Chip MMU Supports Extended Address Space
Two DMA Channels
On-Chip Wait State Generators
Two Universal Asynchronous Receiver/Transmitter (UART) Channels
Two 16-Bit Timer Channels
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On-Chip Interrupt Controller
On-Chip Clock Oscillator/Generator
Clocked Serial I/O Port
Code Compatible with ZiLOG Z80 CPU
Extended Instructions

GENERAL DESCRIPTION

Based on a microcoded execution unit and an advanced CMOS manufacturing technology, the Z80180, Z8S180, Z8L180 (Z8X180) is an 8-bit MPU which provides the benefits of reduced system costs and low power operation while offering higher performance and maintaining compatibility with a large base of industry standard software written around the ZiLOG Z8X CPU.
Higher performance is obtained by virtue of higher operating frequencies, reduced instruction execution times, an enhanced instruction set, and an
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on-chip memory management unit (MMU) with the capability of addressing up to 1 MB of memory.
Reduced system costs are obtained by incorporating several key system functions on-chip with the CPU. These key functions include I/O devices such as DMA, UART, and timer channels. Also included on-chip are several glue functions such as dynamic RAM refresh control, wait state generators, clock oscillator, and interrupt controller.
Not only does the Z8X180 consume a low amount of power during normal operation, but processors with Z8S180 and Z8L180 class processors also provides two operating modes that are designed to drastically reduce the power consumption even further. The SLEEP mode reduces power by placing the CPU into a stopped state, thereby consuming less current, while the on-chip I/O device is still operating. The SYSTEM STOP mode places both the CPU and the on-chip peripherals into a stopped state, thereby reducing power consumption even further.
When combined with other CMOS VLSI devices and memories, the Z8X180 provides an excellent solution to system applications requiring high performance, and low power operation.
Figures 1 through 3 illustrate the three pin packages in the Z8X180 MPU family:
64-Pin Dual In-line Package (DIP), Figure 1
68-Pin Plastic Leaded Chip Carrier (PLCC), Figure 2
80-Pin Quad Flat Pack (QFP), Figure 3
Pin out package descriptions for other Z8X180-based products are covered in their respective product specifications.
Figure 4 depicts the block diagram that is shared throughout all configurations of the Z8X180.
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XTAL
EXTAL
WAIT
BUSACK
BUSREQ
RESET
NMI
INT0
INT1
INT2
ST
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10 A11
A12
A13
A14
A15 A16 A17
A18/TOUT
V
CC
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1
SS
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30 31
32
Z8X180
64
Phi
RD
63
62
WR
61
MI E
60
59
MREQ
58
IORQ
57
RFSH
56
HALT
55
TEND1
54
DREQ1
53
CKS
52
RXS/CTS1
51
TXS
50
CKA1/TEND0
RXA1
49
48
TXA1 CKA0/DREQ0
47
46
RXA0
45
TXA0
44
DCO0 CTS0
43
RTS0
42
D7
41
40
D6
D5
39
38
D4
37
D3
36
D2 D1
35 34
D0
33
V
SS
Figure 1. 64-Pin DIP
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10
INT0
INT1
11
INT2
12
ST
13
A0
14
A1
15
A2
16
17
A3
18
V
SS
A4
19
20
A5
A6
21
A7
22
A8
23
A9
24
A10
25
26
A11
NMI
9
27
A12
RESET
8
28
A13
BUSREQ
7
29
A14
BUSACK
6
30
A15
WAIT
5
A16
EXTAL
XTAL
432
Z8X180
33
32
A17
VSS
VLS
PhiRDWRMIE
1
68676665646362
35
34
363137383940414243
SS
CC
D0
D2
D1
V
A19
V
D3
D4
MREQ
IORQ
RFSH
61
60
HALT
TEND1
59
58
DREQ1
57
CKS RXS/CTS1
56
55
TXS
54
CKA1/TEND0
53
RXA1
52
TEST
51
TXA1
50
CKA0/DREQ0
49
RXA0
48
TXA0
47
DCD0
46
CTS0
RTS0
45
44
D7
D6
D5
A18/TOUT
Figure 2. 68-Pin PLCC
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SSVSS
K
RESET
BUSREQBUSAC
8079787776757473727170
EXTALNCWAIT
XTAL
V
Phi
RD
WR
69
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MREQ
MI
686766
IORQ
E
65
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5
NMI
NC NC
INT0
INT1
INT2
ST A0
A1
A2
A3
V
SS
A4
NC
A5 A6
A7 A8
A9
A10
A11
NC
NC
A12
1
2
3
4 5
6 7
8 9
10 11
12
13 14
15
16 17 18
19
20
21
22
23
24
10111213141516
A13
A14
A15
A16
Z8X180
NC
A17
17
CC
V
181920
SS
A19
V
D0
21
D1
222324
D2D3D4
64
63
62
61 60
59 58
57 56
55 54
53
52 51
50
49 48 47
46
45
44
43
42
41
25
D5
RFSH
NC NC
HALT
TEND1
DREQ1
CKS RXS/CTS1 TXS
CKA1/TEND0
RXA1 TEST
TXA1 NC
CKA0/DREQ0 RXA0
TXA0 DCD0
CTS
RTS0
D7
NC
NC
D6
Figure 3. 80-Pin QFP
A18/TOUT
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XTAL
EXTAL
RESETRDWRMIMREQ
IORQ
HALT
WAIT
BUSREQ
BUSACK
RFSH
STENMI
INT0
INT1
INT2
Phi
A18/TOUT
TXS
RXS/CTS1
CKS
Timing
Generator
16-bit
Programmable
Reload Timers
Clocked
Serial I/O
Port
MMU
(16-bit)
Address Bus
Bus State Control
CPU
Data Bus (8-bit)
DMACs
(2)
Asynchronous
SCI
(Channel 0)
Asynchronous
SCI
(channel 1)
Interrupt
DREQ1 TEND1
TXA0
CKA0/DREQ0
RXA0
RTS0
CTS0
DCD0
TXA1
CKA1/TEND0
RXA1
Address
Buffer
A0
A19
Data
Buffer
D0
DF
Figure 4. Z80180/Z8S180/Z8L180 Block Diagram
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CC
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SS

PIN DESCRIPTION

A0A19. Address Bus (Output, Active High, 3-state). A0–A19 form a 20- bit address bus. The Address Bus provides the address for memory data bus exchanges, up to 1 MB, and I/O data bus exchanges, up to 64K. The address bus enters a high impedance state during RESET and external bus acknowledge cycles. Address line A18 is multiplexed with the output of PRT channel 1 (TOUT, selected as address output on RESET) and address line A19 is not available in DIP versions of the Z8X180.
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BUSACK
that the requesting device, the MPU address and data bus, and some control signals, have entered their high impedance state.
BUSREQ
external devices (such as DMA controllers) to request access to the system bus. This request has a higher priority than NMI recognized at the end of the current machine cycle. This signal stops the CPU from executing further instructions and places the address and data buses, and other control signals, into the high impedance state.
CKA0, CKA1. Asynchronous Clock 0 and 1 (Bidirectional, Active High). These pins are the transmit and receive clocks for the ASCI channels. CKA0, is multiplexed with DRE TEND
CKS. Serial Clock (Bidirectional, Active High). This line is the clock for the CSIO channel.
CLOCK (PHI). System Clock (Output, Active High). The output is used as a reference clock for the MPU and the external system. The frequency of this output is equal to one-half that of the crystal or input clock frequency.
CTS
modem control signals for the ASCI channels. CTS
. Bus Acknowledge (Output, Active Low). BUSACK indicates
. Bus Request (Input, Active Low). This input is used by
and is always
Q0 and CKA1 is multiplexed with
0.
0, CTS1. Clear to Send 0 and 1 (Inputs, Active Low). These lines are
1 is multiplexed with RXS.
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D0D7. Data Bus (Bidirectional, Active High, 3-state). D0-D7 constitute an 8-bit bidirectional data bus, used for the transfer of information to and from I/O and memory devices. The data bus enters the high impedance state during RESET and external bus acknowledge cycles.
DCD
programmable modem control signal for ASCI channel 0.
0. Data Carrier Detect 0 (Input, Active Low). This input is a
DREQ
0, DREQ1. DMA Request 0 and 1 (Input, Active Low). DREQ is
used to request a DMA transfer from one of the on-chip DMA channels. The DMA channels monitor these inputs to determine when an external device is ready for a read or write operation. These inputs can be programmed to be either level- or edge-sensed. DREQ
0 is multiplexed
with CKA0.
E. Enable Clock (Output, Active High). Synchronous machine cycle clock output during bus transactions.
EXTAL. External Clock/Crystal (Input, Active High). Crystal oscillator connection. An external clock can be input to the Z8X180 on this pin when a crystal is not used. This input is Schmitt-triggered.
HALT
after the CPU has executed either the HALT
. Halt/Sleep Status (Output, Active Low). This output is asserted
or SLP instruction, and is waiting for either non-maskable or maskable interrupt before operation can resume. HALT
is also used with the M1 and ST signals to decode
status of the CPU machine cycle.
0. Maskable Interrupt Request 0 (Input, Active Low). This signal is
INT
generated by external I/O devices. The CPU honors this request at the end of the current instruction cycle as long as the NMI
and BUSREQ signals are inactive. The CPU acknowledges this interrupt request with an interrupt acknowledge cycle. During this cycle, both the M
1 and IORQ
signals become Active.
1, INT2. Maskable Interrupt Requests 1 and 2 (Inputs, Active Low).
INT
This signal is generated by external I/O devices. The CPU honors these requests at the end of the current instruction cycle as long as the NMI
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BUSREQ, and INT0 signals are inactive. The CPU acknowledges these interrupt requests with an interrupt acknowledge cycle. Unlike the acknowledgment for INT
0, during this cycle neither the M1 or IORQ
signals become Active.
. I/O Request (Output, Active Low, 3-state). IORQ indicates that the
IORQ
address bus contains a valid I/O address for an I/O read or I/O write operation. IORQ acknowledgment of the INT
is also generated, along with M1, during the
0 input signal to indicate that an interrupt response vector can be placed onto the data bus. This signal is analogous to the IOE
1. Machine Cycle 1 (Output, Active Low). Together with MR EQ , M1
M
signal of the Z64180.
indicates that the current cycle is the Op Code fetch cycle of an instruction execution. Together with IORQ cycle is for an interrupt acknowledge. It is also used with the HALT
, M1 indicates that the current
and ST signal to decode status of the CPU machine cycle. This signal is analogous to the LIR
signal of the Z64180.
9
MREQ
. Memory Request (Output, Active Low, 3-state). MREQ indicates
that the address bus holds a valid address for a memory read or memory write operation. This signal is analogous to the ME
. Non-maskable Interrupt (Input, negative edge triggered). NMI has
NMI
a higher priority than INT
and is always recognized at the end of an
signal of the Z64180.
instruction, regardless of the state of the interrupt enable flip-flops. This signal forces CPU execution to continue at location
. Read (Output active Low, 3-state). RD indicates that the CPU wants
RD
0066H.
to read data from memory or an I/O device. The addressed I/O or memory device must use this signal to gate data onto the CPU data bus.
. Refresh (Output, Active Low). Together with MREQ, RFSH
RFSH
indicates that the current CPU machine cycle and the contents of the address bus must be used for refresh of dynamic memories. The low order 8 bits of the address bus (A7–A0) contain the refresh address.
This signal is analogous to the REF
signal of the Z64180.
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RTS0. Request to Send 0 (Output, Active Low). This output is a programmable modem control signal for ASCI channel 0.
RXA0, RXA1. Receive Data 0 and 1 (Inputs, Active High). These signals are the receive data to the ASCI channels.
RXS. Clocked Serial Receive Data (Input, Active High). This line is the receiver data for the CSIO channel. RXS is multiplexed with the CTS signal for ASCI channel 1.
1
ST. Status (Output, Active High). This signal is used with the M1 HALT
output to decode the status of the CPU machine cycle. Table 1
and
provides status summary.
Table 1. Status Summary
ST HALT
0 1 0 CPU operation (1st Op Code fetch)
1 1 0 CPU operation (2nd Op Code and 3rd Op Code fetch)
1 1 1 CPU operation (MC
0X
0 0 0 HALT mode
1 0 1 SLEEP mode (including SYSTEM STOP mode)
1
M1 Operation
1 DMA operation
2
except for Op Code fetch)
1. X = Don't care
2. MC = Machine cycle
TEND
0, TEND1. Transfer End 0 and 1 (Outputs, Active Low). This
output is asserted active during the last write cycle of a DMA operation. It is used to indicate the end of the block transfer. TEND
0 in multiplexed
with CKA1.
TEST. Test (Output, not on DIP version). This pin is for test and must be left open.
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TOUT. Timer Out (Output, Active High). TOUT is the pulse output from PRT channel 1. This line is multiplexed with A18 of the address bus.
TXA0, TXA1. Transmit Data 0 and 1 (Outputs, Active High). These signals are the transmitted data from the ASCI channels. Transmitted data changes are with respect to the falling edge of the transmit clock.
TXS. Clocked Serial Transmit Data (Output, Active High). This line is the transmitted data from the CSIO channel.
. Wait (Input; Active Low). WAIT indicates to the CPU that the
WAIT
addressed memory or I/O devices are not ready for a data transfer. This input is used to induce additional clock cycles into the current machine cycle. The WAIT
input is sampled on the falling edge of T2 (and subsequent Wait States). If the input is sampled Low, then additional Wait States are inserted until the WAIT
input is sampled High, at which time
execution continues.
11
. Write (Output, Active Low, 3-state). WR indicates that the CPU data
WR
bus holds valid data to be stored at the addressed I/O or memory location.
XTAL. Crystal (Input, Active High). Crystal oscillator connection. This pin must be left open if an external clock is used instead of a crystal. The oscillator input is not a TTL level (reference DC characteristics).
Multiplexed pins are described in Table 2.
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Table 2. Multiplexed Pin Descriptions
Multiplexed Pins Descriptions
A18/TOUT
CKA0/
DREQ0
TEND0
CKA1/
During RESET, this pin is initialized as A18 pin. If either TOC1 or TOC0 bit of the Timer Control Register (TCR) is set to 1, TOUT function is selected. If TOC1 and TOC0 bits are cleared to 0, A18 function is selected.
During RESET, this pin is initialized as CKA0 pin. If either DM1 or SM1 in DMA Mode Register (DMODE) is set to 1,
During RESET, this pin is initialized as CKA1 pin. If CKA1D bit in ASCI control register ch 1 (CNTLA1) is set to 1, CKA1 function is selected.
DREQ0 function is always selected.
TEND0 function is selected. If CKA1D bit is set to 0,
During RESET, this pin is initialized as RXS pin. If CTS1E bit
RXS/
CTS1
in ASCI status register ch 1 (STAT1) is set to 1, is selected. If CTS1E bit is 0, RXS function is selected.

ARCHITECTURE

The Z8X180 combines a high performance CPU core with a variety of system and I/O resources useful in a broad range of applications. The CPU core consists of five functional blocks: clock generator, bus state controller (including dynamic memory refresh), interrupt controller, memory management unit (MMU), and the central processing unit (CPU). The integrated I/O resources make up the remaining four functional blocks:
Direct Memory Access (DMA) Control (2 channels)
Asynchronous Serial Communications Interface (ASCI, 2 channels),
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Programmable Reload Timers (PRT, 2 channels)
Clock Serial I/O (CSIO) channel.
Other Z8X180 family members (such as Z80183, Z80S183, Z80185/195) feature, in addition to these blocks, additional peripherals and are covered in their associated Product Specification
Clock Generator
This logic generates the system clock from either an external crystal or clock input. The external clock is divided by two and provided to both internal and external devices.
Bus State Controller
13
This logic performs all of the status and bus control activity associated with both the CPU and some on-chip peripherals. This includes Wait State timing, RESET cycles, DRAM refresh, and DMA bus exchanges.
Interrupt Controller
This block monitors and prioritizes the variety of internal and external interrupts and traps to provide the correct responses from the CPU. To remain compatible with the Z80 CPU, three different interrupt modes are supported.
Memory Management Unit
The MMU allows the user to map the memory used by the CPU (logically only 64K) into the 1MB addressing range supported by the Z8X180. The organization of the MMU object code features compatibility with the Z80 CPU while offering access to an extended memory space. This capability is accomplished by using an effective common area - banked area scheme.
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Central Processing Unit
The CPU is microcoded to provide a core that is object code compatible with the Z80 CPU. It also provides a superset of the Z80 instruction set, including 8-bit multiply and divide. This core has been enhanced to allow many of the instructions to execute in fewer clock cycles.
DMA Controller
The DMA controller provides high speed transfers between memory and I/O devices. Transfer operations supported are memory-to-memory, memory to/from I/O and I/O to I/O. Transfer modes supported are REQUEST, BURST, and CYCLE STEAL. DMA transfers can access the full 1MB addressing range with a block length up to 64KB, and can cross over 64K boundaries.
Asynchronous Serial Communications Interface (ASCI)
The ASCI logic provides two individual full-duplex UARTs. Each channel includes a programmable baud rate generator and modem control signals. The ASCI channels can also support a multiprocessor communications format.
Programmable Reload Timer (PRT)
This logic consists of two separate channels, each containing a 16-bit counter (timer) and count reload register. The time base for the counters is derived from the system clock (divided by 20) before reaching the counter. PRT channel 1 provides an optional output to allow for waveform generation.
Clocked Serial I/O (CSIO)
The CSIO channel provides a half-duplex serial transmitter and receiver. This channel can be used for simple high-speed data connection to another microprocessor or microcomputer.
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OPERATION MODES

The Z8X180 can be configured to operate like the Hitachi HD64180. This functionality is accomplished by allowing user control over the M IORQ
, WR, and RD signals. The Operation Mode Control Register (OMCR), illustrated in Figure 5, determines the M the IORQ
, RD, and WR signals, and the RETI operation.
1 options, the timing of
Operation Mode Control Register
Bit 7654 0
Bit/Field M1E M1TE
R/W R/W W R/W
Reset 1 1 1
Note: R = Read W = Write X = Indeterminate? = Not Applicable
IOC Reserved
1,
15
Figure 5. Operation Mode Control Register
M1E (M1 Enable): This bit controls the M1 output and is set to a 1 during RESET.
When M1E is
1, the M1 output is asserted Low during the Op Code fetch
cycle, the INT0 acknowledge cycle, and the first machine cycle of the
acknowledge. This action also causes the M1 signal to be Active
NMI during both fetches of the RETI instruction sequence, and may cause corruption of the external interrupt daisy chain. Therefore, this bit must be
0 for the Z8X180. When M1E is 0 the M1 output is normally inactive and
asserted Low only during the refetch of the RETI instruction sequence and the INT
0 acknowledge cycle (Figure 6).
UM005003-0703
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