High-Performance 16-Bit Microcontrollers
ZNEO® CPU Core
User Manual
UM018809-0611
Copyright ©2011 Zilog®, Inc. All rights reserved.
www.zilog.com
ZNEO® CPU Core
Warning:
User Manual
ii
This publication is subject to replacement by a later edition. To determine whether a later edition exists, or
to request copies of publications, visit www.zilog.com
.
DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A critical component is any componen t in a li fe supp ort device o r syste m whose failure to p erform ca n be re asonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2011 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, eZ80, and ZNEO are trademarks or registered trademarks
of Zilog, Inc. All other product or service names are the property of their respective owners.
UM018809-0611
Revision History
Each instance in the Revision History table below reflects a change to this document from
its previous version. For more details, click the appropriate links in the table.
Revision
Date
May
2011
Aug
2010
Feb
2008
Sep
2007
Mar
2007
May
2006
Level Section Description Page
09 All Updated for style. All
Using the Program Counter as
a Base Address
LEA
SDIV Corrected After address in Example. 152
08 ADC, ADD Updated Syntax and Opcodes table. 68, 71
07 Flags Register (FLAGS) Updated User Flag description. 9
Loading an Effective Address Updated example. 33
System Exceptions Updated first paragraph. 49
Stack Overflow Updated second step for Stack Overflow
06 Instruction Set Reference Updated Examples for DEC Instruction. 65
05 Loading an Effective Address Change in instruction. 33
Flags Register (FLAGS), Vectored Interrupts, Instruction Set
Reference
04 Multiple Updated ZNEO trademark issues. Applied
Features, Control Registers,
Address Space, I/O Memory,
Direct Memory Addressing
CPU Control Register
(CPUCTL)
Memory Map, Jump Addressing
Internal Nonvolatile Memory,
Internal RAM
Direct Memory Addressing 16-bit address range is in highest and low-
®
ZNEO
Added note. 34
Added addressing mode offset description.
protection.
Updated with CIRQE bit. 9, 41, 65
current publications template.
Clarified size of address space. 1, 8, 15,
Clarified section. 13
Jump addresses FF_E000H and above
are reserved.
Clarified use of assembler address
ranges.
est 32K blocks, not 8K blocks.
CPU Core
User Manual
122
50
All
18, 29
16, 39
17, 17
29
iii
UM018809-0611 Revision History
ZNEO® CPU Core
User Manual
iv
Date
Jan
2006
Revision
Level Section Description Page
03 Multiple Updated ZNEO trademark. All
02 Instruction Opcodes Moved opcodes beginning 0000 1011
and 0001 001+ to correct listing order.
(Opcode-to-instruction relationship is not
changed); corrected sequence of unimplemented opcodes and removed duplicate
row.
UDIV64 Corrected “After” register in example. 182
55
Revision History UM018809-0611
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .ix
List of Tables. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xi
Manual Objectives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii
About This Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii
Intended Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii
Manual Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiii
Manual Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xiv
Safeguards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .xvi
ZNEO
®
CPU Core
User Manual
v
Architectural Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Program Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Processor Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Fetch Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Execution Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Instruction Cycle Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Instruction Fetch Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Execution Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Program Counter Overflow Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Stack Pointer Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Flags Register (FLAGS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
CPU Control Register (CPUCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Address Space. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Internal Nonvolatile Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Internal RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
I/O Memory Precautions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
External Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Endianness . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Bus Widths . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Assembly Language Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ZNEO CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
UM018809-0611 Table of Contents
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User Manual
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Operand Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Immediate Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Register Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Direct Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Memory Data Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Resizing Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Register-Indirect Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Loading an Effective Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Using the Program Counter as a Base Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Memory Address Decrement and Increment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Using the Stack Pointer (R15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Using the Frame Pointer (R14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Bit Manipulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Clearing Bits (Masked AND) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Setting Bits (Masked OR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Testing Bits (TM and TCM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Jump Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Vectored Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Interrupt Enable and Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Interrupt Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Returning From a Vectored Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Interrupt Priority and Nesting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Software Interrupt Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Polled Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
System Exceptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Program Counter Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Stack Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Divide-by-Zero . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Divide Overflow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Illegal Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Software Traps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Instruction Opcodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Instruction Set Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Numerical and Expression Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Miscellaneous Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Example Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Mnemonic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table of Contents UM018809-0611
®
ZNEO
CPU Core
User Manual
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
ADD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
ATM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
BRK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
CALL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
CALLA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
CLR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
COM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
CP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
CPC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
CPCZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
CPZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
DEC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
DI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
DJNZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
EXT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
HALT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
ILL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
INC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
IRET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
JP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
JPA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
JP cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
LD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
LD cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
LDES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
LEA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
LINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
MUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
NEG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
NOFLAGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
NOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
POP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
POPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
POPMLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
POPMHI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
PUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
PUSHF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
vii
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PUSHMHI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
PUSHMLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
RET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
RL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
SBC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
SDIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152
SLL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
SLLX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
SMUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
SRA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
SRAX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
SRL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
SRLX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166
STOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
SUB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
TCM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
TM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
TRAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
UDIV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
UDIV64 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
UMUL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
UNLINK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table of Contents UM018809-0611
List of Figures
Figure 1. ZNEO CPU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Flags Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 3. ZNEO CPU Memory Map (24 Significant Address Bits) . . . . . . . . . . . . . . 16
Figure 4. Endianness of Words and Quads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 5. Alignment of 16-Bit and 32-Bit Operations on 16-Bit Memories . . . . . . . . 20
Figure 6. Example Assembly Language Statement . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 7. Mapping of Register to Memory Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
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Figure 8. Register-Indirect Memory Addressing Example . . . . . . . . . . . . . . . . . . . . . 33
Figure 9. Masked Logic Example: Clearing a Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 10. Effects of an Interrupt on the Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 11. Interrupt Vectoring Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
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List of Figures UM018809-0611
List of Tables
Table 1. Instruction Execution Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 2. Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 3. Condition Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 4. CPU Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 5. Reserved Memory Map Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 6. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 7. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 8. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 9. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 10. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 11. CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 12. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 13. 16-Bit Addressing (Object Code Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. Data Sizes for Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 15. Relative Jump Offset Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 16. Bit Field Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 17. Operand Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 18. ZNEO CPU Instructions Listed by Opcode . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 19. Symbols Used in Expressions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 20. Abbreviations Used in Text and Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 21. Truth Table for AND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 22. Truth Table for OR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 23. Truth Table for XOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188
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UM018809-0611 List of Tables
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List of Tables UM018809-0611
Manual Objectives
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xiii
This user manual describes the CPU architecture and instruction set common to all Zilog
devices that incorporate the ZNEO
internal peripherals and memory, and I/O registers for each device, refer to the device-specific Product Specification.
About This Manual
Zilog® recommends you to read and understand everything in this manual before setting
up and using the product. We have designed this manual to be used either as an instructional manual or a reference guide to important data.
Intended Audience
This document is written for Zilog customers with experience in writing microprocessor,
assembly code, and compilers. Some introductory material is included to help new customers who are less familiar with this device.
Manual Organization
®
CPU. For complete information about interfaces,
This user manual is divided into nine chapters to describe the following device characteristics:
Architectural Overview
Describes the ZNEO CPU’s features and benefits, architecture, and control registers.
Address Space
Introduces the ZNEO CPU’s unified memory address space, with a memory map illustrating how the available memory areas are addressed.
Assembly Language Introduction
Briefly introduces some of the assembly language terminology used in the following chapters and lists ZNEO CPU instructions in functional groups.
Operand Addressing
Explains ZNEO CPU operand addressing and data sizes.
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Interrupts
Introduces the use of vectored and polled interrupts to service interrupt requests from
peripherals or external devices.
System Exceptions
Explains system exceptions and the events which cause the processor overflow, stack
overflow, divide-by-zero, divide overflow, and illegal instruction.
Software Traps
Explains the software trap instruction.
Instruction Opcodes
Numerical list of ZNEO CPU instruction opcodes and syntax.
Instruction Set Reference
Alphabetical list of ZNEO CPU instruction descriptions, with syntax and opcodes.
Manual Conventions
The following manual conventions provide clarity and ease of use.
Notations specific to assembly language, address operands, opcodes, and instruction
descriptions are explained in the chapters discussing those topics.
Courier Typeface
User-typed commands, code lines and fragments, bit names, equations, hexadecimal
addresses, and executable items are distinguished from general text by the use
Courier typeface. Where the use of the font is not indicated (for example, Index)
of the
the name of the entity is presented in upper case.
For example, Internal RAM begins at
Binary Values
Binary values are designated by an uppercase ‘B’ suffix. For readability, underscore ‘_’
characters separate large values into four-digit groups, except in program statements.
For example, 8-bit binary value
FFFF_0000H.
0100_0010B.
Hexadecimal Values
Hexadecimal values are designated by an uppercase ‘H’ and appear in the Courier typeface. For readability, underscore ‘_’ characters separate lar ge values into four-digit groups,
except in program statements as illustrated in the below examples:
Manual Objectives UM018809-0611
®
ZNEO
Example 1: R1 is set to F8H.
Example 2: 32-bit hexadecimal value 1234_5678H
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Bit Numbering
Bits are numbered in order of significance, from 0 to n–1 where 0 indicates the least significant bit and n indicates the total number of bits.
For example, 8 bits of a memory byte are numbered from 0 to 7.
Registers, memory bytes, and binary values are illustrated with the highest-numbered bit
on the left and the lowest-numbered bit on the right.
xv
For example, Bit 6 of the value
0100_0000B is 1.
Brackets
In text, square brackets, [ ], indicate one or more bits of a register, memory location, or
bus. A colon between bit numbers indicates a range of bits. A comma between bit numbers
indicates individual bits as given below:
Example 1: ADDR[31:0] refers to bit 31 through bit 0 of the ADDR bus or memory loca-
tion. ADDR[31] is the most significant bit (msb), and ADDR[0] is the least significant bit
(lsb). ADDR[31:24] is the most significant byte (MSB), and ADDR[7:0] is the least significant byte (LSB).
Example 2: If the value of R1[7:0] is 0100_0010B, the bits R1[6,2] are both 1.
Braces
The curly braces, { }, indicate a single register, memory address or bus created by concatenating combination of smaller registers, addresses, buses or individual bits.
For example, the 32-bit effective address {
hexadecimal value (
FFFFH) and a 16-bit direct address. FFFFH is the most significant
FFFFH, ADDR[15:0]} consists of a 16-bit
word (16 bits) and ADDR[16:0] is the least significant word of the resulting 32-bit
address.
Use of the Words Set, Reset and Clear
The word set indicates a 1 is stored in a register or memory bit or flag. The words reset or
clear indicates a 0 is stored in a register or memory bit or flag.
Use of the Terms LSB, MSB, lsb and msb
In this document, the terms LSB and MSB, when appearing in upper case, mean least significant byte and most significant byte, respectively. The lowercase forms (lsb and msb)
mean least significant bit and most significant bit, respectively.
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Use of Initial Uppercase Letters
Initial uppercase letters designate settings, modes, and conditions in general text:
Example 1: Stop mode.
Example 2: The receiver forces the SCL line to Low.
Example 3: The Master can generate a Stop condition to abort the transfer.
Use of All Uppercase Letters
The use of all uppercase letters designates assembly mnemonics or the names of states and
hardware commands.
Example 1: The bus is considered BUSY after the Start condition.
Example 2: A START command triggers the processing of the initialization sequence.
Safeguards
It is important to understand the following safety terms:
Indicates that a procedure or file may become corrupted if you do not follow directions.
Indicates that you are in a situation that could cause bodily injury. Before you work on
any equipment, be aware of the hazards involved with electrical circuitry and be familiar with standard practices for preventing accidents.
Manual Objectives UM018809-0611
Architectural Overview
Zilog’s ZNEO CPU meets the continuing demand for faster and more code-efficient
microcontrollers. ZNEO CPU’s architecture greatly improves the execution
code developed using higher-level programming languages like ‘C’ language
Features
The key features of ZNEO CPU architecture include:
•
Highly efficient register-based architecture with sixteen 32-bit registers. All register
operations are 32 bits wide
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efficiency of
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•
Up to 4 GB linear address space (16 MB on current devices) with multiple internal
and external memory and I/O buses
•
Short 16-bit addressing for internal RAM, I/O, and 32K of nonvolatile memory
•
Instructions using memory can operate on 8-bit, 16-bit, or 32-bit values
•
Support for 16-bit memory paths (internal and external)
•
Pipelined instruction fetch, decode, and execution
•
Bus arbiter supports simultaneous instruction and memory access (when possible)
Other features of the ZNEO CPU include:
•
Direct register-to-register architecture allows each 32-bit register to function as an
accumulator. This improves the execution time and decreases the memory required for
programs.
•
Expanded stack support:
– Push/Pop instructions use one 32-bit register as Stack Pointer
– Single-instruction push and pop of multiple registers
– Stack Pointer overflow protection
– Predecrement/postincrement Load instructions simplify the use of multiple stacks
– Link and Unlink operations with enhanced Frame Pointer-based instructions for
efficient access to arguments and local variables in subroutines
•
Program Counter overflow protection
•
User-selectable bus bandwidth control for DMA and CPU sharing
UM018809-0611 Architectural Overview
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Program Control
ZNEO CPU is controlled by a program stored in memory as object code. An object code is
a sequence of numerical opcode and operand bytes. An opcode specifies an instruction to
perform while operands specify the data addresses to be operated upon. Numerical object
code is rarely used to write programs. Instead, programs is written in a symbolic assembly
language using easily remembered (mnemonic) instructions. A program called an assembler translates assembly language into object code.
This user manual provides details about using ZNEO CPU instructions in both object code
and assembly language. Those interested in writing assembly language can skip object
code details handled by the assembler.
Programmers using high-level languages like ‘C’ require this manual while writing optimized routines in assembly language. Otherwise, the compiler or interpreter’s documentation should describe processor-specific details affecting program operation.
Processor Block Diagram
The ZNEO CPU consists of following two major functional blocks:
•
Fetch Unit
•
Execution Unit
The Fetch and Execution units access memory through a bus arbiter. The Execution Unit
is subdivided into the Instruction State Machine, Program Counter, Arithmetic Logic Unit
(ALU), and ALU registers. Figure 1 on page 3 displays the ZNEO CPU architecture.
Architectural Overview UM018809-0611
ZNEO
Fetch Unit
Instruction and
Operand Fetch
Instruction State Machine
Arithmetic Logic Unit (ALU)
32-bit ALU Registers, R0-R15
Bus Arbiter
16
Internal
Non-volatile
Memory
16
Internal
RAM
8/16
Internal I/O
8/16
External
Memory
Interface
Program
Counter
Control
Registers
Execution Unit
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Fetch Unit
The Fetch Unit’s primary function is to fetch opcodes and operand words (including
immediate data) from memory. The Fetch Unit also fetches interrupt vectors. The Fetch
Unit is pipelined and operates semi-independently from the execution unit. This Unit performs a partial decoding of the opcode to determine the number of bytes to fetch for the
operation.
The Fetch Unit operation sequence functions as follows:
1. Fetch the first 2-byte opcode word.
2. Determine number of remaining opcode and operand words (one or two).
3. Fetch the remaining opcode and operand words.
4. Present the opcode and operands to the Instruction State Machine.
A ZNEO CPU instruction is always 1, 2, or 3 words long, including operands, and must be
aligned on an even address.
Figure 1. ZNEO CPU Block Diagram
UM018809-0611 Architectural Overview
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4
Execution Unit
The Execution Unit performs the processing functions required by the instruction opcodes
and operands which it receives from the Fetch Unit.
Instruction State Machine
The Instruction State Machine is the controller for the ZNEO CPU Execution Unit. After
the initial operation decode by the Fetch Unit, the Instruction State Machine takes over
and completes the instruction. The Instruction State Machine generates effective addresses
and controls memory read and write operations.
Program Counter
The Program Counter contains a counter and adder to monitor the address of the current
instruction and calculates the next instruction address. According to the number of bytes
fetched by the Fetch Unit, the Program Counter increments automatically. The adder
increments and handles Program Counter jumps for relative addressing. The initial value
of the program counter is programmable through the RESET vector.
refer to the ZNEO product specification that is specific to your device for the RESET vector location.
Programs cannot address the Program Counter directly but the instruction
LEA Rd, 4(PC) can be used to load the current Program Counter value (the next instruc-
tion address) into an ALU Register. The JP, CALL, and related instructions are used to
alter the program counter value.
The I/O memory register described in Program Counter Overflow Register on page 9 provides access to the program counter overflow feature.
Arithmetic Logic Unit
The Arithmetic Logic Unit (ALU) performs arithmetic and logical operations on data.
arithmetic operations including addition, subtraction, and multiplication. Logical operations include binary logic operations, bit shifting, and bit rotation.
ALU Registers
The ZNEO CPU provides 16 highly efficient 32-bit registers associated with the ALU.
The 16 ALU registers are named from R0 to R15.
These registers have the following characteristics:
•
The CPU can access ALU registers more quickly than ordinary internal or external
memory.
Architectural Overview UM018809-0611
®
Note:
ZNEO
•
All 32 bits of a source or destination ALU Register are used for arithmetic and logical
operations.
•
When an 8-bit or 16-bit memory read is performed, the value is extended to 32-bits in
the destination register. Unsigned (zero) or Signed extension can be specified.
•
When an 8-bit or 16-bit memory write is performed, the source register’ s value is trun-
cated (only the least significant 8 or 16 bits are stored in memory.)
•
The CALL, IRET, LINK, POP, POPM, PUSH, PUSHM, RET, TRAP, and UNLINK
instructions; system interrupts; and exceptions use Register R15 as the Stack Pointer.
If not used, R15 behaves like any other ALU Register.
•
The LINK, UNLINK, and some LD operations use Register R14 as a Frame Pointer. If
not used, R14 behaves like any other ALU Register.
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5
Instruction Cycle Time
Instruction cycle times vary from instruction to instruction. Instructions are pipelined
which means the current instruction executes while the next instruction is being fetched.
This allows higher performance at a specific clock speed.
Instruction Fetch Cycles
The following equation is used to calculate the minimum number of cycles required to
fetch an instruction into the CPU:
Fetch Cycles = (bus_wait_states + 1) opcode_bytes/bus_bytes
In the above equation, the following points are true:
•
Bus wait states is configured on a bus to accommodate memory specifications. The
number of wait states is added to each memory read or write on that bus.
For details about wait states, refer to the ZNEO product specification that is specific to
your device .
•
The opcode bytes value can be 2, 4 or 6, depending on the instruction. Immediate
operands, if any, are included in the opcode fetch, so they do not affect execution
cycles.
•
The bus bytes value can be 1 or 2, for fetches from an 8-bit or 16-bit bus, respectively.
For more details, see the Bus Widths
UM018809-0611 Architectural Overview
section on page 19.
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6
Execution Cycles
Instructions always begin at an even address; therefore, instruction fetches are not subject
to uneven alignment delays.
An instruction fetch delay cycle can occur if the Fetch and Execution Units request access
to the same bus on the same cycle. In this case, the bus arbiter gives precedence to the
Execution Unit. This kind of delay can be avoided by storing instructions and data in different memory spaces; for example, instructions in ROM or Flash and data in RAM.
The minimum instruction execution time for most CPU instructions is one system clock
cycle. Additional cycles are required for shift, multiply, divide operations, and operations
which read or write memory locations. Table 1 lists minimum Execution Unit cycle times
for the various instructions. The symbol bus_time is described in the text following the
table, as other factors that affect execution of some instructions.
Table 1. Instruction Execution Cycles
Instruction Operand Types Minimum Execution Unit Cycles
LD, LEA Immediate, Register-to-Reg-
ister
To or From Memory 1
EXT, LDES, ATM, BRK, DI, DJNZ,
EI, HALT, IRET, NOP, RET, STOP
PUSH, POP,
PUSHF, POPF
PUSHM, POPM — Variable
CLR Register 1
CP, CPZ, TM, TCM Immediate, Register-to-Reg-
ADC, ADD, AND, COM, CPC,
CPCZ, DEC, INC, NEG, OR, SBC,
SUB, XOR
—1
—1
Memory 1
ister
To or From Memory 1 +
Immediate, Register-to-Reg-
ister
Memory to Register 1 +
1
bus_time
bus_time
bus_time
1
bus_time
1
bus_time
Register to Memory 2 bus_time
Architectural Overview UM018809-0611
®
ZNEO
Table 1. Instruction Execution Cycles (Continued)
Instruction Operand Types Minimum Execution Unit Cycles
MUL, SMUL, UMUL Operands 1_0000H 10
Operands 1_0000H 18
SDIV Destination 1_0000H 17 if result is positive, 18 if negative
Destination 1_0000H 33 if result is positive, 34 if negative
UDIV Destination 1_0000H 17
Destination 1_0000H 33
UDIV64 — 34
SRA, SRL, SLL, RL — (src/8) + (src % 8)
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SRAX, SRLX, SLLX — src + 1
JP, JP cc, CALL, NOFLAGS, Extend
Prefix
ILL, TRAP — 1 + 4
—0
IROM_bus_time
stack_bus_time
+ 6
+ next_instruction_words
LINK — 2 + 4 stack_bus_time
UNLINK — 1 + 4 stack_bus_time
Execution cycles can be affected by the following factors:
•
The symbol bus_time stands for the time to read or write a value to the addressed
memory bus, as given by the formula below:
(bus_wait_states + 1) ceiling(data_bytes/bus_bytes)
In the above equation, the following points can be considered:
– Bus wait states is configured for a bus to accommodate memory specifications.
The number of wait states is added to each memory read or write on that bus.
–The ceiling function rounds up to the nearest integer. This accounts for a 1-byte
access on a 2-byte bus, which takes a full memory access cycle, not 1/2 cycle.
–The data bytes value can be 1, 2 or 4, depending on the size of the addressed data
(for direct or register-indirect addressed memory).
–The bus bytes value can be 1 or 2, for fetches from an 8-bit or 16-bit bus, respec-
tively.
An unaligned 16-bit or 32-bit read or write requires additional cycles. For more
details, see the Bus Widths
section on page 19.
UM018809-0611 Architectural Overview
ZNEO® CPU Core
Note:
Note:
Note:
User Manual
8
•
•
For details about wait states, refer to the ZNEO product specification that is specific to
your device .
Control Registers
For LD and LEA instructions, a delay cycle is inserted if a register is loaded immediately before it is used for the base address in a register-indirect instruction.
If execution of an instruction ends before all the next instruction words are fetched,
the Execution Unit delays for the number of cycles required by the Fetch unit to complete the instruction fetch. After an ILL or TRAP instruction executes, the entire next
instruction must be fetched.
The ZNEO CPU and internal peripheral control registers are accessed in the I/O memory
space starting at
FF_E000H (24-bit address space devices). Table 2 lists control registers
common to all Zilog devices that incorporate the ZNEO CPU. In this table, “X” indicates
an undefined hex digit value.
For complete information about peripheral control registers for a particular device, refer to
the device specific Product Specification.
Table 2. Control Registers
Reset Value
Address (Hex) Register Description Mnemonic
FF_E004–FF_E007 Program Counter Overflow PCOV FFFFFFFF
FF_E008–FF_E00B Reserved — xxxxxxxx
FF_E00C–FF_E00F Stack Pointer Overflow SPOV 00000000
FF_E010 Flags FLAGS xx
FF_E011 Reserved — xx
FF_E012 CPU Control CPUCTL FF
(Hex)
I/O memory locations can be accessed using a 16 bit address operand. For more details, see
the Direct Memory Addressing section on page 29.
Architectural Overview UM018809-0611
Program Counter Overflow Register
CZSVBF1 CIRQE IRQE Flags Register
Bit
0
Bit
7
Master Interrupt Enable
Chained Interrupt Enable
User Flag 1
Blank Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
The Program Counter Overflow Register (PCOV) implements program counter overflow
protection. For more details, see the Program Counter Overflow
Stack Pointer Overflow
The Stack Pointer Overflow Register (SPOV) is used to provide stack pointer overflow
protection. For more details, see the Stack Overflow
IRET, POP, PUSH, RET and TRAP instructions, system interrupts and exceptions use the
ALU Register. R15 is used as the Stack Pointer.
Flags Register (FLAGS)
®
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section on page 50.
section on page 50. CALL, ILL,
CPU Core
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9
This byte register contains the status information regarding the most recent arithmetic,
logical, bit manipulation or rotate and shift operation. The Flags Register contains six bits
of status information that are set or cleared by CPU operations. Five of the bits (C, Z, S, V
and B) can be tested with conditional jump instructions. The
rupt Enable flag, and the CIRQE bit is the Chained Interrupt Enable flag. Figure 2 displays
the flags and their bit positions in the Flags Register.
IRQE bit is the Master Inter-
Figure 2. Flags Register
Interrupts, System Exceptions, and the software Trap (TRAP) instruction write the value
of the Flags Register to the stack. Executing an Interrupt Return (IRET) instruction
restores the value saved on the stack into the Flags Register.
UM018809-0611 Architectural Overview
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User Manual
10
Flag settings depend on the data size of the result, which can be 8 bits (Byte), 16 bits
(Word), or 32 bits (Quad, the default). For instructions with destinations in memory, the
mnemonic suffix determines the destination size. If the destination is a register, Flags are
based on the 32-bit result. For more information, see the Memory Data Size
section on
page 30.
Carry Flag
The Carry (C) flag is 1 when the result of an arithmetic operation generates a carry out of
or a borrow into the most significant bit (msb) of the data. Otherwise, the Carry flag is 0.
Some bit rotate or shift instructions also affect the Carry flag. Bit [31] is considered msb
for register destinations; the msb for a memory destination depends on the data size.
Zero Flag
For arithmetic and logical operations, Zero (Z) flag is 1 if the result is 0. Otherwise, the
Zero flag is 0. If the result of testing bits is
0, Zero flag is 1; otherwise, the Zero flag is 0.
Also, if the result of a rotate or shift operation is
0, the Zero flag is 1; otherwise, the Zero
flag is 0. The test considers 32 bits for a register destination or the destination size for a
memory destination.
Sign Flag
The Sign (S) flag stores the value of the most significant bit (msb) of a result following an
arithmetic, logical, rotate, or shift operation. For signed numbers, the ZNEO CPU uses
binary two’s complement to represent the data and perform the arithmetic operations. A 0
in the msb position identifies a positive number; therefore, the Sign flag is also 0. A 1 in
the most significant position identifies a negative number; therefore, the Sign flag is also
1. Bit [31] is considered msb for register destinations; the msb for a memory destination
depends on the data size.
Overflow Flag
For signed arithmetic, rotate or shift operations, the Overflow (V) flag is 1 when the result
is greater than the maximum possible number or less than the minimum possible number
which is represented with the specified data size in signed (two’s complement) form. For
signed data size ranges, see Table 14
occurs. Following logical operations, the Overflow flag is 0.
Following addition operations, the Overflow flag is 1 when the operands have the same
sign, but the result has the opposite sign. Following subtraction operations, the Overflow
flag is 1 if the two operands are of opposite sign and the sign of the result is same as the
sign of the source operand. Following shift/rotation operations, the Overflow flag is 1 if
the sign bit of the destination changed during the last bit shift iteration.
on page 32. The Overflow flag is 0 if no overflow
Architectural Overview UM018809-0611
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ZNEO
CPU Core
User Manual
Blank Flag
For some arithmetic, logical, and load operations, the Blank (B) flag is set to 1 if a tested
operand value is 0 before the operation. Otherwise,
operands might be tested, but which operands are tested depends on the operation being
performed. See the instruction descriptions for details.
B is 0. Both source and destination
11
Unlike other flags, the
B flag can be altered by POP and some LD instructions. 8-bit or 16-
bit memory operands are tested after unsigned or signed extension, depending on the
instruction
The
the following statement executes,
. For more information, see the Resizing Data section on page 31.
B flag is useful for operations involving a null-terminated strings. For example, after
Z is set if the tested byte is a carriage return (0DH), or B
is set if the byte is zero.
CP.B (R6), #0DH
User Flag
The User Flag (F1) are available as general-purpose status bits. The User Flag is unaffected by arithmetic operations and must be set or cleared by instructions. The User Flag
must not be used with conditional Jumps. The User Flag is 0 after initial power-up or
Reset.
Chained Interrupt Enable Flag
The Chained Interrupt Enable flag (CIRQE) is used to enable or disable chained-interrupt
optimization, which allows program control to pass directly from one interrupt service
routine to another while omitting unneeded stack operations. For more information, see
the Returning From a Vectored Interrupt
Whenever a vectored interrupt or system exception occurs, the previous state of the
flag is copied to
CIRQE after the Flags Register is pushed onto the stack. This disables
interrupt chaining if interrupts are globally disabled (
rupt or system exception occurs.
section on page 44.
IRQE
IRQE=0) when a nonmaskable inter-
The
CIRQE flag is unaffected by other operations, but it may be set or cleared by instruc-
tions, if desired. The
CIRQE flag cannot be used with conditional Jumps. The CIRQE flag
is 0 after initial power-up or Reset.
Master Interrupt Enable Flag
The Master Interrupt Enable bit (IRQE) globally enables or disables interrupts. For more
information, see the Interrupts
chapter on page 41.
Condition Codes
The C, Z, S, V, and B flags control the operation of the conditional jump (JP cc) instruc-
tions. Sixteen frequently useful functions of the flag settings are encoded in a 4-bit field
UM018809-0611 Architectural Overview
ZNEO® CPU Core
Note:
User Manual
12
called the condition code (cc), which are assembled into each conditional jump opcode.
Table 3 summarizes condition codes and their assembly language mnemonics.
Some binary condition codes are expressed by more than one mnemonic.
The result of the flag test operation determines if the conditional jump executes.
Table 3. Condition Codes
Assembly
Binary Hex
0000 0 B Blank B = 1
0001 1 LT Less Than (S XOR V) = 1
0010 2 LE Less Than or Equal (Z OR (S XOR V)) = 1
0011 3 ULE Unsigned Less Than or Equal (C OR Z) = 1
0100 4 OV Overflow V = 1
0101 5 MI Minus S = 1
0110 6 ZZero Z = 1
0110 6 EQ Equal Z = 1
0111 7 CCarry C = 1
0111 7 ULT Unsigned Less Than C = 1
1000 8 NB Not Blank B = 0
1001 9 GE Greater Than or Equal (S XOR V) = 0
1010 A GT Greater Than (Z OR (S XOR V)) = 0
1011 B UGT Unsigned Greater Than (C OR Z) = 0
1100 C NOV No Overflow V = 0
1101 D PL Plus S = 0
1110 E NZ Non-Zero Z = 0
1110 E NE Not Equal Z = 0
1111 F NC No Carry C = 0
1111 F UGE Unsigned Greater Than or
Mnemonic Definition
Equal
Flag Test Operation
(Jump if T rue)
C = 0
Architectural Overview UM018809-0611
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Note:
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CPU Control Register (CPUCTL)
Bits [1:0] of the CPU Control Register (see Table 4 on page 13) control access to the
ZNEO CPU buses through DMA bandwidth selection.
For more details about the available peripheral control and data registers, and additional
information about DMA operation, refer to the device specific Product Specification.
Table 4. CPU Control Register
Bit 7 6 5 4 3 2 1 0
Field
Reset
R/W
Address
Note: R = Read-only; R/W = Read/Write; R/W0 = Read/Write to 0.
11111111
RRRRRRR/WR/W
Reserved DMABW
FFFF_E012H
13
Bit
Position Description
[7:2] Reserved; must be zero.
[1:0] DMA Bandwidth Selection (DMABW)
The ZNEO CPU can be configured to support four levels of Direct Memory Access (DMA) Con troller bus bandwidth. Write one of the fo llowing values to DMABW[1:0] to se lect the portion of
bus bandwidth allocated to DMA operations:
00 = DMA can consume 100% of the bus bandwidth
01 = DMA is allowed one transaction for each CPU operation
10 = DMA is allowed one transaction for every two CPU operations
11 = DMA is allowed one transaction for every three CPU operations
UM018809-0611 Architectural Overview
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14
Architectural Overview UM018809-0611
Address Space
The ZNEO CPU has a unique memory architecture with a unified address space. It supports memory and I/O up to four buses:
•
Internal Non-Volatile Memory (Flash, EEPROM, EPROM, or ROM)
•
Internal RAM
•
Internal I/O Memory (internal peripherals)
•
External Memory (and/or memory-mapped peripherals)
The ZNEO CPU Fetch Unit and Execution Unit can access separate buses at the same
time. The CPU can access memories with either 8-bit or 16-bit bus widths. ZNEO CPU
uses 32-bit addressing internally. Therefore, the CPU is capable of addressing up to 4 GB
of addresses.
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15
Current ZNEO CPU products ignore address bits [31:24], providing a 24-bit address space
with 16 MB (16,777,216 bytes) of unique memory addresses. Address bits [31:24] must
be written appropriately for the addressed space to allow for possible future expansion.
The CPU also provides instructions which use 16-bit addressing. 16-bit addresses are sign
extended by the CPU to access the highest and lowest 32 KB of the available address
space.
Example: The 16-bit address FEFFH resolves to FF_FEFFH in the 24-bit address space.
Most CPU instructions also use Arithmetic and Logic Unit (ALU) registers for either
source or destination data. See the ALU Registers
The ZNEO CPU address space includes the following features:
•
Memory Map
•
Internal Nonvolatile Memory
•
Internal RAM
•
I/O Memory
•
External Memory
•
Endianness
•
Bus Widths
section on page 4.
UM018809-0611 Address Space
ZNEO® CPU Core
Internal Non-Volatile
External Memory Interface
00_0000H
FF_8000H
FF_E000H
FF_FFFFH
FF_xxxxH
Data Addresses
Jump Addresses
(Execution Unit)
(Fetch Unit)
Internal Bus (One of Three)
External Bus
00_xxxxH
00_0xxxH
FF_xxxxH
xxxxH
Device-Specific Boundary
16-Bit Address Sp ace
00_7FFFH
Internal I/O &
Control Registers
Option Bits and Vectors
Memory
External Memory Interface
Internal RAM
Reserved
User Manual
16
Memory Map
Figure 3 displays a memory map of the ZNEO CPU. It displays the location of internal
nonvolatile memory, internal RAM, and internal I/O Memory. External memory can be
accessed at addresses not occupied by internal memory or I/O.
Figure 3. ZNEO CPU Memory Map (24 Significant Address Bits)
Address Space UM018809-0611
To determine the amount of internal RAM and internal nonvolatile memory available for
Note:
Note:
the specific device and for details about the available option bits and vectors, refer to the
ZNEO product specification that is specific to your device .
Internal Nonvolatile Memory
Internal nonvolatile memory consists of executable program code, constants, and data.
The ZNEO CPU assembler provides configurable address range mnemonics (ROM and
EROM) that can be specified to locate data and program elements in nonvolatile memory.
ROM selects nonvolatile memory in the 16-bit address space, while EROM selects nonvolatile memory in the 32-bit address space. For more details about data space and segment definitions, refer to the assembler documentation.
ZNEO
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17
For each product within the ZNEO CPU family, a block of memory beginning at address
00_0000H is reserved for option bits and system vectors (RESET, trap, interrupts, System
Exceptions; etc.). Table 5 provides an example reserved memory map for a ZNEO CPU
product with 24 interrupt vectors.
Internal RAM
Internal RAM is employed for data and stacks. However, internal RAM can also contain
program code for execution. Most ZNEO CPU devices contain some internal RAM. The
base (lowest address) and top (highest address) of internal RAM are a function of the
amount of internal RAM available.
Table 5. Reserved Memory Map Example
Memory Address (Hex) Description
00_0000–00_0003 Option Bits
00_0004–00_0007 RESET Vector
00_0008
00_000C–00_000F Reserved
00_0010–00_006F Interrupt Vectors
–
00_000B System Exception Vector
To determine the amount and location of internal RAM, refer to the ZNEO product specification that is specific to your device .
UM018809-0611 Address Space
ZNEO® CPU Core
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I/O Memory
The ZNEO CPU assembler provides a configurable address range mnemonic (RAM) that
can be specified to locate data and (possibly) program elements in the RAM space
accessed using 16-bit addressing. For more details about data space and segment definitions, refer to the assembler documentation.
ZNEO CPU supports 8 KB (8,192 bytes) of internal I/O Memory space located at
addresses
addresses are reserved for control of the ZNEO CPU, the on-chip peripherals, and the I/O
ports.
For descriptions of the peripheral and I/O control registers, refer to the ZNEO product
specification that is specific to your device . Attempts to read from unavailable I/O Memory addresses return
no effect.
FF_E000H through FF_FFFFH (in the 24-bit address space). The I/O Memory
FFH. Attempts to write to unavailable I/O Memory addresses produce
The ZNEO CPU assembler provides a configurable address range mnemonic, IODATA,
that can be specified to locate an address in the reserved I/O Memory space or (if present)
external I/O configured in the adjacent 16-bit addressable memory space. For more details
about data space and segment definitions, refer to the assembler documentation.
I/O Memory Precautions
Some control registers within the I/O Memory provide read-only or write-only access.
When accessing these read-only or write-only registers, ensure that the instructions do not
attempt to read from a write-only register or, conversely, write to a read-only register.
External Memory
ZNEO CPU products support external data and address buses for connecting to additional
external memories and/or memory-mapped peripherals. The external addresses can be
used for storing program code, data, constants, stack, etc. The results of reading from or
writing to unavailable external addresses are undefined.
The ZNEO CPU assembler’s EROM and ERAM address range mnemonics can be configured to include external memory configured in 32-bit addressed memory. These mnemonics can be used to locate data and program elements in nonvolatile or RAM memory, as
required. For more information about data space and segment definitions, refer to the
assembler documentation.
Address Space UM018809-0611
Endianness
FF_0080H
FF_0081H
FF_0082H
FF_0083H
MSB
LSB
Address
of Quad
FF_0080H
FF_0081H
MSB
LSB
Address
of Word
The ZNEO CPU accesses data in Big Endian order; which means the address of a multibyte Word or Quad points to the most significant byte (MSB). Figure 4 displays the Endianness of the ZNEO CPU.
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19
Figure 4. Endianness of Words and Quads
Bus Widths
The ZNEO CPU can access 8-bit or 16-bit wide memories. The data buses of the internal
nonvolatile memory and internal RAM are 16-bits wide. The internal peripherals are a mix
UM018809-0611 Address Space
of 8-bit and 16-bit peripherals. The external memory bus can be configured as an 8-bit or
16-bit memory bus.
If a 16-bit or 32-bit operation is performed on a 16-bit wide memory, the number of memory accesses depends on the alignment of the address. If the address is even, a 16-bit operation takes one memory access and a 32-bit operation takes two memory accesses. If the
address is odd (unaligned), a 16-bit operation takes two memory accesses and a 32-bit
operation takes three memory accesses. Figure 5 displays this behavior for 16-bit and 32bit access.
ZNEO® CPU Core
MSB
LSB
FF_0080H FF_0081H
MSB
LSB
FF_0082H
FF_0081H
Aligned 16-Bit Access
Unaligned 16-Bit Access
MSB
LSB
FF_0080H FF_0081H
FF_0082H FF_0083H
MSB
LSB
FF_0081H
FF_0082H
FF_0083H
FF_0084H
Aligned 32-Bit Access
Unaligned 32-Bit Access
FF_0080H
FF_0083H
FF_0085H
FF_0080H
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Figure 5. Alignment of 16-Bit and 32-Bit Operations on 16-Bit Memories
Address Space UM018809-0611
Assembly Language Introduction
LOOP: SUB R5, R7 ;Subtract
Label
(Optional)
Instruction
Mnemonic
Destination
Operand
Source
Operand
Comment
(Optional)
Assembly language uses mnemonic symbols to represent instruction opcodes. Operands
such as register names and immediate data is represented symbolically, numerically, as
expressions, or by labels defined elsewhere in the program.
Figure 6 displays a typical assembly language statement.
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Figure 6. Example Assembly Language Statement
An assembly statement can include one or more the following elements:
Label. An optional text string used to refer to this statement elsewhere in the program. A
string is considered a label definition if it is not an assembler keyword, and it either begins
a line or is followed by a colon. The label definition identifies the address of the instruction that follows it.
Instruction Mnemonic. The mnemonic code for the desired operation.
Destination Operand. The destination location for the operation. In assembly, the desti-
nation operand is always first if both operands are specified.
Source Operand. The source location or immediate data for the operation.
Comment. An optional text field ignored by the assembler. Comments are used to
describe the flow of a program so it is easier to understand and maintain later.
Instead of instruction mnemonics, some assembly statements contain assembler directives
(also called pseudo-ops), which are not translated into object code. Directives are used to
select memory segments, allocate storage in memory, define macros, and control the
assembly process.
Example Assembly Language Source
An assembly language program is written in a plain text file called as source file, which
contains a sequence of assembly language statements and directives.
Below is an example of an assembly source file:
SEGMENT NEAR_TEXT ; Directive to place the following statements
UM018809-0611 Assembly Language Introduction
ZNEO® CPU Core
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22
; in data (RAM space) memory
Str_Data: ; Make Str_Data label equal to current addr.
DB "NEVAR" ; Directive to allocate and initialize data
; bytes
Str_Length EQU $ - Str_Data ; Equate Str_Length to current
assembly
; address ("$") minus Str_Data address.
Blank_Data: ; Allocate an uninitialized data block
DS Str_Length ; that is the same size as the Str_Data block.
SEGMENT CODE ; Directive to put the following statements in
; instruction (ROM space) memory
REVERSE: ; Routine to reverse a block of data
LD R8, #Str_Data ; Load R8 with 1st address in Str_Data block
LD R12, #Blank_Data+Str_Length ;Next addr. after Blank_Data
LOOP: ; Start of loop
LD.UB R5,(R8++) ; Load byte pointed to by R8 into R5 LSB
; Increment R8 after load.
LD.B (--R12),R5 ; Decrement R12, then
; Load byte pointed to by R12 with R5 LSB
CP R12, #Blank_Data ; Did we write all the bytes?
JP NZ,LOOP ; Repeat until Blank_Data block contains
; reversed copy of Str_Data bytes
For details about assembly instructions, see the Instruction Set Reference chapter on
page 65. For details about operand addressing and data sizes, see the Operand Addressing
chapter on page 27.
For information about how program flow can be interrupted, see the Interrupts
chapter on
page 41, System Exceptions on page 49, and Software Traps on page 53.
For details about assembly language syntax, expressions, directives, and using the assem-
bler, refer to the Zilog Developer Studio II – ZNEO User Manual (UM0171)
.
ZNEO CPU Instruction Classes
ZNEO CPU instructions can be divided functionally into the following groups:
•
Arithmetic
•
Logical
•
Bit Manipulation
•
Rotate and Shift
Assembly Language Introduction UM018809-0611
®
•
Load
•
CPU Control
•
Program Control
ZNEO
CPU Core
User Manual
Tables 6 through 12 list the instructions for each of the above groups and the number of
operands required for each instruction. Some instructions appear in more than one table as
these instructions can be considered members of more than one category. The abbreviations dst and src refer to destination and source operands, respectively.
Table 6. Arithmetic Instructions
Mnemonic Operands Instruction Page
ADC dst, src Add with Carry 68
ADD dst, src Add 71
CP dst, src Compare 86
CPC dst, src Compare with Carry 89
CPCZ dst Compare to Zero with Carry 92
CPZ dst Compare to Zero 94
DEC dst Decrement 96
INC dst Increment 108
MUL dst, src Multiply (32 bit) 125
NEG dst Negate 127
SBC dst, src Subtract with Carry 149
SDIV dst, src Signed Divide (32 bit) 152
SMUL dst, src Signed Multiply (64 bit) 158
SUB dst, src Subtract 169
UDIV dst, src Unsigned Divide (32 bit) 180
UDIV64 dst, src Unsigned Divide (64 bit) 182
UMUL dst, src Unsigned Multiply (64 bit) 184
23
Table 7. Logical Instructions
Mnemonic Operands Instruction Page
AND dst, src Logical AND 74
COM dst Complement 84
OR dst, src Logical OR 131
XOR dst, src Logical Exclusive OR 188
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Table 8. Bit Manipulation Instructions
Mnemonic Operands Instruction Page
TCM dst, src Test Complement Under Mask 172
TM dst, src Test Under Mask 175
Table 9. Rotate and Shift Instructions
Mnemonic Operands Instruction Page
RL dst Rotate Left 147
SLL dst, src Shift Left Logical 154
SLLX dst, src Shift Left Logical, Extended 156
SRA dst, src Shift Right Arithmetic 160
SRAX dst, src Shift Right Arithmetic,
Extended
SRL dst, src Shift Right Logical 164
SRLX dst, src Shift Right Logical, Extended 166
162
Table 10. Load Ins truct io n s
Mnemonic Operands Instruction Page
CLR dst Clear Value 82
EXT dst, src Extend Value 103
LD dst, src Load 115
LD cc dst Load Condition Code 120
LDES dst Load and Extend Sign Flag 121
LEA dst Load Effective Address 122
LINK src Link Frame Pointer 124
POP dst Pop 134
POPF dst Pop Flags 136
POPM mask Pop Multiple 137
PUSH src Push 140
PUSHF src Push Flags 142
PUSHM mask Push Multiple 143
UNLINK Unlink Frame Pointer 186
Assembly Language Introduction UM018809-0611
Table 11. CPU Control Instructions
Mnemonic Operands Instruction Page
ATM — Atomic Operation Modifier 77
DI — Disable Interrupts 98
EI — Enable Interrupts 102
HALT — Halt Mode 105
NOFLAGS — No Flags Modifier 129
NOP — No Operation 130
STOP — Stop Mode 168
Table 12. Program Control Instructions
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Mnemonic Operands Instruction Page
BRK — On-Chip Debugger Break 78
CALL dst Call 79
CALLA dst Call Absolute 81
DJNZ dst, src Decrement, Jump if Nonzero 100
IRET — Interrupt Return 110
JP dst Jump 112
JPA dst Jump Absolute 113
JP cc dst Jump Conditional 114
RET — Return from Call 146
TRAP vector Software Trap 178
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Assembly Language Introduction UM018809-0611
Operand Addressing
Most ZNEO CPU instructions operate on one or two registers, or one register and one
memory address. Operands following the instruction specify which register or memory
address to use.
Example. The assembly language statement below loads one 32-bit register with data
from another:
LD R7, R8
The first operand almost always specifies the destination, and the second operand (if any)
specifies the source for the operation. In this example, the R7 register is loaded with the
value from R8 register.
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There are four kinds of operand addressing, each of which is described in this chapter:
•
Immediate Data, in which the value specified by the operand is used for operation.
•
Register Addressing, in which the specified 32-bit register is used for operation.
•
Direct Memory Addressing, in which the value specified by the operand addresses a
memory location that is used for the operation. This section introduces the following
topics:
– Memory Data Size
– Resizing Data
These topics also apply to Register-Indirect memory addressing.
•
Register-Indirect Memory Addressing, in which the specified 32-bit register and
optional offset point to a memory location that is used for the operation. This section
covers the following topics specific to register-indirect addressing:
– Loading an Effective Address
– Using the Program Counter as a Base Address
– Memory Address Decrement and Increment
– Using the Stack Pointer (R15)
– Using the Frame Pointer (R14)
This chapter also describes Bit Manipulation
page 39).
UM018809-0611 Operand Addressing
(see page 37) and Jump Addressing (see
ZNEO® CPU Core
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Immediate Data
An Immediate Data operand specifies a source value to be used directly by the instruction.
Example. The assembly language statement below loads ALU Register R7 with the value
42H:
LD R7, #42H
The hash mark prefix (#) on the second (source) operand indicates to the assembler that
the value is Immediate Data, so this example loads the R7 register with the value
Immediate data is stored as part of the instruction opcode. Depending on the opcode, an
immediate data value can be of the same size as the destination (8, 16 or 32 bits), or it may
contain fewer bits to shorten the opcode.
A destination-sized immediate operand (imm syntax symbol) is used directly by the operation. A shorter immediate operand must be considered signed (simm) or unsigned (uimm).
A signed immediate value is sign-extended to the destination size before it is used. An
unsigned immediate operand is ze ro-e x tended to the destination size before it is used. For
more information, see the Memory Data Size
section on page 31.
section on page 30 and the Resizing Data
42H.
An immediate value does not address data memory, so it cannot be used as the destination
operand. Immediate data is read by the Fetch Unit, so it is not affected by the constraints
described in the I/O Memory Precautions
Register Addressing
A Register operand specifies a 32-bit Arithmetic and Logic Unit (ALU) register to be used
with the instruction. ALU registers are the CPU’s high-speed work space, much faster than
ordinary internal or external memory. There are 16 ALU registers, named R0 to R15. See
the ALU Registers
As mentioned previously , the following assembly language statement loads the destination
register, R7, with data from the source register, R8:
LD R7, R8
Depending on the instruction, a register name can be used for either the source or destination operand, or both. Each register is 32-bits (four bytes) wide, and all 32 bits of a register
are used unless the register’s value is loaded into an 8-bit or 16-bit memory location.
The ZNEO CPU assembler recognizes FP as a synonym for R14 and SP as a synonym for
R15. For details, see the Using the Frame Pointer (R14)
the Stack Pointer (R15) section on page 36. The UDIV64 instruction uses a 64-bit RRd
register pair operand that employs two 32-bit ALU registers. See the UDIV64
page 182 for details.
section on page 18.
section on page 4 for details.
section on page 37 and the Using
section on
Operand Addressing UM018809-0611
Direct Memory Addressing
Note:
A Direct Memory operand specifies a memory address to be used by the instruction.
Example. The following assembly language statement loads ALU register R7 with the
value in memory address
LD.SB R7, B002H
Any data operand which does not contain an immediate value (#n) or register name (Rn) is
assumed to be a memory address. Depending on the instruction, a direct memory address
can be used in either the source or destination operand, but a destination’s effective
address must be a writable memory or I/O location.
ZNEO CPU uses 32-bit memory addresses, but it includes instruction opcodes which
accept 16-bit addresses. A 16-bit address operand in object code is sign-extended by the
CPU (see the Resizing Data
feature splits the 16-bit address range between the highest and lowest 32K blocks of the 16
GB address space. Table 13 provides the 16-bit address ranges for object code.
0000_B002H:
section on page 31) to create the effective address used. This
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Table 13. 16-Bit Addressing (Object Code Only)
16-Bit Address Range 32-Bit Effective Addresses Memory Space
0000H to 7FFFH 0000_000H to 0000_7FFFH ROM
8000H to FFFFH FFFF_8000H to FFFF_FFFFH RAM and I/O
Effective addresses are expressed as 32-bit values. Current devices ignore address bits
[31:24], providing a 24-bit address space.
Internal RAM and I/O memory falls in the range
FF_8000H to FF_FFFFH on devices that ignore address bits [31:24]), so 16-bit address-
(
FFFF_8000H to FFFF_FFFFH
ing provides efficient access to internal RAM and I/O memory.
The ZNEO CPU assembler does not automatically use 16-bit addressing if an unmodified
16-bit address is specified, as in the previous example. In this case the assembler selects
16-bit or 32-bit addressing to ensure the address is used as specified.
However, you can append address range mnemonics to specify whether the assembler
should use 16-bit or 32-bit addressing. The RAM, IODAT A, and ROM mnemonics tell the
assembler to use 16-bit addressing, as shown in the following example statements:
LD.SB R7, B002H:RAM ; Effective address is FFFF_B002H
LD.SB R7, E002H:IODATA ; Effective address is FFFF_E002H
LD.SB R7, 3002H:ROM ; Effective address is 0000_3002H
UM018809-0611 Operand Addressing
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The ERAM and EROM address space suffixes tell the assembler to use 32-bit addressing,
as shown in the following statements. A full 32-bit address can access external memory or
memory-mapped I/O anywhere in the 4 GB address space.
LD.SB R7, B002H:EROM ; Effective address is 0000_B002H
LD.SB R7, B002H:ERAM ; Effective address is 0000_B002H
The assembler uses memory space mnemonics only to select an appropriate address size
(16 or 32 bit). The assembler does not check an absolute address to make sure it actually
resides in the specified space, but the assembler generates a warning if a label is used in a
space other than the space in which it was declared. See the Address Space
page 15 for more information about memory spaces.
Memory Data Size
The ZNEO CPU’s default data size is 32 bits (Quad). Any instruction that addresses an 8bit or 16-bit value in memory must use a mnemonic suffix to specify the data size. The
previous examples use the ‘.B’ suffix to tell the CPU that only 8 bits (one byte) must be
loaded. The following data size suffixes can be used (using LD as an example):
section on
LD (No Suffix). Read or write 32 bits (four bytes). In a read, for example, the byte at the
specified effective address loads into bits [31:24] of the destination register . The three subsequent memory bytes load into bits [23:16], [15:8], and [7:0] of the destination register,
in that order.
LD.W. Read or write 16 bits (two bytes). In an unsigned read, for example, bits [31:16] of
the destination register are cleared, the byte at the specified effective address loads into
bits [15:8] of the register, and the byte at the next (+1) address loads into bits [7:0] of the
register.
LD.B. Read or write 8 bits (one byte). In an unsigned read, for example, bits [31:8] of the
destination register are cleared, and the byte at the specified effective address loads into
bits [7:0] of the register.
Figure 7
on page 31 displays the mapping of register bytes to memory bytes for different
data sizes. When 8-bit or 16-bit memory is read or written, the high-order bits are filled or
truncated as described in the Resizing Data
section on page 31.
Operand Addressing UM018809-0611
®
ALU Registers Memory Space
7:015:823:1631:24Bits:
FFFF_7005H
(Effective Address)
FFFF_7006H
FFFF_7007H
FFFF_7004H
7:015:823:1631:24Bits:
FFFF_7009H
(Effective Address)FFFF_7008H
7:015:823:1631:24Bits:
FFFF_700AH (Effective Address)
8-Bit
16-Bit
32-Bit
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Figure 7. Mapping of Register to Memory Bytes
Resizing Data
When an 8-bit or 16-bit memory location is written, the value from the source register is
truncated, so only the least-significant 8 or 16 bits of the register value are written, respectively. The source register itself is not changed. When an 8-bit or 16-bit memory location
UM018809-0611 Operand Addressing
is read, the value from memory must be extended to a full 32 bits before it is used or stored
in a register.
One of the following two kinds of data extension must be used:
Unsigned (Zero) Extension. The upper bits of the new 32-bit value are filled with zeroes.
Unsigned extension is invoked by including a ‘U’ in the mnemonic suffix. For example,
the following instruction loads the byte at
with zeroes:
LD.UB R10,7002H
Signed Extension.
The upper bits of the new 32-bit value are filled with ones or zeroes,
FFFF_7002H into R10[7:0] and fills R10[31:8]
depending on the source value’s most-significant (sign) bit, to preserve the sign of the
loaded value. Signed extension is invoked by including an ‘S’ in the mnemonic suffix.
For example, the following instruction loads the byte at address
bits R10[7:0] and copies bit 7 of that byte into each bit of R10[31:8].
FFFF_7002H into register
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LD.SB R10,7002H
By default, the ZNEO CPU assembler uses an unsigned instruction opcode if the extension type is not specified for an 8- or 16-bit memory read. The EXT instruction is provided
for extending 8-bit or 16-bit values contained in a register.
The CPU uses ordinary two’s complement notation to represent signed values. In this
notation, the negative of a number is its binary complement, plus one. The most significant bit (msb) represents the sign—a one in the msb indicates that the number is negative.
Y ou can use signed or unsigned instructions with a particular memory location. Ensure the
correct usage of extension type whenever a memory location is read.
Table 14 lists data sizes, suffixes, and ranges for signed and unsigned values.
Table 14. Data Sizes for Memory Read
Signed or
Size Bits
Byte 8 Unsigned .UB 0 to FF 0 to 255
Word 16 Unsigned .UW 0 to FFFF 0 to 65,535
Quad 32 Unsigned (none) 0 to FFFF_FFFF 0 to 4,294,967,295
Unsigned Mnemonic Suffix Range (Hex) Range (Decimal)
Signed .SB 80 to FF,
00 to 7F
Signed .SW 8000 to FFFF,
0000 to 7FFF
Signed (none) 8000_0000 to
FFFF_FFFF,
0000_0000 to
7FFF_FFFF
–128 to –1,
0 to 127
–32,768 to –1,
0 to 32,767
–2,147,483,648 to –1,
0 to 2,147,483,647
Register-Indirect Memory Addressing
A register-indirect operand uses an address contained in an ALU register, plus an optional
offset, to address data in a memory location.
Example. The following assembly-language statement loads the destination register, R10,
with data from a memory byte pointed to by register R12, plus an offset.
LD.UB R10, 4(R12)
Figure 8 displays this example. It reads a base address value from R12, adds the signed
offset, 4, to create an effective address in memory, and then loads register R10 with the
value at that address. The parentheses indicate a register-indirect operand.
Operand Addressing UM018809-0611
®
LD.UB R10,4(R12)
42H
FFFF_7006H
R12FFFF_7002H
4 + FFFF_7002H
32-Bit ALU Registers
Memory Space
Value Loaded:
42H
—
—
R11—
R13—
0000_0042H R10
(Effective Address)
Note:
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Depending on the instruction, register-indirect addressing can be used for either the source
or destination operand, but a destination’s effective address must be a writable memory or
I/O location. The range allowed for the signed offset depends on the instruction used. For
the LD, CLR, CPZ, CPCZ, INC, and DEC instructions, the register-indirect offset range is
–4,096 to +4,095. For other instructions that accept an indirect offset, the range is –8,192
to +8,191.
For allowed JP and CALL offsets, see the Jump Addressing section on page 39.
Several register-indirect instructions have alternate opcodes that do not accept an offset,
and therefore use fewer opcode words. When the offset is omitted in a register-indirect
operand, the ZNEO CPU uses the shorter instruction opcode if one is available.
Loading an Effective Address
The following assembly language statement is a an example of how you can initialize a
register with a base address:
LD R6, #FFFFB002H
Addresses in the range FFFF_8000H to FFFF_FFFFH are common because that is where
I/O memory and internal RAM are addressed, but using a 32-bit LD to initialize a register
Figure 8. Register-Indirect Memory Addressing Example
UM018809-0611 Operand Addressing
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is not necessary. The ZNEO® CPU assembler automatically uses a shorter LD opcode if
possible.
The LEA mnemonic is provided as an alternative to the immediate LD instruction.
Example. The following statement performs the same initialization as in the previous
example:
LEA R6, FFFFB002H
LEA and LD accept the memory space notation described in Direct Memory Addressing
on page 29, so the following statements are equivalent to the two previous examples:
LEA R6,B002H:RAM ; Load address of FFFF_B002H
LEA R7,B002H:RAM ; Load address FFFF_B002H
Once a register is initialized with a base address, the LEA instruction can be used to generate a new effective address based on that register value.
Example. If the value in register R8 is FFFF_7002H, the following assembly language
statement loads register R7 with the value
LEA R7, 4(R8)
FFFF_7006H:
This LEA operation loads the effective address indicated by the source operand, while a
similar LD instruction would load the contents of the address. The allowed offset range for
a register-based LEA operand is –8,192 to +8,191.
Using the Program Counter as a Base Address
Some LD and LEA instructions use the Program Counter (PC) as the base address for indirect addressing with an offset. Normally these instructions are used to access a data block
declared in line with the program.
For example, the following statements declare a variable and load it into register R7:
DATA: DB 00H, 00H, 00H, 42H
LD R7, DATA(PC)
The ZNEO CPU assembler automatically calculates the correct relative offset to access
the labeled address using PC as a base address. If a constant (non-label) offset is used with
PC in assembly language, the assembler measures the offset from the start of the current
instruction. The actual offset used in object code is a signed 14-bit value measured from
the end of the current instruction, but the assembler makes this adjustment automatically.
A program can use LEA to load the actual PC contents into a register. The following statements both load the PC value (the next instruction’s address) into register R5:
LEA R5, NEXT(PC)
NEXT: LEA R5, 4(PC)
A PC-based address cannot be used for the destination operand. The allowed offset range
for a PC-based LD or LEA operand is –8,192 to +8,191.
Operand Addressing UM018809-0611
If the required offset for a PC-based instruction exceeds the allowed range, the assembler
Note:
may silently convert the instruction to use the 32-bit immediate addressing mode.
Memory Address Decrement and Increment
In certain circumstances, a register-indirect LD operation can automatically decrement or
increment the base address register. A decrement is selected by adding a ‘--’ (doubleminus) prefix to the destination register name. The decrement always takes place before
the load is performed. This is called predecrement.
Example. The following statement decrements the base address in register R5, then loads
the memory location pointed to by R5 with the 32-bit contents of R6:
LD (--R5), R6
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Predecrement is supported only for destination operands. An LD store using predecrement
is similar to a PUSH, except the LD mnemonic allows a value in any register to be used as
the base address (See the Using the Stack Pointer (R15)
section on page 36 for more infor-
mation).
An increment is selected by adding a ‘++’ (double-plus) suffix to the source or destination
register name. The increment always takes place after the load is performed. This is called
postincrement.
Example. The following statement loads the memory location pointed to by register R5
with the contents of R6, then increments the base address in R5:
LD (R5++), R6
Postincrement can also be used for source operands. For example, the following statement
loads register R6 with the contents of the memory location pointed to by R5, then increments the base address in R5:
LD R6, (R5++)
An LD read using postincrement is similar to a POP, except the LD mnemonic allows a
value in any register to be used as the base address. The predecrement and postincrement
features can be used to implement high-level stack data structures independent of the
Stack Pointer. To help ensure that the next base address is valid, the increment or decrement amount varies with the size of the LD operation.
This is illustrated in the following example statements:
LD.B (--R5), R6 ; Decrement R5 by 1 and store 1 byte
LD.W (--R5), R6 ; Decrement R5 by 2 and store 2 bytes
LD (--R5), R6 ; Decrement R5 by 4 and store 4 bytes
Predecrement or postincrement operands cannot include an offset.
UM018809-0611 Operand Addressing
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Using the Stack Pointer (R15)
Stack operations are a special kind of register-indirect memory access. The ZNEO CPU
system stack is implemented using ALU Register R15 as the Stack Pointer (SP). R15 can
be addressed like any register, but because of its Stack Pointer role it would be awkward to
use for any other purpose. The ZNEO CPU assembler recognizes SP as a synonym for
R15.
The system program startup routine initializes R15 to point to the highest address in internal RAM, plus 1. Subsequent PUSH, PUSHM, CALL, and LINK instructions; interrupts,
system exceptions, and traps all decrement SP before they store data on the stack. POP,
POPM, RET , UNLINK, and IRET instructions all increment SP to release stack space as it
is no longer needed. A program can also allocate or release stack space by changing the
register R15 (SP) value directly.
A system exception is provided to help keep the stack from overwriting other data; see the
Stack Overflow
POPM instructions to store and retrieve data from the stack.
section on page 50. Software can use the PUSH, POP, PUSHM, and
PUSH decrements SP and stores the source value onto the stack. POP loads the last value
on the stack into the specified register and increments SP. The assembler uses predecrement and postincrement LD opcodes to implement most PUSH and POP instructions.
PUSH and POP can be used with 8-, 16-, or 32-bit data sizes. 8-bit and 16-bit POP instructions can be either Unsigned or Signed.
When a 16-bit or 32-bit value is pushed onto the stack, the low-order bytes are pushed first
to store the value in the ZNEO CPU’s normal big-endian fashion.
Example
A 16-bit value is stored with bits [7:0] in the value’ s higher -addressed byte, and bits [15:8]
in the value’s base address byte.
If the stack is located on a 16-bit bus, an assembly language program might improve stack
performance by maintaining an even SP value—for example, by avoiding the single-byte
PUSH.B and POP.B instructions. This may require some effort, especially if the program
includes compiled C routines or any other code that does not preserve stack alignment.
The PUSHM and POPM instructions push or pop multiple registers with a single instruction. For example, the following statements push R0, R5, R6, R7 and R13 onto the stack
(in reverse numerical order), and then pop the same registers (in numerical order, so
pushes and pops remain symmetrical):
PUSHM <R0, R5-R7, R13>
POPM <R0, R5-R7, R13>
Operand Addressing UM018809-0611
The PUSHM and POPM instructions always push or pop all 32 bits of each register. The
ZNEO CPU assembler uses the PUSHMHI, PUSHMLO, POPMLO, and POPMHI
opcodes to implement PUSHM and POPM.
Using the Frame Pointer (R14)
Subroutines often use the stack for temporary variable space. For example, a CALL
sequence begins by pushing arguments onto the stack before calling the subroutine. When
the subroutine starts, it stores a copy of SP in another register called the Frame Pointer
(FP) and decrements SP to create stack space for local variables. When the subroutine is
finished, it copies FP back into SP and returns. Finally, the calling routine deallocates the
stack space it used for arguments.
The ZNEO CPU provides the LINK and UNLINK instructions to help program this
sequence. These instructions use register R14 as the FP register. The ZNEO CPU assembler recognizes FP as a synonym for R14.
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LINK is used at the beginning of a subroutine to copy the SP contents to FP and d ecrement
SP as needed. UNLINK copies FP back to SP, releasing the allocated space. LINK pushes
R14 on the stack before changing it, and UNLINK pops R14 after it is done, so routines
not using LINK or UNLINK can use R14 normally.
While the subroutine executes, it can access its arguments and variables using registerindirect addressing with the FP register. For constant (non-label) offsets in the range –32
to +31, the assembler uses special opcodes that make FP-based accesses more efficient.
Bit Manipulation
The ZNEO CPU does not provide any special instructions to address only one bit in memory, but individual bits are easily manipulated using masked logical instructions.
The following sections introduce the most basic bit manipulation techniques. The instructions used here are AND, OR, TM, and TCM. Other useful bit, logic and shift operations
are listed by groups in the ZNEO CPU Instruction Classes
Clearing Bits (Masked AND)
The logical AND instruction (discussed on page 74) stores a 1 bit only if the corresponding bit is set in both the source and destination. In effect, if the source (mask) bit is 0, the
destination bit is cleared. If the mask bit is 1, the destination bit is not changed.
section on page 22.
Example. The following assembly language statements initialize register R15 and then
clear bit 5 of that register:
LD R15, #FFFFFF70H ; LSB = 0111_0000B
AND R15, #FFFFFFDFH ; Clear R15 bit 5
UM018809-0611 Operand Addressing
ZNEO® CPU Core
0 1 1 1 0 0 0 0
R15[7:0] = 70H
1 1 0 1 1 1 1 1
MASK = FFFF_FFDFH
0 1 0 1 0 0 0 0
R15[7:0] = 50H
Bit
5
Bit
32
AND R15, #FFFFFFDFH ; Clear Bit 5 of Register 15
1 1 1 1 1 1 1 11 1 1 1 1 1 1 11 1 1 1 1 1 1 1
Bit
0
1 1 1 1 1 1 1 11 1 1 1 1 1 1 11 1 1 1 1 1 1 1
1 1 1 1 1 1 1 11 1 1 1 1 1 1 11 1 1 1 1 1 1 1
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This leaves the value FFFF_FF50H in register R15. Figure 9 displays how this example
clears only one bit of register R15.
Figure 9. Masked Logic Example: Clearing a Bit
Setting Bits (Masked OR)
The logical OR instruction stores a 0 bit only if the corresponding bit is clear in both the
source and destination. In effect, if the source (mask) bit is 1, the destination bit is set. If
the mask bit is 0, the destination bit is not changed.
Example. The following assembly language statements initialize register R15 and then set
bits [2,1] of that register:
LD R15, #00000070H ; LSB = 0111_0000B
OR R15, #00000006H ; Set R15 bits 1 and 2
This leaves the value 0000_0076H (LSB = 0111_0110B) in register R15.
Testing Bits (TM and TCM)
The TM instruction performs an internal AND to test mask-selected bits in the destination
register, but does not changes the source or destination register contents. Instead, TM sets
the
Z flag if the tested destination bits are all 0.
To select a bit to test, set the corresponding bit in the source (mask) operand as given in
the example below.
Example. The following assembly language statements initialize register R15 and then
test bit 2 of that register:
Operand Addressing UM018809-0611
LD R15, #00000070H ; LSB = 0111_0000B
TM R15, #00000004H ; Test bit 2
JP Z, BIT_IS_CLEAR
This leaves R15 unchanged, but sets the Z flag as R15[2] is clear.
Note:
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The TCM instruction (Test Complement under Mask, discussed on page 172
ments the destination value before ANDing it to the mask. In effect, TCM is identical to
TM except it sets the
Example . The following assembly language statements initialize register R15 and then
test bits [2,1] of that register:
LD R15, #00000070H ; LSB = 0111_0000B
TCM R15, #00000006H ; Test bits 1 and 2
JP Z, BITS_ARE_ONES
As a result, R15 remains unchanged but clears the Z flag because neither bit R15[2,1] is 1.
Jump Addressing
The ZNEO CPU jump instructions (JP and CALL), are used to alter the program flow.
These instructions alter the Program Counter, which indicates the next instruction to be
fetched. A few considerations are listed below.
•
All instructions must begin on an even address.
•
Instruction fetches bypass the internal I/O space. The result of an instruction fetch is
not defined in the range
devices that ignore address bits [31:24]).
) comple-
Z flag if the tested destination bits are all 1.
FFFF_E000H–FFFF_FFFFH (FF_E000H–FF_FFFFH on
•
A small device-specific address block starting at 0000_0000H is reserved for CPU
option bits and interrupt, trap, or exception vectors.
For details about option bits and vectors, refer to the ZNEO product specification that is
specific to your device .
Assembly language stat ements us e a label, expression, or numeric value to indicate the 32bit jump destination. The ZNEO CPU assembler analyzes the address and determines the
best address mode to use in the assembled object code.
In object code, following two jump address modes are available:
Direct Address. The JP, JP cc, or CALL opcode includ es four operand bytes containing
the 32-bit jump destination address. The destination address is written directly to the Program Counter to indicate the next instruction. Bit [0] of the operand is ignored.
UM018809-0611 Operand Addressing
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Relative Address. The JP, JP cc, or CALL opcode includes a signed relative offset field
of 8, 12, 16, or 24 bits, which is added to the Program Counter’s contents. Table 15 provides the relative address operand ranges. For jumps within the same module, the assembler uses the most efficient offset size. For relative jumps across modules, the assembler
uses a default offset size that can be configured at assembly time.
Table 15. Relative Jump Offset Ranges
Operand Bits Offset Range
8 –128 to +127
12 –2,048 to +2,047
16 –32,768 to +32,767
24 –8,388,608 to +8,388,607
Operand Addressing UM018809-0611
Interrupt s
Note:
Note:
Peripherals use an interrupt request (IRQ) signal to get the CPU’s attention when it needs
to perform some action, such as moving peripheral data or exchanging status and control
information.
There are two ways to handle interrupt requests:
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Vectored Interrupts
interrupt service routine (ISR). The ISR must end with an Interrupt Return (IRET) instruction.
Polled Interrupts
the software tests the device’s interrupt request bits periodically. If action is required, the
software uses CALL and RET to invoke the appropriate service routine.
Interrupts are generated by internal peripherals, external devices (through the port pins) or
software. The Interrupt Controller prioritizes and handles individual interrupt requests
before passing them to the ZNEO CPU. The interrupt sources and trigger conditions are
device dependent.
To determine available interrupt sources (internal and external), triggering edge options,
and exact programming details, refer to the ZNEO Product Specification that is specific to
your device.
Vectored Interrupts
Each ZNEO CPU interrupt is assigned an interrupt vector that points to the appropriate
service routine for that interrupt. Vectors are stored in a reserved block of 4-byte memory
quads in the nonvolatile memory space. Each interrupt vector is a 32-bit pointer (service
routine address) stored in a memory quad.
. Asserting the IRQ signal forces the CPU to execute the corresponding
. Vectored interrupts are disabled (globally or only for the device), and
For interrupt vector locations, refer to the ZNEO Product Specification that is specific to
your device.
Interrupt Enable and Disable
Vectored interrupts are globally enabled and disabled by executing the Enable Interrupts
(EI) and Disable Interrupts (DI) instructions, respectively. These instructions affect the
UM018809-0611 Interrupts
ZNEO® CPU Core
Note:
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Master Interrupt Enable flag (IRQE) in the FLAGS register in I/O memory . It is possible to
enable or disable interrupts by writing to the Flags Register directly. You can enable or
disable the individual interrupts using control registers in the Interrupt Controller.
For information about the Interrupt Controller, refer to the ZNEO Product Specification
that is specific to your device.
Interrupt Processing
When an enabled interrupt occurs, the ZNEO CPU performs the following tasks to pass
control to the corresponding interrupt service routine:
1. Push the Flags Register, including the Master Interrupt Enable bit (
IRQE), onto the
stack.
2. Push
00H (so SP alignment is not changed).
3. Push PC[7:0] (Program Counter bits [7:0]) onto the stack.
4. Copy the state of the
IRQE flag into the Chained Interrupt Enable flag (CIRQE).
5. Push PC[15:8] onto the stack.
6. Push PC[23:16] onto the stack.
7. Push PC[31:24] onto the stack.
8. Disable interrupts (clear
IRQE).
9. Fetch interrupt vector bits [31:24] into PC[31:24].
10. Fetch interrupt vector bits [23:16] into PC[23:16].
11. Fetch interrupt vector bits [15:8] into PC[15:8].
12. Fetch interrupt vector bits [7:0] into PC[7:0].
13. Begin execution at the new Program Counter address specified by the Interrupt Vector.
Figure 10 displays the effect of vectored interrupts on the Stack Pointer and the contents of
the stack.
Interrupts UM018809-0611
ZNEO
Top of StackStack Pointer
FLAGS[7:0]
PC[15:8]
PC[7:0]
Stack Pointer
Stack Pointer and Stack
Before an Interrupt
Stack Pointer and Stack
After an Interrupt
PC[23:16]
PC[31:24]
00H
—
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Figure 10. Effects of an Interrupt on the Stack
Example. Figure 11 displays an example of addresses used during an interrupt operation.
In this example, the interrupt vector quad address is
vector address contained by that quad (
0023_4567H) is loaded into the Program Counter .
The execution of the interrupt service routine begins at
0000_0014H. The 32-bit interrupt
0023_4567H.
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Memory
Interrupt Vector Quad
Interrupt
Vector
Table
Interrupt Service
Routine First
Vector[23:16] = 23H
Vector[15:8] = 45H
0023_4567H
0000_0014H
0000_0015H
Vector[7:0] = 67H
0000_0016H
0000_0017H
Vector[31:24] = 00H
Quad Base Address
Address
Instruction
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Interrupts UM018809-0611
Figure 11. Interrupt Vectoring Example
Returning From a Vectored Interrupt
If no interrupts are pending or the Chained Interrupt Enable Flag (CIRQE) is 0, executing
the Interrupt Return (IRET) instruction at the end of an interrupt service routine results in
the following operations:
1. Pop PC[31:24] from the stack.
2. Pop PC[23:16] from the stack.
3. Pop PC[15:8] from the stack.
4. Pop PC[7:0] from the stack.
5. Increment SP by 1 (so SP alignment is not changed).
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6. Pop the Flags register, including the Master Interrupt Enable bit (IRQE), from the
stack. This returns the
IRQE bit to its state before the interrupt occurred (assuming the
contents of the stack are not altered by the interrupt service routine).
7. Begin execution at the new Program Counter address.
If the
CIRQE flag is 1 and one or more vectored interrupts are pending, executing the IRET
instruction results in the following operation:
1. Disable interrupts (clear the IRQE flag).
2. Load the Program Counter directly from the vector table quad for the highest-priority
pending interrupt.
3. Begin execution at the new Program Counter address.
45
This chained-interrupt optimization omits unneeded pop and push cycles when program
control passes directly from one interrupt service routine to another.
Whenever a vectored interrupt or system exception occurs, the previous state of the
flag is copied to the
CIRQE flag after the Flags Register is pushed onto the stack. As a
result, interrupt chaining is disabled if interrupts are globally disabled (
nonmaskable interrupt or system exception occurs.
Programs that branch to interrupt service routines directly—for example, by executing a
PUSHF followed by a CALL—must set or clear the
terrupt chaining, respectively. Otherwise, the IRET that ends the routine might chain to
another interrupt unexpectedly.
The following assembly language statements clear the
LD.UB R5, FLAGS ;Read the current FLAGS value
AND R5, #11111101B ;Clear bit 1 (CIRQE)
LD.B FLAGS, R5 ;Write back with CIRQE flag cleared
Interrupt Priority and Nesting
The Interrupt Controller assigns a specific priority to each IRQ signal. When two IRQ signals are asserted at the same time, the higher priority interrupt service routine is executed
first. An interrupt service routine enables the vectored interrupt nesting, which allows
higher priority requests to interrupt the request being serviced.
IRQE
IRQE=0) when a
CIRQE flag to enable or disable in-
CIRQE flag:
Observe the following steps during the interrupt service routine to enable vectored interrupt nesting:
1. Push the current value of the Interrupt Enable Registers in I/O memory onto the stack.
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2. Configure the Interrupt Enable Registers to disable lower priority interrupts.
3. Execute an EI instruction to enable vectored interrupts.
4. Proceed with the interrupt service routine processing.
5. After processing is complete, execute a DI instruction to disable interrupts.
6. Restore the Interrupt Enable Registers values from the stack.
7. Execute an IRET instruction to return from the interrupt service routine.
For information about Interrupt Priority and Interrupt Enable Registers, refer to the ZNEO
Product Specification that is specific to your device.
Software Interrupt Generation
Software can generate a vectored interrupt request directly by writing to the Interrupt
Request Registers in I/O memory. The Interrupt Controller and CPU handle software
interrupts in the same manner as hardware-generated interrupt requests.
To generate a Software Interrupt, write 1 to the appropriate interrupt request bit in the
selected Interrupt Request Register.
Example. The following instruction writes 1 to Bit 5 of Interrupt Request Register 1
(IRQ1SET):
LD R5, #00100000B ; Load mask for bit 5
OR.B IRQ1SET:IODATA, R5 ; Set interrupt request bit 5
If an interrupt at Bit 5 is enabled and there are no higher priority interrupt requests pending, program control gets transferred to the interrupt service routine specified by the corresponding interrupt vector.
For more information about the Interrupt Controller and Interrupt Request registers, refer
to the ZNEO Product Specification that is specific to your device.
Polled Interrupts
The ZNEO CPU supports polled interrupt processing. Polled interrupts are used when it is
not desirable to enable vectored interrupts for one or more devices. If interrupts are disabled for a device (or globally), no action is taken after the device asserts its IRQ signal
unless software explicitly polls (tests) the corresponding interrupt bit.
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Polling is performed in a frequently-executed section of code, such as the main loop of an
interactive program. For processor-intensive applications, there can be a trade-off between
the responsiveness of polled interrupts and the overhead of frequent polling.
To poll the bits of interest in an Interrupt Request register, use the Test Under Mask (TM)
or similar bit test instruction. If the bit is 1, perform a software call or jump to the interrupt
service routine. The interrupt service routine must clear the Interrupt Request Bit (by writing 1 to the bit) in the Interrupt Request Register and then return or branch back to the
main program.
Example. The following example outlines the sequence of a polling routine:
INCLUDE "device.INC" ; Include device-specific label
; definitions
LD R0, #00100000B ; Load mask for bit 5
TM.B IRQ1, R0 ; Test for 1 in IRQ1 Bit 5
JP Z, NEXT ; If no IRQ, go to NEXT
CALL SERVICE ; If IRQ, call the interrupt
; service routine.
NEXT:
;[Insert additional program code here.]
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SERVICE: ; Process interrupt request
;Service routine code here.
LD.B IRQ1, R0 ; Write a 1 to clear IRQ1 bit 5
RET ; Return to address after CALL
Do not use IRET when returning from a polled interrupt service routine.
For information about the Interrupt Request registers, refer to the ZNEO Product Specification that is specific to your device.
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Interrupts UM018809-0611
System Exceptions
Note:
System exceptions are similar to Vectored Interrupts; however, exceptions are generated
by the CPU and cannot be masked or disabled. There are five ZNEO CPU events that generate system exceptions; each is listed below and described in this chapter.
•
Program Counter Overflow
•
Stack Overflow
•
Divide-by-Zero
•
Divide Overflow
•
Illegal Instruction
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It is possible for individual ZNEO CPU products to generate system exceptions in addition
to those listed above.
To determine if your device generates other system exceptions, refer to the ZNEO product
specification that is specific to your device .
Following a system exception, the Flags and Program Counter are pushed on the stack.
The Program Counter value that is pushed onto the stack points to the next instruction (not
the instruction that generated the system exception).
The system exception vector is stored in a reserved memory quad at
nonvolatile memory space. The vector is a 32-bit pointer (service routine address) stored
in the 4-byte quad. When an exception occurs, the vector replaces the value in the Program
Counter (PC). Program execution continues with the instruction pointed to by the new PC
value.
0000_0008H in the
Symbolic Operation of System Exception
A symbolic operation of system exceptions is exemplified below.
SP
SP – 1
(SP)
Flags
SP – 5
SP
PC
(SP)
PC
Vector
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Program Counter Overflow
The Program Counter Overflow exception can be used to restrict program execution to the
memory space below a certain address. On each instruction fetch, the 32-bit PC value is
compared to the value in the Program Counter Overflow register (PCOV) in I/O memory.
If the PC value is greater than the PCOV value, a Program Counter Overflow system
exception is generated after the instruction fetch completes. After a Program Counter
Overflow occurs, the
EXCP) is set to 1. After the first PCOV exception has executed, no additional PCOV
exceptions are generated until the
the bit to 0.
For detailed information regarding the System Exception register (SYSEXCP), refer to the
ZNEO product specification that is specific to your device .
PCOVF bit in the System Exception register in I/O memory (SYS-
PCOVF bit is cleared. Writing 1 to the PCOVF bit clears
The IRET instruction must not be used to end a PCOV exception service routine. After
a PCOV exception occurs, the Program Counter value on the stack points to an address
following the presumably invalid instruction that was fetched.
To set up Program Counter Overflow Protection, initialize PCOV to the highest address
that you intend to use for program instructions.
Stack Overflow
The Stack Overflow exception can be used to help restrict stack growth to the memory
space above a certain address. Whenev er the re gister R15 Stack Pointer (SP) is changed,
its value is compared to the value in the Stack Pointer Overflow register (SPOV) in I/O
memory. If the SP value is less than the SPOV value, a Stack Pointer Overflow system
exception is generated after the current instruction completes.
After a Stack Pointer Overflow occurs, the
I/O memory (SYSEXCP) is set to 1. After the first SPOV exception has executed, no additional SPOV exceptions are generated until the
SPOVF bit clears the bit to 0.
SPOVF bit in the System Exception register in
SPOVF bit is cleared. Writing 1 to the
For more information about the System Exception register (SYSEXCP), refer to the ZNEO
product specification that is specific to your device .
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Observe the following steps to set up Stack Overflow Protection.
1. Initialize the Stack Pointer (SP) to its starting location (the highest RAM address +1).
2. Initialize SPOV to the lowest address to which it is safe for the stack to extend, minus
at least 12 bytes to allow room for interrupt completion.
An SPOV exception does not block writes to the stack. When initializing the SPOV register, you must provide for at least 12 additional bytes of stack data that might be written
below the programmed address. This occurs if an interrupt generates a Stack Overflow on
the first byte it pushes. In this case the interrupt pushes 5 additional bytes and the exception itself must push six more before the exception handler can start.
The 11-byte allowance described here is not sufficient if user code manipulates the Stack
Pointer (register R15), either directly or by using the LINK instruction. The allowance
must be increased to accommodate the largest expected decrement of SP.
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Divide-by-Zero
If the divisor is zero during execution of a divide instruction (UDIV or SDIV), the ZNEO
CPU generates a Divide-by-Zero system exception. After a Divide-by-Zero has occurred,
the
DIV0 bit in the System Exception register in I/O memory (SYSEXCP) is set to 1. After
the first Divide-by-Zero system exception has executed, no additional Divide-by-Zero
system exceptions are generated until the
bit to 0.
For more information about the System Exception register (SYSEXCP), refer to the ZNEO
product specification that is specific to your device .
Divide Overflow
If execution of a divide instruction (UDIV64) results in an overflow, the ZNEO CPU generates a Divide Overflow system exception. After a Divide Overflow has occurred, the
DIVOVF bit in the System Exception register in I/O memory (SYSEXCP) is set to 1. After
the first Divide Overflow system exception has executed, no additional Divide Overflow
system exceptions are generated until the
clears the bit to 0.
DIV0 bit is cleared. Writing 1 to DIV0 clears the
DIVOVF bit is cleared. Writing 1 to DIVOVF
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For more information about the System Exception register (SYSEXCP), refer to the ZNEO
product specification that is specific to your device .
Illegal Instruction
If the Program Counter addresses any unimplemented opcode, the ZNEO CPU generates
an Illegal Instruction system exception.
memory word, so the
instruction.
The Break opcode (BRK, 0000H) operates as an ILL exception if On-Chip Debugger
(OCD) breaks are disabled. For details about the OCD, refer to the ZNEO product specification that is specific to your device.
FFFFH is the default value of an unprogrammed
FFFFH opcode is defined as the Illegal Instruction Exception (ILL)
An illegal instruction invokes the System Exception vector at
0000_0008H in memory.
An ILL is similar to other system exceptions except the Program Counter does not increment before it is pushed onto the stack, so the Program Counter value on the stack points
to the instruction that caused the exception.
After an illegal instruction exception occurs, the
in I/O memory (
SYSEXCP) is set to 1. After the first ILL exception has executed, addi-
tional ILL exceptions will not push the Program Counter again until the
Writing 1 to the
ILL bit clears the bit to 0. For more information, see the description of the
ILL bit in the System Exception register
ILL bit is cleared.
ILL instruction on page 106.
For more information about the System Exception register (SYSEXCP), refer to the ZNEO
product specification that is specific to your device .
An IRET instruction must not be performed to end an illegal instruction exception service routine. As the stack contains the Program Counter value of the illegal instruction,
the IRET instruction returns the code execution to this illegal instruction.
System Exceptions UM018809-0611
Sof tware Traps
Note:
The TRAP Vector instruction allows software to invoke any vectored service routine, par-
ticularly software-defined traps. The TRAP instruction executes the pointed service routine by the specified vector . Software traps use the same vector space as system exceptions
and interrupts. Like other vectors, the 32-bit trap vector value is stored in a memory quad.
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Possible vectors are numbered from 0 to 255 (
includes memory quads
address is 4
Example. The following instruction executes a software-defined service routine pointed
Vector.
to by Vector 255 stored in quad
TRAP #FFH
0000_0000H to 0000_03FCH. Each vector quad’s physical
0000_03FCH:
0H to FFH). The possible vector space
A software trap service routine must execute an IRET instruction to return from the trap.
Other vectors not used by the CPU or peripherals are available for software-defined traps.
For example, Vector 255 (vector quad
input error handling routine, which is then invoked by a
0000_03FCH) is initialized with a pointer to a user-
TRAP FFH instruction.
For a list of vectors used by the CPU and internal peripherals, refer to the ZNEO product
specification that is specific to your device .
A TRAP instruction is used with exception or interrupt vectors but the TRAP instruction
does not sets any register bits in I/O memory that the corresponding service routine is
likely to inspect. For more information, see the Software Interrupt Generation
section on
page 46.
Some locations in the vector space may be reserved by the CPU for other uses. For exam-
ple, a typical ZNEO CPU uses the memory quad at
fore, Vector 00 is not available for service routines. Software can use the instruction
#01
to invoke the RESET vector at 0000_0004H. For more information, see the TRAP
0000_0000H for option bits; there-
TRAP
instruction on page 178.
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Software Traps UM018809-0611
Instruction Opcodes
This chapter provides a complete list of ZNEO CPU instruction opcodes.
Each instruction opcode listed in this chapter consists of one, two or three 16-bit words. T o
abbreviate the listing, certain bit positions are represented symbolically by function.
Table 16 lists the bit field symbols used.
Table 16. Bit Field Symbol s
Bit Character Meaning
1 Literal 1 bit.
0 Literal 0 bit.
o Binary operation (BOP) number: 000B=ADD, 001B=SUB, 010B=AND,
011B=OR, 100B=XOR, 101B=CP, 110B=TM, 111B=TCM.
Unary operation (UOP) number: 00B=CLR, 01B=CPZ, 10B=INC, 11B=DEC.
d Destination register number.
s Source register number.
m Register mask for PUSHM, POPM.
i Immediate operand bits.
c Condition code.
r Relative offset (in Words).
v Vector number.
w Select Word or Quad (0=16, 1=32 bits)
b Select Byte or Word (0=8 bits, 1=16 bits)
z Select extension (0=Unsigned, 1=Signed)
+ Select pointer predecrement or postincrement.
For a destination pointer: 0=predecrement, 1=postincrement.
For a source pointer: 0=no increment, 1=postincrement
x Don't care digit (ignored by CPU).
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Table 17 lists the abbreviations used in place of register names or explicit values in this
chapter. Normal assembly syntax for operands is described in the Operand Addressing
chapter on page 27.
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Table 17. Operand Symbols
Operand Abbreviation Meaning
addr16, addr32 16- or 32-bit direct address.
cc4 4-bit condition code.
imm32 Immediate destination-sized operand with the specified number of bits.
uimm8 Unsigned immediate short operand with the specified number of bits.
simm16 Signed immediate short operand with the specified number of bits.
mask Register mask (list of ALU registers).
vector8 8-bit vector number.
Rs Source register name.
Rd Destination register name.
src Source operand.
dst Destination operand.
soff14, soff13, soff6 Signed indirect address (pointer) offset.
rel Relative jump offset.
Table 18 lists instructions by opcode. Unimplemented opcodes are shaded in grey.
Table 18. ZNEO CPU Instructions Listed by Opcode
Opcode Format Instruction, Operands Description
0000 0000 0000 0000 BRK Debugger Break.
0000 0000 0000 0001 UNLINK Unlink Frame
(LD R15, R14; POP R14).
0000 0000 0000 0010 PUSHF Push Flags Register .
0000 0000 0000 0011 POPF Pop Flags Register.
0000 0000 0000 0100 ATM Disable Interrupts and DMA during next three
instructions.
0000 0000 0000 0101 NOFLAGS Disable write to FLAGS on next instruction.
0000 0000 0000 0110 — Unimplemented
0000 0000 0000 0111 — Extend prefix used to select extended function
for next ADD, SUB, CP, CPZ, SRR, SRA, SLL,
or UDIV instruction.
0000 0000 0000 1xxx — Unimplemented
0000 0000 0001 xxxx — Unimplemented
Instruction Opcodes UM018809-0611
Table 18. ZNEO CPU Instructions Listed by Opcode (Continued)
Opcode Format Instruction, Operands Description
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0000 0000 0010 dddd
0xrr rrrr rrrr rrrr
0000 0000 0010 dddd
LD Rd, soff14(PC) Load Quad pointed to by program counter plus
14-bit signed offset.
LEA Rd, soff14(PC) Load register with PC-based effective address.
1xrr rrrr rrrr rrrr
0000 0000 0011 dddd
zbrr rrrr rrrr rrrr
LD.UB Rd, soff14(PC)
LD.SB Rd, soff14(PC)
LD.UW Rd, soff14(PC)
Load memory Byte or Word pointed to by program counter plus 14-bit signed offset with
Unsigned/Signed extension.
LD.SW Rd, soff14(PC)
0000 0000 01xx xxxx — Unimplemented
0000 0000 1xxx xxxx — Unimplemented
0000 0001 cccc dddd LD cc, Rd Load register with condition code.
0000 0010 xxxx xxxx — Unimplemented
0000 0011 00bz dddd
aaaa aaaa aaaa aaaa
LD.UB Rd, addr16
LD.SB Rd, addr16
Load memory Byte or Word with Unsigned/
Signed extension; 16-bit address.
LD.UW Rd, addr16
LD.SW Rd, addr16
0000 0011 0100 dddd
LD Rd, addr16 Load memory Quad; 16-bit address.
aaaa aaaa aaaa aaaa
0000 0011 0101 ssss
LD.B addr16, Rs Store memory Byte; 16-bit address.
aaaa aaaa aaaa aaaa
0000 0011 0110 ssss
LD.W addr16, Rs Store memory Word; 16-bi t address.
aaaa aaaa aaaa aaaa
0000 0011 0111 ssss
LD addr16, Rs Store memory Quad; 16-bit address.
aaaa aaaa aaaa aaaa
0000 0011 10bz dddd
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
LD.UB Rd, addr32
LD.SB Rd, addr32
LD.UW Rd, addr32
Load memory Byte or Word with Unsigned/
Signed extension; 32-bit address.
LD.SW Rd, addr32
0000 0011 1100 dddd
LD Rd, addr32 Load memory Quad; 32-bit address.
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
0000 0011 1101 ssss
LD.B addr32, Rs Store memory Byte; 32-bit address.
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
0000 0011 1110 ssss
LD.W addr32, Rs Store memory Word; 32-bi t address.
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
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Table 18. ZNEO CPU Instructions Listed by Opcode (Continued)
Opcode Format Instruction, Operands Description
0000 0011 1111 ssss
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
0000 0100 mmmm mmmm PUSHMLO mask Push multiple registers, R7–R0.
0000 0101 mmmm mmmm PUSHMHI mask Push multiple registers, R15–R8.
0000 0110 mmmm mmmm POPMLO mask Pop multiple registers, R7–R0.
0000 0111 mmmm mmmm POPMHI mask Pop multiple registers, R15–R8.
0000 1000 iiii iiii LINK #uimm8 Link Frame (PUSH R14; LD R14,R15; SUB
0000 1001 00xx xxxx — Unimplemented
0000 1001 010+ dddd
xxxx xxxx iiii iiii
0000 1001 011w dddd
iiii iiii iiii iiii
0000 1001 10+w dddd
iiii iiii iiii iiii
0000 1001 1100 dddd
xxxx xxxx iiii iiii
LD addr32, Rs Store memory Quad; 32-bit address.
R15,#uimm8).
LD.B (--Rd), #imm8
LD.B (Rd++), #imm8
LD.W (Rd), #imm16
LD (Rd), #simm16
LD.W (--Rd), #imm16
LD.W (Rd++), #imm16
LD (--Rd), #simm16
LD (Rd++), #simm16
LD.B (Rd), #imm8 Store immediate 8 bits to Byte.
Store immediate 8 bits with Predecrement/
Postincrement.
Store signed immediate 16 bits to Word or
Quad.
Store signed im mediate 16 bit s to Wor d or Quad
with Predecrement/Postincrement.
0000 1001 1101 dddd
iiii iiii iiii iiii
iiii iiii iiii iiii
0000 1001 111+ dddd
iiii iiii iiii iiii
iiii iiii iiii iiii
0000 1010 iiii iiii PUSH.B #imm8 Push immediate 8 bits onto system stack.
0000 1011 ssss dddd LD (Rd), Rs Store register to Quad.
0000 110w iiii iiii PUSH.W #simm8
0000 111b ssss dddd LD.B (Rd), Rs
0001 000+ ssss dddd LD (--Rd), Rs
Instruction Opcodes UM018809-0611
LD (Rd), #imm32 Store immediate 32 bits to Quad.
LD (--Rd), #imm32
LD (Rd++), #imm32
PUSH #simm8
LD.W (Rd), Rs
LD (Rd++), Rs
Store immediate 32 bi ts to Quad with Predecre-
ment/Postincrement.
Push signed immediate 8 bits to Word or Quad
on system stack.
Store register to Byte or Word.
Store register to Quad with Predecrement/
Postincrement.
Table 18. ZNEO CPU Instructions Listed by Opcode (Continued)
Opcode Format Instruction, Operands Description
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0001 001+ ssss dddd LD Rd, (Rs)
LD Rd, (Rs++)
0001 01b+ ssss dddd LD.B (--Rd), Rs
LD.B (Rd++), Rs
Load dst register from Quad with optional
Postincrement.
Store register to Byte or Word with Predecre-
ment/Postincrement.
LD.W (--Rd), Rs
LD.W (Rd++), Rs
0001 1zb+ ssss dddd LD.UB Rd, (Rs)
LD.SB Rd, (Rs)
LD.UB Rd, (Rs++)
Load dst register from Byte or Word with
optional Postincrement and Unsigned/Signed
extension.
LD.SB Rd, (Rs++)
LD.UW Rd, (Rs)
LD.SW Rd, (Rs)
LD.UW Rd, (Rs++)
LD.SW Rd, (Rs++)
0010 dddd ssss ssss ADD Rd, Rs1+Rs2 Add using two src registers, one dst.
0011 dddd iiii iiii LD Rd, #simm8 Load dst register from immediate 8 bits with
Signed extension.
0100 00zb ssss dddd EXT.UB Rd, Rs
EXT.SB Rd, Rs
Load 8 or 16 bits to dst from src register with
Unsigned/Signed extension.
EXT.UW Rd, Rs
EXT.SW Rd, Rs
0100 0100 ssss dddd LD Rd, Rs Load dst from src register.
0100 0101 000z dddd
iiii iiii iiii iiii
0100 0101 0010 dddd
LD Rd, #simm17 Load dst register from immediate 16 bits plus
sign bit z; Signed extension.
LD Rd,#imm32 Load dst register from immediate 32 bits.
iiii iiii iiii iiii
iiii iiii iiii iiii
0100 0101 0011 dddd LDES Rd Fill dst from Sign bit.
0100 0101 0100 dddd COM Rd Complement destination.
0100 0101 0101 dddd NEG Rd N egate ds t (subtract from zero).
0100 0101 011x xxxx — Unimplemented
0100 0101 1xxx xxxx — Unimplemented
0100 011x xxxx xxxx — Unimplemented
0100 1000 ssss dddd
0xrr rrrr rrrr rrrr
LD Rd, soff14(Rs) Load dst from Quad pointed to by src plus
signed offset.
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Table 18. ZNEO CPU Instructions Listed by Opcode (Continued)
Opcode Format Instruction, Operands Description
0100 1000 ssss dddd
1xrr rrrr rrrr rrrr
0100 1001 ssss dddd
zbrr rrrr rrrr rrrr
0100 1010 ssss dddd
xxrr rrrr rrrr rrrr
0100 1011 ssss dddd
xbrr rrrr rrrr rrrr
0100 11rr rrrr dddd LEA Rd, soff6(FP) Load dst with FP-based effective address.
0101 0brr rrrr ssss LD.B soff6(FP), Rs
0101 10rr rrrr ssss LD soff6(FP), Rs Load Quad, pointed to by R14 plus signed off-
0101 11rr rrrr dddd LD Rd, soff6(FP) Load dst from Quad pointed to by R14 plus
0110 zbrr rrrr dddd LD.UB Rd, soff6(FP)
LEA Rd, soff14(Rs) Load dst with effective address of src operand.
LD.UB Rd, soff14(Rs)
LD.SB Rd, soff14(Rs)
LD.UW Rd, soff14(Rs)
LD.SW Rd, soff14(Rs)
LD soff14(Rd), Rs Load Quad, pointed to by dst plus signed offset,
LD.B soff14(Rd), Rs
LD.W soff14(Rd), Rs
LD.W soff6(FP), Rs
LD.SB Rd, soff6(FP)
LD.UW Rd, soff6(FP)
LD.SW Rd, soff6(FP)
Load dst from Byte or Word pointed to by src
plus signed offset, with Unsigned/Signed exten-
sion.
from src register.
Load Byte or Word, pointed to by dst plus
signed offset, from src register.
Load Byte or Word, pointed to by R14 plus
signed offset, from src register.
set, from src register.
signed offset.
Load dst from Byte or Word pointed to by R14
plus signed offset, with Unsigned/Signed exten-
sion.
0111 0ooo 00bz dddd
aaaa aaaa aaaa aaaa
0111 0ooo 0100 dddd
aaaa aaaa aaaa aaaa
0111 0ooo 0101 ssss
aaaa aaaa aaaa aaaa
0111 0ooo 0110 ssss
aaaa aaaa aaaa aaaa
0111 0ooo 0111 ssss
aaaa aaaa aaaa aaaa
0111 0ooo 10bz dddd
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
Instruction Opcodes UM018809-0611
BOP.UB Rd, addr16
BOP.SB Rd, addr16
BOP.UW Rd, addr16
BOP.SW Rd, addr16
BOP Rd, addr16 Binary operation ‘ooo’ on dst using Quad; 16- bit
BOP.B addr16, Rs Binary operation ‘ooo’ on Byte; 16-bit address.
BOP.W addr16, Rs Binary operation ‘ooo’ on Word; 16-bit address.
BOP addr16, Rs Binary operation ‘ooo’ on Quad; 16-bit address.
BOP.UB Rd, addr32
BOP.SB Rd, addr32
BOP.UW Rd, addr32
BOP.SW Rd, addr32
Binary operation ‘ooo’ on dst using Byte or
Word with Unsigned/Signed extension; 16-bit
address.
address.
Binary operation ‘ooo’ on dst using Byte or
Word with Unsigned/Signed extension; 32-bit
address.
Table 18. ZNEO CPU Instructions Listed by Opcode (Continued)
Opcode Format Instruction, Operands Description
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0111 0ooo 1100 dddd
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
0111 0ooo 1101 ssss
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
0111 0ooo 1110 ssss
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
0111 0ooo 1111 ssss
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
0111 1ooo ssss dddd
0bzr rrrr rrrr rrrr
0111 1ooo ssss dddd
100r rrrr rrrr rrrr
0111 1ooo ssss dddd
101r rrrr rrrr rrrr
0111 1ooo ssss dddd
110r rrrr rrrr rrrr
BOP Rd, addr32 Binary operation ‘ooo’ on dst using Quad; 32- bit
address.
BOP.B addr32, Rs Binary operation ‘ooo’ on Byte; 32-bit address.
BOP.W addr32, Rs Binary operation ‘ooo’ on Word; 32-bit address.
BOP addr32, Rs Binary operation ‘ooo’ on Quad; 32-bit address.
BOP.UB Rd, soff13(Rs)
BOP.SB Rd, soff13(Rs)
Binary operation ‘ooo’ on dst using Byte or
Word with Unsigned/Signed extension.
BOP.UW Rd, soff13(Rs)
BOP.SW Rd, soff13(Rs)
BOP Rd, soff13(Rs) Binary operation ‘ooo’ on dst using Quad.
BOP.B soff13(Rd), Rs Binary operation ‘ooo’ on Byte.
BOP.W soff13(Rd), Rs Binary operation ‘ooo’ on Word.
0111 1ooo ssss dddd
BOP soff13(Rd), Rs Binary operation ‘ooo’ on Quad.
111r rrrr rrrr rrrr
1000 dddd iiii iiii ADD Rd, #simm8 Add 8 signed immediate bits to dst.
1001 dddd iiii iiii CP Rd, #simm8 Compare 8 signed immediate bits to dst.
1010 0ooo ssss dddd BOP Rd, Rs Binary operation ‘ooo’ on dst, src.
1010 100x xxxx xxxx — Unimplemented
1010 1010 0ooo dddd
iiii iiii iiii iiii
1010 1010 1ooo dddd
iiii iiii iiii iiii
BOP Rd, #uimm16 Binary operation ‘ooo’ on dst using unsigned
immediate 16 bits.
BOP Rd, #imm32 Binary operation ‘ooo’ on dst using immediate
32 bits.
iiii iiii iiii iiii
1010 1011 0ooo dddd
iiii iiii iiii iiii
BOP.W (Rd), #imm16 Binary operation ‘ooo’ on Word using immediate
Word.
UM018809-0611 Instruction Opcodes
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Table 18. ZNEO CPU Instructions Listed by Opcode (Continued)
Opcode Format Instruction, Operands Description
1010 1011 1ooo dddd
iiii iiii iiii iiii
iiii iiii iiii iiii
1010 1100 0boo dddd UOP.B (Rd)
1010 1100 1xoo dddd UOP (Rd) Unary operation ‘oo’ on Quad.
1010 1101 0ooo dddd
iiii iiii iiii iiii
1010 1101 1000 xxxx — Unimplemented
1010 1101 1001 dddd
xxxx xooo iiii iiii
1010 1101 1010 0boo
aaaa aaaa aaaa aaaa
1010 1101 1010 1xoo
aaaa aaaa aaaa aaaa
1010 1101 1011 0boo
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
1010 1101 1011 1xoo
aaaa aaaa aaaa aaaa
aaaa aaaa aaaa aaaa
BOP (Rd), #imm32 Binary operation ‘ooo’ on Quad using immediate
Quad.
Unary operation ‘oo’ on Byte or Word.
UOP.W (Rd)
BOP (Rd), #simm16 Binary operation ‘ooo’ on Quad using signed
immediate Word.
BOP.B (Rd), #imm8 Binary operation ‘ooo’ on Byte using immediate
Byte.
UOP.B addr16
UOP.W addr 1 6
UOP addr16 Unary operation ‘oo’ on Quad. 16-bit address.
UOP.B addr32
UOP.W addr 3 2
UOP addr32 Unary operation ‘oo’ on Quad. 32-bit address.
Unary operation ‘oo’ on Byte or Word. 16-bit
address.
Unary operation ‘oo’ on Byte or Word. 32-bit
address.
1010 1101 11oo dddd
0brr rrrr rrrr rrrr
1010 1101 11oo dddd
1xrr rrrr rrrr rrrr
1010 1110 ssss dddd UDIV Rd, Rs Unsigned Divide, 64-bit result.
1010 1111 ssss dddd SDIV Rd, Rs Signed Divide, 64-bit result.
1011 0000 ssss dddd UMUL Rd, Rs Unsigned Multiply, 64-bit result.
1011 0001 ssss dddd SMUL Rd, Rs Signed Multiply, 64-bit result.
1011 0010 ssss dddd MUL Rd, Rs Unsigned Multiply, 32-bit result.
1011 0011 xxxx xxxx — Unimplemented
1011 0100 ssss dddd SRA Rd, Rs Arithmetic shift right by src bits. Extend modifier
1011 0101 ssss dddd SRL Rd, Rs Logical shift right by src bits. Extend modifier
Instruction Opcodes UM018809-0611
UOP.B soff14(Rd)
UOP.W soff14(Rd)
UOP soff14(Rd) Unary operation ‘oo’ on Quad.
Unary operation ‘oo’ on Byte or Word.
causes shifted-out bits to overwrite src.
causes shifted-out bits to overwrite src.
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Table 18. ZNEO CPU Instructions Listed by Opcode (Continued)
Opcode Format Instruction, Operands Description
1011 0110 ssss dddd SLL Rd, Rs Logical shift left by src bits. Extend modifier
causes shifted-out bits to overwrite src.
1011 0111 ssss dddd RL Rd, Rs Rotate left by src bits.
1011 100i iiii dddd SRA Rd, #uimm5 Arithmetic shift right by uimm bits. Extend modi-
fier causes shifted-out bits to overwrite src.
1011 101i iiii dddd SRL Rd, #uimm5 Logical shift right by uimm bits. Extend modifier
causes shifted-out bits to overwrite src.
1011 110i iiii dddd SLL Rd, #uimm5 Logical shift left by uimm bits. Extend modifier
causes shifted-out bits to overwrite src.
1011 111i iiii dddd RL Rd, #uimm5 Rotate left by uimm bits.
63
1100 rrrr rrrr rrrr JP rel12 Jump with 12-bit offset.
1101 rrrr rrrr rrrr CALL rel12 Call with 12-bit offset.
1110 cccc rrrr rrrr JP cc, rel8 Conditional Jump, signed 8-bit offset.
1111 0000 rrrr rrrr
JP rel24 Jump with 24-bit offset.
rrrr rrrr rrrr rrrr
1111 0001 rrrr rrrr
CALL rel24 Call with 24-bit offset.
rrrr rrrr rrrr rrrr
1111 0010 0000 ssss JP (Rs) Jump to address pointed to by src.
1111 0010 0001 ssss CALL (Rs) Call address pointed to by src.
1111 0010 0010 cccc
JP cc,rel16 Conditional Jump, 16-bit offset.
rrrr rrrr rrrr rrrr
1111 0010 0011 0000
JPA #imm32 Jump to immediate address.
iiii iiii iiii iiii
iiii iiii iiii iiix
1111 0010 0011 0001
CALLA #imm32 Call immediate address.
iiii iiii iiii iiii
iiii iiii iiii iiix
1111 0010 0011 001x — Unimplemented
1111 0010 0011 01xx — Unimplemented
1111 0010 0011 1xxx — Unimplemented
1111 0010 01xx xxxx — Unimplemented
1111 0010 1xxx xxxx — Unimplemented
1111 0011 xxxx xxxx — Unimplemented
UM018809-0611 Instruction Opcodes
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Table 18. ZNEO CPU Instructions Listed by Opcode (Continued)
Opcode Format Instruction, Operands Description
1111 01xx xxxx xxxx — Unimplemented
1111 10xx xxxx xxxx — Unimplemented
1111 1100 xxxx xxxx — Unimplemented
1111 1101 rrrr dddd DJNZ Rd, urel4 Decrement dst and jump if nonzero.
1111 1110 vvvv vvvv TRAP #vector8 Software trap.
1111 1111 0xxx xxxx — Unimplemented
1111 1111 10xx xxxx — Unimplemented
1111 1111 110x xxxx — Unimplemented
1111 1111 1110 xxxx — Unimplemented
1111 1111 1111 00xx — Unimplemented
1111 1111 1111 010x — Unimplemented
1111 1111 1111 0110 — Unimplemented
1111 1111 1111 0111 WDT Watchdog Timer Refresh.
1111 1111 1111 1000 STOP Enter STOP.
1111 1111 1111 1001 HALT Enter HALT.
1111 1111 1111 1010 EI Enable Interrupts.
1111 1111 1111 1011 DI Disable Interrupts.
1111 1111 1111 1100 RET Return from subroutine.
1111 1111 1111 1101 IRET Return from interrupt.
1111 1111 1111 1110 NOP No operation.
1111 1111 1111 1111 ILL Explicit illegal instruction.
Instruction Opcodes UM018809-0611
Instruction Set Reference
This chapter provides detailed description of the assembly language instructions available
with the ZNEO CPU.
Instruction Notation
Tables 19 and 20 list the symbolic notation for expressions and other miscellaneous symbols used to describe the operation of ZNEO CPU instructions. For general notation
details, see Manual Conventions on page xiv. For operand notation details, see the Oper-
and Addressing section on page 27. The operand abbreviations are explained in Table 17
on page 56.
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Numerical and Expression Notation
T able 19 lists symbols and operators used in expressions in this document. This is a subset
of operators recognized by the assembler. For more details, refer to the assembler documentation.
Table 19. Symbols Used in Expressions
Symbol Definition
$ During assembly, returns the current address.
H Hexadecimal number suffix.
B Binary number suffix.
xB, xH Binary or hexadecimal “don’t care” digit (ignored by CPU).
% Alternate hexadecimal number prefix.
Modulus operator (remainder of division) when preceded and followed by spaces.
* Multiplication operator (in assembly source).
/ Divisio n op er at or.
+ Addition operator.
– Subtraction operator. Minus sign or negation when used as unary prefix.
~ One’s complement unary operator.
!= Not equal relational operator. True if terms are not equal.
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Miscellaneous Abbreviations
Table 20 lists additional symbols used in the instruction set descriptions.
Table 20. Abbreviations Used in Text and Tables
Symbol Definition
dst Destination Operand.
src Source Operand.
Rd Destination Register.
Rs Source Register.
cc Condition Code.
An arrow (indicates assignment of a value. Fo r ex am p le,
dst dst + src indicates that sum of the operands is stored in the destination location.
A double arrow () indicates the exchange of two values.
Multiplication sign (arithmetic); repeated operation count.
FLAGS Flags Register.
C Carry Flag.
Z Zero Flag.
S Sign Flag.
V Overflow Flag.
B Blank Flag.
CIRQE Chained Interrupt Enable.
IRQE Master Interrupt Enable.
* Flag bit state depends on result of operation.
– Flag bit state is not affected by operation.
0 Flag bit is cleared to 0.
1 Flag bit is set to 1.
SP Stack Pointer.
PC Program Counter.
FP Frame Pointer.
Instruction Set Reference UM018809-0611
Example Description
The instruction sets described on the following pages are organized alphabetically by
mnemonic abbreviation. An example instruction is provided below.
MNEMONIC
Definition
Definition of instruction mnemonic.
Syntax
Simplified description of assembly coding.
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Operation
Symbolic description of the operation performed.
Description
Detailed description of the instruction operation.
Flags
Information about how the CPU flags are affected by instruction operation.
Syntax and Opcodes
A table providing assembly syntax and corresponding opcodes.
Example
A sample code example using the instruction.
UM018809-0611 Mnemonic
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ADC
Definition
Syntax
Operation
Description
Add with Carry
ADC dst, src
dstdst + src + C
The source operand and the Carry (C) flag are added to the destination operand using signed
(two’s-complement) addition. The sum is stored in the destination operand. The contents of the
source operand are not affected. This instruction is used in multiple-precision arithmetic to
include the carry from the addition of low-order operands into the addition of high-order operands.
The Zero (Z) flag is set only if the initial state of the Z flag is 1 and the result is 0. This instruction
is generated by using the Extend prefix,
Flags
76543210
C Z S V B CIRQE IRQE
*****–––
Legend
C = Set to 1 if the result generated a carry; otherwise set to 0.
Z = Set to 1 if Z is initially 1 and the result is zero; otherwise set to 0.
S = Set to 1 if the result msb is 1; otherwise set to 0.
V = Set to 1 if an arithmetic overflow occurs; otherwise set to 0.
B = Set to 1 if the initial destination or source value is 0; otherwise set to 0.
CIRQE = No change.
IRQE = No change.
0007H, with the ADD opcodes.
Flags are set based on the memory destination size, or 32 bits for register destinations.
ADC Instruction UM018809-0611
ZNEO
User Manual
Syntax and Opcodes
Extend
Instruction, Operands
Prefix Word 0 Word 1 Word 2
ADC Rd, #imm32 0007H {AA8H, Rd} imm[31:16] imm[15:0]
ADC Rd, #simm8 0007H {8H, Rd, simm8}
ADC Rd, #uimm16 0007H {AA0H, Rd} uimm16
ADC Rd, Rs 0007H {A0H, Rs, Rd}
ADC Rd,Rs1,Rs2 0007H {2H, Rd, Rs, Rs}
ADC Rd, addr16 0007H {704H, Rd} addr16
ADC Rd, addr32 0007H {70CH, Rd} addr[31:16] addr[15:0]
ADC Rd, soff13(Rs) 0007H {78H, Rs, Rd} {100B, soff13}
ADC addr16, Rs 0007H {707H, Rs} addr16
ADC addr32, Rs 0007H {70FH, Rs} addr[3 1:16] addr[15:0]
ADC (Rd), #imm32 0007H {AB8H, Rd} imm[31:16] imm[15:0]
ADC (Rd), #simm16 0 007H {AD0H, Rd} simm16
ADC soff13(Rd), Rs 0007H {78H, Rs, Rd} {111B, soff13}
ADC.W addr16, Rs 0007H {706H, Rs} addr16
ADC.W addr32, Rs 0007H {70EH, Rs} addr[31:16] addr[15:0]
ADC.W (Rd), #imm16 0007H {AB0H, Rd} imm16
ADC.W soff13(Rd), Rs 0007H {78H, Rs, Rd} {110B, soff13}
ADC.SW Rd, addr16 0007H {703H, Rd} addr16
ADC.SW Rd, addr32 0007H {70BH, Rd} addr[31:16] addr[15:0]
ADC.SW Rd, soff13(Rs) 0007H {78H, Rs, Rd} {011B, soff13}
ADC.UW Rd, addr16 0007H {702H, Rd} addr16
ADC.UW Rd, addr32 0007H {70AH, Rd} addr[31:16] addr[15:0]
ADC.UW Rd, soff13(Rs) 0007H {78H, Rs, Rd} {010B, soff13}
ADC.B addr16, Rs 0007H {705H, Rs} addr16
ADC.B addr32, Rs 0007H {70DH, Rs} addr[31:1 6] addr[15:0]
ADC.B (Rd), #imm8 0007H {AD9H, Rd} { xH, x000B, imm8}
ADC.B soff13(Rd), Rs 00 07H {78H, Rs, Rd} {101B, soff13}
ADC.SB Rd, addr16 0007H {701H, Rd} addr16
ADC.SB Rd, addr32 0007H {709H, Rd} addr[31:16] addr[15:0]
ADC.SB Rd, soff13(Rs) 0007H {78H, Rs, Rd} {001B, soff13}
ADC.UB Rd, addr16 0007H {700H, Rd} addr16
ADC.UB Rd, addr32 0007H {708H, Rd} addr[31:16] addr[15:0]
ADC.UB Rd, soff13(Rs) 0007H {78H, Rs, Rd} {000B, soff13}
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UM018809-0611 ADC Instruction
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Examples
Before:
ADC R3, R11 ;Object Code: 0007 A0B3
After:
Before: R3=16H, R11=20H, Flag C=0
ADC R3, R11 ;Object Code: 0007 A0B3
After:
R3=16H, R11=20H, Flag C=1
R3=37H, Flags C, Z, S, V, B = 0
R3=36H, Flags C, Z, S, V, B = 0
ADC Instruction UM018809-0611
ADD
Note:
Definition
Add
Syntax
ADD dst, src
Operation
dstdst + src
Description
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Add the source operand to the destination operand. Perform signed (two’ s-complement) addition.
Store the sum in the destination operand. The contents of the source operand are not affected.
Flags
76543210
C Z S V B CIRQE IRQE
*****–––
Legend
C = Set to 1 if the result generated a carry; otherwi se set to 0.
Z = Set to 1 if the result is zero; otherwise, set to 0.
S = Set to 1 if the result msb is 1; otherwise set to 0.
V = Set to 1 if an arithmetic overflow occurs; otherwise set to 0.
B = Set to 1 if the initial destination or source value is 0; otherwise set to 0.
CIRQE = No change.
IRQE = No change.
Flags are set based on the memory destination size, or 32 bits for register destinations.
UM018809-0611 ADD Instruction
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Syntax and Opcodes
Instruction, Operands Word 0 Word 1 Word 2
ADD Rd, #imm32 {AA8H, Rd} imm[31:16] imm[15:0]
ADD Rd, #simm8 {8H, Rd, simm8}
ADD Rd, #uimm16 {AA0H, Rd} uimm16
ADD Rd, Rs {A0H, Rs, Rd}
ADD Rd,Rs1,Rs2 {2H, Rd, Rs, Rs}
ADD Rd, addr16 {704H, Rd} addr16
ADD Rd, addr32 {70CH, Rd} addr[31:16] addr[15:0]
ADD Rd, soff13(Rs) {78H, Rs, Rd} {100B, soff13}
ADD addr16, Rs {707H, Rs} addr16
ADD addr32, Rs {70FH, Rs} addr[31:16] addr[15:0]
ADD (Rd), #imm32 {AB8H, Rd} imm[31:16] imm[15:0]
ADD (Rd), #simm16 { AD0H, Rd} simm16
ADD soff13(Rd), Rs {78H, Rs, Rd} {111B, soff13}
ADD.W addr16, Rs {706H, Rs} addr16
ADD.W addr32, Rs {70EH, Rs} addr[31:16] addr[15:0]
ADD.W (Rd), #imm16 {AB0H, Rd} imm16
ADD.W soff13(Rd), Rs {78H, Rs, Rd} {110B, soff13}
ADD.SW Rd, addr16 {703H, Rd} addr16
ADD.SW Rd, addr32 {70BH, Rd} addr[31:16] addr[15:0]
ADD.SW Rd, soff13(Rs) {78H, Rs, Rd} {011B, soff13}
ADD.UW Rd, addr16 {702H, Rd} addr16
ADD.UW Rd, addr32 {70AH, Rd} addr[31:16] addr[15:0]
ADD.UW Rd, soff13(Rs) {78H, Rs, Rd} {010B, soff13}
ADD.B addr16, Rs {705H, Rs} addr16
ADD.B addr32, Rs {70DH, Rs} addr[31:16] addr[15:0]
ADD.B (Rd), #imm8 {AD9H, Rd} {xH, x000B, imm8}
ADD.B soff13(Rd), Rs {78H, Rs, Rd} {101B, soff13}
ADD.SB Rd, addr16 {701H, Rd} addr16
ADD.SB Rd, addr32 {709H, Rd} addr[31:16] addr[15:0]
ADD.SB Rd, soff13(Rs) {78H, Rs, Rd} {001B, soff13}
ADD.UB Rd, addr16 {700H, Rd} addr16
ADD.UB Rd, addr32 {708H, Rd} addr[31:16] addr[15:0]
ADD.UB Rd, soff13(Rs) {78H, Rs, Rd} {000B, soff13}
ADD Instruction UM018809-0611
Examples
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Before:
ADD R3, R11 ;Object Code: A0B3
After:
Before: R3=FFFF_B023H, FFFF_B023H=702EH
ADD.W (R3), #1055H ;Object Code: AB03 1055
After:
Before: R12=16H, R10=FFFF_B020H, FFFF_B020H=91H
ADD.UB R12, (R10) ;Object Code: 78AC 0000
After:
Before: R12=16H, R10=FFFF_B020H, FFFF_B020H=91H
ADD.SB R12, (R10) ;Object Code: 78AC 2000
After:
Before: FFFF_B034H=2EH, R12=1BH
ADD.B B034H:RAM, R12;Object Code: 705C B034
R3=16H, R11=20H
R3=36H, Flags C, Z, S, V, B = 0
FFFF_B023H=8083H, Flags S=1, C, Z, V, B=0
R12=A7H, Flags C, Z, S, V, B = 0
R12=FFFF_FFA7H, Flags S=1 C, Z, V, B = 0
After:
FFFF_B034H = 49H, Flags C, Z, S, V, B =0
UM018809-0611 ADD Instruction
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AND
Definition
Syntax
Operation
Description
Logical AND
AND dst, src
dstdst AND src
The source operand is logically ANDed with the destination operand. An AND operation stores a
1 when the corresponding bits in the two operands are both 1; otherwise the operation stores a 0.
The result is written to the destination. The contents of the source are unaffected. Table 21 summarizes the AND operation.
Table 21. Truth Table for AND
dst src Result (dst)
00 0
10 0
01 0
11 1
Flags
76543210
C Z S V B CIRQE IRQE
–**0*–––
Legend
C = No change.
Z = Set to 1 if the result is zero; otherwise, set to 0.
S = Set to 1 if the result msb is 1; otherwise set to 0.
V = Cleared to 0.
B = Set to 1 if the initial destination or source value is 0; otherwise set to 0.
CIRQE = No change.
IRQE = No change.
AND Instruction UM018809-0611
Flags are set based on the memory destination size, or 32 bits for register destinations.
Note:
Syntax and Opcodes
Instruction, Operands Word 0 Word 1 Word 2
AND Rd, #imm32 {AAAH, Rd} imm[31:16] imm[15:0]
AND Rd, #uimm16 {AA2H, Rd} uimm16
AND Rd, Rs {A2H, Rs, Rd}
AND Rd, addr16 {724H, Rd} addr16
AND Rd, addr32 {72CH, Rd} addr[31:16] addr[15:0]
AND Rd, soff13(Rs) {7AH, Rs, Rd} {100B, soff13}
AND addr16, Rs {727H, Rs} addr16
AND addr32, Rs {72FH, Rs} addr[31:16] addr[15:0]
AND (Rd), #imm32 {ABAH, Rd} imm[31:16] imm[15:0]
AND (Rd), #simm16 {AD2H, Rd} simm16
AND soff13(Rd), Rs {7AH, Rs, Rd} {111B, soff13}
AND.W addr16, Rs {726H, Rs} addr16
AND.W addr32, Rs {72EH, Rs} addr[31:16] addr[15:0]
AND.W (Rd), #imm16 {AB2H, Rd} imm16
AND.W soff13(Rd), Rs {7AH, Rs, Rd} {110B, soff13}
AND.SW Rd, addr16 {723H, Rd} addr16
AND.SW Rd, addr32 {72BH, Rd} addr[31:16] addr[15:0]
AND.SW Rd, soff13(Rs) {7AH, Rs, Rd} {011B, soff13}
AND.UW Rd, addr16 {722H, Rd} addr16
AND.UW Rd, addr32 {72AH, Rd} addr[31:16] addr[15:0]
AND.UW Rd, soff13(Rs) {7AH, Rs, Rd} {010B, soff13}
AND.B addr16, Rs {725H, Rs} addr16
AND.B addr32, Rs {72DH, Rs} addr[31:16] addr[15:0]
AND.B (Rd), #imm8 {AD9H, Rd} {xH, x010B, imm8}
AND.B soff13(Rd), Rs {7AH, Rs, Rd} {101B, soff13}
AND.SB Rd, addr16 {721H, Rd} addr16
AND.SB Rd, addr32 {729H, Rd} addr[31:16] addr[15:0]
AND.SB Rd, soff13(Rs) {7AH, Rs, Rd} {001B, soff13}
AND.UB Rd, addr16 {720H, Rd} addr16
AND.UB Rd, addr32 {728H, Rd} addr[31:16] addr[15:0]
AND.UB Rd, soff13(Rs) {7AH, Rs, Rd} {000B, soff13}
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UM018809-0611 AND Instruction
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Examples
Before:
AND R1, R14 ;Object Code: A2E1
After:
Before: R4[31:8]=FFFF_FFH, R4[7:0]=79H (0111_1001B), FFFF_B07BH=EAH
R1[7:0]=38H (0011_1000B), R14[7:0]=8DH (1000_1101B)
R1[7:0]=08H (0000_1000B), Flags Z, V, S, B=0
(1110_1010B)
AND.SB R4, B07BH:RAM;Object Code: 7214 B07B
After:
R4[31:8]=FFFF_FFH, R4[7:0]=68H (0110_1000B), Flags S=1; Z, V, B=0
Before: R4[31:8]=FFFF_FFH, R4[7:0]=79H (0111_1001B), FFFF_B07BH=EAH
(1110_1010B)
AND.UB R4, B07BH:RAM;Object Code: 7204 B07B
After:
R4[31:8]=0000_00H, R4[7:0]=68H (0110_1000B), Flags Z, V, S, B= 0
Before: R13=FFFF_B07AH, FFFF_B07AH=C3F7H (1100_0011_1111_0111B)
AND.W (R13), #80F0H ;Object Code: AB2D 80F0
After:
FFFF_B07AH=80F0H (1000_0000_1111_0000B), Flags S=1; Z, V, B=0
AND Instruction UM018809-0611
ATM
Definition
Atomic Execution
Syntax
ATM
Operation
Block all interrupt and DMA requests during execution of the next 3 instructions.
Description
ZNEO
User Manual
®
CPU Core
77
The Atomic instruction forces the ZNEO CPU to execute the next three instructions as a single
block (that is, atom) of operations. During execution of these next three instructions, all interrupts and DMA requests are prevented. This allows operations to be performed on memory locations that might otherwise be changed or used during the operation by interrupts or DMA.
Flags
Flags are not affected by this instruction.
Syntax and Opcodes
Instruction, Operands Word 0 Word 1 Word 2
ATM 0004H
Example
The following example tests a bit used to lock a resource, then sets the bit if it is clear. ATM
ensures that the tested bit can be set before another routine tests it.
LD R7, #00000010B ;Load mask for bit 1 Object Code: 3702
ATM ;Block interrupt/DMA requests Object Code: 0004
TM.B B047H:RAM, R7 ;Test semaphore with bit mask Object Code: 7657 B047
JP NZ, Msg1_In_Use ;JP if resource is in use Object Code: EE xx
OR.B B047H:RAM, R7 ;Else set masked bit
; to lock resource
Object Code: 7357 B047
UM018809-0611 ATM Instruction
ZNEO® CPU Core
Note:
User Manual
78
BRK
Definition
Syntax
Operation
Description
On-Chip Debugger Break
BRK
None
If the Break capability is enabled, execution of the BRK instruction initiates an On-Chip Debugger break at this address. If the Break capability is not enabled, the BRK instruction operates as
an Illegal Instruction Exception (ILL).
Refer to the ZNEO product specification that is specific to your device for information
regarding the On-Chip Debugger.
Flags
Flags are not affected by this instruction.
Syntax and Opcodes
Instruction, Operands Word 0 Word 1 Word 2
BRK 0000H
BRK Instruction UM018809-0611
CALL
Definition
Syntax
Operation
CALL Procedure
CALL dst
SPSP4
(SP)PC
PCdestination address
ZNEO
User Manual
®
CPU Core
79
Description
A CALL instruction decrements the Stack Pointer (R15) by four and stores the current Program
Counter value on the top of the stack. The pushed PC value points to the first instruction following the CALL instruction. Then the destination address is loaded into the Program Counter and
execution of the procedure begins. After the procedure completes, it uses a RET instruction to
pop the previous PC value and return from the procedure.
In assembly language, the destination is specified as a label or 32-bit address operand. When possible, the ZNEO CPU assembler automatically calculates a relative offset and generates relative
CALL opcodes to produce more efficient object code. For a relative CALL, the destination
address is the PC value plus two times the relative operand value.
In the CALL (Rs) syntax, if the contents of Rs are odd the least significant bit is discarded, so that
the call destination address is always an even number.
To invoke a 32-bit addressed call explicitly, use the CALLA instruction.
Flags
Flags are not affected by this instruction.
Syntax and Opcodes
Instruction, Operands Word 0 Word 1 Word 2
CALL (Rs) {F21H, Rs}
CALL rel12 {DH, rel12}
CALL rel24 {F1H, rel[23:16]} rel[15:0]
UM018809-0611 CALL Instruction
ZNEO® CPU Core
User Manual
80
Example
Before:
CALL (R7) ;Object Code: F217
After:
PC=0000_0472H, SP=FFFF_DE24H, R7=0000_3521H
PC=0000_3520, SP=FFFF_DE20H, FFFF_DE20H=0000_0478H
CALL Instruction UM018809-0611
CALLA
Definition
Syntax
Operation
CALL Absolute
CALLA dst
ZNEO
User Manual
®
CPU Core
81
SP SP
(SP) PC
PC dst
Description
– 4
The CALLA instruction decrements the Stack Pointer (R15) by four and stores the current Program Counter value onto the top of the stack. The pushed PC value points to the first instruction
following the CALLA instruction. Then the 32-bit immediate operand is loaded into the Program
Counter and execution of the procedure begins. After the procedure completes, it uses a RET
instruction to pop the previous PC value and return from the procedure.
If the immediate operand is odd, the least significant bit is discarded so that the call destination
address is always an even number.
The CALLA instruction is used to explicitly invoke the 32-bit immediate call opcode in situations when a fixed opcode size is desired, such as a jump table.
Flags
Flags are not affected by this instruction.
Syntax and Opcodes
Instruction, Operands Word 0 Word 1 Word 2
CALLA imm32 F231H imm[31:16] imm[15:0]
Example
Before:
CALLA 00352920H ;Object Code: F231 0035 2920
After:
UM018809-0611 CALLA Instruction
PC=0000_044EH, SP=FFFF_DB22H
PC=0035_2920, SP=FFFF_DB1EH, FFFF_DB1EH=0000_0454H
ZNEO® CPU Core
User Manual
82
CLR
Definition
Syntax
Operation
Description
Clear
CLR dst
dst
0
All bits of the destination operand are cleared to 0.
Flags
Flags are not affected by this instruction.
Syntax and Opcodes
Instruction, Operands Word 0 Word 1 Word 2
CLR Rd {3H, Rd, 00H}
CLR addr16 {ADAH, 1x00B} addr16
CLR addr32 {ADBH, 1x00B} addr[31:16] addr[15:0]
CLR (Rd) {ACH, 1x00B, Rd}
CLR soff14(Rd) {ADCH, Rd} {1xB, soff14}
CLR.W addr16 ADA4H addr16
CLR.W addr32 ADB4H addr[31:16] addr[15:0]
CLR.W (Rd) {AC4H, Rd}
CLR.W soff14(Rd) {ADCH, Rd} {01B, soff14}
CLR.B addr16 ADA0H addr16
CLR.B addr32 ADB0H addr[31:16] addr[15:0]
CLR.B (Rd) {AC0H, Rd}
CLR.B soff14(Rd) {ADCH, Rd} {00B, soff14}
Note:
1. The ZNEO CPU assembler uses an LD opcode to implement CLR Rd.
1
CLR Instruction UM018809-0611
Examples
ZNEO
User Manual
®
CPU Core
83
Before:
CLR B032H:RAM ;Object code: ADA8 B032 or ADAE B032
After:
Before: R7=FFFF_B023H, FFFF_B023H=FCH
CLR.B (R7) ;Object code: AC07
After:
FFFF_B032H=8BF7_47AFH
FFFF_B032H=0000_0000H
FFFF_B023H=00H
UM018809-0611 CLR Instruction
ZNEO® CPU Core
Note:
User Manual
84
COM
Definition
Syntax
Operation
Complement
COM dst
dst
Description
~dst
The contents of the destination operand are complemented (one’s complement). All 1 bits are
changed to 0 and all 0 bits are changed to 1.
Flags
76543210
C Z S V B CIRQE IRQE
0**0*–––
Legend
C = Cleared to 0.
Z = Set to 1 if the result is zero; otherwise, set to 0.
S = Set to 1 if the result msb is 1; otherwise set to 0.
V = Cleared to 0.
B = Set to 1 if the initial destination value was 0; otherwise set to 0.
CIRQE = No change.
IRQE = No change.
Flags are set based on the 32-bit destination register value.
Syntax and Opcodes
Instruction, Operands Word 0 Word 1 Word 2
COM Rd {454H, Rd}
COM Instruction UM018809-0611
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