Zilog Z16C35 User Manual
Z16C35
ISCC
User Manual
UM011002-0808
Copyright © 2008 by Zilog®, Inc. All rights reserved.
ww.zilog.com
w
ISCC
Warning:
User Manual
DO NOT USE IN LIFE SUPPORT
LIFE SUPPORT POLICY
ZILOG'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A
critical component is any component in a life support device or system whose failure to perform can be
reasonably expected to cause the failure of the life support device or system or to affect its safety or
effectiveness.
ii
Document Disclaimer
©2008 by Zilog, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZILOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY
OF THE INFORMATION, DEVICES , OR TECHNOLOGY DESCRIBED IN THIS DOCU MENT.
ZILOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. The information contained within this
document has been verified according to the general principles of electrical and me chanical engineering.
Z8, Z8 Encore!, Z8 Encore! XP, Z8 Encore! MC, Crimzon, eZ80, and ZNEO are trademarks or registered
trademarks of Zilog, Inc. All other product or service names are the property of their respective owners.
UM011002-0808
Revision History
Each instance in Revision History reflects a change to this document from its previous
revision. For more details, refer to the corresponding pages and appropriate links in the
table below.
Revision
Date
Aug 2008 02
June 2001 01 Original issue All
Level Description Page No
ISCC
User Manual
iii
Reformatted with the latest UM template All
UM011002-0808 Revision History
Table of Contents
General Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Interfacing the ISCC™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
BUS INTERFACE UNIT (BIU) DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Non-Multiplexed Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Multiplexed Bus Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Transfers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O INTERFACE CAPABILITIES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
DMA Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
REGISTER ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SCC Cell Register Access, Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
SCC Cell Register Access, Non-Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
SCC Cell Register Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DMA Cell Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DMA Register Access, Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DMA Register Access, Non-Multiplexed Bus Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Notes on Pointer Accesses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Z8 CPU Core
User Manual
iv
ISCC™ DMA and Ancillary Support Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Receiver DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Transmitter DMA Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
BAUD RATE GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
DATA ENCODING/DECODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
DIGITAL PHASE-LOCKED LOOP (DPLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
DPLL Operation in the NRZI Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
DPLL Operation in the FM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
DPLL Operation and Encoding in the Manchester Mode . . . . . . . . . . . . . . . . . . . . . . . 38
CLOCK SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
CRYSTAL OSCILLATORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Data Communication Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
UM011002-0808 Table of Contents
Z8 CPU Core
User Manual
General Description of the Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
General Description of the Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
ASYNCHRONOUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Asynchronous Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Asynchronous Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
BYTE-ORIENTED SYNCHRONOUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Byte Oriented Synchronous Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Byte-Oriented Synchronous Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Transmitter/Receiver Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
BIT-ORIENTED SYNCHRONOUS MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
SDLC Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
SDLC Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
SDLC LOOP MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
SDLC Loop Mode Receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
SDLC Loop Mode Transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
v
Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Write Registers, SCC Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Read Registers, SCC Cell . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
DMA Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
SCC CELL REGISTER OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
WRITE REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Write Register 0 (Command Register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Write Register 1 (Transmit/Receive Interrupt and Data Transfer Mode Definition) . . 94
Write Register 2 (Interrupt Vector) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Write Register 3 (Receive Parameters and Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Write Register 4 (Transmit/Receiver Miscellaneous Parameters and Modes) . . . . . . 100
Write Register 5 (Transmit Parameter and Controls) . . . . . . . . . . . . . . . . . . . . . . . . . 103
Write Register 6 (Sync Characters or SDLC Address Field) . . . . . . . . . . . . . . . . . . . 104
Write Register 7 (SYNC Character or SDLC Flag) . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Write Register 8 (Transmit Buffer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Write Register 9 (Master Interrupt Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Write Register 10 (Miscellaneous Transmitter/Receiver Control Bits) . . . . . . . . . . . 108
Write Register 11 (Clock Mode Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Write Register 12 (Lower Byte of Baud Rate Generator Time Constant) . . . . . . . . . 114
Write Register 13 (Upper Byte of Baud Rate Generator Time Constant) . . . . . . . . . 115
Write Register 14 (Miscellaneous Control Bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Write Register 15 (External/Status Interrupt Control) . . . . . . . . . . . . . . . . . . . . . . . . 118
READ REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Read Register 0 (Transmit/receive buffer Status and External Status) . . . . . . . . . . . . 120
UM011002-0808 Table of Contents
Z8 CPU Core
User Manual
Read Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Read Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Read Register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Read Register 8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Read Register 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Read Register 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Read Register 13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Read Register 15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
DMA CELL REGISTER DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Channel Command/Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
DMA Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Interrupt Vector Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Interrupt Command Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
DMA Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
DMA Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
Receive DMA Count Registers A, B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139
Transmit DMA Count Registers A, B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Receive DMA Address Registers A, B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Transmit DMA Address Registers A, B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Bus Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
vi
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
UM011002-0808 Table of Contents
Chapter 1 General Description
Page 1 of 316
1.1 INTRODUCTION
The Z16C35, ISCC is a CMOS superintegration device with a flexible Bus Interface Unit
(BIU) connecting a built-in Direct Memory Access (DMA) cell to the CMOS Serial Communications Control (SCC) cell.
The ISCC is a dual-channel, multi-protocol data communications peripheral which easily
interfaces
The advanced CMOS process offers lower power consumption, higher performance, and
superior noise immunity. The programming flexibility of the internal registers allow the
ISCC to be configured for a wide variety of serial communications applications. The many
on-chip features such as streamlined bus interface, four channel DMA, baud rate generators, digital phase-locked loops, and crystal oscillators dramatically reduce the need for
external logic. Additional features,
high speed SDLC transfers using on-chip DMA controllers.
to CPU’s with either multiplexed or non-multiplexed address and data buses.
including a 10x19 bit status FIFO, are added to support
ISCC
User Manual
1
The ISCC can address up to 4 gigabytes per DMA channel by using the /UAS and /AS signals to strobe out 32-bit multiplexed addresses.
The ISCC handles asynchronous formats, synchronous byte-oriented protocols such as
IBM Bisync, and synchro
versatile device supports virtually any serial data transfer application (terminals, printers,
diskette, tape drives, etc.).
The device can generate and check CRC codes in any synchronous mode and can be programmed to check data integrity in various modes. The ISCC also has facilities for modem
controls in both channels.
controls can be used for general-purpose I/O.
The standard Zilog interrupt daisy chain is supported for interrupt hiera
nally, the SCC cell has higher interrupt priority than the DMA cell.
The DMA
from each SCC channel, respectively.
The DMA cell adopts a simple fly-by-mode DMA transfer, providing a powerful and efficient DMA acce
Priorities between the four DMA
tions. Arbitration of Bus prior-ity control signals between the ISCC DMA
tem DMA’s should be handled outside the ISCC.
The BIU has a universal interface
write to the ISCC after a hardware reset will
mented.
cell consists of four DMA channels; one for transmit and one for receive to and
ss. The cell does not support memory-to-memory transfer.
nous bit-oriented protocols such as HDLC and IBM SDLC. This
In applications
chan
to most system/CPU bus structures and timing. The first
where these controls are not needed, the modem
rchy control. Inter-
nels are programmable to custom-fit user applica-
and other sys-
configure the bus interface type being imple-
UM011002-0808
ISCC
Page 2 of 316
User Manual
2
1.2 Features
•
•
•
•
•
•
•
UM011002-0808
Figure 1–1. Block Diagram
Low Power CMOS Technology
Two General-Purpose SCC Channels, Four DMA Channels; and Universal Bus Inter-
face Unit
Software Compatible to the Zilog CMOS SCC
Four DMA Channels; Two Transmit and Two Receive Channels to and from the SCC
Four Gigabyte Address Range per DMA Channel
Flyby DMA Transfer Mode
Programmable DMA Channel Priorities
User Manual
Page 3 of 316
•
Independent DMA Register Set
•
A Universal Bus Interface Unit Providing Simple Interface to Most CPUs Multiplexed
or Non-Multiplexed Bus; Compatible with 680X0 and 8X86 CPUs
•
32-Bit Addresses Multiplexed to 16-pin Address/Data Lines
•
8-Bit Data Supporting High/Low Byte Swapping
•
10 MHz Timing
•
12.5 and 16 MHz Timing Planned
•
68-Pin PLCC
•
Supports all Zilog CMOS SCC Features:
•
Two Independent, 0 to 4.0 Mbit/Second, Full-Duplex Channels, Each with a Separate
Crystal Oscillator, Baud Rate Generator, and Digital Phase-Locked Loop Circuit for
Clock Recovery.
ISCC
3
•
Multi-Protocol Operation under Program Control; Programmable for NRZ, NRZI, or
FM Data Encoding.
•
Asynchronous Mode with Five to Eight Bits and One, One and One-Half, or Two Stop
Bits per Character; Programmable Clock Factor; Break Detection and Generation; Parity, Overrun, and Framing Error Detection.
•
Synchronous Mode with Internal or External Character Synchronization on One or
Two Synchronous Characters and CRC Generation and Checking with CRC-16 or
CRC-CCITT preset to either 1’s or 0’s.
•
SDLC/HDLC Mode with Comprehensive Frame-Level Control, Automatic Zero Insertion and Deletion, I-Field Residue Handling, Abort Generation and Detection, CRC
Generation and Ch
•
Local Loopback and Auto Echo modes
•
Supports T1 Digital Trunk
•
Enhanced SDLC 10x19 Status FIFO for DMA Support
•
Full CMOS SCC Register Set
ecking, and SDLC Loop Mode Operation.
UM011002-0808
ISCC
Page 4 of 316
User Manual
4
Figure 1–2. Pin Functions
UM011002-0808
ISCC
ISCC
Z16C35
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
IEO
/INT
/SYNCA
/RTxCA
GND
VCC
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
VCC
N/C
9876543216867666564636261
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
/BUSREQ
PCLK
/SYNCB
/RTxCB
GND
VCC
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
GND
VCC
N/C
RxDA
/TRxCA
TxDA
/DTRA
/R
TSA
/CTSA
/DCDA
GND
N/C
GND
/DCDB
/CTSB
/R
TSB
/DTRB
TxDB
/TRxCB
RxDB
IEI
/W
AIT//READY
/INT
ACK
AI/A//B
A0/SCC//DMA
/CE
/RESET
VCC
N/C
VCC
/AS
/DS
/RD
/WR
R//W
/UAS
/BUSACK
Page 5 of 316
User Manual
5
Figure 1–3. Pin Assignments
UM011002-0808
1.3 Pin Description
Page 6 of 316
The following section describes the Z16C35 pin functions. Figures 1-2 and 1-3 detail the
respective pin functions and pin assignments. All references to DMA are internal.
ISCC
User Manual
6
/CTSA, /CTSB.
enables if they are programmed for Auto Enables (WR3, D5). If these pins are programmed as Auto Enables, a Low on the inputs enables the respective transmitters. If not
programmed as Auto Enables, they
are Schmitt-trigger buffered to accommodate slow rise-time inputs. The SCC cell detects
transitions on these inputs and can interrupt the CPU on both low to high and high to low
transitions.
/DCDA, /DCDB. Data Carrier Detect (inputs,
receiver enables if they are programmed for Auto Enables (WR3 D5), otherwise they are
used as general-purpose input pins. Both pins are Schmitt-trigger buffered to accommodate slow rise time signals. The SCC cell detects transitions on these
rupt the CPU on both low to high and high to low transitions.
/DTR//REQA, /DTR//REQB. Data Terminal
These pins a
DMA request lines. When programmed for the DTR function these outputs follow the
state programmed into the DTR bit of Write Register 5 (WR5, D7). When programmed for
the Ready mode, these pins serve as DMA requests for the transmitter. Note that this DMA
request is not associated with the on-chip DMA and is intended for use in requesting DMA
service from an external DMA.
IEI. Interrupt Enable In (input, active High). IEI is used with IEO to form an interrupt
daisy chain when there is more than one interrupt d
no other higher priority device has an interrupt under service or is requesting an interrupt.
Clear To Send (inp
re programmable (WR14, D2) to serve as either general-purpose outputs or as
uts, active Low). These pins function as transmitter
may be used as general-purpose inputs. Both inputs
active Low). These pins function as
inputs and can inter-
Ready/Request (outputs, active Low).
riven device. A high IEI indicates that
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IEO. Interrupt Enable Out (output, acti
CPU is not servicing the ISCC (SCC or DMA) interrupt or the ISCC is not requesting an
interrupt (Interrupt Acknowledge cycle only). IEO is connected to the next lower priority
device’s IEI input and thus inhibits interrupts from lower priority devices.
/INT. Interrupt (output, active Low). This signal is ac
requests an interrupt. Note that /INT is pulled high and is not an open-drain output.
/INTACK. Interru
that an interrupt acknowledge cycle is in progress. During this cycle, the SCC and DMA
interrupt daisy chain is resolved. The device is capable of returning an interrupt vector that
may be encoded with the type of interrupt pending during this acknowledge cycle when /
RD or /DS become high. /INTACK may be programmed to accept a status acknowledge, a
single pulse acknowledge, or a double pulse acknowledge. This is programmed in the Bus
pt Acknowledge (input, activ
ve High). IEO is High only if IEI is High and the
tivated when the SCC or DMA
e Low). This is a strobe which indicates
ISCC
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User Manual
Configuration Register (BCR). The double pulse acknowledge is co mpatible with 8X86
family microprocessors.
PCLK. Clock (input). This is the master SCC cell and DMA cell clock used to synchronize internal signals. PCLK is a TTL level signal. PCLK is not required to have any phase
relationship with the master system clock.
7
RxDA, RxDB. Receive
Data (inputs, active
High). These input signals receive serial data
at standard TTL levels.
/RTxCA, /RTxCB. Receive/Transmit Clocks (inputs, ac
grammed to several modes of operation. In each channel, /RTxC may supply the rec
tive Low). These pins can be pro-
eive
clock, the transmit clock, the clock for the baud rate generator, or the clock for the Digital
Phase-Locked Loop. These pins can also be programmed for use with the respective /
SYNC pins as a crystal oscillator. The receive clock may be 1, 16, 32, or 64 times the data
rate in asynchronous modes.
/RTSA, /RTSB. Request To Send (outputs, active Low). When the Request To
Send
(R TS) bit in W rite Register 5 is set, the /R TS signal goes Low. When the RTS bit is reset in
the Asynchronous mode and Auto Enable is on, the signal goes High after the transmitter
is empty . In Sync hronous mo de or in Asynchrono us mode with Auto Enable off, the /RTS
pin strictly follows the state of the RTS bit. Both pins can be used as general-purpose outputs.
/SYNCA, /SYNCB. Synchronization (inputs o
r outputs, active Low). These pins can act
either as inputs, outputs, or part of the crystal oscillator circuit. In the Asynchronous
Receive mode (crystal oscillator option not selected), these pins are inputs similar to /CTS
and /DCD. In this mode, transitions on these lines affect the state of the Sync/Hunt status
bits in Read Register 0 but have no other function.
In External Synchronization mode with
act as
inputs. In this mode, /SYNC must be driven Low two receive clock cycles after the
the crystal oscillator not selected, these lines also
last bit in the synchronous character is received. Character assembly begins on the rising
edge of the receive clock immediately preceding the activation of /SYNC.
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In the Internal Synchronization mode (Monosync and Bi-sync) with the crystal oscillator
not selected, these pins act
as outputs and are active only during the part of the receive
clock cycle in which sync condition is not latched. These outputs are active each time a
sync pattern is recognized (regardless of character boundaries). In SDLC mode, the pins
act as outputs and are valid on receipt of a flag. The output is active for one receive clock
period (refer to Chapter 4).
TxDA, TxDB. Transmit Data (outputs, active high). These output signa
ls transmit serial
data at standard TTL levels.
/TRxCA, /TRxCB. Transmit/Receive Clocks (inputs or outputs, active Low). These pins
can be programmed
in several different modes of operation. /TRxC may supply the
receive clock or the transmit clock in the input mode or supply the output of the Digital
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User Manual
Phase-Locked Loop, the crystal os cillator, the baud rate generator, or the transmit clock in
the output mode.
/CE. Chip Enable (input, active Low). This signal selects the ISCC for a peripheral read or
write operation. This signal is ignored when the ISCC is bus master.
8
AD15-AD0. Data bus (bidirectional, tri-state). Thes
e lines carry data and commands to
and from the ISCC.
/RD. Read (bidirectional
, active Low). When the ISCC is a
peripheral (i.e., bus slave), this
signal indicates a read operation and when the ISCC is selected, enables the ISCC’s bus
drivers. As an input, /RD indicates that the CPU wants to read from the ISCC read registers. During the Interrupt Acknowledge cycle, /RD gates the interrupt vector onto the bus
if the ISCC is the highest priority
device requesting an interrupt. When the ISCC is the bus
master, this signal is used to read data. As an output, after the ISCC has taken control of
the system buses, /RD indicates a DMA-controlled read from a memory or I/O port
address.
/WR. Write (bidirectional, active Low). When the ISCC is selected, this signal indicates a
write operation. As an input, this indicates that t
he CPU wants to write control or command bytes to the ISCC write registers. As an output, after the ISCC has taken control of
the s
ystem buses /WR indicates a DMA-controlled write to a memory or I/O port address.
/DS. Data Strobe (bidirectional, active Low). A Low on this signal indicates
that the
AD15-AD0 bus is used for data transfer. When the ISCC is not in control of the system
bus and the external system is transferring information to or from the ISCC, /DS is a timing input used by the ISCC to move data to or from the AD15-AD0 bus. Data is written
into the IS
CC by the external system on the High to Low /DS transition. Data is read from
the ISCC by the external system while /DS is Low. There are no timing requirements
between /DS as an input and ISCC clock; this allows use of the ISCC with a system bus
which does not have a bussed clock.
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During a DMA operation when the ISCC is in control of the system, /DS is an output gen-
ed by the ISCC and used by the system to move data to or from the AD15-AD0 bus.
erat
When the ISCC has bus control, it writes
to the external system by placing data on the
AD15-AD0 bus before the High-to-Low /DS transition and holds the data stable until after
the Low-to-High /DS transition; while reading from the external system, the Low-to-High
transition of /DS inputs data from the AD15-AD0 bus into the ISCC.
R//W. Read/Write (bidirectional). Read polarity is High and write polarity is Low
. When
the ISCC is not in control of the system bus and the external system is transferring information to or from the ISCC, R//W is a status input used by the ISCC to determine if data is
entering or leaving on the
AD15-AD0 bus during /DS time. In such a case, Read (High)
indicates that the system is requesting data from the ISCC and Write (Low) indicates that
the system is presenting data to the ISCC. The only timing requirements for R//W as an
input are defined relative to /DS. When the ISCC is in control of the system bus, R//W is
an output generated by the ISCC, with Read (high) indicating that data is being requested
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User Manual
from the addressed location or device, and Write (low) indicating that data is being presented to the addressed location or device.
9
/UAS. Upper Address Strobe (O
utput, active Low). This signal is used if the output
address is more than 16-bit. The upper address, A31-A16, can be latched externally by the
rising edge of this signal. /UAS is active first before /AS becomes active. This signal and /
AS are used by the DMA cell.
/AS. Lower Address Strobe (bidirectional, active Low). When the ISCC is bus master , this
signal is an output, and is used a
junction with /UAS since the address is 32-bits. This signal and /UAS are us
s a lower address strobe for AD15-AD0. It is used in con-
ed by the
DMA cell when it is bus master. When ISCC is not bus master, this signal is used in the
multiplexed bus modes to latch the address on the AD lines. The /AS signal is not used in
the non-multiplexed bus modes and should be tied to VCC through a resistor in these
cases.
/WAIT//RDY. Wait/Ready (bidirectional, active
Low). This signal may be programmed
to function either as a W ait signal or Ready signal during the BCR write. When the BCR is
written to Channel A (A1/A//B High during the BCR write), this signal functions as a /
WAIT and thus supports the READY function of 8X86 microprocessors family. When the
BCR writes to Channel B (A1/A//B Low), this signal functions as a /READY and supports
the /DTACK function of the 680X0 microprocessor family.
This signal is an output when the ISCC in not bus master. In this case, the /Wait//RDY signal
indicates when the data is available during a read cycle; when the device is rea
dy to
receive data during a write cycle; and when a valid vector is available during an interrupt
acknowledge cycle.
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When the ISCC is the bus master (the DMA cell has taken control of the bus), the /Wait//
RDY signa
l functions as a /WAIT or /READY input. Slow memories and peripheral
devices can assert /WAIT to extend /DS during bus transfers. Similarly, memories and
peripherals use /READY to indicate that its output is valid or that it is ready to latch input
data.
/BUSACK. Bus Acknowledge (input, active Low). Signals the bus has been released to
the DMA. If th
e /BUSACK goes inactive before the DMA transfer is completed, the cur-
rent DMA transfer is aborted.
/BUSREQ. Bus Request (output, active Low). This signal is used by
the DMA to obtain
the bus from the CPU.
A0/SCC//DMA. DMA Channel/SCC Select/DMA Select (bidirectional). When this pin
is
used as input, a high selects the SCC cell and a low selects the DMA cell, (during BCR
Write should be kept Low). When this pin is used as output, the signal on this pin is used
in conjunction with A1/A//B pin output to identify which DMA channel is active. This
information can be used by the user to determine whether to issue a DMA abort command.
A0/SCC//DMA and A1/A//B output encoding is shown on the following page.
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A1/A//B A0/SCC//DMA DMA channel
1 1 RxA
1 0 TxA
0 1 RxB
0 0 TxB
A1/A//B. DMA Channel/Channel A/Channel B (bidirectional). This signal, when used as
input, selects the SCC channel in which the read and write operation occurs. Note that A0/
SCC//DMA pin must be held high to select this feature. When this pin is used as an output,
it is used in conjunction with the A0/SCC//DMA pin output to identify which DMA chan
nel is active. During a DMA peripheral access, the A1/A//B pin is ignored.
10
-
/RESET. (input, active Low). This signal resets the
write to the ISC
C after a reset accesses the BCR to select additional bus options for the
device.
device to a known state. The first
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Chapter 2 Interfacing the ISCC™
Page 11 of 316
2.1 Introduction
This chapter details the interfacing of the 16C35 ISCC to a system. Covered in this chapter
is a description of the Bus Interface Unit (BIU) and information about the ISCC in nonmultiplexed and multiplexed bus operation. The following section entails the ISCC’s
capabilities for three types of I/O operations: polling, interrupt (vectored or non-vectored),
and DMA Transfer modes. Also included in this chapter is information about the ISCC
registers and register access.
2.2 BUS INTERFACE UNIT (BIU) DESCRIPTION
ISCC
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11
The ISCC™ contains a flexible bus interface that is compatible with a variety of microprocessors and microcontrollers. The device is designed
tems and may be used with address/data multiplexed buses or non-multiplexed buses. The
bus interface style is selec
The ISCC contains a Bus Configuration Register, the BCR. This register has no address
and is only accessible in the first transac
transaction must be a write with AØ/sec//DMA Low and is automatically directed to the
Bus Configuration Register by the ISCC. The Bus Configuration Register contains bits
which program the byte swapping feature, the interrupt acknowledge type and other
aspects of the bus interface configuration. Refer to Chapter 5 for BCR details.
The multiplexed bus is selected for the ISCC if there is an Address Strobe prior to or during the transaction wh
ing the transaction which writes the BCR, a non-multiplexed bus is selected. The
strobe is recognized whether or not the ISCC Chip Enable
ted by certain actions which take place after a hardware reset.
tion to the ISCC after a hardware reset; this first
ich writes the BCR. If no Address Strobe is present prior to or dur-
2.2.1 Non-Multiplexed Bus Operation
When the ISCC is initialized for non-multiplexed operation, register addressing for the
ISCC cell is (with the ex-ception of WR0 and RR0), accomplished using an internal
pointer accessed via WR0. Accessing internal registers by this means is a two step operation requiring a write to the pointer followed by access of the desired regist
described in detail in later sections. Note that when the DMA is not used to address the
data, the data registers must be accessed by pointing to Register 8. (This is in contrast to
the Z8530 which allows direct addressing of the data registers through the C/D pin.)
to work with 8- or 16-bit bus sys-
address
is active.
er. This is
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When the ISCC is initialized for non-multiplexed operation, register addressing for the
DMA cell (with the exception of CS
in the SCC cell. In this case the pointer is accessed in the Command Status Address Regis-
AR) is accomplished in a manner similar to that used
ter (CSAR bits 4 - 0). The SCC cell and DMA cell pointers are independent. Detailed
Page 12 of 316
operation is described in a later section.
2.2.2 Multiplexed Bus Operation
When the ISCC is initialized for multiplexed bus operation, all registers in the SCC cell
are directly addressable with the register address occupying AD5 through AD1, or AD4
through AD0 (Shift Left/Shift Right modes). The A0/SCC //DMA pin controls the SCC
cell /DMA selection. The SCC cell channel A/B selection may be controlled either by the
A0/A//B pin or by the A/B selection in the address on AD7-AD0 that is strobed into the
ISCC with /AS. Use of this re-quires that the unused SCC channel select option to be set to
Channel A. That is, if the A0/A//B pin is used to select the channel, then the AD bit for
channel selection must select channel A (the actual bit is determined by the Shift Left/
Shift Right mode employed) and conversely, if the AD bus bit is used to select the channel, then the A0/A//B pin must select channel
pin descriptions for the e
ncoding of these signals.
ISCC
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12
A. Refer to the A0/SCC//DMA and A1/A//B
In the multiplexed bus mode of operation, the register pointer in WR0 of the SCC ce
ignored and has no effec
t on the accessing of the internal registers. Register access is made
ll is
solely through the latched address. However, the pointer in the DMA Channel Command/
Address Register functions in the multiplexed bus mode and may be used to access DMA
registers in a manner identical to that in the non-multiplexed bus mode. To use the DMA
pointer in the multiplexed bus mode, the multiplexed address must always address the
CCAR of the DMA even though the actual register access will be made according to the
pointer. This requires that in the normal multiplexed mode of operation with register
access through the latched address, writes to the DMA CCAR must always write zeros to
the pointer field.
In the multiplexed bus mode in some host configurations, address A0 may be used for byte
transfer control in 16-bit systems. Therefore, it may be necessary to ignore A0 in the register decode. This is accommodated in the IS
CC by providing an option to decode the multiplexed address from A1 upwards rather than from A0 upwards. This option is the Shift
Left/Shift Right mode. The Shift
Left/Shift Right modes for the address decoding for the
internal registers (multiplexed bus) are separately programmable for the SCC cell and for
the DMA cell. For the SCC cell the programming and operation is identical to that in the
SCC; programming is accomplished through Write Register 0 (WR0), bits 1 and 0 (Figure
5-2). The programming of the Shift Left/Shift Right modes for the DMA cell is accomplished in the BCR, bit 0. In this case, the shift function is similar to that for the SCC cell;
with Shift left, the internal register addresses are decoded from
bits AD5 through AD1 and
with Shift Right, the internal register addresses are decoded from bits AD4 through AD0.
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When the multiplexed bus mode is selected, Write Register 0 (WR0) takes on the form of
WR0
in the Z8030 (Figure 5-2).
2.2.3 Data Transfers
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All data transfers to and from the ISCC are done in bytes even though the data may at special times occupy the lower or upper byte of the 16-bit bus. Bus transfers as a slave peripheral are done diffe
transactions. The ISCC is fundamentally an 8-bit peripheral but supports 16-bit buses in
the DMA mode. Slave peripheral and DMA transactions are described in the next paragraphs.
Data Bus Transfers as a Slave Peripheral: When accessed as a peripheral device (when
the
ISCC is not a bus master performing DMA transfers), only 8 bits are t ransferred. When
the ISCC registers are read, the byte data present on the lower 8 bits of the bus is replicated on the upper 8 bits of the bus. Data is accepted by the IS
of the bus.
rently than bus transfers when the ISCC is the bus master dur
ISCC
User Manual
13
ing DMA
CC only on the lower 8 bits
ISCC DMA Bus Transf ers: During DMA transfers, when the ISCC is bus master
, only
byte data is transferred. However, data may be transferred from the ISCC on the upper 8
bits of the bus or on the lower 8 bits of the bus. Moreover, odd or even byte transfers may
be done on the lower or upper 8 bits of the bus. This is programmable and is described
below.
During DMA transfers to memory from the ISCC, byte data only is transferred and the
data appears on the lower 8 bits and is replicated on
the upper 8 bits of the bus. Thus the
data may be written to an odd or even byte of the system memory by address decoding and
strobe generation.
During DMA transfers to the ISCC from memory, byte data only is transferred and normally data is acce
feature may be
pted only on the lower 8 bits of the bus. However, the byte swapping
used to enable data to be accepted on either the lower or upper 8 bits of the
bus. The byte swapping feature is enabled by programming the Byte Swap Enable bit to a
1 in the BCR. The odd/even byte transfer selection is made by programming the Byte
Swap Select bit in the BCR. If Byte Swap Select is a 1, then even address bytes (transfers
where the DMA address has A0 equal 0) are accepted on the lower 8 bits of the bus and
odd address bytes (transfers where the DMA address has A0 equal 1) are accepted on the
upper 8 bits of the bus. If Byte Swap Select is a 0, then even address bytes (transfers where
the DMA address has A0 equal 0) are accepted on the upper 8 bits of the bus and odd
address bytes (transfers where the DMA address has A0 equal 1) are accepted on the lower
8 bits of the bus.
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Table 2–1. ISCC Bus Access Summary
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14
Byte
Process
Read X X data same data
Write X X data read data ignored
DMA Write 0 X data same data
DMA Read 0 X data read data ignored
DMA Write 1 X data same data
DMA Read 1 0 depends upon A0
Enable
Swap
Select Lower 8 Bits Action on Bus Upper 8 Bits
(see below)
In the DMA Read with Byte Swap enabled:
Byte Swap Select A0 ISCC Accepts Data
0 0 Upper 8 Bits of Bus
0 1 Lower 8 Bits of Bus
1 0 Lower 8 Bits of Bus
1 1 Upper 8 Bits of Bus
In this table DMA read refers to a DMA controlled transfer from memory to the ISCC and
DMA write refers to a DMA controlled transfer from the ISCC to memory. Read refers to
a normal peripheral transaction where the CPU reads data from the ISCC and Write refers
to a normal peripheral transaction where the CPU writes data to the ISCC.
2.3 I/O INTERFACE CAPABILITIES
The ISCC offers the choice of Polling, Interrupt (vectored or non-vectored), and DMA
Transfer modes to transfer data, status, and control information to and from the CPU.
2.3.1 Polling
In this mode all interrupts and the DMA’s are disabled. Three status registers in the SCC
are automatically updated whenever any function is performed. For example, end-offrame in SDLC mode sets a bit in one of these status registers. With polling, the CPU must
periodically read a status register until the register contents indicate the need for some
CPU action to be taken. Only one register in the SCC cell needs to be read; depending on
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the contents of the register, the CPU either reads data, writes data, or satisfies an error con-
Page 15 of 316
dition. Two bits in the register indicate the need for data transfer. An alternativ
the Interrupt Pending register to determine the source of an interrupt. The status for both
SCC channels resides in one register.
2.3.2 Interrupts
When the ISCC responds to an Interrupt Acknowledge signal (INTACK) from the CPU,
an interrupt vector is placed on the data bus. Both the SCC and the DMA contain vector
registers. Depending on the source of interrupt, one of these vectors is returned, either
unmodified or modified by the interrupt status to indicate the exact cause of the interrupt.
ISCC
User Manual
15
e is to poll
Each of the six sources of interrupt in the SCC (Transmit, Receive, and External/S
tatus
interrupts in both channels) and each DMA channel has three bits associated with interrupt
source: Interrupt Pending (IP), Interrupt Under Service (IUS), and Interrupt Enable (IE). If
the IE bit is set for any given source of interrupt, then that source can request interrupts.
The only exception to this rule is when the associate Master Interrupt Enable (MIE) bit is
reset, then no interrupts are requested. Both the SCC cell and the DMA have an associated
MIE bit. The IE bits in the SCC cell are write only, but the IE bits in the DMA are read/
write.
The ISCC provides for nesting of interrupt sources with an interrupt daisy chain using the
IEI, IEO, and /INT
ACK pins. As a microprocessor peripheral, the ISCC may request an
interrupt only when no higher priority device is requesting one, e.g., when IEI is High. If
the device in question requests an interrupt, it enables the /INT signal. The CPU then
responds with /INTACK, and the interrupting cell places the ve ctor on the data bus.
In the ISCC, the IP bit signals a need for interru
pt servicing. When
an IP bit is 1 and the
IEI input pin is High, the /INT signal is activated, requesting an interrupt. In the SCC cell,
if the IE bit is not set, then the IP for that source can never be set. The IP bits in the DMA
cell are set independent of the IE bit.
The IUS bits signal that an interrupt request is being ser-viced. If an IUS is set, all interrupt sources of lower priority in the
ISCC and external to the ISCC are preve
nted from
requesting interrupts. The internal interrupt sources are inhibited by the state of the internal daisy chain, while lower priority devices are inhibited by the IEO output of the ISCC
being pu
lled Low and propagated to subsequent peripherals. Internally, the SCC cell is
higher priority than the DMA cell. An IUS bit is set during an Interrupt Acknowledge
cycle if there are no higher priority devices requesting interrupts. The IUS bit must be
cleared by the CPU. This is usually done at the end of the correspond-ing interrupt service
routine.
UM011002-0808
Within the SCC portion of the ISCC there are three types of interrupts: Transmit, Re
ceive,
and External/Status. Each interrupt type is enabled under program control with Channel A
having higher priority than Channel B, and with Receive, Transmit, and External/Status
interrupts prioritized in that order within each channel. When the Transmit interrupt is
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User Manual
enabled, the CPU is interrupted when the transmit buf fer becomes empty. This implies that
data has shifted from the transmit buffer to the transmitter, thus emptying the transmit buf
fer. When enabled, the receiver interrupts the CPU in one of three ways:
16
-
1. Interru
pt on First Receive Character or Special Receive Condition
2. Interrupt on All Receive Characters or Special Receive Condition
3. Interrupt on Special Condition Only
Interrupt on First Character or S
are typically used w
hen doing block transfers with the DMA. A Special Receive Condi-
pecial Condition, and Interrupt on Special Condition Only ,
tion is one of the following: receiver overrun, framing error in Asynchronous mode, endof-frame in SDLC mode and, optionally, a parity error. The Special Receive Condi-tion
inter
rupt is different from an Ordinary Receive Character Available interrupt only by the
status placed in the vector during the Interrupt Acknowledge cycle. In Interrupt on First
Receive Character, an interrupt occurs from Special Receive Conditions any time after the
First Receive Character interrupt.
The main function of the External/Status interrupt is to monitor the signal transitions of
the /CTS
, /DCD, and /SYNC pins; however, an External/S tatus i nterrupt is also caused by
a Transmit Underrun condition, or a zero count in the baud rate generator, or by the detection of a Break (Asynchronous mode), Abort (SDLC mode) or EOP (SDLC Loop mode)
sequence in the data s
tream. The interrupt caused by the Abort or EOP has a special feature allowing the ISCC to interrupt when the Abort or EOP sequence is detected or terminated.
This feature facilitates the proper termination of the current message, correct
initialization of the next message, and th
e accurate timing of the Abort condition in exter-
nal logic.
2.3.3 DMA Interrupts
UM011002-0808
Each DMA in the ISCC has two sources of interrupt, which share an IP bit and an IUS bit,
but have independent enables: Terminal Count and Abort. The Abort interrupt is generated
when an active DMA channel is forced to terminate its transfers because /BUSACK is deasserted during a transfer. The Terminal Count interrupt is generated when the DMA transfer count reaches zero. The DMA channels themselves are prioritized in a fixed order:
Receive
A, Transmit A, Receive B, and Transmit B.
When DMA transfers are used, the on-chip DMA channels transfer data directly to the
transmit buffers or directly from the receive buffers. No other tra
nsfers are possible (for
initialization, for example). The request signals from the receivers and transmitters are
hard-wired to the request inputs of the DMA channels internally. Each DMA channel provides a 32-bit address which is either incremented or decremented with a
16-bit transfer
length. Whenever a DMA channel receives a request from its associated receiver or transmitter and the DMA channel is enabled, the ISCC activates the /BUSREQ signal. Upon
ipt of an active /BUSACK, the DMA channel transfers data between memory and the
rece
SCC cell. This transfer continues until the receiver or transmitter stops requesting a trans-
fer or until the terminal count is reached, or /BUSACK is deactivated. The four DMA
Page 17 of 316
channels operate independently when the Request Per Channel option is selected; other
wise, all requests pending at the time of bus acquisition will be serviced be
released. Each DMA channel is independently enabled and disabled.
2.4 REGISTER ACCESS
ISCC registers may be accessed explicitly, directly or indirectly. Explicit addressing
occurs only for three registers in the ISCC: these are the Bus Configuration Register (for
the first write after a hardware reset), the RDR (Receive Data Register) by a fly-by DMA
read, and the TDR (Transmit Data Register) by a fly-by DMA write. In the non-multiplexed bus case, only WR0/RR0 of the SCC cell and only the Channel Command/Address
Register of the DMA cell are
pointers in these directly accessed registers. In the multiplexed bus case, all registers
(except the WR0, RR0 and CCAR) are accessed through a two step address/read-write bus
transaction. In this case there are two options available for address decoding: shift right
and shift left. These options are independently selectable for both the SCC cell and the
DMA cell.
ISCC
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17
-
fore the bus is
accessed directly. Other registers are accessed using the
2.4.1 SCC Cell Register Access, Multiplexed Bus
The registers in the ISCC in the multiplexed bus mode are addressed via the address on
AD7-AD0 which is latched by the rising edge of /AS. As discussed in the paragraphs
below, the address contains a bit to select the SCC cell channel (A or B). Although this
selection is in the address, the A1/A//B input remains active and must be set to select
Channel A for the selection bit in the AD7-AD0 address to function correctly . Conversely,
the A1/A//B pin may also be used to select the channel instead of the bit in the AD7-AD0
address. In this case, the bit in the AD7-AD0 address must be set to select Channel A for
the A1/A//B input to function correctly.
There are two address decoding modes: shift left and shift right. In shift left mode, the register address is deco
In the shift left mode
Select bit, A/B, is decoded from AD5. The register map for this case is shown in
Table 2-2.
ded from AD5-AD1. This mode is set by a hardware reset.
, the register address itself is placed on AD4-AD1 and the Chan
nel
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Page 18 of 316
Table 2–2. SCC Cell Address Map, Multiplexed Bus Mode, Shift Left
Address AD5-AD1 Write Read
10000 WR0A RR0A
10001 WR1A RR1A
10010 WR2 RR2A
10011 WR3A RR3A
10100 WR4A (RR0A)
10101 WR5A (RR1A)
10110 WR6A (RR2A)
10111 WR7A (RR3A)
11000 WR8A RR8A
11001 WR9 (RR13A)
11010 WR10A RR10A
11011 WR11A (RR15A)
11100 WR12A RR12A
11101 WR13A RR13A
11110 WR14A (RR10A)
11111 WR15A RR15A
Note: The above table applies to Channel “B” also.
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In Shift Right Mode, bits 0-1 in WR0A controls which bits will be decoded to form the
register address. It is placed in this register to simplify programming when the current
state of the Shift Right/Shift Left bit is not known.
The register address is decoded from AD4-AD0. The Shift Right/Shift Left bit is written
via command to make the software writing to WR0 independent of the state of the Shift
Right/Shift Left bit.
AD4-AD0 is the actual register address and AD0
determines the channel se
lection (A//B).
The register map is shown in Table 2-3.
Because the ISCC SCC Cell does not contain 16 read registers, the decoding of the read
registers is not complete; this is indicated in Table 2
-2 and Table 2-3 by parentheses
around the register name. These addresses may also be used to access the read registers.
Note also that in the multiplexed bus mode, only one WR2 and
WR9 are shown in the
address map; these registers may be written from either SCC cell channel.
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Table 2–3. SCC Cell Address Map, Multiplexed Bus Mode, Shift Right
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Address
AD4-AD0 Write Read
00000 WR0B RR0B
00001 WR0A RR0A
00010 WR1B RR1B
00011 WR1A RR1A
00100 WR2 RR2B
00101 WR2 RR2A
0011 0 WR3B RR3B
00111 WR3A RR3A
01000 WR4B RR0B
01001 WR4A RR0A
01010 WR5B (RR1B)
01011 WR5A (RR1A)
01 100 WR6B RR2B
01 101 WR6A RR2A
01110 WR7B (RR3B)
01111 WR7A (RR3A)
10000 WR8B RR8B
10001 WR8A RR8A
10010 WR9 (RR13B)
10011 WR9 (RR13A)
10100 WR10B RR10B
10101 WR10A RR10A
10110 WR11B (RR15B)
10111 WR11A (RR15A)
11000 WR12B RR12B
11001 WR12A RR12A
11010 WR13B RR13B
11011 WR13A RR13A
11100 WR14B (RR10B)
11101 WR14A (RR10A)
11110 WR15B RR15B
11111 WR15A RR15A
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2.4.2 SCC Cell Register Access, Non-Multiplexed Bus
The registers in the SCC cell in the non-multiplexed bus mode are accessed in a two-step
process, using a Register Pointer to perform the addressing. To access a particular register,
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the pointer bits must be set by writing to WR0 bits 2, 1, and 0 and, if required, using the
Point High command to extend the three bit pointer to registers 8 through
15. This write to WR0 to set the pointer bits may be done in either channel. There is only
one pointer register and it is used for both A and B channels. After the pointer bits are set,
the next read or write cycle to the SCC cell will access the desired register in the channel
selected during this read or write cycle. At the conclusion of this read or write cycle, the
pointer bits are reset to “0s,” so that the next access will be to WR0.
The fact that the pointer bits are reset to “0,” unless explicitly set otherwise, means that
WR0 and RR0 may also
be accessed in a single cycle. That is, it is not necessary to write
the pointer bits with “0” before accessing WR0 or RR0. There are three pointer bits in
WR0, and these allow access to the registers with addresses 0 through 7. Note that a command may be written to WR0 at the same time that the pointer bits are written.
To a
ccess the registers with addresses 8 through 15, a special command must accompany
the poi
nter bits; WR0(4-3)=001. This precludes concurrently issuing a command when
pointing to these registers. The register map for the ISCC in the non-multiplexed bus
mode is shown in Table 2-4 below. If, for some reason, the state of the pointer bits is
unknown, they may be reset to “0” by performing a read cycle of the SCC cell. Once the
pointer bits have been set, the desired channel is selected by the state of the A1/A//B pin
during the actual read or write of the desired SCC cell register.)
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Table 2–4. SCC Cell Register Address Map Using Pointer (Non-multiplexed Bus Mode)
Using Null Command
A1/A//B
Address
D2 D1 D0
Write
Register
Read
Register
0 000 WR0B RR0B
0 001 WR1B RR1B
0 010 WR2 RR2B
0 011 WR3B RR3B
0 100 WR4B (RR0B)
0 101 WR5B (RR1B)
0 110 WR6B (RR2B)
0 111 WR7B (RR3B)
1 000 WR0A RR0A
1 001 WR1A RR1A
1 010 WR2 RR2A
1 011 WR3A RR3A
1 100 WR4A (RR0A)
1 101 WR5A (RR1A)
1 110 WR6A (RR2A)
1 111 WR7A (RR3A)
Using Point High Command
A1/A//B
Address
D2 D1 D0
Write
Register
Read
Register
0 000 WR8B RR8B
0 001 WR9 RR13B
0 010 WR10B RR10B
0 011 WR11B (RR15B)
0 100 WR12B RR12B
0 101 WR13B RR13B
0 110 WR14B (RR10B)
0 111 WR15B RR15B
1 000 WR8A RR8A
1 001 WR9A (RR13A)
1 010 WR10A RR10A
1 011 WR11A (RR15A)
1 100 WR12A RR12A
1 101 WR13A RR13A
1 110 WR14A (RR10A)
1 111 WR15A RR15A
Page 21 of 316
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2.4.3 SCC Cell Register Reset
2
Register Hardware Reset Channel Reset
WR0 00000000 00000000
WR1 00x00x00 00x00x00
WR2 xxxxxxxx xxxxxxxx
WR3 xxxxxxx0 xxxxxxx0
WR4 xxxxx1xx xxxxx1xx
WR5 0xx0000x 0xx0000x
WR6 xxxxxxxx xxxxxxxx
WR7 xxxxxxxx xxxxxxxx
WR9 110000xx xx0xxxxx
WR10 00000000 0xx00000
WR11 00001000 xxxxxxxx
WR12 xxxxxxxx xxxxxxxx
WR13 xxxxxxxx xxxxxxxx
WR14 xx100000 xx1000xx
WR15 11111000 11111000
RR0 01xxx100 01xxx100
RR1 00000110 00000110
RR3 00000000 00000000
RR10 00000000 00000000
Page 22 of 316
Table 2-5 lis t s the contents of the SCC cell registers after a hardware reset and after a
channel reset.
Table 2–5. SCC Cell Reset Value
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2.4.4 DMA Cell Registers
The DMA cell contains seventeen registers counting the Bus Configuration Register. All
of these registers are read/write exept the Bus Configuration Register (write only), the
Channel Command Address Register (write only), the DMA Status Register (read only),
the Interrupt Command Register (write only), and the Interrupt Status Register (read only).
The reset content of all of the DMA registers identified in the address map is all zeroes.
2.4.5 DMA Register Access, Multiplexed Bus
The registers in the ISCC in the multiplexed bus mode are addressed via the address on
AD7-AD0 which is latched by the rising edge of /AS.
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There are two address decoding modes: shift left and shift right. In shift left mode, the
register address is decoded from AD5-AD1. This mode is set by a hardware reset. In Shift
right mode, the register address is decoded from AD4-AD0. The shift right/shift left selec
tion for the DMA is located in the Bus Confi
guratin Register, bit D0. When set, this bit
programs the Shift Right mode for the DMA and when reset, this bit programs the Shift
Left Mode.
The address map for the DMA registers is shown in Table 2-6. This Table is also applicable to the non-multiplexed bus mode.
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Table 2–6. DMA Address Map
Address* Name Description
xxxxx BCR Bus Configuration Register
00000 CCAR Channel Command/Address Register (Write)
00000 DSR DMA Status (Read)
00001 ICR Interrupt Control Register
00010 IVR Interrupt Vector Register
00011 ICSR Interrupt Command Register (Write)
00011 ISR I nterrupt Status Register (Read)
00100 DER DMA Enable/Disable Register
00101 DCR DMA Control Register
00110 Reserved Address
00111 Reserved Address
01000 RDCRA Receive DMA Count Register, Channel A (Low Byte)
01001 RDCRA Receive DMA Count Register, Channel A (High Byte)
01010 TDCRA Transmit DMA Count Register, Channel A (Low Byte)
01011 TDCRA Transmit DMA Count Register, Channel A (High Byte)
01100 RDCRB Receive DMA Count Register, Channel B (Low Byte)
01101 RDCRB Receive DMA Count Register, Channel B (High Byte)
01110 TDCRB Transmit DMA Count Register, Channel B (Low Byte)
01111 TDCRB Transmit DMA Count Register, Channel B (High Byte)
10000 RDARA Receive DMA Address Register, Channel A (Bits 0-7)
10001 RDARA Receive DMA Address Register, Channel A (Bits 8-15)
10010 RDARA Receive DMA Address Register, Channel A (Bits 16-23
10011 RDARA Receive DMA Address Register, Channel A (Bits 24-31)
10100 TDARA Transmit DMA Address Register, Channel A (Bits 0-7)
10101 TDARA Transmit DMA Address Register, Channel A (Bits 8-15)
10110 TDARA Transmit DMA Address Register, Channel A (Bits 16-23)
10111 TDARA Transmit DMA Address Register, Channel A (Bits 24-31)
11000 RDARB Receive DMA Address Register, Channel B (Bits 0-7)
11001 RDARB Receive DMA Address Register, Channel B (Bits 8-15)
11010 RDARB Receive DMA Address Register, Channel B (Bits 16-23)
11011 RDARB Receive DMA Address Register, Channel B (Bits 24-31)
11100 TDARB Transmit DMA Address Register, Channel B (Bits 0-7)
11101 TDARB Transmit DMA Address Register, Channel B (Bits 8-15)
11110 TDARB Transmit DMA Address Register, Channel B (Bits 16-23)
11111 TDARB Transmit DMA Address Register, Channel B (Bits 24-31)
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