Zilog Z16C30 User Manual
Z16C30
USC
User’s Manual
UM009402-0201
ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
Z16C30
USC
This publication is subject to replacement by a later edition. To determine whether a later
edition exists, or to request copies of publications, contact:
ZiLOG Worldwide Headquarters
910 E. Hamilton Avenue
Campbell, CA 95008
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
Document Disclaimer
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products
and/or service names mentioned herein may be trademarks of the companies with which they are associated.
©2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded. ZiLOG,
INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF
THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG
ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT
RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY
DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No
licenses are conveyed, implicitly or otherwise, by this document under any intellectual property rights.
UM009402-0201
ZILOG
UM009402-0201
Z16C30 USC® USER'S MANUAL
Thank you for your interest in Zilog's high-speed Integrated Universal Serial Controller.
To aid the designer, the following support material is available when designing
a High Performance Serial Communication application based on Zilog's USC.
Z16C30 User's Manual
Zilog's USC® User's Manual is a comprehensive breakdown of the functions and features of the USC which will
aid in the development of your application. A good place
to start is the
manual, which provides a short description of each feature
Overview
section at the beginning of the
Z16C30 USC® USER'S MANUAL
SUPPLEMENTARY INFORMATION
and chapter. Then any chapter can be reviewed in more
detail as necessary. This User's Manual provides in-depth
descriptions of all functions and features of the USC as well
as supporting block diagrams, timing diagrams, and sample
applications.
Z16C30 Product Specification
The USC® Product Specification is a good resource to help
determine which of Zilog's High Performance Serial Controllers to use. This document provides an in-depth description of the USC, including descriptions of features,
block diagrams, pin assignments, pin descriptions, register bit functions, and AC and DC specifications. This
Application Notes
The following Application Notes are useful in demonstrating how the USC can be used in different applications.
Design a Serial Board to Handle Multiple Protocols
This Application Note details an approach to handling
multiple serial communication protocols using Zilog's
Z16C30 USC. This document is included in the High
Speed SCC Databook, DC-8314-01 mentioned above.
Demonstration/Evaluation Boards
By selecting the board that most closely resembles your
desired application, you may be able to use parts of the
design in your implementation. These boards can be used
as software platforms while the application hardware is
being developed.
Z8018600ZCO - This kit contains an assembled circuit
board, software, and documentation to support the evaluation and development of code for Zilog's Z16C30 USC,
Z16C32 IUSC, Z85C30 SCC, Z85230 ESCC, and Z16C35
specification can be found in the High Speed Serial Communication Controllers Databook, DC-8314-01, which also
includes a product specification on the Z16C30 USC as
well as related Application Notes, support products, and a
list of third party support vendors.
The Zilog Datacom Family with the 80186 CPU
This Application Note, DC-2560-03, explains and illustrates how Zilog's datacom family interfaces and communicates with the 80186 on an evaluation board.
ISCC. The purpose of the board is to illustrate how the
datacom family interfaces and communicates with the
80186 CPU. This will help potential customers evaluate
Zilog's datacommunications with the 80186 CPU. A boardresident monitor program allows code to be downloaded
and executed. A specification on this product is included
in the High Speed Serial Communication Controllers
Databook, DC-8314-01 mentioned above.
UM97USC0100
ZILOG
UM009402-0201
Demonstration/Evaluation Boards (Continued)
Z16C30 USC® USER'S MANUAL
SUPPLEMENTARY INFORMATION
Z16C3001ZCO - This kit contains an assembled PC/XT/AT
circuit board with two high-speed serial connections, DB9
and DB25 connectors selectively driven by RS-232 or
RS422 line drivers.
The kit also contains software and documentation to support software and hardware development for Zilog's USC.
The board illustrates the use of Zilog's USC in communications applications such as ASYNC, SDLC/HDLC and highspeed ASYNC. (Please refer to the Product Specification
Databook for a detailed description.)
© 1997 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.com
UM97USC0100
ZILOG
UM009402-0201
Z16C30 USC® USER'S MANUAL
TABLE OF CONTENTS
HAPTER TITLE AND SUBSECTIONS PAGE
C
Chapter 1 Introduction
1.1 Introduction ....................................................................................................... 1-1
1.2 Features............................................................................................................. 1-1
1.3 Logic Symbol..................................................................................................... 1-2
1.4 Packaging ......................................................................................................... 1-3
1.5 Overview of the USC and this Manual............................................................... 1-4
1.5.1 Bus Interfacing ....................................................................................... 1-4
1.5.2 Serial Interfacing..................................................................................... 1-4
1.5.3 Serial Modes and Protocols.................................................................... 1-4
1.5.4 DMA Operation ....................................................................................... 1-4
1.5.5 Interrupts ................................................................................................ 1-4
1.5.6 Software Summary.................................................................................. 1-4
1.6 Device Structure .............................................................................................. 1-12
1.6.1 The Transmit Data Path ........................................................................ 1-12
1.6.2 The Receive Data Path ......................................................................... 1-12
1.6.3 Clocking................................................................................................ 1-12
1.6.4 Interrupts .............................................................................................. 1-12
1.7 Document Structure ........................................................................................ 1-13
Z16C30 USC
USER'S MANUAL
®
Chapter 2 Bus Interfacing
2.1 Introduction ....................................................................................................... 2-1
2.2 Multiplexed/Non-Multiplexed Operation............................................................ 2-1
2.3 Read/Write Data Strobes ................................................................................... 2-3
2.4 Bus Width .......................................................................................................... 2-4
2.5 ACK vs. WAIT Handshaking.............................................................................. 2-4
2.6 Pin Descriptions ................................................................................................ 2-5
2.7 Pull-up Resistors and Unused Pins ................................................................... 2-7
2.8 The Bus Configuration Register (BCR).............................................................. 2-7
2.8.1 WAIT vs. Ready Selection ...................................................................... 2-7
2.8.2 Bits and Fields in the BCR ...................................................................... 2-7
2.9 Register Addressing.......................................................................................... 2-8
2.9.1 Implicit Data Register Addressing.......................................................... 2-8
2.9.2 Direct Register Addressing on AD13-AD8 ............................................. 2-8
2.9.3 Direct Register Addressing on AD6-AD0/7-1 ......................................... 2-9
2.9.4 Indirect Register Addressing in the CCAR ............................................. 2-9
2.9.5 About the Register Address Tables ..................................................... 2-10
2.9.6 Serial Data Registers TDR & RDR ........................................................ 2-14
2.9.7 Byte Ordering ....................................................................................... 2-14
2.9.8 Register Read & Write Cycles .............................................................. 2-14
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CHAPTER TITLE AND SUBSECTIONS PAGE
Chapter 3 A Sample Introduction
3.1 Introduction ....................................................................................................... 3-1
Chapter 4 Serial Interfacing
4.1 Introduction ....................................................................................................... 4-1
4.2 Serial Interface Pin Descriptions ....................................................................... 4-1
4.3 Transmit and Receive Clocking ........................................................................ 4-2
4.3.1 CTR0 and CTR1...................................................................................... 4-2
4.3.2 The Baud Rate Generators ..................................................................... 4-2
4.3.3 Introduction to the DPLL ......................................................................... 4-5
4.3.4 TxCLK and RxCLK Selection .................................................................. 4-5
4.3.5 Clocking for Asynchronous Mode .......................................................... 4-6
4.3.6 Synchronous Clocking............................................................................ 4-6
4.3.7 Stopping the Clocks ............................................................................... 4-6
4.4 Data Formats and Encoding ............................................................................. 4-7
4.5 More About the DPLL ........................................................................................ 4-8
4.6 The RxD and TxD Pins .................................................................................... 4-10
4.7 Edge Detection and Interrupts ........................................................................ 4-11
4.8 The /DCD Pin ................................................................................................... 4-13
4.9 The /CTS Pin .................................................................................................... 4-15
4.10 The /RxC and /TxC Pins .................................................................................. 4-16
4.11 The /RxReq and /TxReq Pins .......................................................................... 4-17
4.12 The /RxACK and /TxACK Pins ......................................................................... 4-17
Z16C30 USC
USER'S MANUAL
®
Chapter 5 Serial Modes and Protocols
5.1 Introduction ....................................................................................................... 5-1
5.2 Asynchronous Modes........................................................................................ 5-1
5.3 Character Oriented Synchronous Modes.......................................................... 5-3
5.4 Bit Oriented Synchronous Modes ..................................................................... 5-4
5.5 The Mode Registers (CMR,TMR & RMR) .......................................................... 5-5
5.5.1 Enabling and Disabling the Receiver and Transmitter ........................... 5-7
5.5.2 Character Length.................................................................................... 5-7
5.5.3 Parity, CRC, Serial Encoding .................................................................. 5-8
5.6 Asynchronous Mode ......................................................................................... 5-9
5.6.1 Break Conditions .................................................................................. 5-10
5.7 Isochronous Mode........................................................................................... 5-10
5.8 Nine-Bit Mode.................................................................................................. 5-11
5.9 External Sync Mode ........................................................................................ 5-12
5.10 Monosync and Bisync Modes ......................................................................... 5-12
5.11 Transparent Bisync Mode ............................................................................... 5-14
5.12 Slaved Monosync Mode .................................................................................. 5-15
5.13 IEEE 802.3 (Ethernet) Mode ............................................................................ 5-16
5.14 HDLC/SDLC Mode .......................................................................................... 5-18
5.14.1 Received Address and Control Field Handling .................................... 5-18
5.14.2 Frame Length Residuals ....................................................................... 5-20
5.14.3 Handling a Received Abort .................................................................. 5-20
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CHAPTER TITLE AND SUBSECTIONS PAGE
5.15 HDLC/SDLC Loop Mode ................................................................................. 5-21
5.16 Cyclic Redundancy Checking......................................................................... 5-22
5.17 Parity Checking ............................................................................................... 5-25
5.18 Status Reporting .............................................................................................. 5-26
5.18.1 Detailed Status in the TCSR ................................................................. 5-28
5.18.2 Detailed Status in the RCSR ................................................................. 5-29
5.19 DMA Support Features .................................................................................... 5-31
5.19.1 The Character Counters ....................................................................... 5-31
5.19.2 The RCC FIFO ...................................................................................... 5-35
5.19.3 Transmit Control Blocks ........................................................................ 5-36
5.19.4 Receive Status Blocks .......................................................................... 5-38
5.19.5 Finding the End of a Received Frame .................................................. 5-39
5.20 Commands ...................................................................................................... 5-40
5.21 Resetting a USC Channel................................................................................ 5-44
5.22 The Data Registers and the FIFO's ................................................................. 5-45
5.22.1 Accessing the TDR & RDR ................................................................... 5-45
5.22.2 TxFIFO and RxFIFO Operation ............................................................. 5-45
5.22.3 Fill Levels .............................................................................................. 5-46
5.22.4 DMA & Interrupt Request Levels .......................................................... 5-46
5.23 Handling Overruns & Underruns ..................................................................... 5-47
5.23.1 Tx Underruns ........................................................................................ 5-47
5.23.2 Rx Overruns .......................................................................................... 5-47
5.23.3 Rx Overrun Scribbling .......................................................................... 5-48
5.23.4 Fill Level Correctness & Extra Bytes..................................................... 5-48
5.24 Between Frames, Messages, or Characters ................................................... 5-49
5.24.1 Synchronous Transmission ................................................................... 5-49
5.24.2 Async Transmission .............................................................................. 5-49
5.24.3 Synchronous Reception ....................................................................... 5-51
5.25 Synchronizing Frames/Messages with Software Response............................ 5-51
Z16C30 USC
USER'S MANUAL
®
Chapter 6 Direct Memory Access (DMA) Interfacing
6.1 Introduction ....................................................................................................... 6-1
6.2 Flyby vs. Flowthrough DMA Operation.............................................................. 6-1
6.3 DMA Requests by the Receiver & Transmitter .................................................. 6-6
6.3.1 Programming the DMA Request Levels ................................................. 6-7
6.4 DMA Acknowledge Signals ............................................................................... 6-8
6.5 Separating Received Frames in Memory .......................................................... 6-8
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CHAPTER TITLE AND SUBSECTIONS PAGE
Chapter 7 Interrupts
7.1 Introduction ....................................................................................................... 7-1
7.2 Interrupt Acknowledge Daisy-Chains................................................................ 7-1
7.3 External Interrupt Control Logic ........................................................................ 7-2
7.4 Using /RxReq and /TxReq as Interrupt Requests ............................................. 7-3
7.5 Interrupt Types & Sources................................................................................. 7-4
7.6 Internal Interrupt Operation ............................................................................... 7-6
7.7 Details of the Model........................................................................................... 7-8
7.8 Interrupt Option in the BCR ............................................................................... 7-9
7.9 Interrupt Acknowledge Cycles .......................................................................... 7-9
7.10 Interrupt Acknowledge vs. Read Cycles ......................................................... 7-14
7.11 Interrupt Types ................................................................................................ 7-14
7.11.1 Receive Status Interrupt Sources and IA Bits ...................................... 7-14
7.11.2 Receive Data Interrupts ........................................................................ 7-15
7.11.3 Transmit Status Interrupt Sources and IA Bits...................................... 7-18
7.11.4 Transmit Data Interrupts ....................................................................... 7-19
7.11.5 I/O Pin Interrupt Sources and IA Bits .................................................... 7-20
7.11.6 Miscellaneous Interrupt Sources and IA Bits ....................................... 7-20
7.12 Interrupt Pending and Under Service Bits ...................................................... 7-21
7.13 Interrupt Enable Bits ........................................................................................ 7-22
7.14 Channel Interrupt Options ............................................................................... 7-22
7.15 Interrupt Vectors .............................................................................................. 7-23
7.16 Software Requirements ................................................................................... 7-24
7.16.1 Nested Interrupts .................................................................................. 7-24
7.16.2 Which Type(s) to Handle? .................................................................... 7-24
7.16.3 Handling a Type ................................................................................... 7-25
7.16.4 Exiting the ISR ...................................................................................... 7-27
Z16C30 USC
USER'S MANUAL
®
Chapter 8 Software Summary
8.1 Introduction ....................................................................................................... 8-1
8.2 About Resetting ................................................................................................. 8-1
8.3 Programming Order .......................................................................................... 8-2
8.4 Using DMA to Initialize a Channel ..................................................................... 8-2
8.5 Determining the Device Revision Level............................................................. 8-3
8.6 Tips & Techniques............................................................................................. 8-3
8.6.1 Common Hardware Problems ................................................................ 8-3
8.6.2 Common Software Problems .................................................................. 8-3
8.7 Test Modes ........................................................................................................ 8-6
8.8 Register Reference.......................................................................................... 8-10
8.8.1 Register Addresses .............................................................................. 8-10
8.8.2 Conditions/Context ............................................................................... 8-10
8.8.3 Description ........................................................................................... 8-10
8.8.4 RW Status ............................................................................................. 8-10
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CHAPTER TITLE AND SUBSECTIONS PAGE
Appendix A Appendix Changes
A.1 Introduction ............................................................................................................ A-1
A.1.1 Transmit Status Blocks/Transmit Control Blocks .................................... A-1
A.1.2 Interrupt Enable (for Individual Sources) Interrupt Arm ......................... A-1
A.2 Commands ........................................................................................................ A-1
A.2.1 Reload RCC/TCC
Load RCC/TCC ....................................................................................... A-1
A.2.2 Select Straight/Swapped Memory ..........................................................A-1
A.2.3 Preset CRC Clear Tx/Rx CRC Generator................................................ A-1
A.3 Bit/Field Names ................................................................................................. A-1
Appendix B
Questions and Answers ...............................................................................................B-1
Z16C30 USC
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®
UM97USC0100
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FIGURE TITLES PAGE
Chapter 1
Figure 1-1. USC Logic Symbol ................................................................................. 1-2
Figure 1-2. USC 68-pin PLCC Pinout ........................................................................ 1-3
Figure 1-3. USC Block Diagram.............................................................................. 1-11
Chapter 2
Figure 2-1. Simple Multiplexed System .................................................................... 2-1
Figure 2-2. Simple Interface to Non-Multiplexed Bus ............................................... 2-2
Figure 2-3. User-Friendly Interface to Non-Multiplexed Bus .................................... 2-2
Figure 2-4. /RD & /WR Signaling ............................................................................... 2-3
Figure 2-5. R//W and /DS Signaling .......................................................................... 2-3
Figure 2-6. A Fast and Slow Cycle with Three Kinds of Handshaking ..................... 2-5
Figure 2-7. The USC's Bus Configuration Register (BCR) ........................................ 2-7
Figure 2-8. The Channel Command/Address Register (CCAR) ............................. 2-10
Figure 2-9. USC Register Addressing .................................................................... 2-11
Figure 2-10. A Register Read Cycle with Multiplexed Addresses and Data ............ 2-15
Figure 2-11. A Register Write Cycle with Multiplexed Addresses and Data ............ 2-16
Figure 2-12. A Register Read Cycle with Non-Multiplexed Data Lines .................... 2-17
Figure 2-13. A Register Write Cycle with Non-Multiplexed Data Lines..................... 2-18
Z16C30 USC
USER'S MANUAL
®
Chapter 3
Figure 3-1. Sample Application ................................................................................ 3-2
Figure 3-2. Serial Interface for Sample Application .................................................. 3-3
Chapter 4
Figure 4-1. A Model of a USC Channel's Clocking Logic ......................................... 4-3
Figure 4-2. The Clock Mode Control Register (CMCR) ............................................ 4-4
Figure 4-3. The Hardware Configuration Register (HCR) ......................................... 4-4
Figure 4-4. Data Formats/Encoding .......................................................................... 4-7
Figure 4-5. The Channel Command/Status Register (CCSR) ................................... 4-9
Figure 4-6. The Input/Output Control Register (IOCR) ........................................... 4-10
Figure 4-7. The Status Interrupt Control Register (SICR)........................................ 4-12
Figure 4-8. The Miscellaneous Interrupt Status Register (MISR) ............................ 4-12
Figure 4-9. /DCD Auto-Enable Timing .................................................................... 4-14
Figure 4-10. /CTS Auto-Enable Timing ..................................................................... 4-15
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FIGURE TITLES PAGE
Chapter 5
Figure 5-1. Asynchronous Data ................................................................................ 5-2
Figure 5-2. Character Oriented Synchronous Data .................................................. 5-2
Figure 5-3. HDLC/SDLC Data ................................................................................... 5-4
Figure 5-4. The Channel Mode Register (CMR) ....................................................... 5-6
Figure 5-5. The Transmit Mode Register (TMR)........................................................ 5-6
Figure 5-6. The Receive Mode Register (RMR) ........................................................ 5-6
Figure 5-7. Carrier Detection for a Received Ethernet Frame ................................ 5-16
Figure 5-8. The Channel Command/Status Register (CCSR) ................................. 5-21
Figure 5-9. A Model of the Receive Datapath......................................................... 5-24
Figure 5-10. How a USC Channel Provides the "Queued" Status Bits in the RCSR. 5-27
Figure 5-11. The Transmit Command/Status Register (TCSR) ................................. 5-28
Figure 5-12. The Receive Command/Status Register (RCSR).................................. 5-29
Figure 5-13. A Model of the Transmit Character Counter Feature............................ 5-33
Figure 5-14. A Model of the Receive Character Counter Feature ............................ 5-34
Figure 5-15. The Channel Command/Status Register (CCSR) ................................. 5-37
Figure 5-16. The Channel Control Register (CCR) ................................................... 5-37
Figure 5-17. A 32-Bit Transmit Control Block in a DMA Buffer ................................. 5-37
Figure 5-18. A 32-Bit Receive Status Block in a DMA Buffer.................................... 5-38
Figure 5-19. The Channel Command/Address Register (CCAR) ............................. 5-41
Z16C30 USC
USER'S MANUAL
®
Chapter 6
Figure 6-1. Flowthrough DMA Transfer Memory to Peripheral Device ..................... 6-2
Figure 6-2. Flowthrough DMA Transfer, Peripheral Device to Memory .................... 6-3
Figure 6-3. Flyby DMA Transfer, Memory to Peripheral Device ............................... 6-4
Figure 6-4. *Flyby DMA Transfer, Peripheral Device to Memory .............................. 6-5
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FIGURE TITLES PAGE
Chapter 7
Figure 7-1. An Interrupt Daisy Chain ........................................................................ 7-2
Figure 7-2. External Interrupt Control........................................................................ 7-3
Figure 7-3. USC Interrupt Types & Sources ............................................................. 7-5
Figure 7-4. A Model of the Interrupt Logic for Source "s" and type "t" ...................... 7-7
Figure 7-5. An Interrupt Acknowledge Cycle Signaled by /SITACK, .............................
on a Multiplexed Bus ............................................................................ 7-10
Figure 7-6. An Interrupt Acknowledge Cycle Signaled by /SITACK, .............................
on a Non-Multiplexed Bus .................................................................... 7-11
Figure 7-7. A /PITACK Interrupt Acknowledge Cycle with 2PulseIACK=0 ............. 7-12
Figure 7-8. A /PITACK Interrupt Acknowledge Cycle with 2PulseIACK=1 ............. 7-13
Figure 7-9. The Receive Command/Status Register (RCSR).................................. 7-15
Figure 7-10. The Receive Interrupt Control Register (RICR) .................................... 7-15
Figure 7-11. A Sample Service Routine for Receive Data Interrupts........................ 7-17
Figure 7-12. The Transmit Command/Status Register (TCSR) ................................. 7-18
Figure 7-13. The Transmit Interrupt Control Register (TICR) .................................... 7-18
Figure 7-14. The Status Interrupt Control Register (SICR)........................................ 7-19
Figure 7-15. The Miscellaneous Interrupt Status Register (MISR)............................ 7-19
Figure 7-16. The Daisy-Chain Control Register (DCCR)........................................... 7-22
Figure 7-17. The Interrupt Control Register (ICR)..................................................... 7-22
Figure 7-18. The Interrupt Vector Register (IVR) ...................................................... 7-24
Z16C30 USC
USER'S MANUAL
®
Chapter 8
Figure 8-1. Test Mode Data Register with TMCR 4-0=00101 (Clock Mux Outputs) ... 8-7
Figure 8-2. Test Mode Data Register with TMCR 4-0=00111 (Clock Mux Inputs)...... 8-8
Figure 8-3. Test Mode Data Register with TMCR 4-0=01110 (I/O and Misc Status) .. 8-9
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TABLE TITLES PAGE
Chapter 1
Table 1-1. Bus Interfacing Features of the USC ...................................................... 1-5
Table 1-2. Serial Interfacing Features of the USC ................................................... 1-6
Table 1-3. Serial Controller Features of the USC ..................................................... 1-7
Table 1-4. More Serial Controller Features of the USC............................................ 1-8
Table 1-5. DMA Features of the USC ...................................................................... 1-9
Table 1-6. Interrupt Features of the USC ............................................................... 1-10
Chapter 2
Table 2-1. USC Registers, in Address Order ........................................................ 2-12
Table 2-2. USC Registers, in Alphabetical Order .................................................. 2-13
Z16C30 USC
USER'S MANUAL
®
© 1997 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
UM97USC0100
Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.com
ix
ZILOG
UM009402-0201
1.1 INTRODUCTION
U
SER
’s M
ANUAL
CHAPTER 1
INTRODUCTION
Z16C30 USC
USER'S MANUAL
®
The Universal Serial Controller (USC®) is the next-generation successor to Zilog’s popular SCC family of multiprotocol serial controllers, and is recommended for new
designs. Compared to the SCC family and most competing devices, the USC features more serial protocols, a 16or 8-bit data bus, higher data rates, larger FIFOs, better
support for DMA operation, and more convenient software
1.2 FEATURES
■ Two Full-Duplex Multi-Protocol Serial Controllers
■ Supports External DMA Channels with two Request
and two Acknowledge Lines
■ Serial Data Rates to 10 Mbits/Second
■ 32-Character Transmit and Receive FIFOs for each
Channel
■ 8- or 16-Bit Transfers for both Serial Data and
Registers
handling. The USC can handle higher data rates because
it takes its timing reference from the software-selected
receive and transmit clocks and the host bus control
signals, rather than from a separate “bus clock” or “master
clock”.
■ Async Features Include False-Start Filtering, Stop Bit
Length Programmable by 1/16-bit steps, Parity
Generation/Checking, Break Generation/Detection
■ HDLC/SDLC Features Include 8-Bit Address Checking,
Extended Address Support, 16/32 bit CRC,
Programmable Idle State, Auto Preamble Option, Loop
Mode
■ Sync Features Include 2 to 16-Bit Sync Pattern, Sync
Strip Option, 16/32-bit CRC, Programmable Idle State,
Auto Preamble Option, X.21 XMIT/RCV Slaving
■ Flexible Adaptation to Various System Buses
■ Serial Modes Include Asynchronous, Bisync, SDLC,
HDLC, Ethernet, and Nine-Bit
■ Two Baud Rate Generators per Channel
■ Digital Phase Locked Loop for each Channel
■ Carrier Detect, Clear to Send, and Two Serial Clock
pins for each Channel
■ Transmit and Receive Frame-Length Counters for
each Channel
UM97USC0100
■ Improved Bus/Serial Interlocks Prevent extra Rx DMA
Characters and Ensure Correct FIFO Fill Level
Reporting
■ Flexible Interrupt Modes Including Interrupt
Acknowledge Daisy Chain
■ High-Speed, Low Power CMOS Technology
■ 68-Pin PLCC
1-1
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1.3 LOGIC SYMBOL
VDD
Z16C30 USC
USER'S MANUAL
®
/RESET
/CS
A//B
D//C
/AS
R//W
/DS
/RD
/WR
/SITACK
/PITACK
IEIA, B
/RxACKA,B
/TxACKA,B
/RxCA,B
/TxCA,B
RxDA,B
/CTSA,B
/DCDA,B
Figure 1-1. USC Logic Symbol
Z16C30
USC
VSS
AD15-AD0
/WAIT//RDY
/INTA,B
IEOA,B
/RxREQA,B
/TxREQA,B
/TxDA,B
1-2
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1.4 PACKAGING
/TxACKA
/WAIT//RDY
9
8
/SITACK6A//B5D//C4/CS3/RESET
7
2
VDD
1
VDD
68 67
VDD
/AS
66
/DS
65
/RD
64
/W/R
63
/PITACK61/TxACKB
R//W
62
Z16C30 USC
USER'S MANUAL
®
/RxACKA
/INTA
IEIA
IEOA
VSS
VDD
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
VSS
VDD
/RxREQA
10
11
12
13
14
15
16
17
Z16C30 USC
18
19
20
21
22
23
24
25
26
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
(Top View)
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
/RxACKB
/INTB
IEIB
/IEOB
VSS
VDD
AD8
AD9
AD10
AD11
AD12
AD13
AD14
AD15
VSS
VDD
/RxREQB
UM97USC0100
/RxCA
/TxREQA
VSS
VSS
RxDA
/DCDA
Figure 1-2. USC® 68-Pin PLCC Pinout
TxDA
/TxCA
/CTSA
VSS
TxDB
/CTSB
/TxCB
/DCDB
RxDB
/RxCB
/TxREQB
1-3
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1.5 OVERVIEW OF THE USC AND THIS MANUAL
Z16C30 USC
USER'S MANUAL
®
The following descriptions and Tables should be helpful in
initial evaluation of the USC® and in finding your way
around this document. Subjects in the Tables are arranged
in the same order they are covered in Chapters 2 and 4-8.
1.5.1 Bus Interfacing
Chapter 2 describes interfacing the USC to a processor or
backplane bus. The USC includes several flexible interfacing options as described in Table 1-1. Some of these
options are controlled by the Bus Configuration Register
(BCR), which is implicitly the destination of the first write to
the USC after a Reset, and is then no longer accessible to
software.
1.5.2 Serial Interfacing
Chapter 4 covers Serial Interfacing, the “other side” of
hardware design from Bus Interfacing. Table 1-2 summarizes the Serial Interfacing features of the USC, which
include Clock Selection, Baud Rate Generation, serial
data Encoding and Decoding, a Digital Phase Locked
Loop for reconstructing clocking from received data, and
“modem control” pins.
1.5.3 Serial Modes and Protocols
Chapter 5 covers how to program the Transmitter and
Receiver to handle many different protocols and applica-
tions. This Chapter focuses on software aspects of using
the USC while Chapter 4 is more hardware-oriented.
Tables 1-3 and 1-4 show the major subjects that you can
find in Chapter 5.
1.5.4 DMA Operation
Chapter 6 describes how to use the USC with DMA
channels, and is outlined in Table 1-5.
1.5.5 Interrupts
While Chapters 4-6 mention which conditions and events
can be enabled/armed to interrupt the processor, Chapter
7 pulls together all aspects of the USC’s extensive interrupt
capabilities, including interrupt acknowledge cycles, vectors, and use of Interrupt Under Service bits to implement
nested interrupts. Table 1-6 summarizes the subject.
1.5.6 Software Summary
Chapter 8 contains only a small amount of new material: a
few software-related matters that didn’t seem to fit in
anywhere else. The bulk of the Chapter is the Register
Reference tables that summarize the use and function of
each bit and field in each register in the USC.
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Table 1-1 Bus Interfacing Features of the USC (Chapter 2)
Multiplexed or Separate Address and Data Bus(es) can be selected for processor access to USC registers.
Read/Write Control Signals Separate Read and Write strobes, or Data strobe and Direction
control can be used. Only one set of signals should be
connected to the host processor; the other should be pulled
up.
8- or 16-Bit Data Bus DMA efficiency and bandwidth are doubled by using a 16-bit
bus, and software size and tediousness is improved as well.
With an 8-bit data bus and non-multiplexed Address and Data,
the bus pins that would otherwise be unused can be used for
register addressing from the processor.
Ready, Wait, or Acknowledge Handshaking can be selected for processor cycles. If Wait signalling is
selected, the USC drives Wait for interrupt acknowledge cycles
but not for register accesses — its 60 nanosecond register
access time is fast enough for no-Wait operation in almost all
applications. If Acknowledge signaling is selected, the part
drives the Acknowledge line for both interrupt acknowledge
cycles and register accesses.
USER'S MANUAL
®
Interrupt Acknowledge Cycles Separate inputs are provided for “Status line” vs. “pulse”
signalling. In the latter case single-pulse or double-pulse
cycles can be selected. The USC can also be used on buses
that don’t include Interrupt Acknowledge cycles.
Direct or Indirect Register Addressing The board designer can conserve the address space occu-
pied by the USC by requiring software to write register addresses into the USC, or can maximize software efficiency by
presenting register addresses directly. On a non-multiplexed
16-bit data bus, the latter choice requires external components/logic to multiplex the low-order bits of the address onto
the AD pins.
Registers There are 32 16-bit registers in each channel of the USC,
including three selectable subregisters in the MSbyte of two of
them.
Big- or Little-Ending Byte Ordering Motorola or Intel style addressing can be selected for serial
data. Byte addressing within the USC’s 16-bit registers is
inherently Little-Endian/Intel style.
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USER'S MANUAL
1.5.6 Software Summary (Continued)
Table 1-2. Serial Interfacing Features of the USC (Chapter 4)
Clock Selection Clocking for the Transmitter and Receiver can come from the
/RxC or /TxC pins, and can be used directly or can be divided by 4, 8,
16, or 32 by Counters 0 and 1, and/or by any value from 1 to 65,536 by
Baud Rate Generators 0 and 1. Or, clocking can come from the Digital
Phase Locked Loop (DPLL) module, which tracks transitions on the
RxD pin.
Clock Output Clocking can also be driven out on the /TxC or /RxC pin for use by on-
board logic, a modem or other interface.
CTR0, CTR1 These two 5-bit free-running counters can each divide /RxC or /TxC by
4, 8, 16, or 32. They can provide the Transmit or Receive bit clocks
directly, or can act as “prescalers” for the Baud Rate Generators.
Baud Rate Generators BRG0 and BRG1 are 16-bit counters, each of which can divide /RxC,
/TxC, or the output of CTR0 or CTR1 by any value from 1 to 65,536. They
can source the Transmit or Receive bit clocks, act as the reference
clock for the DPLL, or can be used as timers on either a polled or
interrupt-driven basis. They can be stopped and started by software,
and can run continuously or stop when they reach zero. Their period
(time constant) values can be reprogrammed dynamically, effective
immediately or when the BRG counts down to zero.
®
Digital-Phase Locked Loop The DPLL can divide /RxC, /TxC, or the output of BRG0 or BRG1 by 8,
16, or 32, while resynchronizing to transitions on RxD, to recover a
Receive clock from the Receive data signal. This can be done only
when the received data stream includes enough transitions to keep the
recovered clock synchronized to the data. NRZI-Space encoding of
HDLC/SDLC frames, or Biphase (FM) encoding with any protocol,
guarantees such data transitions.
Data Encoding The USC can encode transmitted data and decode received data in
NRZI-Mark, NRZI-Space, Biphase-Mark (FM1), Biphase-Space (FM0),
Biphase-Level (Manchester), or Differential-Biphase-Level modes.
These encodings are used in various applications to maintain synchronization between transmitting and receiving equipment.
Echoing and Looping Received data can be repeated onto TxD, or transmit data can be
looped back to the Receiver for testing.
Modem Controls and Interrupts Carrier Detect and Clear to Send inputs can auto-enable the
Receiver and Transmitter, respectively. Rising and/or falling edges on
these pins can cause interrupts, as can edges on the Transmit and
Receive Clock pins (if they’re not used for clocking), and/or the
Transmit and Receive Request pins if they’re not used for DMA
requests.
DMA Controller Interface Each channel of the USC provides Tx and Rx Request outputs for
connection to a DMA controller, and Tx and Rx Acknowledge inputs for
“flyby” (single-cycle) DMA operation. The Acknowledge pins can be
used for other purposes if “flowthrough” (two-cycle) DMA controller is
employed. Both Request and Acknowledge pins can be used for other
purposes if no DMA controller is used.
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USER'S MANUAL
Table 1-3. Serial Controller Features of the USC
Major Protocol Categories Chapter 4 begins with a small tutorial on the differences between Asynchronous,
Character-Oriented Synchronous, and Bit-Oriented Synchronous (Packet)
protocols.
Asynchronous Protocols In addition to classic Async, the USC can handle the following variations:
■ Isochronous (1X rather than 16-64X clock)
■ Nine-Bit (Address Wake-up — an extra bit signifies Address/Data)
Character-Oriented
Synchronous Protocols ■ External Sync (Receive only: simple character assembly)
■ Monosync (1-character sync pattern, no hardware framing)
■ Bisync (2-character sync pattern, no hardware framing)
■ Transparent Bisync (Bisync + hardware support for Transparency)
■ Slaved Monosync (Xmit only; X.21 Tx character alignment to Rx)
■ IEEE 802.3 (Ethernet; requires external collision detect and backoff)
Bit-Oriented Synchronous
Protocols ■ HDLC/SDLC
■ HDLC/SDLC Loop (RxD is repeated on TxD except when Xmit is
enabled and triggered by a received Go Ahead/Abort sequence)
®
Character Length is programmable from 1 bit/character to:
■ 8 bits including Parity, if any, in synchronous modes
■ 8 bits plus Parity, if any, in Async mode
■ 8 bits plus Parity plus the Address/Data bit in Nine-Bit mode
CRC Generation/Checking In synchronous modes, the USC will generate and check CRC-CCITT, CRC-16, or
CRC-32 codes for each frame or message. For character-oriented modes other
than 802.3, software can selectively control which characters are included in the
CRC, for both transmitting and reception. For HDLC/SDLC and 802.3, CRC status
can be stored in memory for each received frame.
Parity Checking Asynchronous or Synchronous modes. Odd/Even/Mark/Space/None.
Transmit Status Reporting Optional interrupt on: Preamble Sent, Idle Sent, Abort Sent, End of Frame/
Message, CRC Sent, Underrun No interrupt: All Sent, Tx Empty
Receive Status Reporting Optional Interrupt on: Exited Hunt, Idle Received, Break, Abort (immediate or
synchronized with the RxFIFO), Rx Boundary (end of frame/message), Parity
Error, Overrun. No interrupt: Short Frame, Code Violation Type, CRC Error,
Framing Error, Rx Character Available
Character Counters These 16-bit counters decrement for each character received or fetched from
memory for transmission. The Tx CC can control the length of Tx frames in
synchronous modes using DMA. The Rx CC tracks the length of each Rx frame
in synchronous modes using DMA, and optionally interrupts in case an Rx frame
is too long.
RCC FIFO A four-deep store for ending Rx Character Counter values for each frame.
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Table 1-4. More Serial Controller Features of the USC
Transmit Control Blocks A Transmit DMA channel can fetch the Tx CC frame length and other control info
for each frame/message, before the frame in the memory buffer.
Receive Status Blocks The Rx DMA channel can provide the frame status (including CRC status) for
each frame/message after the frame. Optionally it can also provide the the Rx
CC frame length residual, although this is only useful in Rx DMA applications in
which software can read the number of bytes/words that were stored, from the
DMA channel.
Commands Software can write various command codes to 3 different register fields in each
channel, to control the operation of the channel. Commands can be divided into
those that select a long-term configuration of a channel (like selecting which
serial character in a 16-bit word comes first), those that make the part perform
a time-sequenced action (like sending an Abort sequence), and those that
change the state of the part immediately (like purging a FIFO).
Software Reset Software can reset a USC channel by writing a central register bit, similarly to
a hardware-signaled Reset.
Rx and Tx FIFO Storage 32-character FIFOs stand between the Transmit Data Register and the Trans-
mitter, and between the Receiver and the Rx Data Register. Fill level counters
track how many characters are in each FIFO, and independently programmable threshold values determine when DMA operation will be triggered to fill
or empty them, and/or when an interrupt will be requested.
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®
Between Frames/Messages In synchronous modes the Transmitter will do the following before the first
data character of each frame or message, and/or after the last one:
■ optionally send a 8-to 64-bit Preamble for PLL synchronization or mini-
mum inter-frame timing
■ send an "opening" sync sequence or Flag
■ After the last character from memory, sending the CRC accumulated by the
USC is optional. Thus, a CRC received with a frame can be sent back out
without being regenerated.
■ send a "closing" Flag or Sync
■ send a selected "idle" pattern unless/until the next frame is ready to be sent
Waiting for Software Response Software can select 3 optional interlocks between frames, to allow it to do
real-time processing on a frame-by-frame basis.
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Table 1-5. DMA Features of the USC
Flowthrough or Flyby The USC can be used with DMA controllers in a “flowthrough” mode,
in which the REQ line from the USC tells the DMAC when to transfer data
by means of separate accesses to the USC and to memory. Alternatively, the USC and DMA can operate in a “flyby” mode, in which there’s
also an ACK line from the DMAC to tell the USC when to drive data to
the memory or when to capture data from the memory. Flyby operation
requires only one bus cycle per (pair of) character(s).
DMA Requests A USC can provide separate Transmit and Receive DMA Request
outputs from each of its two channels, that become active when the
relevant FIFO reaches a software-selected level of emptiness or
fullness, and stay active until the FIFO is filled or emptied. The Receive
Request for a channel operating in a synchronous block oriented mode
(e.g., HDLC) will also go active when the end of a message or frame is
received.
Separating Receive Frames Chapter 5 ends with a description of how the “Wait for Rx Trigger”
feature can be used to separate received frames into individual
memory buffers, by withholding the Rx DMA Request for the data in a
new frame until after software has read out the length of the frame and/
or programmed the DMA channel with the buffer address for the new
frame.
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Table 1-6. Interrupt Features of the USC
Interrupt Acknowledge
Daisy Chaining was one of Zilog’s original contributions to microprocessor architecture. On the USC
its use (to determine which of several interrupting devices to service first) is optional,
and performance is much improved compared to older devices.
External Interrupt Control can be used instead of a daisy chain to implement interrupt priority schemes other
than strict priority, such as “fairness”, rotating, or first-come first-served.
Types of interrupts that can be selectively enabled or disabled include Receive Status,
Receive Data, Transmit Status, Transmit Data, I/O Pin, and Miscellaneous.
Receive Status Interrupt sources that can be selectively armed or disarmed include Exited Hunt, Idle
Received, Break, Abort (immediate and/or synchronized to received data), End of
Frame/Message, Parity Error, and RxFIFO Overrun.
Receive Data Interrupt can occur when the RxFIFO reaches a programmed level of fullness.
Transmit Status Interrupt sources that can be selectively armed or disarmed include Preamble Sent, Idle
Sent, Abort Sent, End of Frame/Message Sent, CRC Sent, and Tx Underrun.
Transmit Data Interrupt can occur when the TxFIFO reaches a programmed level of emptiness.
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USER'S MANUAL
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I/O Pin Interrupt sources that can be selectively armed or disarmed include rising and/or falling
edges on the /DCD, /CTS, /RxREQ, /TxREQ, /RxC, and /TxC pins.
Miscellaneous Interrupt sources that can be selectively armed or disarmed include Rx Character Counter
Underflow, DPLL Sync Loss, Baud Rate Generator 0 zero, and BRG1=0.
Nested Interrupts are fully supported in that the USC includes an Interrupt Pending and Interrupt
Under Service bit for each type of interrupt.
Interrupt Acknowledge Cycles The USC is compatible with a wide variety of processors in that the signal that
identifies an acknowledge cycle can be sampled like an address bit, or can carry
a single or double pulse similar to a read or write strobe.
Interrupt Vectors The USC can include identification of the highest priority requesting type of interrupt
in the vector that it returns during an interrupt acknowledge cycle.
Non-Acknowledging Buses Software can simulate the effects of interrupt acknowledge cycles if the USC is used
on a bus that doesn’t provide such cycles, like the ISA (AT) bus.
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Transmitter
DPLL
Counters
BRG0, BRG1
Serial Clock
Logic
Receiver
Z16C30 USC
®
USER'S MANUAL
Host
Processor
DMA
Controller,
System
Memory
Bus
Interface
Transmit
FIFO
Transmit
FIFO
Transmitter
Interrupt
Control
Interrupt
Control
Serial Clock
Logic
DPLL
Counters
BRG0, BRG1
Receive
FIFO
Channel A
16-Bit Internal
Data Bus
Channel B
Receive
FIFO
Receiver
UM97USC0100
Figure 1-3. USC® Block Diagram
1-11
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1.6 DEVICE STRUCTURE
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USER'S MANUAL
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Figure 1-1 shows the basic structure of the USC. The Bus
Interface module stands between the external bus pins
and an on-chip 16-bit data bus that interconnects the other
functional modules. It includes several flexible bus interfacing options that are controlled by the Bus Configuration
Register (BCR). The BCR is automatically the destination
of the first write cycle from the host processor to the USC
after a Reset. After that it is no longer accessible to the host
software.
1.6.1 The Transmit Data Path
Either the host processor or an external DMA channel can
write transmit data into a channel’s Transmit First-In, FirstOut (FIFO) memory. At any time, a Transmit FIFO can be
empty or can contain from 1 to 32 characters to be
transmitted. Characters written into the TxFIFO become
available to the Transmitter in the order in which they were
written.
While the host processor can itself write data into the
Transmit FIFOs, it’s more efficient to use external Transmit
DMA channels to fetch the data. The host can program a
USC channel so that its Transmitter will trigger its DMA
controller to fill its FIFO at varying degrees of FIFO “emptiness”. Selecting this point involves balancing the probability and consequences of “underrunning” the transmitter, against the overhead for the DMA channel to acquire
control of the host bus more often.
have to detect and synchronize start bits, check parity and
stop bits, calculate and check CRCs, detect flag, abort
and idle sequences, recognize control characters including transparency considerations, decode the serial data
and clock extraction using any of several encoding
schemes, and/or enable and disable reception based on
the DCD input pin. The Receivers’ checking functions
generate several status bits associated with each character, that accompany the characters through the Receive
FIFOs.
The Receive FIFOs can hold up to 32 characters and their
associated status bits. As the receivers write entries into
their FIFOs, the entries become available to either the host
processor or external Receive DMA channels. As on the
transmit side, the Receive FIFOs include detection logic
for various degrees of “fullness”. Separate thresholds
control the point at which a channel starts requesting its
DMA channel starts to refill its FIFO, and at which a channel
requests an interrupt. Besides the main Receive FIFOs,
each channel has a 4-entry RCC FIFO that can hold values
indicating the length of up to four received frames.
While the host processor can access data from the Receive FIFOs, it’s more efficient to use external Receive
DMA channels to transfer the data directly into buffer areas
in memory. The USC can provide the status (and optionally
the RCC value at the end) of each frame in the serial data
stream, after the last character of the frame.
The serial Transmitters take characters from the Transmit
FIFOs and convert them to serial data on the TxD pins.
While this function is conceptually simple, the USC supports many complex serial protocols, which increases the
complexity of the Transmitters dramatically. Depending on
the serial mode selected, the Transmitters may do any of
the following in addition to parallel-serial conversion: start,
stop, and parity bit generation, calculating and sending
CRCs, automatic generation of opening and closing flags,
encoding the serial data into any of several formats that
guarantee transitions and carry clocking with the data,
and/or controlling transmission based on the CTS pin.
1.6.2 The Receive Data Path
In general, the functions of the Receivers are the inverse of
those of the Transmitters: they monitor the serial data on
the RxD pin, organize it according to the serial mode
selected by the software, and convert the data to parallel
characters that they place in the Receive FIFOs. Again,
there is more to the process than just serial-parallel conversion. Depending on the serial mode the Receivers may
1.6.3 Clocking
Each channel includes a Serial Clocking Logic section that
creates the clocking signals for the channel’s Transmitter
and Receiver. Software can program the clocking logic to
do this in various ways based on one or two external
clock(s) for each channel. Each channel also includes a
Digital Phase Locked Loop (DPLL) circuit that can recover
clocking from encoded data on RxD.
1.6.4 Interrupts
There’s also an Interrupt Control section in each channel,
that gathers the various “request” lines from the Transmitter and Receiver, and takes care of requesting host interrupts and responding to host interrupt-acknowledge cycles
or to software equivalents. Interrupt operation depends on
the data written to the Bus Configuration Register and on
several registers in the Receiver and Transmitter. There
are a separate set of interrupt pins for each channel so that
external logic can control their relative priority.
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1.7 DOCUMENT STRUCTURE
Z16C30 USC
®
USER'S MANUAL
The Chapters in this manual attempt to provide the firsttime reader with a staged and gradual introduction to the
USC. The manual is structured according to the USC’s
major internal blocks and various aspects of their operation, rather than as a list and description of each of its
registers. The various registers and fields are covered in
conjunction with the facilities that they report on and
control. Chapter 8 then reviews the general programming
model and includes a concise description of each register
bit and field for quick reference.
The actual timing parameters and electrical specifications
of the IUSC are given in the companion publication 'USC
Product Specification'.
We at Zilog hope that this newly structured manual will
make the USC more easily understandable and accessible. Naturally, it’s impossible to write at the right level for
all readers; newcomers will find some parts hard going,
while experts will undoubtedly tire of full explanations of
matters that “everyone knows”. Our target audience is
neither newcomers nor experts, but midway between:
working engineers with some datacom background.
© 1997 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of merchantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
UM97USC0100
Zilog’s products are not authorized for use as critical components in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.com
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2.1 INTRODUCTION
U
SER
’s M
ANUAL
CHAPTER 2
BUS INTERFACING
Z16C30 USC
USER'S MANUAL
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The USC® can be used in systems with various microprocessor or backplane buses. Its flexibility with respect to
host bus interfacing derives from its Bus Configuration
Register (BCR), from on-chip logic that monitors bus
activity before software writes the BCR, and from certain
other registers in the serial channels. This section describes how to use these facilities to interface the USC to
a variety of host microprocessors and buses.
2.2 MULTIPLEXED/NON-MULTIPLEXED OPERATION
One important distinction among buses is whether they
include separate sets of lines for addresses and for data,
or whether the same set of lines carries multiplexed addresses and data. On a multiplexed bus, the USC captures
addressing at rising edges on /AS. If this signaling is the
same as that used on the host bus (as with a Zilog 16C0x),
then the USC’s /AS pin can be directly connected to the
corresponding bus signal. Figure 2-1 shows such a system.
AD15:AD0
/AS
16C01
UM97USC0100
AD15:AD0
/AS
USC
Figure 2-1. Simple Multiplexed System
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2.2 MULTIPLEXED/NON-MULTIPLEXED OPERATION (Continued)
Z16C30 USC
USER'S MANUAL
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An 80x86-based system differs only in that the processor’s
ALE signal has to be inverted to produce /AS for the USC.
Figures 2-2 and 2-3 illustrate two ways to interface the USC
to a non-multiplexed host bus. Figure 2-2 includes minimum hardware but requires that software write the register
address into the USC each time it is going to access a
register. In this mode the USC’s /AS pin should be pulled
up to ensure a constant high logic level. Figure 2-3 includes drivers to sequence the low-order bits of the host
address onto the USC’s AD lines, and logic to synthesize
a pulse on the /AS pin. This interfacing method has the
advantage that software can directly address the USC’s
registers.
The USC monitors the /AS pin from the time the /RESET pin
goes high until the software writes the Bus Configuration
Register. If it sees /AS go low at any point in this period,
then after the software writes the BCR, the USC captures
the state of the low-order AD lines, A//B, C//D, and /CS, at
each rising edge of /AS. If /AS remains high, software may
have to write each register address into the Channel
Command/ Address Register (CCAR) before reading or
writing a register. (If the host bus only includes 8 data lines,
AD13-AD8 can carry register addresses.)
D15:D0
A15-A0
D15-D0
Cntrl Signals
Control
Logic
/AS
USC
Figure 2-3. User-Friendly Interface to
/RD, /WR
AD15-AD0
Non-Multiplexed Bus
/AS
68000
AD15:AD0
VCC
/AS
USC
Figure 2-2. Simple Interface to Non-Multiplexed Bus
2-2
UM97USC0100
ZILOG
Read Operation:
Write Operation:
R//W
DS*
R//W
Data Bus (Slave)
Data Bus
DS*
UM009402-0201
2.3 READ/WRITE DATA STROBES
Another difference among host buses is the way in which
read and write cycles are signalled and differentiated.
Figures 2-4 and 2-5 show two standard methods supported by the USC. In Figure 2-4, the bus includes separate strobe lines for read and write cycles, commonly
called /RD and /WR. In Figure 2-5, the bus includes a data
strobe line, /DS, that goes low for both read and write
cycles, and a R//W line that differentiates read cycles from
writes. The USC includes pins for all four of these signals.
The two that match up with host bus signals should be
connected to those signals. The two unused pins should
be pulled up to a high level.
Read Operation:
RD*
WR*
Z16C30 USC
®
USER'S MANUAL
Write Operation:
Data Bus
RD*
WR*
Data Bus
Figure 2-4. /RD and /WR Signaling
Figure 2-5. R//W and /DS Signaling
There is no programmable option for the distinction between /RD-/WR and R//W-/DS operation. The USC simply
responds to either pair of lines, which is why it’s important
to pull up the unused pair. Also, the USC doesn’t demand
that the R//W line remain valid throughout the assertion of
/DS. It captures the state of R//W at the leading/falling edge
of /DS, so that R//W need only satisfy setup and hold times
with respect to this edge.
Only one among the bus signals /DS, /RD, /WR, and
/PITACK may be active at a time. This prohibition also
includes /RxACKA, /RxACKB, /TxACKA, and /TxACKB
when these pins are used as DMA acknowledge signals.
(Chapter 5 covers DMA interfacing including the “ACK”
signals, and Chapter 6 describes the USC’s interrupt
features including /PITACK). If the USC detects more than
one of these inputs active simultaneously, it enters an
inactive state from which the only escape is via the /RESET
pin.
UM97USC0100
2-3
ZILOG
UM009402-0201
2.4 BUS WIDTH
Z16C30 USC
USER'S MANUAL
®
Another major difference among host buses is the number
of data bits that can be transferred in one cycle. Software
can configure the USC to transfer 16 bits at a time, in which
case it is still possible to transfer 8 bits when this is
necessary or desirable. Or, software can restrict operation
to transferring only 8 bits at a time, on the AD7-AD0 pins.
2.5 ACK VS. WAIT HANDSHAKING
The final major difference among host buses involves the
nature of the handshaking signals that slave devices use
for speed-matching with masters. Figure 2-6 illustrates the
three variations in common use. In the first, which we’ll call
Wait signaling, if a master selects a slave and the slave
cannot capture write data or provide read data within the
time allowed to keep the master operating at full speed, it
quickly (combinatorially) drives a Wait output low, and then
returns it to high when it’s ready to complete the cycle.
Some peripheral devices have Wait outputs that are opencollector or open-drain, which can be tied together for a
negative logic wired-Or function. Because the USC drives
its /WAIT//RDY output high or low on a full-time basis, a
logic gate must be used to negative-logic OR (positivelogic AND) its /WAIT//RDY output with the /WAIT signal(s)
for other slaves, to produce the /WAIT input to the master
(e.g., to the processor).
In the second scheme, “Acknowledge” signaling, all slaves
must respond when the master directs a cycle to them, by
driving an Acknowledge signal (sometimes called /DTACK)
low to allow the master to complete the transfer, and
keeping it low until the master does so. As with the previous
scheme, some peripherals provide slave Ack outputs that
are open-collector or open-drain, which can be tied together for a negative logic wired-Or function. Because the
USC drives its /WAIT//RDY output high or low on a full-time
basis, a logic gate must be used to negative-logic OR its
/WAIT//RDY output with the /ACK signals for other slaves,
to produce the Acknowledge input to the master.
This leaves the AD15-AD8 pins unused: another BCR
option allows them to carry register addresses. The latter
option allows software to directly address USC registers
even on a non-multiplexed bus, without having to write an
address into the USC before it accesses a register.
In the third scheme, “Ready” signaling, all slaves must
respond when the master directs a cycle to them, by
driving a Ready signal high to allow the master to complete
the transfer, and keeping it high until the master does so.
This scheme differ from Wait signaling in the default state
of the handshaking signal between cycles (high for Wait
signaling, low for Ready). It has similar timing as Ack
signaling, but differs in the polarity of the handshaking
signal. With Ready signaling, the board designer must
include a logic gate to positive-logic OR the various slaves’
Ready lines to produce a composite Ready input for the
bus master(s).
The USC supports Acknowledge and Ready signaling for
all cycles, and Wait signaling for interrupt acknowledge
cycles. The USC register access times should be short
enough to avoid the need for Wait signaling on all but the
fastest processors. The board designer can combine the
USC’s /WAIT//RDY output with similar signals from other
slaves, by means of an external logic gate or (for Acknowledge and Wait) an external tri-state or open-collector
driver.
If software writes the Bus Configuration Register (BCR) at
an address that makes the A//B pin low, the USC drives
/WAIT//RDY low as an “Acknowledge” signal, while if
software writes the BCR with A//B high, the USC drives
/WAIT//RDY as a “wait” signal.
2-4
UM97USC0100
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