YAMAHA YSS901-E Datasheet

YAMAHA CORPORATION

YSS901CATALOG

CATALOG No.: LSI-4SS901A0

1999. 1

YSS901

SD

Preliminary

Stereo dipole

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Outline

YSS901 is a device that uses the stereo dipole system (SD) with which the transaural system can be constructed. When a stereophonic signal that has been processed with the SD system of this device is inputted to two speakers located adjacently at the center of the field (or to two speakers contained in one cabinet), the virtual sound positioning function of this system produces the stereophonic sound similar to the one that can be obtained by using an ordinary stereophonic sound replay system through the central two speakers. YSS901 has built-in one bit Delta-Sigma type A/D and D/A converters for each of the two channels at its input and output respectively. Thanks to these built-in converters, this device can process analog stereophonic sound signal through the converters in addition to digital stereophonic sound signal. This device performs an advanced convolution through DSP using the FIR filter.

g

Features

n

Two channel virtual sound positioning by using the stereo dipole system.

n

Processes analog or digital signals at each of the two channels.

n

Four types of digital data format are available, including 48 fs Serial-DAC16, 18 and 20 bits, and 64 fs.

n

Six types of parameter coefficients are built in the device. Additional parameter coefficients can be

downloaded externally.

n

The parameter control is made through the DC switches or synchronous three-wire serial system.

n

Uses a clock of 2.822 MHz from the crystal. External clock can also be used.

n

Has a built-in PLL circuit for generating clock for operation.

n

Internal operating frequency of 512 fs.

n

Allows fading in or out the output of the results of the convolution when switching the coefficient.

n

Power supply voltage: 5 V

n

Si-gate CMOS process.

n

64 QFP

YSS901

2

g

Pin configuration

<64QFP TOP VIEW>

YSS901

1234567891011

63

23

24

25

26

27

28

29

30

20

21

61

22

343536373839404142

62

43 33

53

54

55

56

57

58

59

60

TSTNI

AILRET

AIR

LOUT

ROUT

TSTNO

AVDD

DSEL2AVSS

AVSS

DIN

DOUT

BCLK

DSEL1

DSEL0

SYNCN

CTLSEL

CSEL1

BSFT0

CSN

SCK

SI

RESETN

XTAL

TST2

TSTSEL

DVSS

TSTCK

PLLC

DVSS

EXTAL

AIL

AIRRET

AILOUT

AIROUT

DVSS

DVDD

VREF

CSEL0

CSEL2

BSFT1

DVDD

TST1

12 13 14 15 16 17 18 19

31

32

4445464748495051

52

64

N.C

N.C N.C

N.C

N.CN.C

N.C

YSS901

3

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Pin Description

No. Pin name I/O

Function

5 DVDD

-

Digital signal power supply : +5 V

6

CTLSEL I Selection of control method 7 SYNCN I Digital input/output synchronization signal 8 BCLK

I

Digital input/output bit clock

9

CSN

I

Serial control interface chip select signal

10 DOUT

O

Digital signal output

11

DIN

I

Digital signal input

12 DSEL2

I

Analog/digital input selection

13 DSEL1

I

Digital input/output format selection

14 DSEL0

I

Digital input/output format selection

15 DVDD

-

Digital signal power supply : +5 V

21 TST2

-

Test (To be open.)

22 DVSS

- Digital signal ground

23 AVSS

-

Analog signal ground

24

AIRRET AO Right channel analog signal input return

25

AIROUT AO Right channel analog signal input out

26

AIR

AI

Right channel analog signal input

27

AILRET AO Left channel analog signal input return

28

AILOUT AO Left channel analog signal input out

29

AIL

AI

Left channel analog signal input

30 VREF

AI

Analog signal VREF

31 AVDD

-

Analog signal power supply : +5 V 37 LOUT AO Left channel analog signal outp ut 38 ROUT AO Right channel analog signal output 39 PLLC

AI

PLL auxiliary input 40 AVSS

-

Analog signal ground 41 EXTAL

I

Crystal clock input 42 XTAL

O

Crystal clock output 43 DVSS

-

Digital signal ground 44 TSTCK

-

Test (Connect with DVSS.) 45 TST1

-

Test (To be open.) 46 TSTNI

I

Test (Connect with DVSS.) 47 TSTNO O Test (To be open.) 53 DVDD

-

Digital signal power supply: +5 V

54

TSTSEL - Test (Connect with DVSS.)

55 CSEL2

I

Coefficient selection (Enabled when CTLSEL = 0) 56 CSEL1

I

Coefficient selection (Enabled when CTLSEL = 0) 57 CSEL0

I

Coefficient selection (Enabled when CTLSEL = 0) 58 RESETN I Reset signal input 59 BSFT1

I

Bit shift selection (Enabled when CTLSEL = 0) 60 BSFT0

I

Bit shift selection (Enabled when CTLSEL = 0) 61

SCK

I

Serial control interface clock input 62

SI

I

Serial control interface data input 63 DVSS

-

Digital signal ground

Notes:

1. Pins of No. 1 to 4, 16 to 20, 32 to 36, 48 to 52 and 64 are to be open.

2. I: input pin O: output pin

AI: analog signal input pin

AO: analog output pin.

YSS901

4

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Block Diagram

NGATE

AILRET

AIR

AIL

AIRRET

AILOUT

AIROUT

AD

DA

Digital

In

Digital

Out

Noise Gate

Serial

Control

COEF

stereo dipole

Timing

Fader

SYNCN

BCLK

DIN

ROUT

LOUT

DOUT

PLLC

EXTAL

XTAL

RESETN

CSEL0

CSEL1

CSEL2

BSFT0

BSFT1

CSN

SCK

SI

CTLSEL

Lch

Rch

COEF 1

COEF 2

COEF 1

COEF 2

DSEL1

DSEL0

Bit

Shift

DSEL2

NGO

AVSS

AVDD

VREF

DVDD

DVSS

Lch

Rch

(Input Level Check)

YSS901

5

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Outline of Functions

1. Clock signals

XTAL, EXTAL

and

PLLC

For the clock signal, use the crystal connected to XTAL EXTAL pin with which the clock signal is obtained by the self-oscillation at the cr ystal osc illatio n cir cuit, o r e xternal signa l supp lied thr o ugh EXT AL p in. The frequency of the clock obtained by the self-oscillation is 2.822 MHz (or 44.1 kHz * 64). The internal operation is carried out with 512 fs clock that is made by the PLL. Insert an analog filter in between PLLC and GND pins.

2. Data input/output signals

Analog/digital input selection pin:

DSEL2

This pin is used to select a type of the input signal. DSEL2 = 0 selects the digital signal input, or DSEL2 = 1 selects the analog signal input.

2-1) Digital signal

Digital signal input/output pins:

DIN, BCLK, SYNCN

and

DOUT

Digital signals should be inputte d through DIN, BCLK and SYNCN pins. DIN signal (PCM data) must be in synchronous with BCLK (bit clock) and SYNCN (word clock) signals. Digital signal is outputted from DOUT pin.

Input/output format designation pins:

DSEL1

and

DSEL0

These pins are used to designate a data format for DAC. The settings of DSEL1 and DSEL0 and their output formats are as follows.

DSEL1 DSEL0

DAC output format

00

48 fs 16 bits Data LSB justified

01

48 fs 18 bits Data LSB justified (Bits 1 and 0 are “0”.)

10

48 fs 20 bits Data LSB justified (Bits 3 through 0 are “0”.)

11

64 fs 16 bits Data MSB justified (Delay by one bit)

For the details of the format, refer to “Serial Data Interface” explained later in this document.

2-2) Analog signal

Analog input/output pins:

AIL, AILOUT, AILRET, LOUT, AIR, AIROUT, AIRRET

and

ROUT

Analog signals should b e inputted through AIL and AI R pins. The signals that have been processed by the stereo dipole (SD) are outputted from LOUT and ROUT pins respectively. Add an analog filter circuit, an example of which is shown later in this document.

Center voltage pin

VREF

This pin outputs a reference voltage for analog signal processing. Connect an appropriate capacitor between VREF and GND pins.

3. Controlling functions

3-1) Control method selection pin:

CTLSEL

This pin is used for selection of a control method as described below.

CTLSEL = 0 : Selection of CSEL2, CSEL1 or CSEL0 by means of DC switch (H/L) is enabled. CTLSEL = 1 : Selection of CSN, SI or SCK through the microcomputer is enabled.