Yamaha YSS912 User Manual

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YSS912

AC3D2

Dolby Digital (AC-3) / Pro Logic / DTS decoder + Sub DSP

INTRODUCTION

The YSS912 is one chip LSI consisting two built-in DSP’s ; Dolby Digital (AC-3) / Pro Logic / DTS decoder (Main DSP) and a sound processing DSP (Sub DSP). Sub DSP is capable of realizing various sound fields, such as virtual surround, by down-loading the program and coefficient. Sub DSP is compatible with YSS902, the Sub DSP programs developed for YSS902 are also applicable to YSS912.

FEATURERS

Pin compatible with YSS902 (AC3D).

Dolby Digital (AC-3) / Pro Logic and DTS decode. 24 bit DSP. (Group-A Dolby Digital decoder)

No external memory is required (Memory for center and surround channel delay is included) when DTS decoding as well as AC-3 / Pro Logic.

Possible to decode multi-language encoded data. (possible to decode based on data-stream-number) AC-3 karaoke mode.

Original compression mode as well as four compression modes recommended by Dolby. (when AC-3 decoding)

Included de-emphasis filter.

Pro Logic decoding for Dolby digital 2 channels decoded signal as well as ordinary PCM.

High performance 25 MIPS programmable DSP suitable for a variety of sound field processing such as original surround , filtering, virtual surround etc.

Up to 1.36 second delay time is capable when used with an external 1Mbit SRAM. (at fs= 48 kHz)

Reads Dolby Digital (AC-3)/DTS decode information through the microprocessor interface. Provide total sixteen I/O ports.

Possible to connect most of SPDIF receivers, A/D and D/A converters, by setting I/O data interface format. Has a built-in PLL oscillation circuit to generates its own operating clock.

Internal operating clock is 30 MHz.

Supply Voltage: 3.3v for core logic. 5v for I/Os. Power saving mode.

Si-gate CMOS process. 100 QFP.(YSS912-F)

Note: "AC-3" and "Pro Logic" are registered trademarks of Dolby Laboratories Licensing Corporation. "DTS" is a registered trademark of DTS, Inc.

Use of this LSI must be licensed by both Dolby Laboratories Licensing Corporation and DTS, Inc.

YAMAHA CORPORATION

YSS912CATALOG

CATALOG No.:LSI-4SS912A2

1998. 10

PIN CONFIGURATION

			VSS	IPORT0		IPORT1	IPORT2	IPORT3	IPORT4	IPORT5	IPORT6		IPORT7	VDD2	VSS		RAMOEN	RAMWEN		RAMA0	RAMA1	SDIA1		SDIA0	SDBCK0	SDWCK0	VDD2


		100		99	98		97	96	95	94	93	92		91	90	89		88	87		86	85	84		83	82	81
		100		99	98		97	96	95	94	93	92		91	90	89		88	87		86	85	84		83	82	81
VDD1	1																										80
RAMCEN	2																										79
RAMCEN	2																										79
RAMA16	3																										78
RAMA16	3																										78
RAMA15	4																										77
RAMA15	4																										77
SDIB0	5																										76
SDIB0	5																										76
SDIB1	6																										75
SDIB1	6																										75
SDIB2	7																										74
SDIB2	7																										74
XI	8																										73
XI	8																										73
XO	9																										72
XO	9																										72
VSS	10																										71
VSS	10																										71
AVDD	11																										70
AVDD	11																										70
SDIB3	12																										69
SDIB3	12																										69
TEST	13																										68
TEST	13																										68
TEST	14																										67
TEST	14																										67
OVFB	15																										66
OVFB	15																										66
DTSDATA	16																										65
DTSDATA	16																										65
AC3DATA	17																										64
AC3DATA	17																										64
SDOB3	18																										63
SDOB3	18																										63
CPO	19																										62
CPO	19																										62
AVSS	20																										61
AVSS	20																										61
VDD2	21																										60
VDD2	21																										60
SDOA2	22																										59
SDOA2	22																										59
SDOA1	23																										58
SDOA1	23																										58
SDOA0	24																										57
SDOA0	24																										57
RAMA14	25																										56
RAMA14	25																										56
RAMA13	26																										55
RAMA13	26																										55
RAMA12	27																										54
RAMA12	27																										54
RAMA11	28																										53
RAMA11	28																										53
RAMA10	29																										52
RAMA10	29																										52
VSS	30	31		32	33		34	35	36	37	38	39		40	41	42		43	44		45	46	47		48	49	51
VSS	30																										51
																											50


			VDD1	OPORT0	OPORT1		OPORT2	OPORT3	OPORT4	OPORT5	OPORT6		OPORT7	VSS	VDD2	RAMA9		RAMA8	RAMA7		SDOB2	SDOB1	SDOB0		SDBCK1	SDWCK1	VSS

< 100QFP TOP VIEW >

YSS912

VSS RAMD7 RAMD6 RAMD5 RAMD4 RAMD3 RAMD2 RAMD1 RAMD0 VDD1 RAMA2 SCK

SO /CS /CSB

RAMA3 TEST /IC RAMA4 VSS RAMA5 RAMA6

/SDBCK0 SURENC KARAOKE MUTE CRC NONPCM VDD2

YSS912

PIN FUNCTION

No.

Name

I/O

FUNCTION

VDD1	-	+5V power supply (for I/Os)
RAMCEN	O	External SRAM interface /CE
RAMA16	O	External SRAM interface address 16
RAMA15	O	External SRAM interface address 15
SDIB0	I+	PCM input 0 to Sub DSP
SDIB1	I+	PCM input 1 to Sub DSP
SDIB2	I+	PCM input 2 to Sub DSP
XI	I	Crystal oscillator connection (12.288 MHz)
XO	O	Crystal oscillator connection
VSS	-	Ground
AVDD	-	+3.3 V power supply (for PLL circuit)
SDIB3	I+	PCM input 3 to Sub DSP
TEST		Test terminal (to be open in normal use)
TEST		Test terminal (to be open in normal use)
OVFB	O	Detection of overflow at Sub DSP
DTSDATA	O	Detection of DTS data
AC3DATA	O	Detection of AC-3 data
SDOB3	O	PCM output from Sub DSP
CPO	A	Output terminal for PLL, to be connected to ground through the external analog filter circuit
AVSS	-	Ground (for PLL circuit)
VDD2	-	+3.3 V power supply (for core logic)
SDOA2	O	PCM output from Main DSP (C, LFE)
SDOA1	O	PCM output from Main DSP (LS, RS )
SDOA0	O	PCM output from Main DSP (L, R)
RAMA14	O	External SRAM interface address 14
RAMA13	O	External SRAM interface address 13
RAMA12	O	External SRAM interface address 12
RAMA11	O	External SRAM interface address 11
RAMA10	O	External SRAM interface address 10
VSS	-	Ground
VDD1	-	+5V power supply (for I/Os)
OPORT0	O	Output port for general purpose
OPORT1	O	Output port for general purpose
OPORT2	O	Output port for general purpose
OPORT3	O	Output port for general purpose
OPORT4	O	Output port for general purpose
OPORT5	O	Output port for general purpose
OPORT6	O	Output port for general purpose
OPORT7	O	Output port for general purpose
VSS	-	Ground
VDD2	-	+3.3 V power supply (for core logic)
RAMA9	O	External SRAM interface address 9
RAMA8	O	External SRAM interface address 8
RAMA7	O	External SRAM interface address 7
SDOB2	O	PCM output from Sub DSP
SDOB1	O	PCM output from Sub DSP
SDOB0	O	PCM output from Sub DSP
SDBCK1	I+	Bit clock input for SDOA, SDIB, SDOB
SDWCK1	I+	Word clock input for SDOA, SDIB, SDOB
VSS	-	Ground
VDD2	-	+3.3 V power supply (for core logic)
NONPCM	O	Detection of non-PCM data
CRC	O	Detection of AC-3 CRC error
MUTE	O	Detection of auto mute
KARAOKE	O	Detection of AC-3 karaoke data

YSS912

No.	Name	I/O	FUNCTION

56	SURENC	O	Detection of AC-3 2/0 mode Dolby surround encoded input
57	/SDBCK0	O	Inverted SDBCK0 clock output (refer to Block diagram)
58	RAMA6	O	External SRAM interface address 6
59	RAMA5	O	External SRAM interface address 5
60	VSS	-	Ground
61	RAMA4	O	External SRAM interface address 4
62	/IC	Is	Initial clear
63	TEST		Test terminal (to be open in normal use)
64	RAMA3	O	External SRAM interface address 3
65	/CSB	Is+	Sub DSP Chip select
66	/CS	Is	Microprocessor interface Chip select input
67	SO	Ot	Microprocessor interface Serial data output
68	SI	Is	Microprocessor interface / Sub DSP Serial data input
69	SCK	Is	Microprocessor interface / Sub DSP clock input
70	RAMA2	O	External SRAM interface address 2
71	VDD1	-	+5V power supply (for I/Os)
72	RAMD0	I+/ O	External SRAM interface data (STREAM0 output when External SRAM is not in use)
73	RAMD1	I+/ O	External SRAM interface data (STREAM1 output when External SRAM is not in use)
74	RAMD2	I+/ O	External SRAM interface data (STREAM2 output when External SRAM is not in use)
75	RAMD3	I+/ O	External SRAM interface data (STREAM3 output when External SRAM is not in use)
76	RAMD4	I+/ O	External SRAM interface data (STREAM4 output when External SRAM is not in use)
77	RAMD5	I+/ O	External SRAM interface data (STREAM5 output when External SRAM is not in use)
78	RAMD6	I+/ O	External SRAM interface data (STREAM6 output when External SRAM is not in use)
79	RAMD7	I+/ O	External SRAM interface data (STREAM7 output when External SRAM is not in use)
80	VSS	-	Ground
81	VDD2	-	+3.3 V power supply (for core logic)
82	SDWCK0	I	Word clock input for SDIA, SDOA, SDIB, SDOB
83	SDBCK0	I	Bit clock input for SDIA, SDOA, SDIB, SDOB
84	SDIA0	I	AC-3 bitstream (or PCM) data input for Main DSP
85	SDIA1	I	AC-3 bitstream (or PCM) data input for Main DSP
86	RAMA1	O	External SRAM interface address 1
87	RAMA0	O	External SRAM interface address 0
88	RAMWEN	O	External SRAM interface /WE
89	RAMOEN	O	External SRAM interface /OE
90	VSS	-	Ground
91	VDD2	-	+3.3 V power supply (for core logic)
92	IPORT7	I+	Input port for general purpose
93	IPORT6	I+	Input port for general purpose
94	IPORT5	I+	Input port for general purpose
95	IPORT4	I+	Input port for general purpose
96	IPORT3	I+	Input port for general purpose
97	IPORT2	I+	Input port for general purpose
98	IPORT1	I+	Input port for general purpose
99	IPORT0	I+	Input port for general purpose
100	VSS	-	Ground

NOTE) Is:	Schmidt trigger input terminal
I+:	Input terminal with a pull-up resistor
O:	Digital output terminal
Ot:	Tri-state digital output terminal
A:	Analog terminal

4

YSS912

BLOCK DIAGRAM

SDBCK1

SDWCK1

SDOB0

SDOB1

SDOB2

SDOB3

SDIBCKSEL SDOBCKSEL

SDOB Interface

Data RAM

/CSB

Coefficient/ Program RAM

SCK

24 * 16

OVFB

Sub DSP

External RAM

interface

RAMA0 - 16

RAMOEN

RAMWEN

RAMCEN

SDIB Interface

ERAMUSE

RAMD0 - 7

SDIBSEL

SDIB3

SDIB2

SDIB1

C, LFE

SDIB0

LS, RS

SDOA2

SDOA1

SDOA0

SDOA Interface

OPORT0 - 7

Control signals

SDOACKSEL

L,R

24 * 24

RAM

Main DSP

SCK

Microprocessor Interface

Control Registers

AC-3/Pro Logic/DTS

Delay

decoder

Operating clock

(30MHz)

STREAM0 - 7

CPO

/CS

PLL

IPORT0 - 7

Input Buffer

signals

Control

SDIA Interface

CRC

SDIASEL

/SDBCK0

SDBCK0

SDWCK0

SDIA0

SDIA1

SURENC

KARAOKE

MUTE

CRC

AC3DATA

DTSDATA

NONPCM

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