PARTS LIST
BLOCK DIAGRAM(ブロックダイアグラム)
WIRING(基板結線図)
CIRCUIT DIAGRAM(回路図)
PA
200901-
011934
オープンプライス
HAMAMATSU, JAPAN
Copyright (c) Yamaha Corporation. All rights reserved. PDF & ’09.01
SB168-ES
IMPORTANT NOTICE
This manual has been provided for the use of authorized Yamaha Retailers and their service personnel. It has been assumed that basic
service procedures inherent to the industry, and more specifically Yamaha Products, are already known and understood by the users,
and have therefore not been restated.
WARNING : Failure to follow appropriate service and safety procedures when servicing this product may result in personal injury,
IMPORTANT : This presentation or sale of this manual to any individual or firm does not constitute authorization certification,
The data provided is belived to be accurate and applicable to the unit(s) indicated on the cover. The research engineering, and service
departments of Yamaha are continually striving to improve Yamaha products. Modifications are, therefore, inevitable and changes in
specification are subject to change without notice or obligation to retrofit. Should any discrepancy appear to exist, please contact the
distributor’s Service Division.
WARNING : Static discharges can destroy expensive components. Discharge any static electricity your body may have accumulated
destruction of expensive components and failure of the product to perform as specified. For these reasons, we advise
all Yamaha product owners that all service required should be performed by an authorized Yamaha Retailer or the
appointed service representative.
recognition of any applicable technical capabilities, or establish a principal-agent relationship of any form.
by grounding yourself to the ground bus in the unit (heavy gauge black wires connect to this bus.)
IMPORTANT : Turn the unit OFF during disassembly and parts replacement. Recheck all work before you apply power to the unit.
WARNING: This product contains chemicals known to the State of California to cause cancer, or birth defects or other reproductive harm.
DO NOT PLACE SOLDER, ELECTRICAL/ELECTRONIC OR PLASTIC COMPONENTS IN YOUR MOUTH FOR ANY REASON WHAT SO EVER!
Avoid prolonged, unprotected contact between solder and your skin! When soldering, do not inhale solder fumes or expose eyes to solder/
flux vapor!
If you come in contact with solder or components located inside the enclosure of this product, wash your hands before handling food.
LITHIUM BATTERY HANDLING
This product uses a lithium battery for memory back-up.
WARNING :
Leave lithium battery replacement to qualifi ed service personnel.
Always replace with batteries of the same type.
When installing on the PC board by soldering, solder using the connection terminals provided on the battery cells.
Never solder directly to the cells. Perform the soldering as quickly as possible.
Never reverse the battery polarities when installing.
Do not short the batteries.
Do not attempt to recharge these batteries.
Do not disasemble the batteries.
Never heat batteries or throw them into fi re.
ADVARSEL!
Lithiumbatteri-Eksplosionsfare ved fejlagtig håndtering. Udskiftning må kun ske med batteri af samme fabrikat og type. levér det brugte batteri tilbage til
leverandren.
VARNING
Explosionsfara vid felaktigt batteribyte.
Använd samma batterityp eller en ekvivalent typ som rekommenderas av apparattillverkaren.
Kassera använt batteri enligt fabrikantens instruktion.
VAROITUS
Paristo voi räjähtää, jos se on virheellisesti asennettu.
Vaihda paristo ainoastaan laitevalmistajan suosittelemaan tyyppiiin.
Hävitä käytetty paristo valmistajan ohjeiden mukaisesti.
The following information complies with Dutch offi cial Gazette 1995. 45; ESSENTIALS OF ORDER ON THE COLLECTION OF BATTERIES.
• Please refer to the diassembly procedure for the removal of Back-up Battery.
• Leest u voor het verwijderen van de backup batterij deze beschrijving.
Lithium batteries are dangerous because they can be exploded by improper handling. Observe the following precautions when
IMPORTANT. The wires in this mains lead are coloured in accordance with the following code:
GREEN-AND-YELLOW : EARTH
BLUE : NEUTRAL
BROWN : LIVE
As the colours of the wires in the mains lead of this apparatus may not correspond with the coloured markings identifying the terminals
in your plug proceed as follows:
The wire which is coloured GREEN-and-YELLOW must be connected to the terminal in the plug which is marked by the letter E or by
the safety earth symbol or colored GREEN or GREEN-and-YELLOW.
The wire which is coloured BLUE must be connected to the terminal which is marked with the letter N or coloured BLACK.
The wire which is coloured BROWN must be connected to the terminal which is marked with the letter L or coloured RED.
• This applies only to products distributed by Yamaha Music U.K. Ltd. (3 wires)
WARNING
Components having special characteristics are marked and must be replaced with parts having specifi cation equal to those
originally installed.
*1. XLR-3-31 type connectors are balanced. (1=GND, 2=HOT, 3=COLD)
* In these specifications, when dBu represents a specific voltage, 0 dBu is referenced to 0.775 Vrms.
* AD converters are 24-bit linear, 128-times oversampling.
Operation free-air : ±0 °C to +40 °C
Storage : -20 °C to +60 °C
GAIN
-62 dB
Actual Load
Impedance
3 kΩ
For Use With Nominal
50–600 Ω Mics &
600 Ω Lines
NominalMax. before clip
-62 dBu
(0.616 mV)
Input Level
-42 dBu (6.16 mV)
+30 dBu (24.5 V)+10 dBu (2.45 V)+10dB
Connector
XLR-3-31 type
(Balanced)*
1
Analog Output Characteristics
Output
Terminals
OUTPUT 1–875 Ω600 Ω Lines
*1. XLR-3-32 type connectors are balanced. (1=GND, 2=HOT, 3=COLD)
* In these specifications, when dBu represents a specific voltage, 0 dBu is referenced to 0.775 Vrms.
* DA converters are 24-bit, 128-times oversampling.
Actual Source
Impedance
For Use With
Nominal
Max. Output Level
Select SW
+24 dB (default)+4 dBu (1.23 V)+24 dBu (12.3 V)
+18 dB-2 dBu (616 mV)+18 dBu (6.16 V)
Output Level
NominalMax. before clip
Connector
XLR-3-32 type
(Balanced)*
1
Digital Input/Output Characteristics
TerminalFormatData LengthLevelAudioConnector
EtherSound
*1. Use a RJ-45 connector compliant with Neutrik EtherCon
* Use a CAT5e STP (Shielded Twisted Pair) cable compliant with EtherSound.
* Use electrically conductive tape to securely connect the metal part of the connector with the shielded part of the cable in order to prevent
electromagnetic interference.
* An EtherSound certified cable is recommended. Maximum length available depends on each cable specification.
IN
OUT
EtherSound24bit100 Base-TX
®
8 ch Input/
16 ch Output
RJ-45*
1
Control I/O Characteristics
TerminalFormatLevelConnector
NETWORKIEE802.3
* A CAT5e STP (Shielded Twisted Pair) cable is recommended. Maximum length is 100 m.
10 Base-T/
100 Base-TX
RJ-45
4
Electrical Characteristics(電気的特性)
Output impedance of single generator: 150 Ω
Measured with another SB168-ES through EtherSound
Frequency ResponseFs= 44.1 kHz or 48 kHz@20 Hz–20 kHz, reference to the nominal output level @ 1 kHz
InputOutputRLConditionsMin.Typ.Max.Unit
INPUT 1–16OUTPUT 1–8600 ΩGAIN: +10dB-1.500.5dB
Gain ErrorFs= 44.1 kHz, 48 kHz@ 1 kHz
InputOutputRLConditionsMin.Typ.Max.Unit
Input level: -62 dBu, GAIN: -62dB →
INPUT 1–16OUTPUT 1–8600 Ω
Output level +4.0 dBu (Typ.)
Input level: +10 dBu, GAIN: +10dB →
Output level +4.0 dBu (Typ.)
Total Harmonic DistortionFs= 44.1 kHz or 48 kHz
InputOutputRLConditionsMin.Typ.Max.Unit
INPUT 1–16OUTPUT 1–8600 Ω
* Total Harmonic Distortion is measured with a 18 dB/octave filter @80 kHz.
* Hum & Noise are measured with a 6 dB/octave filter @12.7 kHz; equivalent to a 20 kHz filter with infinite dB/octave attenuation.
Rs=150 Ω, GAIN: -62 dB
Rs=150 Ω, GAIN: -10 dB-80-84
EIN
-62
Dynamic RangeFs= 44.1 kHz or 48 kHz
InputOutputRLConditionsMin.Typ.Max.Unit
INPUT 1–16OUTPUT 1–8600 ΩdB108GAIN: +10 dB
* Dynamic Range is measured with a 6 dB/octave filter @12.7 kHz; equivalent to a 20 kHz filter with infinite dB/octave attenuation.
Crosstalk @ 1 kHzFs= 44.1 kHz or 48 kHz
From/ToTo/FromConditionsMin.Typ.Max.Unit
INPUT NINPUT (N-1) or (N+1)
INPUT 1–16, adjacent inputs,
GAIN: +10dB
-80
-80OUTPUT 1–8, input to outputOUTPUT (N-1) or (N+1)OUTPUT N
Phantom Voltage
OutputConditionsMin.Typ.Max.Unit
dBu
dB
V504846hot & cold: No loadINPUT 1–16
Sampling Frequency
ParameterConditionsMin.Typ.Max.Unit
Internal Clock
Frequency48kHz
Accuracy50ppm
kHz49.2043.00Frequency RangeExternal Clock
5
SB168-ES
PANEL LAYOUT(パネルレイアウト)
• Front Panel(フロントパネル)
/
q [INPUT 1–16] Connectors
w [+48V] Indicators
e [SIG] Indicators
r [PEAK] Indicators
t EtherSound [IN]/[OUT] Connectors
y IN/OUT [TX]/[RX] Indicators
u DIP Switches [1–8]
i [+48V MASTER] Switch
o Power Indicator
!0 [POWER] Switch
!1 OUTPUT [1–8] Connectors
4)0
1
q [INPUT(インプット)1 〜 16]端子
w [+48V]インジケーター
e [SIG(シグナル)]インジケーター
r [PEAK(ピーク)]インジケーター
t EtherSound[IN]/[OUT]端子
y IN/OUT[TX]/[RX]インジケーター
u ディップスイッチ[1 〜 8]
i [+48VMASTER](+48Vマスター )スイッチ
o 電源インジケーター
!0 [POWER]スイッチ
!1 OUTPUT(アウトプット)[1 〜 8]端子
2*- 6
• Rear Panel(リアパネル)
/4
q Earth Screw
w [AC IN] Socket
e NETWORK Connector
r [FAN] Switch
6
)0
q アース用ネジ
q [ACIN]端子
q NETWORK端子
q [FAN]スイッチ
DIMENSIONS(寸法図)
SB168-ES
(4)
350
132
359.7
5.7
480
142
10
Unit(単位): mm
7
SB168-ES
CIRCUIT BOARD LAYOUT(ユニットレイアウト)
• Front View(前面から見た図)
FRONT PANEL
HAAD2
(ch 1-8)
LD1
(フロントパネル)
ES
SW
PS
LD2
(ch 9-16)
• Top View <Upper section> (上面から見た図〈上段〉)
DM
DAHAAD2
REAR PANEL
(リアパネル印刷品)
DC
FRONT PANEL
(フロントパネル)
8
SB168-ES
• Top View <Middle section> (上面から見た図〈中段〉)
HAAD2
(CH1-8)
LD1
REAR PANEL
(リアパネル印刷品)
PS
• Top View <Lower section> (上面から見た図〈下段〉)
POWER SUPPLY UNIT
(電源ユニット)
HAAD2
(CH9-16)
LD2
ES
FRONT PANEL
(フロントパネル)
(リアパネル印刷品)
SW
REAR PANEL
DA
FRONT PANEL
(フロントパネル)
9
SB168-ES
DISASSEMBLY PROCEDURE(分解手順)
Precautions
* Notes on Flat Cable
Contacts are visible from the back. Pay attention not to
insert and install the cable to the connector inversely.
(Photo 1)
1. Top Cover
(注意事項)
Front Side
(Time required: About 4 minutes)
(表面)
Photo 1
1-1 Remove the eight (8) screws marked [1160]. The right
and left rack angle can then be removed. (Fig. 1)
1-2 Remove the eighteen (18) screws marked [1110]. The
Wave memory data bus 6
Wave memory data bus 7
Wave memory data bus 8
Wave memory data bus 9
-
Power supply +1.2 V
-
Ground
-
Power supply +3.3 V
-
Ground
-
-
Power supply +3.3 V
-
Ground
-
Power supply +3.3 V
-
Ground
-
-
Power supply +1.2 V
-
SH2A-CPU data bus 31
SH2A-CPU data bus 30
SH2A-CPU data bus 29
SH2A-CPU data bus 28
Wave memory data bus 2
Wave memory data bus 3
Wave memory data bus 4
Wave memory data bus 5
-
Power supply +1.2 V
-
SH2A-CPU data bus 27
SH2A-CPU data bus 26
SH2A-CPU data bus 25
SH2A-CPU data bus 24
Wave memory address bus 2
Wave memory address bus 1
Wave memory data bus 0
Wave memory data bus 1
-
Ground
-
SH2A-CPU data bus 23
SH2A-CPU data bus 22
SH2A-CPU data bus 21
SH2A-CPU data bus 20
Wave memory address bus 6
Wave memory address bus 5
Wave memory address bus 4
Wave memory address bus 3
-
Power supply +3.3 V
-
SH2A-CPU data bus 19
SH2A-CPU data bus 18
-
Power supply +3.3 V
-
Wave memory address bus 10
Wave memory address bus 9
Wave memory address bus 8
Wave memory address bus 7
-
-
-
Ground
-
-
-
SH2A-CPU data bus 17
SH2A-CPU data bus 16
I
Clock output control for SDRAM
Clock output for SDRAM
Wave memory address bus 14
Wave memory address bus 13
Wave memory address bus 12
Wave memory address bus 11
-
Power supply +1.2 V
-
-
Ground
-
-
-
Power supply +1.2 V
Clock enable for SDRAM
SH2A-CPU data bus 15
Wave memory address bus 15
Wave memory address bus 16
Wave memory address bus 17
Wave memory address bus 18
Power supply +1.2 V
-
-
Ground
-
Power supply +1.2 V
SH2A-CPU data bus 11
SH2A-CPU data bus 12
SH2A-CPU data bus 13
SH2A-CPU data bus 14
Wave memory address bus 19
Wave memory address bus 20
Wave memory address bus 21
Wave memory address bus 22
-
-
Ground
-
-
SH2A-CPU data bus 7
SH2A-CPU data bus 8
SH2A-CPU data bus 9
SH2A-CPU data bus 10
Wave memory address bus 23
Wave memory address bus 24
Wave memory address bus 25
Wave memory address bus 26
Power supply +3.3 V
SH2A-CPU data bus 3
SH2A-CPU data bus 4
SH2A-CPU data bus 5
SH2A-CPU data bus 6
Wave memory chip select 3
Wave memory chip select 2
Wave memory chip select 1
Wave memory write enable
Ground
SH2A-CPU read/write enable
SH2A-CPU data bus 0
SH2A-CPU data bus 1
SH2A-CPU data bus 2
Wave memory chip select 0
Wave memory read enable
BOOT ROM switching control
I
Parallel port A0
Power supply +1.2 V
Writing byte of D31 - D24/Selecting D31 - D24 in case of SDRAM
RAS output for SDRAM
CAS output for SDRAM
SH2A-CPU read enable
Parallel port A1
Parallel port A2
Parallel port A3
Parallel port A4
Power supply +1.2 V
-
-
Ground
-
Power supply +3.3 V
-
Ground
Power supply +3.3 V
-
-
Ground
-
Power supply +3.3 V
-
Ground
Power supply +1.2 V
SH2A-CPU address bus 0
Writing byte of D7 - D0/Selecting D7 - D0 in case of SDRAM
Writing byte of D15 - D8/Selecting D15 - D8 in case of SDRAM
Writing byte of D23 - D16/Selecting D23 - D16 in case of SDRAM
Parallel port A5
Parallel port A6
Parallel port A7
Power supply +3.3 V
External CPU data bus 1
External CPU data bus 5
External CPU data bus 9
External CPU data bus 13
External CPU address bus 2
I
External CPU chip select
I
Bit clock output
Interrupt input 0
I
SH2A-CPU address bus 25
SH2A-CPU address bus 21
SH2A-CPU address bus 17
SH2A-CPU address bus 13
Power supply +3.3 V
SH2A-CPU address bus 3
SH2A-CPU address bus 2
SH2A-CPU address bus 1
Parallel port B0
Parallel port B1
Power supply +3.3 V
Parallel port B6
External CPU data bus 2
External CPU data bus 6
External CPU data bus 10
External CPU data bus 14
External CPU address bus 3
I
Serial audio input 0
I
Word clock output 2/Serial audio output 2
Interrupt input 1
I
SH2A-CPU data bus width configuration
I
SH2A-CPU address bus 22
SH2A-CPU address bus 18
SH2A-CPU address bus 14
SH2A-CPU address bus 10
Power supply +3.3 V
SH2A-CPU address bus 5
SH2A-CPU address bus 4
Parallel port B2
Power supply +3.3 V
Parallel port B4
Parallel port B7
External CPU data bus 3
External CPU data bus 7
External CPU data bus 11
External CPU data bus 15
External CPU read enable
I
Serial audio input 1
I
Word clock output
Clock output 2
External wait input
I
SH2A-CPU address bus 23
SH2A-CPU address bus 19
SH2A-CPU address bus 15
SH2A-CPU address bus 11
SH2A-CPU address bus 8
Power supply +3.3 V
SH2A-CPU address bus 6
Power supply +3.3 V
Parallel port B3
Parallel port B5
External CPU data bus 0
External CPU data bus 4
External CPU data bus 8
External CPU data bus 12
External CPU address bus 1
I
External CPU write enable
I
Serial audio output 0
Serial audio output 1
Clock output
Sync. input from external device
I
SH2A-CPU address bus 24
SH2A-CPU address bus 20
SH2A-CPU address bus 16
SH2A-CPU address bus 12
SH2A-CPU address bus 9
SH2A-CPU address bus 7
Power supply +3.3 V
(Connected to VSS on P.C.B.)
(Pulled up on P.C.B.)
Output port B8
Output port B9
IO power supply (3.3V)
Ground
Output port A0
CPU chip select 6
CPU chip select 5
CPU read enable
CPU write enable H
CPU write enable L
Output port A1
CPU address bus 11
CPU address bus 12
CPU address bus 13
CPU address bus 14
CPU address bus 15
Output port A2
Ground
Internal power supply (2.5V)
IO power supply (3.3V)
Ground
CPU address bus 1
CPU address bus 2
CPU address bus 3
CPU address bus 4
CPU address bus 5
CPU address bus 6
CPU address bus 7
CPU address bus 8
Ground
Internal power supply (2.5V)
IO power supply (3.3V)
Ground
CPU data bus 0
CPU data bus 1
CPU data bus 2
CPU data bus 3
CPU data bus 4
CPU data bus 5
IO power supply (3.3V)
Ground
CPU data bus 6
CPU data bus 7
CPU data bus 8
CPU data bus 9
Internal power supply (2.5V)
Ground
(Connected to VDD on P.C.B.)
(Connected to VDD on P.C.B.)
(Pulled up on P.C.B.)
CPU data bus 10
CPU data bus 11
CPU data bus 12
CPU data bus 13
CPU data bus 14
CPU data bus 15
Ground
Output port A3
CPU wait signal
Chip select (103V)
Chip select (105V)
Chip select (JK1)
Chip select (CONT)
Power supply
Chip select (SLOT1)
Chip select (SLOT2)
Chip select (S104)
Chip select (REC2)
Chip select (MTLED)
Power supply
Chip select (USB)
Chip select (SMPTE)
Chip select (UART)
Ground
Power supply
System reset
CPU clock
(Connected to VSS on P.C.B.)
Ground
Ground
Chip select (ATSC1)
Power supply
Chip select (ATSC2)
Output port A4
Output port A5
Output port A6
Internal counter synchronous signal output
Internal counter synchronous signal input
Power supply
Chip select (DSP7_1)
Chip select (DSP7_2)
Chip select (DSP7_3)
Chip select (DSP7_4)
Chip select (DSP7_5)
Chip select (DSP7_6)
Power supply
Output port A7
Output port A8
Chip select (DSP6_1)
Chip select (DSP6_2)
Chip select (DSP6_3)
Chip select (DSP6_4)
(Pulled up on P.C.B.)
Power supply
(Connected to VSS on P.C.B.)
(Connected to VSS on P.C.B.)
Ground
Power supply
Chip select (DSP7_ALL)
Chip select (DSP6_ALL)
Output port A9
256FS synchronous clock output
256FS synchronous clock input (Master)
256FS synchronous clock input (Slave)
Ground
Power supply
For internal clock 88.2k, 44.1k
For internal clock 96k, 48k
Clock for X1 of DIR2
Output port A10
Ground
Power supply
External word clock input 1
External word clock input 2
External word clock input 3
External word clock input 4
Ground
Power supply
External WC (256FS) input 1
External WC (256FS) input 2
Output port A11
MCA input of DIR2
MCB input of DIR2
WC input of DIR2
Ground
Power supply
MCC input of DIR2
SYNC input of DIR2
EXTWC clock select output
DIRWC clock select output
Output port A12
PLL VCO OUT input
Ground
Power supply
EXT WC SEL to MWC comparison circuit output
Output port A13
Master clock (256FS)
System clock (128FS)
Ground
Power supply
(Connected to VDD on P.C.B.)
(Connected to VSS on P.C.B.)
(Pulled up on P.C.B.)
(Pulled up on P.C.B.)
System clock (64FS)
Word clock
Synchronous signal
Output port A14
WC output for BNC connector
Output port A15
Clock (256FS) for MY SLOT1
Clock (256FS) for MY SLOT2
Power supply
Synchronous signal for MY SLOT1
Synchronous signal for MY SLOT2
Output port 80
Clock (12MHz) for MY SLOT
Clock (6MHz) for MY SLOT
Ground
Clock (3MHz) for MY SLOT
Output port B1
Word clock (48/44) for MY SLOT
Synchronous signal (48/44) for MY SLOT
Output port B2
Clock for analog circuit
Power supply
PLL lock detect signal
DIR2 PLL lock signal
Ground
Scan test input
ATPG test input
Test mode selection
Power supply
2TR DIN UNLOCK input
2TR DIN UNLOCK input
Ground
Output port B3
Lock select output
Lock delay input
Output port B4
Mute input
Power supply
Mute output 1
Mute output 2
Mute output 3
Mute output 4
Mute output 5
Mute output 6
Power supply
Output port B5
Register setting value output
Register setting value output
Output port B6
SLOT1 16/8 ch selection
SLOT2 16/8 ch selection
Output port B7
FUNCTION
SB168-ES
YM3436D-VZ (XG948F00) DIR2 (Digital Format Interface Receiver)
PIN
NO.
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
DAUX
HDLT
DOUT
VFL
OPT
SYNC
MCC
WC
MCB
MCA
SKSY
XI
XO
P256
LOCKN
Vss
TST2
DIM1
DIM0
DOM1
DOM0
KM1
I/OFUNCTIONNAME
I
O
O
O
O
O
O
O
O
O
I
I
O
O
O
O
I
I
I
I
I
Audio data auxiliary input
Asynchronous buffer operation flag output
Audio data output
Validity flag output
Synchronous signal output (fs) for DAC
Synchronous signal output (fs) for DSP
Bit clock output (64fs)
Word clock output (fs)
Bit clock output (128fs)
Bit clock output (256fs)
Clock synchronous control input
Crystal oscillator connection or external
clock input (256fs)
Crystal oscillator connection
VCO clock output (256fs when locked)
PLL lock flag output
Ground (for logic block)
LSI test terminal (usually disconnected)
Data input mode select 1
Data input mode select 0
Data output mode select 1
Data output mode select 0
Clock mode select 1
PIN
NO.
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
RSTN
Vdda
CTLN
PCO
(NC)
CTLP
Vssa
TSTN
KM2
KM0
FS1
FS0
CSM
EXTW
DDIN
LR
Vdd
ERR
EMP
CD0
CCK
CLD
I/OFUNCTIONNAME
I
I
O
I
I
I
I
O
O
I
I
I
O
O
O
O
I
I
DM: IC207
System reset input
+5V power supply (for VCO block, connected with
VDD externally)
VCO control input
PLL phase comparator output
VCO adjastment input (usually connected with VSSA)
Ground (for VCO block, connected with VSS externally)
LSI test terminal (usually disconnected)
Clock mode select 2
Clock mode select 0
Sampling frequency code output 1/channel status output
Sampling frequency code output 0/user data output
Channel status, user data output select
audio data auxiliary input word clock
EIAJ (AES/EBU) digital audio interface signal input
PLL word clock output (fs when locked)
+5V power supply (for logic block)
Data error flag output
Emphasis control code output/block start
synchronous signal output
Microprocessor interface data output
Microprocessor interface clock input
Microprocessor interface load input
AK5385BVF-E2 (X5364B00) ADC (Analog to Digital Converter)
PIN
NO.
10
11
12
13
14
1
2
3
4
5
6
7
8
9
VREFL
AVSS
VCOM
LIN+
LIN–
CKS0
DVDD
DVSS
OVF
PDN
DIF
M/S
LRCK
BICK
I/OFUNCTIONNAME
O
O
I/O
I/O
I
–
Lch voltage reference input
Analog ground
Common voltage output
I
I
I
–
–
Lch analog positive input
Lch analog negative input
Master clock select 0
Digital power supply (3.0 - 5.25 V)
Digital ground
Analog input overflow detect
I
I
I
Power down mode
Audio interface format
Master / Slave mode
Output channel clock
Audio serial data clock
PIN
NO.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
SDTO
CKS1
MCLK
DFS0
HPFE
DFS1
BVSS
AVSS
AVD D
RIN–
RIN+
TEST
AVSS
VREFR
I/OFUNCTIONNAME
O
I
I
I
I
I
–
–
–
I
I
I
–
I
AK4393VF-E2 (XW029A0R) DAC (Digital to Analog Converter)
PIN
NO.
1
2
3
4
5
6
7
8
SMUTE//CS
9
10
DEM0/CCLK
11
DEM1/CDTI
12
13
14
DVSS
DVDD
MCLK
/PD
BICK
SDATA
LRCK
DFS
DIF0
DIF1
DIF2
I/OFUNCTIONNAME
-
I
I
I
I
I
I
I
I
I
Digital ground
Digital power supply
Master clock
Power down mode
Audio serial data clock
Audio serial data input
L/R clock
Soft mute
Double speed sampling mode
De-emphasis enable
I
I
Digital input format
I
PIN
NO.
15
16
17
18
19
20
21
22
23
24
25
26
27
28
BVSS
VREFL
VREFH
AVDD
AVSS
AOUTR-
AOUTR+
AOUTL-
AOUTL+
VCOM
P//S
CKS0
CKS1
CKS2
I/OFUNCTIONNAME
I
I
-
-
O
O
O
O
O
I
I
I
I
HAAD2: IC106, IC306, IC506, IC706
Audio serial date output
Master clock select 1
Master clock input
Sampling speed select 0
High pass filter enable
Sampling speed select 1
Substrate ground
Analog ground
Analog power supply (4.75 - 5.25 V)
Rch analog negative input
Rch analog positive input
Test pin
Analog ground
Rch voltage reference input
DA: IC903–906
Substrate ground
Low level voltage reference
High level voltage reference
Analog power supply +5 V
Analog ground
Rch negative analog output
Rch positive analog output
Lch negative analog output
Lch positive analog output
Common voltage output
Parallel/serial select
Master clock select
RD-0759 (X7792A00) DC-DC MODULE
26
PIN
NO.
10
11
12
1
2
3
4
5
6
7
8
9
NAME
PGOOD
ON/OFF1
+VIN
+VIN
+VIN
-VIN
-VIN
-VIN
ON/OFF2
MODE
FIN
NC
I/O
FUNCTION
I
O
O
Signal input for external synchronization
Power good flag (O.D)
VOUT1 output ON/OFF control and soft start control
I
I
Voltage input
I
-
Non-connection
-
-
Ground on input side
-
O
O
VOUT2 output ON/OFF control and soft start control