Yamaha OPL3-SA3 User Manual

YMF715E

OPL3-SA3

Preliminary

OPL3 Single-chip Audio System 3

OUTLINE

■■■■

YMF715E-S (OPL3-SA3) is a single audio chip that integrates OPL3 and its DAC, 16bit Sigma-delta CODEC, MPU401 MIDI interface, joystick port, and a 3D enhanced controller including all the analog components which is suitable for multi-media application. This LSI is fully compliant with Plug and Play ISA 1.0a, and supports all the necessary features, i.e. 16bit address decode, more IRQs and DMAs in compliance with PC’96. This LSI also supports the expandability, i.e. Zoomed Video, Modem and CDROM interface in a Plug and Play manner, and power management (power down, power save, partial power down, and suspend/resume) that is indispensable with power-conscious application.

FEATURES

■■■■

Built-in OPL3 (FM-synthesizer)

●

Supports Sound Blaster Game compatibility

●

Supports Windows Sound System compatibility

●

Supports Plug & Play ISA 1.0a compatibility

●

Full Duplex operation

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Built-in MPU401 Compatible MIDI I/O port

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Built-in Joystick port

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Built-in the 3D enhanced controller including all the analog components

●

Supports multi-purpose pin function

●

(Support 16-bit address decode, DAC interface for OPL4-ML/ML2, Zoomed Video port, EEPROM

interface, MODEM interface, IDE CD-ROM interface)

Hardware and software master volume control

●

Supports monaural input

●

24 mA TTL bus drive capability

●

Supports Power Management(power down, power save, partial power down, and suspend/resume)

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+5V/ +3.3V power supply for digital, 5V power supply for analog.

●

100 pin SQFP package (YMF715E-S)

●

The contents of this catalog are target specifications and are subject to change without prior notice. When using this device, please recheck the specifications.

YAMAHA

CORPORATION

May 21, 1997

YMF715E

/ /

PIN CONFIGURATION

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YMF715E-S

SBFLTR

SBFLTL

SYNSHL

SYNSHR

TRECR

TRECL

AUX2L

AUX2R

MIC

MIN

VREFO

VREFI

AVSS

AVDD

LINEL

LINER

AUX1L

AUX1R

OUTL

OUTR

VOCIL

VOCIR

VOCOR

VOCOL

ADFLTL

AVSS

AVDD

GP0 GP1 GP2 GP3 GP4 GP5 GP6 GP7

DVSS

RESET

/IOW

/IOR

DVDD

AEN

A11 A10

A9 IRQ3 IRQ5 IRQ7 IRQ9

IRQ10 IRQ11

9998979695949392919089888786858483828180797877

100

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

26272829303132333435363738394041424344454647484950

75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

ADFLTR DVSS SEL0 SEL1 SEL2 MP0 MP1 MP2 MP3 MP4 MP5 MP6 MP7 MP8 MP9 DVDD

VOLUP

VOLDW A0 A1 A2 X33O X33I X24O X24I

D0D1D2

DRQ0

DRQ1

/DACK0

DRQ3

/DACK1

/DACK3

DVSS

DVDD

D4D5D6

100 pin SQFP Top View

A8A7A6A5A4

RXD

DVSS

TXD

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YMF715E

PIN DESCRIPTION

■

ISA bus interface: 36 pins

name D7-0 8 I/O TTL 24mA Data Bus A11-0 12 I TTL - Address Bus AEN 1 I TTL - Address Bus Enable /IOW 1 I /IOR 1 I RESET 1 I IRQ3,5,7,9,10,11 6 T TTL 12mA Interrupt request DRQ0, 1, 3 3 T TTL 12mA DMA Request /DACK0, 1, 3 3 I TTL - DMA Acknowledge

Analog Input & Output : 24 pins

name OUTL 1 O - - Left mixed analog output

OUTR 1 O - - Right mixed analog output VREFI 1 I - - Voltage reference input VREFO 1 O - - Voltage reference output AUX1L 1 I - - Left AUX1 input AUX1R 1 I - - Right AUX1 input AUX2L 1 I - - Left AUX2 input AUX2R 1 I - - Right AUX2 input LINEL 1 I - - Left LINE input LINER 1 I - - Right LINE input MIC 1 I - - MIC input MIN 1 I - - Monaural input TRECL 1 - - - Left Treble capacitor TRECR 1 - - - Right Treble capacitor SBFLTL 1 - - - Left SBDAC filter SBFLTR 1 - - - Right SBDAC filter SYNSHL 1 - - - Left SYNDAC sample / hold capacitor SYNSHR 1 - - - Right SYNDAC sample / hold capacitor ADFLTL 1 - - - Left input filter ADFLTR 1 - - - Right input filter VOCOL 1 O - - Left voice output VOCOR 1 O - - Right voice output VOCIL 1 I - - Left voice input VOCIR 1 I - - Right voice input

ins I/O type Size function

Schmitt Schmitt Schmitt

ins I/O type size function

- Write Enable

- Read Enable

- Reset

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YMF715E

)

Multi-purpose pins : 13 pins

name SEL2-0 3 I+ CMOS - Refer to “Multi-purpose pins” section MP9-0 10 I+/O TTL 2mA Refer to “multi-purpose pins” section

Others : 27 pins

name GP3-0 4 IA - - Game Port GP7-4 4 I+ RXD 1 I+ TXD 1 O TTL 4mA MIDI Data Transfer /VOLUP 1 I+ /VOLDW 1 I+ X33I 1 I CMOS - 33.8688 MHz X33O 1 O CMOS 2mA 33.8688 MHz X24I 1 I CMOS - 24.576 MHz X24O 1 O CMOS 2mA 24.576 MHz AVDD 2 - - - Analog Power Supply (put on +5.0V DVDD 3 - - - Digital Power Supply (put on +5.0 V or +3.3V AVSS 2 - - - Analog GND DVSS 4 - - - Digital GND

ins I/O type size function

Schmitt Schmitt

- Game Port

- MIDI Data Receive

- Hardware Volume (Up)

- Hardware Volume (Down)

Total : 100 pins

Note :

I+: Input Pin with Pull up Resistor T: TTL-tri-state output pin Schmitt: TTL-Schmitt input pin

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YMF715E

BLOCK DIAGRAM

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May 21, 1997

YMF715E

)

(

)

(

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FUNCTION OVERVIEW

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1. Multi-purpose pin 1-1. Multi-purpose function

OPL3-SA3 can support the various functions listed below by programming SEL2-0 pins.

A. 16-bit address decode B. EEPROM interface C. Zoomed video port D. CPU and DAC interface for OPL4-ML/ML2 E. MODEM interface F. IDE CD-ROM interface

Following table shows what combinations of the above functions are available for each SEL2-0 pins.

SEL 16bit Dec. EEPROM ZV port

0 - - - - - - Test mode

○

1 2 3 4 5 6 - - - - - - reserved 7

(*1)

○○

○

(*4)

○

(*4)

○

○○ ○○

OPL4-ML/ML2

○

(*2)

○

(*3)

○

(*3)

○

MODEM CDROM Remark

○○ ○

--S/C

- - Note PC

○

- - M/B, Note PC

(*1)

-S/C

- Note PC

S/C,C/C(add-in

Where,

S/C : Sound Card C/C : Combo Card (Sound and Modem) M/B : Desktop Mother Board

SEL=0 SEL=1 SEL=2 SEL=3 SEL=4 SEL=5 SEL=6 SEL=7 SEL0 pin01010101 SEL1 pin00110011 SEL2 pin00001111

add-in add-in

Notice

*1 : External PAL is needed. *2 : External wavetable synthesizer (ex.OPL4-ML/ML2) is mixed as analog signal using external

DAC.

*3 : Clock module (ex.MK1420) is used to generate the clock for OPL4-ML/ML2 and it will be

mixed analog signal by having an additional DAC. *4 : External TTLs (ex.LS138) is needed. See section 1-2 and 1-3 for implementation detail.

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YMF715E

purp

)

1-2. Pin description

SEL=0 SEL=1 SEL=2 SEL=3 SEL=4 SEL=5 SEL=6 SEL=7 MP0 - /MCS /MCS /EXTEN /EXTEN /MCS - /EXTEN MP1 - MIRQ MIRQ /SYNCS /SYNCS MIRQ - /SYNCS MP2 - ROMCLK ROMCLK ROMCLK BCLK_ZV A12 - A12 MP3 - ROMCS ROMCS ROMCS LRCK_ZV A13 - A13 MP4 - ROMDI ROMDI ROMDI SIN_ZV A14 - A14 MP5 - ROMDO ROMDO ROMDO /XRST A15 - A15 MP6 - /CDCS0 A12 BCLK_ML BCLK_ML BCLK_ZV - BCLK_ML MP7 - /CDCS1 A13 LRCK_ML LRCK_ML LRCK_ZV - LRCK_ML MP8 - CDIRQ A14 SIN_ML SIN_ML SIN_ZV - SIN_ML MP9 - CLKO A15 CLKO CLKO /XRST - CLKO

Note : do not select SEL=0 and SEL=6.

SEL=0 ; TEST mode SEL=6 ; reserved

Mutil-

name I/O function /MCS O Chip select output for MODEM chip (COM MIR ROMCLK O Serial data clock output for external EEPROM ROMCS O Chip select output for external EEPROM ROMDI I+ Serial data input for external EEPROM ROMDO O Serial data output for external EEPROM /CDCS0 O Chip select output for IDE CD-ROM (/CS1FX /CDCS1 O Chip select output for IDE CD-ROM (/CS3FX CDIR A12 - 15 I Address bus for ISA-bus /EXTEN I+ Enable OPL4-ML/ML2 interface /SYNCS O Chip select output for OPL4-ML/ML2 BCLK_ML I+ Bit clock input for OPL4-ML/ML2 LRCK_ML I+ L/R clock input for OPL4-ML/ML2 SIN_ML I+ Serial data input for OPL4-ML/ML2 CLKO O Master clock output (33.8688MHz BCLK_ZV I+ Bit clock input for Zoomed Video port (I2S LRCK_ZV I+ L/R clock input for Zoomed Video port (I2S SIN_ZV I+ Serial data input for Zoomed Video port (I2S /XRST O Inverted RESET output

ose pins:

I+ Interrupt request input for MODEM (COM

I+ Interrupt request input for IDE CD-ROM

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YMF715E

1-3. System Block Diagram

(1) SEL=1 (Sound Card and Combo Card Add-in)

SD15-8

SA2-0

SA15-12

AEN

RESETDRV

SD7-0

/IOW,/IOR

SA11-0

SD7-0

16V8

/CDCS1

/CDCS0

MP7

MP6

RESET

IOW,/IOR A11-0 D7-0

ENH

RESET

ENL

CDIRQ

AEN*

MP8

AEN

YMF715E-S (OPL3-SA3)

245

AUX2L

AUX2R

MP0 MP1

IDE CD-ROM I/F

MCS

MIRQ

MODEM I/F

}

MP3

MP2

MP4

ROMDI

ROMCS

ROMCL

EEPROM

MP5

ROMDO

TXD

MP9

TXD

CLKO

RXD

CLKO

BCO

LRORESET DO2

YAC516

OPL4-ML/ML2

1. External PAL(16V8 etc.) (i) connect the signal AEN* generated by decoding SA15-12 and AEN to the AEN of OPL3-

SA3.

(ii) generate the /G(enable) signal for Data Bus Buffer (LS245) by decoding the /CDCS1-0 and

SA2-0.

(iii) generate the /RESET signal from RESETDRV.

May 21, 1997

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YMF715E

2. Master Clock

Both 33.8688MHz and 24.576MHz are used or 14.31818MHz and clock module

(ex.MK1420 by Micro Clock) are used.

3. OPL4-ML/ML2

The external DAC (YAC516) is necessary for wavetable upgrade.

(2) SEL=2 (Sound Card and Combo Card for Add-in)

RESETDRV

/IOW,/IOR

AEN

SA15-12

SA11-0

SD7-0

24.576MHz

33.8688MHz

MK1420

RESET

IOW,/IOR AEN MP9-6 A11-0 D7-0 X24I X33I

MP2

ROMCL

YMF715E-S (OPL3-SA3)

MP4

MP3

MP5

ROMDI

ROMCS

ROMDO

EEPROM

14.31818MHz

AUX2L

AUX2R

TXD

RXD

RESET

OPL4-ML/ML2

MP0 MP1

CLKO

BCO

LRO DO2

MCS

MIRQ

YAC516

MODEM I/F

}

1. OPL4-ML/ML2 The external DAC (YAC516) and the clock module (ex.MK1420 by Micro Clock) are

necessary for wavetable upgrade.

2. MK1420 The MK1420 is the clock module that generates all clocks necessary for this chipset . It is by

Micro Clock and its package is SOP8.

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YMF715E

(3) SEL=3 (Sound Card for Add-in)

SA15-12

AEN

RESETDRV

/IOW,/IOR

SA11-0

SD7-0

/IOW,/IOR

SA2-0 SD7-0

AEN*

138

AEN

RESET

IOW,/IOR A11-0 D7-0

MP3

MP2

MP4

ROMDI

ROMCS

ROMCL

EEPROM

245

YMF715E-S (OPL3-SA3)

MP5

ROMDO

/EXTEN

RESET /IOW

/IOR A2-0 D7-0

DBDIR

MP0

OPL4-

ML/ML2

MP6 MP7 MP8

TXD

MP9

MP1

TXD

CLKO

/SYNCS

XII

/OPLCS

RXD

DO2

LRO

BCO

BCLK_ML LRCK_ML SIN_ML

1. 16bit Address Decode The signal AEN* generated by decoding SA15-12 and AEN needs to be connected to the

AEN of OPL3-SA3.

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YMF715E

(4) SEL=4 (for Notebook PC)

SA15-12

AEN

RESETDRV

/IOW,/IOR

SA11-0

SD7-0

/IOW,/IOR

SA2-0 SD7-0

AEN*

138

AEN

RESET

IOW,/IOR A11-0 D7-0

245

YMF715E-S (OPL3-SA3)

MP0

MP1

/EXTEN

RESET /IOW

/IOR A2-0 D7-0

DBDIR

/SYNCS

/OPLCS

OPL4-

ML/ML2

MP2 MP3 MP4 MP5 MP6 MP7 MP8

TXD

MP9

TXD

CLKO

XII

RXD

DO2

LRO

BCO

BCLK_ZV LRCK_ZV SIN_ZV

XRST BCLK_ML LRCK_ML SIN_ML

}

ZV Port

Peripheral Equipment

1. 16bit Address Decode The signal AEN* generated by decoding SA15-12 and AEN needs to be connected to the

AEN of OPL3-SA3.

2. ZV Port and OPL4-ML/ML2 I/F ZV port is supported by using the internal DAC of OPL3-SA3 that is originally dedicated for

the use of internal OPL3.

(i) either OPL4-ML/ML2 or ZV port is active at a time and simultaneous use is not

possible.

(ii) which function the internal DAC is used for is determined by the SA3 Control

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YMF715E

(5) SEL=5 (for Notebook PC)

RESETDRV

/IOW,/IOR

AEN

SA15-12

SA11-0

SD7-0

24.576MHz

33.8688MHz

MK1420

RESET

IOW,/IOR AEN MP5-2 A11-0 D7-0 X24I X33I

YMF715E-S (OPL3-SA3)

14.31818MHz

MP0 MP1 MP6 MP7 MP8 MP9

AUX2L

AUX2R

TXD

RXD

RESET

CLKO

OPL4-ML/ML2

BCO

LRO DO2

BCLK_ZV LRCK_ZV SIN_ZV

XRST

YAC516

MCS

MIRQ

}

MODEM I/F

ZV Port

Peripheral Equipment

1. Internal DAC The internal OPL3 and the ZV Port shares the internal DAC, which is very similar to the case

mentioned the previous section.

(i) either internal OPL3 or ZV port is active at a time and simultaneous use is not

possible.

(ii) which function the internal DAC is used for is determined by the SA3 control

2. OPL4-ML/ML2 The external DAC (YAC516) and the clock module (ex.MK1420 by Micro Clock) are

necessary for wave table upgrade.

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YMF715E

(6) SEL=7 (for Notebook PC, Desktop P C )

RESETDRV

/IOW,/IOR

AEN

SA15-12

SA11-0

SD7-0

/IOW,/IOR

SA2-0 SD7-0

RESET

IOW,/IOR AEN MP5-2 A11-0 D7-0

245

YMF715E-S (OPL3-SA3)

MP0

MP1

/EXTEN

RESET /IOW

/IOR A2-0 D7-0

DBDIR

/SYNCS

/OPLCS

OPL4-

ML/ML2

MP6 MP7 MP8

MP9

TXD

CLKO

XII

RXD

DO2

LRO

BCO

BCLK_ML LRCK_ML SIN_ML

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YMF715E

2. ISA Interface

OPL3-SA3 supports ISA Plug and Play (PnP) that frees the users from configuring the I/O address, IRQ and DMA channel. Those system resources are set automatically by the system. However even when used in Non PnP system, the configuration can be changed with software.

2-1. PnP Auto-Configuration mode

OPL3-SA3 has the following I/O port to support the Plug and Play ISA.

Address port: 279h Write Data Port: A79h Relocatable Read Data Port: 203h - 03FFh

The following four Logical Devices are supported by OPL3-SA3.

Logical Device No. 0

Sound Blaster compatible Playback system (SB Base) 16-bit CODEC (WSS Base) MPU401 (MPU Base) OPL3 (AdLib Base) OPL3-SA3 control register (CTRL Base)

Logical Device No. 1

Joy Stick

Logical Device No. 2 (Optional)

MODEM (COM port)

Logical Device No. 3 (Optional)

IDE CD-ROM interface

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May 21, 1997

YMF715E

2-2. PnP ISA Configuration Register

OPL3-SA3 has the fo llowing Registers defined in the PnP ISA software.

0x00

0x22 0x30

Card Control

LDN=0, SA3 Sound S

0x75

LDN=1, Joy Stick

LDN=2, MODEM

LDN=3, CDROM

stem

Listed below is the register map of card control register and logical device registers. For the detailed description of each register, please refer to the Plug and Play ISA Specification 1.0a

Card Control Registers

Index R/W D7 D6 D5 D4 D3 D2 D1 D0

00h W Set RD_DATA 01h R Serial Isolation

02h W Config Control 03h W Wake [CSN] 04h R Resource Data 05h R Status 06h R/W Card Select Number 07h R/W Logical Device Number 20h W Resource Data Write 21h W IKD RDWE

RDWE : Resource Data Write Enable Setting “1” to this bit means the host can download the resources data to EEPROM and internal SRAM via 20h. IKD : Initiation Key Disable Setting “1” to this bit means OPL3-SA3 should not detect the initiation key in the Wait for Key state.

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YMF715E

Logical Device Number = 0 : SA3 Sound System

30h R/W Activate 60h R/W I/O port base address[15..8], Descriptor 0 (SB base) 61h R/W I/O port base address[7..0], Descriptor 0 (SB base) 62h R/W I/O port base address[15..8], Descriptor 1 (WSS base) 63h R/W I/O port base address[7..0], Descriptor 1 (WSS base) 64h R/W I/O port base address[15..8], Descriptor 2 (AdLib base) 65h R/W I/O port base address[7..0], Descriptor 2 (AdLib base) 66h R/W I/O port base address[15..8], Descriptor 3 (MPU base) 67h R/W I/O port base address[7..0], Descriptor 3 (MPU base) 68h R/W I/O port base address[15..8], Descriptor 4 (CTRL base) 69h R/W I/O port base address[7..0], Descriptor 4 (CTRL base) 70h R/W Interrupt request level select 0 (for IRQ-A) 71h R Interrupt request type select 0 (for IRQ-A) 72h R/W Interrupt request level select 1 (for IRQ-B) 73h R Interrupt request type select 1 (for IRQ-B) 74h R/W DMA channel select 0 (for DMA-A) 75h R/W DMA channel select 1 (for DMA-B)

Logical Device Number = 1 : Joystick

30h R/W Activate 60h R/W I/O port base address[15..8] 61h R/W I/O port base address[7..0]

Logical Device Number = 2 : MODEM (Optional)

30h R/W Activate 60h R/W I/O port base address[15..8] 61h R/W I/O port base address[7..0] 70h R/W Interrupt request level select 71h R Interrupt request type select

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YMF715E

Logical Device Number = 3 : CD-ROM (Optional)

30h R/W Activate 60h R/W I/O port base address [15..8], Descriptor 0 (/CDCS0) 61h R/W I/O port base address [7..0], Descriptor 0 (/CDCS0) 62h R/W I/O port base address [15..8], Descriptor 1 (/CDCS1) 63h R/W I/O port base address [7..0], Descriptor 1 (/CDCS1) 70h R/W Interrupt request level select 71h R Interrupt request type select

2-3. Recommended Resource Data

The recommended resource data is the followings.

(1) LDN=0:SA3 Sound System

I/O (SB base): 16bit address decode