Page 1
M2500
LSI PIN DESCRIPTION
HD6435208A00P (XK278A00) CPU <H8/520>
PIN
NO.
NAME I/O FUNCTION
1 EXT I Clock 33 A7 O
2 EXTAL I 34 A8 O
3 /WAIT I Bus cycle wait 35 A9 O
4 /IRQ0 O Interrupt request 36 A10 O
5 A18 O 37 A11 O Address bus
6 A17 O Address bus 38 A12 O
7 A16 O 39 A13 O
8 /AS O Address strobe 40 A14 O
9 /RD O Read strobe 41 A15 O
10 /WR O Write strobe 42 AVCC Analog power supply
11 VCC Power supply 43 P50 O
12 MD0 I 44 P51 O
13 MD1 I Mode select 45 P52 O
14 MD2 I 46 P53 O Port 5
15 /RES I Reset 47 P54 O
16 NMI I Non-maskable interrupt request 48 P55 O
17 VSS Ground 49 P56 O
18 D0 I/O 50 P57 O
19 D1 I/O 51 VSS Ground
20 D2 I/O 52 AVSS Analog ground
21 D3 I/O Data bus 53 AN0 I
22 D4 I/O 54 AN1 I Analog data input
23 D5 I/O 55 AN2 I
24 D6 I/O 56 AN3 I
25 D7 I /O 57 AVCC Analog power supply
26 A0 O 58 TXD2 O Transmit data
27 A1 O 59 RXD2 I Receive data
28 A2 O 60 A19 O Address bus
29 A3 O Address bus 61 TXD1 O Transmit data
30 A4 O 62 RXD1 I Receive data
31 A5 O 63 SCLK I Clock for serial operation
32 A6 O 64 VSS Ground
PIN
NO.
NAME I/O FUNCTION
AK4320-VM-E1 (XR361A00) DAC
PIN
NO.
NAME I/O FUNCTION
1 CKS I Clock select 13 DEM1 I De-emphasis mode
2 DVDD Digital VDD 14 DIF
3 DVSS Digital GND 15 DIF1 I
4X TOO Xtal out 16 VCNT I Mute Control
5 XTI I Xtal in 17 AOUT
6
7 BICK I Serial bit clock 19 VCOM O Common
8 SDAT
9 LRCK I L/R clock 21 AVSS Analog VSS
10 SMUT
11 HOLD I Soft mute hold 23 DZF O Zero input
12 DEM0 I De-emphasis mode 24 ZMUT
PD I Power down 18 AOUT
I Serial data input 20 AVDD Analog VDD
I Soft mute 22 VREF I V reference
PIN
NO.
NAME I/O FUNCTION
I
O Analog output R
O Analog output L
I Zero mute
Input format
26
Page 2
LZ95300 (XP451A00) Gate Array
PIN
NO.
NAME I/O FUNCTION
PIN
NO.
NAME I/O FUNCTION
1 INC O INPUT CUE ON/OFF 15 /CSW I CUE switch input
2 CPR O VCA CUE PRE PAN ON/OFF 16 VCA8 I
3 CPST O VCA CUE POST PAN ON/OFF 17 VCA7 I
4 COFF O All CUE OFF 18 VCA6 I
5 CPU I H: CPU mode, L: Local mode 19 VCA5 I VCA GROUP switch input
6 C0 I 20 VCA4 I
7 C1 I CPU address bus 21 VCA3 I
8 C2 I 22 VCA2 I
9 C3 I 23 VCA1 I
10 /RES I Reset 24 /SLSF I SOLO SAFE switch input
11 DATA I/O Data input/output 25 /CHK I CHECK LED ON/OFF
12 IRQ O
When /ONSW and /CSW change; H.
When CPU reads data; L.
26 /ONSW I ON switch input
13 /CS I Chip select 27 /ONRY O ON relay & LED ON/OFF
14 GND Digital ground 28 VDD Digital power supply
Function of DATA
DATA
C3 C2 C1 C0 R/W
MODE FUNCTION 0 1
0000WO N RELAY SET Sets /ONRY OFF ON
0001 RO N S W READ Reads /ONSW OFF ON
0010WCUE RELAY SET Sets INC ON OFF ON
0011 RCUE SW READ Reads /CSW OFF ON
0100WCHECK LED SET Sets /CHK OFF ON
0101WVCA PRE/POST SET Sets CVCA CUE PRE/POST PAN POST PRE
0110WSOLO SET
Sets SOLO
When SOLO is set, CUE or
SOLO SAFE is not ON, /ONRY is
set to OFF.
OFF SOLO
0111WVCA1 CUE SET Sets VCA1 CUE OFF ON
1000WVCA1 CUE SET Sets VCA1 CUE OFF ON
1001WVCA2 CUE SET Sets VCA2 CUE OFF ON
:::: : : : : :
:: : : :
1111WVCA8 CUE SET Sets VCA8 CUE OFF ON
M2500
::::
27
Page 3
M2500
YSP99 LZ95XD59 (XM047A00) Gate Array
PIN
NO.
NAME I/O FUNCTION
1N C 4 1A 9 I
2 MCLK O Master clock 42 A8 I
3 DESYN O Sync for DEQI
4 CD04 I 44 CD1 I
5 CD03 I 45 CDROM I CARD/ROM select
6 CD02 I 46 ROM4 I
7 CD01 I 47 ROM3 I
8 CDI
9 CDI
10 CDI
11 CDI1 O Control data output (DEQ IC19
12 +Vdd 52 GND
13 GND 53 +Vdd
14 L4 O 54 SEL2 I
15 L3 O 55 SEL1 I
16 L2 O 56 XX2 I
17 L1 O 57 XX1 I
18 LCD O LCD enable 58 MDCK O MIDI cloc
19 KEYN O KEY enable 59 TRG
20 LED O LED enable 60 E I
21 CDA14 O 61 RWN I Read write pulse
22 CDA13 O 62 ICN I Initial clear
23 CARDN O CARD enable 63 ACI
24 GND 64 GND
25 RAWN O RAM write enable 65 TXD I DSP control data input
26 RAON O RAM read enable 66 RXD O DSP control data output
27 RMA16 O 67 XCLK O Transfer clock
28 RMA15 O 68 WCLK O Word clock
29 RMA14 O 69 SCLK O Serial data transfer clock 64fs
30 RMA13 O 70 FSYNC O NC
31 +Vdd 71 ADLR O NC
32 GND 72 GND
33 ROMN O ROM read enable 73 +Vdd
34 A15 I 74 SCLKN O Serial data sift clock
35 A14 I 75 DCLK O 256fs clock
36 A13 I 76 XI I Clock input/(Xtal
37 A12 I 77 XO O output/(Xtal
38 A11 I 78 GND
39 A10 I 79 TRIG I Trigger input
40 NC 80 SYNCN O Sync clock
O Control data output (DSP2
O Control data output (MOD
O Control data output (DEQ IC17
Control data input
LED scan pulse
CARD address
ROM address back select
CPU address bus
PIN
NO.
NAME I/O FUNCTION
43 CD2 I
48 ROM2 I
49 ROM1 I
50 YY
51 YY1 I
CARD page select
ROM page control
I
Dividing select
Control data select
O Trigger ou
O ACIA enable
28
Page 4
M2500
YSS228E-F (XQ962D00) DSP3 (Digital Signal Processor)
PIN
NO.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
NAME
VSS
XI
XO
VDD
/SYNCI
/SYNCO
CKI
CKO
CKSL
VSS
MCKS
/SSYNC
/IC
/TEST
BTYP
/IRQ
TRIG
VDD
VSS
/CS
/DS
R/W
CA7
CA6
CA5
CA4
CA3
CA2
CA1
CA0/CD15
CD14
CD13
CD12
CD11
CD10
CD09
CD08
CD07
CD06
VSS
VDD
CD05
CD04
CD03
CD02
CD01
CD00
/DTACK
SI0
SI1
SI2
SI3
SI4
SI5
SI6
SI7
VSS
VDD
SO0
SO1
SO2
SO3
SO4
SO5
SO6
SO7
DB00
DB01
DB02
DB03
DB04
DB05
DB06
DB07
DB08
DB09
DB10
DB11
DB12
VDD
I/O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
FUNCTION
Ground
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
System master clock input (60 M or30 MHz)
System master clock input (60 M or30 MHz)
Power supply
System synch. input
System synch. output
System clock input (30 MHz)
System clock output (30 MHz)
System master clock select (0:60 M,1:30 MHz)
Ground
Master clock for serial I/O(128 xFs)
Synch. signal for serial I/O
Initial clear
Test mode setting
CPU data bus 8/16 bit select(0:8,1:16)
Interrupt request
Trigger signal
Power supply
Ground
Chip select
Data strobe
Read/Write select
CPU address bus
CPU address/data bus
CPU data bus
Ground
Power supply
CPU data bus
DTACK signal output
Serial data input
Ground
Power supply
Serial data output
Parallel data bus
Power supply
PIN
NO.
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
NAME
VSS
DB13
DB14
DB15
DB16
DB17
DB18
DB19
DB20
DB21
DB22
DB23
DB24
DB25
DB26
DB27
DB28
DB29
DB30
DB31
TIMO/DBOE
VSS
VDD
DA00
DA01
DA02
DA03
DA04
DA05
DA06
DA07
DA08
DA09
DA10
DA11
DA12
DA13
DA14
DA15
VSS
VDD
DA16
DA17
DA18
DA19
DA20
DA21
DA22
DA23
DA24
DA25
DA26
DA27
DA28
DA29
DA30
DA31
VDD
VSS
A00
A01
A02
A03
A04
A05
A06
A07
A08
A09
A10
A11
A12
A13
A14
A15/RAS
A16/CAS
A17/CE
/WE
/OE
VDD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
DM : IC2, 3
FUNCTION
Ground
Parallel data bus
Timing signal/Parallel data bus control
Ground
Power supply
External memory data bus
Ground
Power supply
External memory data bus
Power supply
Ground
External memory address bus
External memory address bus/Row address strobe
External memory address bus/Column address strobe
External memory address bus/Chip enable
External memory write enable
External memory output enable
Power supply
29
Page 5
M2500
IC BLOCK DIAGRAM
BA6144 (XA552A00)
ST4: IC121,IC221,IC321,IC421
IN3: IC103,IC203,IC303,IC403,
IC503,IC603,IC703,IC803
METER DRIVER
+ + + + +
1 2 3 4 5 6 7 8 9
+
CONSTANT
CURRENT
NJM2068-D(XM356A00
)
ST1: IC101~106,IC201~204,
IC301~305,IC401~404
MAS3: IC952,IC953
MAS2: IC101,IC151,IC301,IC351,IC501,
IC551,IC751,IC901~903
MAS1: IC101~103,IC301~303,IC501~503,
IC701~703
ISRT:
IC101~104,IC111~115,IC121~124,
IC201~217
IN1: IC103~107,IC303~307,IC503~507,
IC703~707
NJM2082M(T1) (XN797A00)
CTRL: IC108
NJM4558L-D (XQ212A00)
METER1: IC102
METER2: IC102
NJM4556AL (XP844A00)
MAS: IC951
NJM4580L (XF195A00)
ST2: IC101~103,IC301~303
ST3: IC101,IC201,IC301,IC401
MASOUT3:
MSOUT1,2:
MAS3: IC101,IC301,IC501,IC701,
IC901,IC902
MAS1: IC901
IN3: IC101,IC102,IC301,IC501,IC502,
IC701,IC702
IN1: IC101,IC102,IC301,IC501,IC502,
IC701,IC702
M5238AP (XM085A00)
DC: IC101,IC201,IC202
OP AMP OP AMP
+
1A2 3 4 5 6 7 8
IN V
+
IN
OUT
AAA
+
+
IN
BBB
B
OUT
1 Output A
2
Inverting
Input A
Input A
DC Voltage
Supply
3
4
+
V IN
Non-Inverting
IC101,IC201,IC301
IC301,IC201,IC301,IC401
+DC Voltage
+V
8
Supply
7
6
5
Output B
Inverting
Input B
Non-Inverting
Input B
+
+
V
SN74HC00NSR (XE165A00)
CTRL: IC113
SN74HC04NSR (XD830A00)
CTRL: IC109
NAND INVERTER DECODER
1
1A
2
1Y
3
2A
4
2Y
5
3A
6
3Y
7
Vss
14
VDD
13
6A
12
6Y
11
5A
10
5Y
9
4A
8
4Y
30
1
1A
2
1B
3
1Y
4
2A
5
2B
6
2Y
7
SS
V
14
V
DD
13
4B
12
4A
11
4Y
10
3B
9
3A
8
3Y
SN74HC138NSR (XD835A00)
CTRL: IC124
Select
Enable
Output
1
A
2
B
3
C
4
G2A G2A
5
G2B G2B
6
G1 G1
7
Y7 Y7
8
GND
B
C
16
A
Y6
Vcc
15
Y0 Y0
14
Y1 Y1
13
Y2 Y2
12
Y3
Y3
Output
11
Y4 Y4
10
Y5 Y5
9
Y6
Page 6
M2500
SN74HC14NSR (XC725A00)
CTRL: IC110,IC302
SN74HC174NSR (XD836A00)
CTRL: IC123
SN74HC245NSR (XD838A00)
CTRL: IC121,IC125,IC131
INVERTER D-FF BUFFER
GND
1 1A
2
1Y
3
2A
4
2Y
5
3A
6
3Y
7
DD
V
14
6A
13
6Y
12
5A
11
5Y
10
4A
9
4Y
8
SN74HC273NSR (XH223A00)
CTRL: IC132
1
CLEAR
2
DD
1Q
GG
QQ
CK CK
3
1D
4
2D
DCK
G
5
Q
2Q
6
DCK
3D
G
Q
7
3Q
8
GND
SN74HC32NSR (XD833A00)
CTRL: IC112
16
Vcc
15
6Q
14
6D
13
5D
D CK
G
Q
12
5Q
11
D CK
4D
G
Q
10
4Q
9
CK
A1
A2
A3
A4
A5
A6
A7
A8
GND
SN74HC374ANSR (XQ042A00)
CTRL: IC122
D-FF OR D-FF
GND
1 CLEAR
2
1Q
3
1D
4
2D
5
2Q
6
3Q
7
3D
8
4D
9
4Q
10
QQ
CL CL
CK CK
DD
D
CL
QQ
QQ
CL CL
CK
D
DDCK
CL
Q
CC
V
20
8Q
19
8D
18
7D
17
CK
D CK
CL
7Q
16
6Q
15
CK
D
6D
14
5D
13
CK
CL
Q
5Q
12
CLOCK
11
1 1A
2
1B
3
1Y
4
2A
5
2B
6
2Y
7
GND
CC
V
14
4B
13
4A
12
4Y
11
3B
10
3A
9
3Y
8
OUTPUT
CONTROL
GND
1Q
1D
2D
2Q
3Q
3D
4D
4Q
1 D1R
2
3
4
5
6
7
8
9
10
1 20
2 19
Q
Q
OE
OE
DCK
DCK
Q
Q
DCK
DCK
Q
D CK
D CK
OE
OE
Q
Q
OE
OE
D CK
D CK
OE
OE
Q
3 18
4 17
5 16
6 15
7 14
8 13
9 12
10 11
20
19
18
17
16
15
14
13
12
11
CC
V
G
B1
B2
B3
B4
B5
B6
B7
B8
Vcc
8Q
8D
7D
7Q
6Q
6D
5D
5Q
CLOCK
TC4052BP (XA053A00)
METER1: IC101
METER2: IC101
SN74HC02AP (IR000200)
ST4: IC102 MAS4: IC102,502,902
IN4: IC102,IC302
MULTIPLEXER NOR
Y-COM
1
0Y
2
2Y
2Y
Y-COM
3
3Y
4
3Y
5
1Y
1Y
6
INH
INH
7
V
EE
8
VSS
0Y
X-COM
B
16
DD
V
2X
15
2X
14
1X
1X
13
X-COM
0X
12
0X
11
3X
3X
A
10
A
9
B
SN74HC139AP (IR013900)
MAS2: IC910
DECODER
1
1G
1
1Y
2
1A
3
1B
4
2Y
5
2A
6
2B
7
Vss
14
Vcc
13
4Y
12
4A
11
4B
10
3Y
9
3A
8
3B
GND
G
2
A
1A
3
1B
B
4
1Y0
Y0
5
1Y1
Y1
6
1Y2
Y2
7
1Y3
Y3
8
16
Vcc
G
15
2G
A
14
2A
B
13
2B
Y0
12
2Y0
Y1
11
2Y1
Y2
10
2Y2
Y3
9
2Y3
31