Winbond Electronics W29EE512T-90B, W29EE512P-12, W29EE512T-90, W29EE512T-70B, W29EE512T-12B Datasheet

W29EE512

64K × 8 CMOS FLASH MEMORY

GENERAL DESCRIPTION

The W29EE512 is a 512K bit, 5-volt only CMOS flash memory organized as 64K × 8 bits. The device can be programmed and erased in-system with a standard 5V power supply. A 12-volt VPP is not required. The unique cell architecture of the W29EE512 results in fast program/erase operations with extremely low current consumption (compared to other comparable 5-volt flash memory products). The device can also be programmed and erased using standard EPROM programmers.

FEATURES

∙Single 5-volt program and erase operations

∙Fast page-write operations

−128 bytes per page

−Page program cycle: 10 mS (max.)

−Effective byte-program cycle time: 39 μS

−Optional software-protected data write

∙Fast chip-erase operation: 50 mS

∙Read access time: 70/90/120 nS

∙Typical page program/erase cycles: 1K/10K

∙Ten-year data retention

∙Software and hardware data protection

∙Low power consumption

−Active current: 50 mA (max.)

−Standby current: 100 μA (max.)

∙Automatic program timing with internal VPP generation

∙End of program detection

−Toggle bit

−Data polling

∙Latched address and data

∙TTL compatible I/O

∙JEDEC standard byte-wide pinouts

∙Available packages: 32-pin PLCC and TSOP

	Publication Release Date: March 1998
- 1 -	Revision A5

W29EE512

PIN CONFIGURATIONS

BLOCK DIAGRAM

	A	A			V	/
	1	1	N	N	C	W	N
	2	5	C	C	C	E	C
	4	3	2	1	32	31	30
A7	5						29	A14
A6	6						28	A13
A5	7		32-pin				27	A8
A4	8						26	A9
A3	9		PLCC				25	A11
A2	10						24	OE
A1	11						23	A10
A0	12						22	CE
DQ0	13						21	DQ7
	14	15	16	17	18	19	20
	D	D	G	D	D	D	D
	Q	Q	N	Q	Q	Q	Q
	1	2	D	3	4	5	6

A11						1
	A9					2
	A8					3
A13						4
A14						5
	NC					6
	WE					7	32-pin
VCC						8
	NC					9	TSOP
	NC					10
A15						11
A12						12
	A7					13
	A6					14
	A5					15
	A4					16

32				OE
31				A10
30				CE
29				DQ7
28				DQ6
27			DQ5
26				DQ4
25				DQ3
24				GND
23				DQ2
22			DQ1
21			DQ0
20			A0
19				A1
18			A2
17				A3

VDD

VSS

CE

DQ0

OUTPUT

.

OE

CONTROL

.

BUFFER

WE

DQ7

A0

CORE

.

DECODER

.

ARRAY

A15

PIN DESCRIPTION

SYMBOL				PIN NAME
A0−A15				Address Inputs
DQ0−DQ7				Data Inputs/Outputs
				Chip Enable
	CE
				Output Enable
	OE
				Write Enable
	WE
VCC				Power Supply
GND				Ground
	NC			No Connection

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W29EE512

FUNCTIONAL DESCRIPTION

Read Mode

The read operation of the W29EE512 is controlled by CE and OE, both of which have to be low for

the host to obtain data from the outputs. CE is used for device selection. When CE is high, the chip

is de-selected and only standby power will be consumed. OE is the output control and is used to gate

data from the output pins. The data bus is in high impedance state when either CE or OE is high. Refer to the timing waveforms for further details.

Page Write Mode

The W29EE512 is programmed on a page basis. Every page contains 128 bytes of data. If a byte of data within a page is to be changed, data for the entire page must be loaded into the device. Any byte that is not loaded will be erased to "FFh" during programming of the page.

The write operation is initiated by forcing CE and WE low and OE high. The write procedure consists of two steps. Step 1 is the byte-load cycle, in which the host writes to the page buffer of the device. Step 2 is an internal programming cycle, during which the data in the page buffers are simultaneously written into the memory array for non-volatile storage.

During the byte-load cycle, the addresses are latched by the falling edge of either CE or WE,

whichever occurs last. The data are latched by the rising edge of either CE or WE, whichever occurs first. If the host loads a second byte into the page buffer within a byte-load cycle time (TBLC) of 150 μS, after the initial byte-load cycle, the W29EE512 will stay in the page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal programming cycle will start if no additional byte is loaded into the page buffer A7 to A15 specify the page address. All bytes that are loaded into the page buffer must have the same page address. A0 to A6 specify the byte address within the page. The bytes may be loaded in any order; sequential loading is not required.

In the internal programming cycle, all data in the page buffers, i.e., 128 bytes of data, are written simultaneously into the memory array. Before the completion of the internal programming cycle, the host is free to perform other tasks such as fetching data from other locations in the system to prepare to write the next page.

Software-protected Data Write

The device provides a JEDEC-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a series of three-byte program commands (with specific data to a specific address) to be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not be activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up and power-down.

The W29EE512 is shipped with the software data protection enabled. To enable the software data protection scheme, perform the three-byte command cycle at the beginning of a page load cycle. The device will then enter the software data protection mode, and any subsequent write operation must be preceded by the three-byte program command cycle. Once enabled, the software data protection will remain enabled unless the disable commands are issued. A power transition will not reset the software data protection feature. To reset the device to unprotected mode, a six-byte command sequence is required.

	Publication Release Date: March 1998
- 3 -	Revision A5

W29EE512

Hardware Data Protection

The integrity of the data stored in the W29EE512 is also hardware protected in the following ways:

(1)Noise/Glitch Protection: A WE pulse of less than 15 nS in duration will not initiate a write cycle.

(2)VCC Power Up/Down Detection: The programming operation is inhibited when VCC is less than 2.5V.

(3)Write Inhibit Mode: Forcing OE low, CE high, or WE high will inhibit the write operation. This prevents inadvertent writes during power-up or power-down periods.

Data Polling (DQ7)-Write Status Detection

The W29EE512 includes a data polling feature to indicate the end of a programming cycle. When the W29EE512 is in the internal programming cycle, any attempt to read DQ7 of the last byte loaded during the page/byte-load cycle will receive the complement of the true data. Once the programming cycle is completed. DQ7 will show the true data.

Toggle Bit (DQ6)-Write Status Detection

In addition to data polling, the W29EE512 provides another method for determining the end of a program cycle. During the internal programming cycle, any consecutive attempts to read DQ6 will produce alternating 0's and 1's. When the programming cycle is completed, this toggling between 0's and 1's will stop. The device is then ready for the next operation.

5-Volt-only Software Chip Erase

The chip-erase mode can be initiated by a six-byte command sequence. After the command loading cycles, the device enters the internal chip erase mode, which is automatically timed and will be completed in 50 mS. The host system is not required to provide any control or timing during this operation.

Product Identification

The product ID operation outputs the manufacturer code and device code. Programming equipment automatically matches the device with its proper erase and programming algorithms.

The manufacturer and device codes can be accessed by software or hardware operation. In the software access mode, a six-byte command sequence can be used to access the product ID. A read from address 0000H outputs the manufacturer code (DAh). A read from address 0001H outputs the device code (C8h). The product ID operation can be terminated by a three-byte command sequence.

In the hardware access mode, access to the product ID is activated by forcing CE and OE low, WE high, and raising A9 to 12 volts.

- 4 -

W29EE512

TABLE OF OPERATING MODES

Operating Mode Selection

(Operating Range = 0 to 70° C (Ambient Temperature), VCC = 5V ±10%, VSS = 0V, VHH = 12V)

MODE										PINS
										ADDRESS	DQ.
	CE			OE				WE
Read		VIL			VIL			VIH		AIN	Dout
Write		VIL		VIH				VIL		AIN	Din
Standby	VIH				X			X		X	High Z
Write Inhibit		X			VIL			X		X	High Z/DOUT
		X			X			VIH		X	High Z/DOUT
Output Disable		X		VIH				X		X	High Z
5-Volt Software Chip Erase		VIL		VIH				VIL		AIN	DIN
Product ID		VIL			VIL			VIH		A0 = VIL; A1−A15 = VIL;	Manufacturer Code
										A9 = VHH	DA (Hex)
		VIL			VIL			VIH		A0 = VIH; A1−A15 = VIL;	Device Code
										A9 = VHH	C8 (Hex)

	Publication Release Date: March 1998
- 5 -	Revision A5

W29EE512

Command Codes for Software Data Protection

BYTE SEQUENCE	TO ENABLE PROTECTION		TO DISABLE PROTECTION
	ADDRESS	DATA	ADDRESS	DATA
0 Write	5555H	AAH	5555H	AAH
1 Write	2AAAH	55H	2AAAH	55H
2 Write	5555H	A0H	5555H	80H
3 Write	-	-	5555H	AAH
4 Write	-	-	2AAAH	55H
5 Write	-	-	5555H	20H

Software Data Protection Acquisition Flow

Software Data Protection	Software Data Protection
Enable Flow	Disable Flow

Load data AA to

address 5555

Load data 55 to

address 2AAA

Load data AA to

address 5555

Load data 55 to

address 2AAA

		Load data A0
		to
		address 5555
	(Optional page-load	Sequentially load
	operation)	up to 128 bytes
		of page data
		Pause 10 mS

Load data 80 to

address 5555

Load data AA to

address 5555

Load data 55 to

address 2AAA

Exit

Notes for software program code:

Data Format: DQ7−DQ0 (Hex)

Address Format: A14−A0 (Hex)

Load data 20 to

address 5555

Pause 10 mS

Exit

- 6 -