Winbond Electronics W27E512S-90, W27E512S-70, W27E512S-45, W27E512S-55, W27E512S-15 Datasheet

W27E512

64K × 8 ELECTRICALLY ERASABLE EPROM

GENERAL DESCRIPTION

The W27E512 is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized as 65536 × 8 bits that operates on a single 5 volt power supply. The W27E512 provides an electrical chip erase function.

FEATURES

∙High speed access time: 45/55/70/90/120/150 nS (max.)

∙Read operating current: 30 mA (max.)

∙Erase/Programming operating current 30 mA (max.)

∙Standby current: 1 mA (max.)

∙Single 5V power supply

∙+14V erase/+12V programming voltage

∙Fully static operation

∙All inputs and outputs directly TTL/CMOS compatible

∙Three-state outputs

∙Available packages: 28-pin 600 mil DIP, 330 mil SOP, TSOP and 32-pin PLCC

PIN CONFIGURATIONS

																						VCC
			A15					1									28
			A12					2									27					A14
			A7					3									26					A13
			A6					4									25					A8
			A5					5									24					A9
			A4					6			28-pin						23					A11
			A3					7				DIP					22
																						OE/Vpp
								8
			A2														21					A10
			A1					9									20
																						CE
			A0					10									19					Q7
			Q0					11									18					Q6
			Q1					12									17					Q5
			Q2					13										16				Q4
		GND						14									15					Q3
									A		A				V A A
							A	1			1 N C 1 1
					7			2			5 C C 4 3
					4			3		2		1		3			3	3
		A6			5									2			1	0 29					A8
		A5			6															28			A9
																				27			A11
		A4			7															26			NC
		A3			8						32-pin
		A2			9						PLCC									25			OE/Vpp
		A1			10															24			A10
		A0		11																23			CE
																				22
		NC			12 1			1		1		1		1			1	2					Q7
		Q0			13 4			5		6		7		8			9	0		21			Q6
							Q Q G N Q Q Q
					1			2			N C 3 4 5
											D
																								A10
OE/Vpp
					1															28
		A11			2															27				CE
		A9			3															26				Q7
		A8			4															25				Q6
		A13			5															24				Q5
		A14			6							28-pin								23				Q4
		VCC			7															22				Q3
		A15			8							TSOP								21				GND
		A12			9															20				Q2
		A7			10															19				Q1
		A6			11															18				Q0
		A5			12															17				A0
		A4			13															16				A1
		A3			14															15				A2

BLOCK DIAGRAM

Q0

CE

CONTROL

OUTPUT

.

.

BUFFER

OE/VPP

Q7

A0

.

CORE

DECODER

.

ARRAY

A15

VCC

GND

PIN DESCRIPTION

SYMBOL

DESCRIPTION

A0−A15

Address Inputs

Q0−Q7

Data Inputs/Outputs

Chip Enable

CE

/VPP

Output Enable, Program/Erase

OE

Supply Voltage

VCC

Power Supply

GND

Ground

NC

No Connection

	Publication Release Date: June 2000
- 1 -	Revision A9

W27E512

FUNCTIONAL DESCRIPTION

Read Mode

Like conventional UVEPROMs, the W27E512 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE/VPP controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE/VPP, if TACC and TCE timings are met.

Erase Mode

The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27E512 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm.

Erase mode is entered when OE/VPP low, and all other address pins low operation.

is raised to VPE (14V), VCC = VCE (5V), A9 = VPE (14V), A0 and data input pins high. Pulsing CE low starts the erase

Erase Verify Mode

After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode ensures a substantial erase margin if VCC = VCE (3.75V), CE low, and OE/VPP low.

Program Mode

Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only

way to change cell data from "1" to "0." The program mode is entered when OE /VPP is raised to VPP (12V), VCC = VCP (5V), the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing CE low starts the programming operation.

Program Verify Mode

All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if OE/VPP low and CE low.

Erase/Program Inhibit

Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different

data. When CE high, erasing or programming of non-target chips is inhibited, so that except for the CE and OE/VPP pins, the W27E512 may have common inputs.

- 2 -

W27E512

Standby Mode

The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby mode, all outputs are in a high impedance state, independent of OE /VPP.

Two-line Output Control

Since EPROMs are often used in large memory arrays, the W27E512 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur.

System Considerations

An EPROM's power switching characteristics require careful device decoupling. System designers are interested in three supply current issues: standby current levels (ISB), active current levels (ICC), and transient current peaks produced by the falling and rising edges of CE. Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 μ F ceramic capacitor connected between its VCC and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 μF electrolytic capacitor should be placed at the array's power supply connection between VCC and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.

TABLE OF OPERATING MODES

(VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, VCE = 5V, X = VIH or VIL)

MODE

PINS

CE

OE/VPP

A0

A9

VCC

OUTPUTS

Read

VIL

VIL

X

X

VCC

DOUT

Output Disable

VIL

VIH

X

X

VCC

High Z

Standby (TTL)

VIH

X

X

X

VCC

High Z

Standby (CMOS)

V

CC

±0.3V

X

X

X

VCC

High Z

Program

VIL

VPP

X

X

VCP

DIN

Program Verify

VIL

VIL

X

X

VCC

DOUT

Program Inhibit

VIH

VPP

X

X

VCP

High Z

Erase

VIL

VPE

VIL

VPE

VCE

DIH

Erase Verify

VIL

VIL

X

X

3.75

DOUT

Erase Inhibit

VIH

VPE

X

X

VCE

High Z

Product Identifier-manufacturer

VIL

VIL

VIL

VHH

VCC

DA (Hex)

Product Identifier-device

VIL

VIL

VIH

VHH

VCC

08 (Hex)

	Publication Release Date: June 2000
- 3 -	Revision A9

W27E512

DC CHARACTERISTICS

Absolute Maximum Ratings

				PARAMETER	RATING	UNIT
Ambient Temperature with Power Applied					-55 to +125	°C
Storage Temperature					-65 to +125	°C
Voltage on all Pins with Respect to Ground Except					-0.5 to VCC +0.5	V
	OE	/VPP, A9 and VCC Pins
Voltage on				/VPP Pin with Respect to Ground	-0.5 to +14.5	V
			OE
Voltage on A9 Pin with Respect to Ground					-0.5 to +14.5	V
Voltage VCC Pin with Respect to Ground					-0.5 to +7	V

Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability

of the device.

DC Erase Characteristics

(TA = 25° C ±5° C, VCC = 5.0V ±10%)

PARAMETER	SYM.						CONDITIONS				LIMITS			UNIT
										MIN.	TYP.		MAX.
Input Load Current	ILI	VIN = VIL or VIH								-10	-		10	μA
V Erase Current	I						= VIL,		/VPP = VPE	-	-		30	mA
			CE					OE
CC	CP
VPP Erase Current	IPP						= VIL,			-	-		30	mA
				CE
			OE				/VPP = VPE
Input Low Voltage	VIL	-								-0.3	-		0.8	V
Input High Voltage	VIH	-								2.4	-		5.5	V
Output Low Voltage (Verify)	VOL	IOL = 2.1 mA								-	-		0.45	V
Output High Voltage (Verify)	VOH	IOH = -0.4 mA								2.4	-		-	-
A9 Erase Voltage	VID	-								13.25	14		14.25	V
VPP Erase Voltage	VPE	-								13.25	14		14.25	V
VCC Supply Voltage (Erase)	VCE	-								4.5	5.0		5.5	V
VCC Supply Voltage	VCE	-								3.5	3.75		4.0	V
(Erase Verify)

Note: VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP.

- 4 -

W27E512

CAPACITANCE

(VCC = 5V, TA = 25° C, f = 1 MHz)

PARAMETER	SYMBOL	CONDITIONS	MAX.	UNIT
Input Capacitance	CIN	VIN = 0V	6	pF
Output Capacitance	COUT	VOUT = 0V	12	pF

AC CHARACTERISTICS

AC Test Conditions

PARAMETER	CONDITIONS
Input Pulse Levels	0 to 3.0V
Input Rise and Fall Times	5 nS
Input and Output Timing Reference Level	1.5V/1.5V
Output Load	CL = 30 pF,

IOH/IOL = -0.4 mA/2.1 mA

AC Test Load and Waveforms

+1.3V

(IN914)

3.3K ohm

DOUT

100 pF for 90/120/150 nS (Including Jig and Scope

30 pF for 45/55/70 nS (Including Jig and Scope)

Input				Output
Test Point				Test Point
3.0V				1.5V
			1.5V
0V

	Publication Release Date: June 2000
- 5 -	Revision A9