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W78E365 Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. PIN CONFIGURATIONS ..................................................................................................................... 3
4. PIN DESCRIPTION ............................................................................................................................. 4
5. BLOCK DIAGRAM............................................................................................................................... 5
6. FUNCTIONAL DESCRIPTION ............................................................................................................ 6
6.1 RAM...................................................................................................................................................6
6.2 Timers 0, 1, and 2..............................................................................................................................7
6.3 Clock..................................................................................................................................................7
6.4 Power Management...........................................................................................................................7
6.5 Reset .................................................................................................................................................8
6.6 Port 4.................................................................................................................................................9
6.7 Pulse Width Modulated Outputs (PWM) ..........................................................................................14
6.8 Watchdog Timer ..............................................................................................................................17
6.9 In-System Programming (ISP) Mode ...............................................................................................19
6.10 Software Reset ................................................................................................................................20
6.11 H/W Reboot Mode (Boot from LDROM) ..........................................................................................21
6.12 Security............................................................................................................................................24
7. ELECTRICAL CHARACTERISTICS ................................................................................................. 25
7.1 Absolute Maximum Ratings .............................................................................................................25
7.2 D.C. Characteristics.........................................................................................................................25
7.3 A.C. Characteristics.........................................................................................................................27
8. TIMING WAVEFORMS .....................................................................................................................28
8.1 Program Fetch Cycle.......................................................................................................................28
8.2 Data Read Cycle..............................................................................................................................29
8.3 Data Write Cycle..............................................................................................................................30
8.4 Port Access Cycle............................................................................................................................31
9. TYPICAL APPLICATION CIRCUIT ................................................................................................... 32
9.1 External Program Memory and Crystal............................................................................................32
9.2 Expanded External Data Memory and Oscillator .............................................................................33
10. PACKAGE DIMENSIONS .................................................................................................................33
10.1 40-pin DIP........................................................................................................................................33
10.2 44-pin PLCC....................................................................................................................................34
10.3 44-pin PQFP....................................................................................................................................34
11. APPLICATION NOTE........................................................................................................................ 35
11.1 In-system Programming Software Examples ...................................................................................35
12. REVISION HISTORY ........................................................................................................................40
Publication Release Date: April 20, 2005
- 1 - Revision A5
W78E365
1. GENERAL DESCRIPTION
The W78E365 is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78E365 is fully compatible with the standard 8052. The
W78E365 contains a 64K bytes of main Flash APROM and a 4K bytes of auxiliary Flash LDROM
which allows the contents of the 64KB main APROM to be updated by the loader program located at
the LDROM; 256+1K bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an
additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a
eight sources two-level interrupt capability. To facilitate programming and verification, the ROM inside
the W78E365 allows the program memory to be programmed and read electronically. Once the code
is confirmed, the user can protect the code for security.
The W78E365 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
• Fully static design 8-bit CMOS microcontroller
• 64K bytes of in-system programmable Flash EPROM for Application Program (APROM)
• 4K bytes of auxiliary ROM for Loader Program (LDROM)
• 256+1K bytes of on-chip RAM. (Including 1K bytes of AUX-RAM, software selectable)
• Four 8-bit bi-directional ports
• One 4-bit multipurpose programmable port (I/O, interrupt, Chip select function)
• Three 16-bit timer/counters
• One full duplex serial port
• Watchdog timer
• 5 channel PWM
• Software Reset
• P1.0 T2 programmable clock out
• Eight-sources, two-level interrupt capability
• Built-in power management
• Code protection
• Packaged in
− DIP 40: W78E365-40
− PLCC 44: W78E365P-40
− QFP 44: W78E365F-40
- 2 -
3. PIN CONFIGURATIONS
40-Pin DIP (W78E365)
T2, P1.0
T2EX, P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
W78E365
VDD1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
P0.0, AD0
P0.1, AD1
38
P0.2, AD2
37
P0.3, AD3
36
P0.4, AD4
35
P0.5, AD5
34
P0.6, AD6
33
P0.7, AD7
32
31
EA
ALE
30
29
PSEN
P2.7, A15
28
P2.6, A14
27
P2.5, A13
26
P2.4, A12
25
P2.3, A11
24
P2.2, A10
23
P2.1, A9
22
P2.0, A8
21
44-Pin PLCC (W78E365P)
P
1
.
4
6543
7
P1.5
8
P1.6
9
P1.7
10
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
11
12
13
14
15
16
17
P
3
.
6
,
/
W
R
P
1
.
3
P
3
.
7
,
/
R
D
T
2
E
X
,
P
P
1
1
.
.
1
2
X
X
T
T
A
A
L
L
2
1
/
I
A
N
T
D
T
2
0
3
,
,
,
P
P
P
1
V
0
4
.
D
.
.
0
D
0
2
2 1 44 43 42
V
P
P
P
S
2
2
4
S
.
.
.
0
1
0
,
,
A
A
8
9
44-Pin QFP (W78E365F)
/
T
I
2
N
E
T
A
A
A
D
D
D
3
1
2
,
,
,
P
P
P
0
0
0
.
.
.
3
1
2
40
41
39
P0.4, AD4
38
P0.5, AD5
37
P0.6, AD6
36
P0.7, AD7
35
EA
34
P4.1
33
ALE
32
PSEN
31
P2.7, A15
30
P2.6, A14
29
P2.5, A13
2827262524232221201918
P
P
P
2
2
2
.
.
.
3
4
2
,
,
,
A
A
A
1
1
1
1
2
0
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
P
P
1
1
.
.
3
4
43 42 41
44
1
2
3
4
5
6
7
8
9
10
11
12
P
P
3
3
.
.
6
7
,
,
/
/
W
R
R
D
X
2
,
,
P
P
P
1
1
1
.
.
.
1
0
2
403938 37 36 35
V
X
X
S
T
T
S
A
A
L
L
2
1
T
3
,
P
V
4
D
.
D
2
P
P
2
4
.
.
0
0
,
A
8
A
A
A
A
D
D
D
D
3
1
2
0
,
,
,
,
P
P
P
P
0
0
0
0
.
.
.
.
3
1
2
0
34
33
P0.4, AD4
32
P0.5, AD5
31
P0.6, AD6
30
P0.7, AD7
29
EA
28
P4.1
27
ALE
26
PSEN
25
P2.7, A15
24
P2.6, A14
23
P2.5, A13
22212019181716151413
P
P
P
P
2
2
2
2
.
.
.
.
3
1
4
2
,
,
,
,
A
A
A
A
1
9
1
1
1
2
0
Publication Release Date: April 20, 2005
- 3 - Revision A5
4. PIN DESCRIPTION
A
SYMBOL TYPE DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
external ROM. The ROM address and data will not be presented on the bus if
E
I
the
pin is high.
EA
W78E365
PROGRAM STORE ENABLE:
PSEN
ALE O H
RST I L
XTAL1 I
XTAL2 O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS I GROUND: ground potential.
VDD I POWER SUPPLY: Supply voltage for operation.
P0.0 − P0.7
P1.0 − P1.7
P2.0 − P2.7
P3.0 − P3.7
P4.0 − P4.7
O H
I/O D PORT 0: Function is the same as that of standard 8052.
I/O H PORT 1: Function is the same as that of standard 8052.
I/O H
I/O H PORT 3: Function is the same as that of the standard 8052.
I/O H
Port 0 address/data bus. When internal ROM access is performed, no PSEN
strobe signal outputs originate from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory. The P2.6
and P2.7 also provide the alternate function
from LD flash.
PORT 4: A bi-directional I/O. The P4.3 also provides the alternate function
REBOOT which is H/W reboot from LD flash.
PSEN enables the external ROM data in the
REBOOT
which is H/W reboot
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
- 4 -
5. BLOCK DIAGRAM
W78E365
P1.0
P1.7
P3.0
P3.7
P4.0
P4.3
Port
1
Port
Port
Port 1
Latch
ACC
Interrupt
Timer
2
Timer
0
Timer
1
UART
3
4
Port 3
Latch
Port 4
Latch
XTAL1
Oscillator
PSW
Instruction
Decoder
&
Sequencer
Bus & Clock
Controller
ALE
ALU
256+1K bytes
Reset Block
PSEN
T2T1
SFR RAM
Address
RAM & SFR
B
Stack
Pointer
Power control
Temp Reg.
Incrementor
Addr. Reg.
VssVCCRSTXTAL2
Port 0
Latch
DPTR
PC
64KB
Flash APROM
4KB
Flash LDROM
Port 2
Latch
Port
0
Port
2
P0.0
P0.7
P2.0
P2.7
Publication Release Date: April 20, 2005
- 5 - Revision A5
W78E365
6. FUNCTIONAL DESCRIPTION
The W78E365 architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 256+1K bytes of RAM, three
timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K
program address space and a 64K data storage space.
6.1 RAM
The internal data RAM in the W78E365 is 256+1K bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 1K bytes of AUX-RAM. These RAMs are addressed by different ways.
• RAM 0H − 7FH can be addressed directly and indirectly as the same as in 8051. Address pointers
are R0 and R1 of the selected register bank.
• RAM 80H − FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0,
R1 of the selected registers bank.
• AUX-RAM 0H − 3FFH is addressed indirectly as the same way to access external data memory with
the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR
register. An access to external data memory locations higher than 3FFH will be performed with the
MOVX instruction in the same way as in the 8051. The AUX-RAM is enable after a reset. Setting the
bit 4 in CHPCON register will enable the access to AUX-RAM. When executing from internal
program memory, an access to AUX-RAM will not affect the Ports P0, P2,
WR and RD .
Example:
CHPENR REG F6H
CHPCON REG BFH
XRAMAH REG A1H
MOV CHPENR , #87H
MOV CHPENR, #59H
ORL CHPCON, #00010000B ; enable AUX-RAM
MOV CHPENR, #00H
MOV XRAMAH, #01H ; internal high address
MOV R0, #23H
MOV A, #55H
MOVX @R0, A ; Write 55h data to 0123h AUX-RAM address.
MOV XRAMAH, #02H
MOV R1, #FFH ; Read data from 02FFh AUX-RAM address.
MOVX A, @R1
MOV DPTR, #0134H
MOV A, #78H
MOVX @DPTR, A ; Write 78h data to 0134h AUX-RAM address.
MOV DPTR, #7FFFH
MOVX A, @DPRT ; Read data from the external 7FFFh address SRAM
- 6 -
W78E365
6.2 Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1
are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by
the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or
as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating
modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload
mode is the same as that of Timers 0 and 1.
6.2.1 Timer 2 Output
If set T2OE (T2MOD.1) bit and clear C/T2 (T2CON.1) bit at auto-reload mode, P1.0 will be toggled
once overflow.
TIMER 2 Mode
Bit: 7 6 5 4 3 2 1 0
T2OE
Mnemonic: T2MOD Address: C9H
T2OE: Enable this bit to toggle P1.0 pin while Timer2 has been overflowed.
6.3 Clock
The W78E365 is designed with either a crystal oscillator or an external clock. Internally, the clock is
divided by two before it is used by default. This makes the W78E365 relatively insensitive to duty
cycle variations in the clock.
6.3.1 Crystal Oscillator
The W78E365 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground.
6.3.2 External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator.
6.4 Power Management
6.4.1 Idle Mode
Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the
processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor
will exit idle mode when either an interrupt or a reset occurs.
Publication Release Date: April 20, 2005
- 7 - Revision A5
W78E365
6.4.2 Power-down Mode
When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode
all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware
reset or external interrupts
INT0 to
6.4.3 Reduce EMI Emission
The W78E365 allows user to diminish the gain of on-chip oscillator amplifier by using programmer to
clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the
external crystal operating improperly at high frequency. The value of C1 and C2 may need some
adjustment while running at lower gain.
ALE Off Function
Auxiliary Register
Bit: 7 6 5 4 3 2 1 0
- - - - - - - ALEOFF
ALEOFF: Set this bit to disable ALE output.
INT1
when enabled and set to level triggered.
Mnemonic: AUXR Address: 8EH
6.5 Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E365 is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
6.5.1 W78E365 Special Function Registers (SFRs) and Reset Values
F8
F0
E8
E0
D8
D0
C8
C0
+B
00000000
+ACC
00000000
+P4
11111111
+PSW
00000000
+T2CON
00000000
+XICON
00000000
PWMP
00000000
T2MOD
00000000
PWM0
00000000
RCAP2L
00000000
P4CONA
00000000
PWM1
00000000
RCAP2H
00000000
P4CONB
00000000
PWMCON1
00000000
TL2
00000000
SFRAL
00000000
PWM2
00000000
TH2
00000000
SFRAH
00000000
CHPENR
00000000
PWM3
00000000
PWMCON2
00000000
SFRFD
00000000
PWM4
00000000
SFRCN
00000000
- 8 -
Continued
B8
B0
A8
A0
98
90
88
80
Notes:
1. The SFRs marked with a plus sign(+) are both byte- and bit-addressable.
2. The text of SFR with bold type characters are extension function registers.
+IP
00000000
+P3
00000000
+IE
00000000
+P2
11111111
+SCON
00000000
+P1
11111111
+TCON
00000000
+P0
11111111
XRAMAH
00000000
SBUF
xxxxxxxx
TMOD
00000000
SP
00000111
P43AL
00000000
P42AL
00000000
TL0
00000000
DPL
00000000
P41AL
00000000
TL1
00000000
DPH
00000000
TH0
00000000
P40AL
00000000
P43AH
00000000
P42AH
00000000
P41AH
00000000
TH1
00000000
P40AH
00000000
W78E365
CHPCON
0xx00000
P4CSIN
00000000
AUXR
00000000
POR
00000000
WDTC
00000000
PCON
00110000
6.6 Port 4
Port 4, address D8H, is a 8-bit multipurpose programmable I/O port. Each bit can be configured
individually by software. The Port 4 has four different operation modes.
Mode 0: P4.0
Mode 1: P4.0
addresses. These signals can be used as chip-select signals for external peripherals.
Mode 2: P4.0
addresses. These signals can be used as chip-select signals for external peripherals.
Mode 3: P4.0
specified addresses. These signals can be used as chip-select signals for external
peripherals.
When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range
depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH
and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the
control bits to configure the Port 4 operation mode.
−P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as
external interrupt
−P4.3 are read strobe signals that are synchronized with
PSEN
and
INT2
if enabled.
signal at specified
RD
−P4.3 are write strobe signals that are synchronized with WR signal at specified
−P4.3 are read/write strobe signals that are synchronized with
or WRsignal at
RD
Publication Release Date: April 20, 2005
- 9 - Revision A5
W78E365
6.6.1 Port Options Register
Bit: 7 6 5 4 3 2 1 0
- - - - - - - P0UP
Mnemonic: POR Address: 86H
P0UP: Enable Port 0 weak up. The pins of Port 0 can be configured with either the open drain or
standard port with internal pull-up. By the default, Port 0 is an open drain bi-directional I/O port. When
the P0UP bit in the POR register is set, the pins of port 0 will perform a bi-directional I/O port with
internal pull-up that is structurally the same Port2.
6.6.2
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
INT2
/ INT3
) bit" instruction. For example,
CLR
- 10 -
Eight-source interrupt information:
A
W78E365
INTERRUPT SOURCE
External Interrupt 0 03H 0 (highest) IE.0 TCON.0
Timer/Counter 0 0BH 1 IE.1 -
External Interrupt 1 13H 2 IE.2 TCON.2
Timer/Counter 1 1BH 3 IE.3 -
Serial Port 23H 4 IE.4 -
Timer/Counter 2 2BH 5 IE.5 -
External Interrupt 2 33H 6 XICON.2 XICON.0
External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3
VECTOR
ADDRESS
POLLING SEQUENCE
WITHIN PRIORITY
LEVEL
ENABLE
REQUIRED
SETTINGS
INTERRUPT TYPE
EDGE/LEVEL
P4CONB (C3H)
BIT NAME FUNCTION
7, 6 P43FUN1
P43FUN0
5, 4 P43CMP1
P43CMP0
3, 2 P42FUN1
P42FUN0
1, 0 P42CMP1
P42CMP0
00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.
01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The
address range depends on the SFR P43AH, P43AL, P43CMP1, and
P43CMP0.
Chip-select signals address comparison:
00: Compare the full address (16 bits length) with the base address register
P43AH, P43AL.
01: Compare the 15 high bits (A15
register P43AH, P43AL.
10: Compare the 14 high bits (A15
register P43AH, P43AL.
11: Compare the 8 high bits (A15
register P43AH, P43AL.
The P4.2 function control bits which are the similar definition as P43FUN1,
P43FUN0.
The P4.2 address comparator length control bits which are the similar definition
as P43CMP1, P43CMP0.
−A1) of address bus with the base address
−A2) of address bus with the base address
−
8) of address bus with the base address
Publication Release Date: April 20, 2005
- 11 - Revision A5
W78E365
P4CONA (C2H)
BIT NAME FUNCTION
7, 6
5, 4
3, 2
1, 0
P4CSIN (AEH)
BIT NAME FUNCTION
P41FUN1
P41FUN0
P41CMP1
P41CMP0
P40FUN1
P40FUN0
P40CMP1
P40CMP0
7 P43CSINV
6 P42CSINV The similarity definition as P43SINV.
5 P41CSINV The similarity definition as P43SINV.
4 P40CSINV The similarity definition as P43SINV.
3 - Reserve
2 - Reserve
1 - 0
0 - 0
6.6.3 Port 4 Base Address Registers
P40AH, P40AL:
The Base address register for comparator of P4.0. P40AH contains the high-order byte of address,
P40AL contains the low-order byte of address.
The P4.1 function control bits which are the similar definition as P43FUN1,
P43FUN0.
The P4.1 address comparator length control bits which are the similar definition
as P43CMP1, P43CMP0.
The P4.0 function control bits which are the similar definition as P43FUN1,
P43FUN0.
The P4.0 address comparator length control bits which are the similar definition
as P43CMP1, P43CMP0.
The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe
signal.
= 1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe signal.
= 0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe signal.
P41AH, P41AL:
The Base address register for comparator of P4.1. P41AH contains the high-order byte of address,
P41AL contains the low-order byte of address.
P42AH, P42AL:
The Base address register for comparator of P4.2. P42AH contains the high-order byte of address,
P42AL contains the low-order byte of address.
P43AH, P43AL:
The Base address register for comparator of P4.3. P43AH contains the high-order byte of address,
P43AL contains the low-order byte of address.
- 12 -
W78E365
P4 (D8H)
BIT NAME FUNCTION
7 P47 I/O pin
6 P46 I/O pin.
5 P45 I/O pin.
4 P44 I/O pin.
3 P43 Port 4 Data bit which outputs to pin P4.3 at mode 0.
2 P42 Port 4 Data bit. which outputs to pin P4.2 at mode 0.
1 P41 Port 4 Data bit. which outputs to pin P4.1at mode 0.
0 P40 Port 4 Data bit which outputs to pin P4.0 at mode 0.
Here is an example to program the P4.0 as a write strobe signal at the I/O port address 1234H −
1237H and positive polarity, and P4.1 − P4.3 are used as general I/O ports.
MOV P40AH, #12H
MOV P40AL, #34H ; Base I/O address 1234H for P4.0
MOV P4CONA, #00001010B ; P4.0 a write strobe signal and address line A0 and A1 are masked.
MOV P4CONB, #00H ; P4.1
MOV P2ECON, #10H ; Write the P40SINV = 1 to inverse the P4.0 write strobe polarity
; default is negative.
− P4.3 as general I/O port which are the same as PORT1
Then any instruction MOVX @DPTR, A (with DPTR = 1234H
− 1237H) will generate the positive
polarity write strobe signal at pin P4.0. And the instruction MOV P4, #XX will output the bit3 to bit1 of
data #XX to pin P4.3
REGISTER
P4xAL
P4xAH
− P4.1.
P4 REGISTER
P4.x
READ
WRITE
ADDRESS BUS
EQUAL
Bit Length
REGISTER
P4xCMP0
P4xCMP1
Selectable
comparator
P4xCSINV
P4xFUN0
P4xFUN1
P4.x INPUT DATA BUS
DATA I/O
RD_CS
MUX 4->1
WR_CS
RD/WR_CS
PIN
P4.x
Publication Release Date: April 20, 2005
- 13 - Revision A5
W78E365
6.7 Pulse Width Modulated Outputs (PWM)
There are five pulse width modulated output channels to generate pulses of programmable length and
interval. The repetition frequency is defined by an 8-bit prescaler PWMP, which supplies the clock for
the counter. The prescaler and counter are common to both PWM channels. The 8-bit counter counts
modular 255 (0 ~ 254). The value of the 8-bit counter compared to the contents of five registers:
PWM0, PWM1, PWM2, PWM3 and PWM4. Provided the contents of either these registers is greater
than the counter value, the corresponding PWM0, PWM1, PWM2, PWM3 or PWM4 output is set
HIGH. If the contents of these registers are equal to, or less than the counter value, the output will be
LOW. The pulse-width-ratio is defined by the contents of the registers PWM0, PWM1, PWM2, PWM3
and PWM4. The pulse-width-ratio is in the range of 0 to 1 and may be programmed in increments of
1/255. ENPWM0, ENPWM1, ENPWM2, ENPWM3 and ENPWM4 bit will enable or disable PWM
output.
Buffered PWM outputs may be used to drive DC motors. The rotation speed of the motor would be
proportional to the contents of PWM0/1/2/3/4. The repetition frequency
output is given by:
f
=
f
pwm
Prescaler division factor = PWM + 1
PWMn high/low ratio of
osc
PWMP
255)1(2 ×+×
PWMn =
PWMn)(
(PWMn)-255
pwmf , at the PWM0/1/2/3/4
This gives a repetition frequency range of 123 Hz to 31.4K Hz (
registers with either 00H or FFH, the PWM channels will output a constant HIGH or LOW level,
respectively. Since the 8-bit counter counts modulo 255, it can never actually reach the value of the
PWM registers when they are loaded with FFH.
When a compare register (PWM0, PWM1, PWM2, PWM3, PWM4) is loaded with a new value, the
associated output updated immediately. It does not have to wait until the end of the current counter
period. There is weakly pulled high on PWM output.
- 14 -
= 16M Hz). By loading the PWM
oscf
W78E365
ENPWM 0/1/2/3/4/5
1/2
Fosc
Please refer as below code.
PWMP
Counter
PWM0
Register
8-bits Counter
PWM1
Register
PWM2
Register
PWM3
Register
PWM4
Register
FIGURE 1 PWM DIAGRAM
PWM0
Counter
PWM1
Counter
PWM2
Counter
PWM3
Counter
PWM4
Counter
X
+
+
>
Y
-
-
PWM0OE
PWM0
(P1.3)
X
+
>
Y
-
X
+
>
Y
-
X
+
>
Y
-
X
+
>
Y
-
PWM1OE
PWM2OE
PWM3OE
PWM4OE
PWM1
(P1.4)
PWM2
(P1.5)
PWM3
(P1.6)
PWM4
(P1.7)
mov pwmcon1, #00110011b ; enable pwm3, 2, 1, 0
mov pwmcon2, #00000101b ; enable pwm4
mov pwmp, #40h ; Fpwm = XT/(2*(1+pwmp)*255)
jb p1.3, $
mov pwm0, #14h ; duty cycle high/low = pwm0/(255-pmw0)
jb p1.4, $
mov pwm1, #18h
jb p1.5, $
mov pwm2, #20h
jb p1.6, $
mov pwm3, #b0h
jb p1.7,$
mov pwm4, #40h
mov pwmcon1, #11111111b ; output enable pwm3, 2, 1, 0
Publication Release Date: April 20, 2005
- 15 - Revision A5
W78E365
PWM3 Register
Bit: 7 6 5 4 3 2 1 0
PWM2 Register
Bit: 7 6 5 4 3 2 1 0
PWM Control 1 Register
Bit: 7 6 5 4 3 2 1 0
PWM3OE PWM2OE ENPWM3 ENPWM2 PWM1OE PWM0OE ENPWM1 ENWPM0
PWM3OE: Output enable for PWM3
PWM2OE: Output enable for PWM2
ENPWM3: Enable PWM3
ENPWM2: Enable PWM2
PWM1OE: Output enable for PWM1
PWM0OE: Output enable for PWM0
ENPWM1: Enable PWM1
ENPWM0: Enable PWM0
Mnemonic: PWM3 Address: DEH
Mnemonic: PWM2 Address: DDH
Mnemonic: PWMCON1 Address: DCH
PWM1 Register
Bit: 7 6 5 4 3 2 1 0
PWM0 Register
Bit: 7 6 5 4 3 2 1 0
PWMP Register
Bit: 7 6 5 4 3 2 1 0
Mnemonic: PWM1 Address: DBH
Mnemonic: PWM0 Address: DAH
Mnemonic: PWMP Address: D9H
- 16 -
W78E365
PWM4 Register
Bit: 7 6 5 4 3 2 1 0
PWM Control 2 Register
Bit: 7 6 5 4 3 2 1 0
- - - - - PWM4OE - ENWPM4
PWM4OE: Output enable for PWM4
ENPWM: Enable for PWM4
6.8 Watchdog Timer
The Watchdog timer is a free-running timer which can be programmed by the user to serve as a
system monitor, a time-base generator or an event timer. It is basically a set of dividers that divide the
system clock. The divider output is selectable and determines the time-out interval. When the time-out
occurs, a system reset can also be caused if it is enabled. The main use of the Watchdog timer is as a
system monitor. This is important in real-time control applications. In case of power glitches or electromagnetic interference, the processor may begin to execute errant code. If this is left unchecked the
entire system may crash. The watchdog time-out selection will result in different time-out values
depending on the clock speed. The Watchdog timer will de disabled on reset. In general, software
should restart the Watchdog timer to put it into a known state. The control bits that support the
Watchdog timer are discussed below.
Mnemonic: PWM4 Address: CFH
Mnemonic: PWMCON2 Address: CEH
Watchdog Timer Control Register
Bit: 7 6 5 4 3 2 1 0
ENW CLRW WIDL - - PS2 PS1 PS0
Mnemonic: WDTC Address: 8FH
ENW : Enable watch-dog if set.
CLRW : Clear watch-dog timer and prescaler if set. This flag will be cleared automatically
WIDL : If this bit is set, watch-dog is enabled under IDLE mode. If cleared, watch-dog is disabled
under IDLE mode. Default is cleared.
Publication Release Date: April 20, 2005
- 17 - Revision A5
W78E365
PS2, PS1, PS0: Watch-dog prescaler timer select. Prescaler is selected when set PS2−0 as follows:
PS2 PS1 PS0 PRESCALER SELECT
0 0 0 2
0 0 1 4
0 1 0 8
0 1 1 16
1 0 0 32
1 0 1 64
1 1 0 128
1 1 1 256
The time-out period is obtained using the following equation:
1
14
2100012
OSC
PRESCALER×× × × mS
Before Watchdog time-out occurs, the program must clear the 14-bit timer by writing 1 to WDTC.6
(CLRW). After 1 is written to this bit, the 14-bit timer, prescaler and this bit will be reset on the next
instruction cycle. The Watchdog timer is cleared on reset.
WIDL
IDLE
OSC 1/12
Watchdog Timer Block Diagram
ENW
PRESCALER
CLRW
Typical Watch-Dog time-out period when OSC = 20 MHz
PS2 PS1 PS0 WATCHDOG TIME-OUT PERIOD
0 0 0 19.66 mS
0 0 1 39.32 mS
0 1 0 78.64 mS
0 1 1 157.28 mS
1 0 0 314.57 mS
1 0 1 629.14 mS
1 1 0 1.25 S
1 1 1 2.50 S
EXTERNAL
RESET
14-BIT TIMER
CLEAR
INTERNAL
RESET
- 18 -
W78E365
6.9 In-System Programming (ISP) Mode
The W78E365 equips one 64K byte of main ROM bank for application program (called APROM) and
one 4K byte of auxiliary ROM bank for loader program (called LDROM). In the normal operation, the
microcontroller executes the code in the APROM. If the content of APROM needs to be modified, the
W78E365 allows user to activate the In-System Programming (ISP) mode by setting the CHPCON
register.
then 59H sequentially to the CHPENR register to enable the CHPCON write attribute. Writing
CHPENR register with the values except 87H and 59H will close CHPCON register write
attribute.
Mode, program, erase, read ... etc, during device in the idle mode. Setting the bit CHPCON.0 the
device will enter in-system programming mode after a wake-up from idle mode. Because device needs
proper time to complete the ISP operations before awaken from idle mode, software may use timer
interrupt to control the duration for device wake-up from idle mode. To perform ISP operation for
revising contents of APROM, software located at APROM setting the CHPCON register then enter idle
mode, after awaken from idle mode the device executes the corresponding interrupt service routine in
LDROM. Because the device will clear the program counter while switching from APROM to LDROM,
the first execution of RETI instruction in interrupt service routine will jump to 00H at LDROM area. The
device offers a software reset for switching back to APROM while the content of APROM has been
updated completely.
to reset the CPU
makes the job easy and efficient in which the application needs to update firmware frequently. In some
applications, the in-system programming feature make it possible to easily update the system firmware
without opening the chassis.
The CHPCON is read-only by default, software must write two specific values 87H,
The W78E365 achieves all in-system programming operations including enter/exit ISP
Setting CHPCON register bit 0, 1 and 7 to logic-1 will result a software reset
. The software reset serves as a external reset. This in-system programming feature
SFRAH, SFRAL: The objective address of on-chip ROM in the in-system programming mode.
SFRAH contains the high-order byte of address, SFRAL contains the low-order byte of address.
SFRFD: The programming data for on-chip ROM in programming mode.
SFRCN: The control byte of on-chip ROM programming mode.
SFRCN (C7)
BIT NAME FUNCTION
7 - Reserve.
On-chip ROM bank select for in-system programming.
6 WFWIN
5 OEN ROM output enable.
4 CEN ROM chip enable.
3, 2, 1, 0 CTRL[3:0] The flash control signals
= 0: 64K bytes ROM bank is selected as destination for re-programming.
= 1: 4K bytes ROM bank is selected as destination for re-programming.
Publication Release Date: April 20, 2005
- 19 - Revision A5
W78E365
MODE WFWIN CTRL<3:0> OEN CEN SFRAH, SFRAL SFRFD
Erase 64KB APROM 0 0010 1 0 X X
Program 64KB APROM 0 0001 1 0 Address in Data in
Read 64KB APROM 0 0000 0 0 Address in Data out
Erase 4KB LDROM 1 0010 1 0 X X
Program 4KB LDROM 1 0001 1 0 Address in Data in
Read 4KB LDROM 1 0000 0 0 Address in Data out
6.9.1 In-System Programming Control Register (CHPCON)
CHPCON (BFH)
BIT NAME FUNCTION
SWRESET
7
6 - Reserve.
5 LD/AP
4 ENAUXRAM
3 1 Must be 1
2 - Reserve.
1 FBOOTSL
0 FPROGEN
When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
This bit is read only. 1: CPU is running LDROM program. 0: CPU is running
APROM program.
1: Enable on-chip AUX-RAM.
0: Disable the on-chip AUX-RAM
When this bit is set to 1, and both SWRESET and FPROGEN are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
When this bit is set to 1, and both SWRESET and FBOOTSL are set to 1. It
will enforce microcontroller reset to initial condition just like power on reset.
This register is protected by CHPENR register. Please write as below procedures while you would like
to write CHPCON register.
Mov CHPENR, #87h
Mov CHPENR, #59h
Anl CHPCON, #EFh ; Disable AUX-RAM
Mov CHPENR, #0h
6.10 Software Reset
Set CHPCON = 0X83, timer and enter IDLE mode. CPU will reset and restart from APFLASH after
time out.
- 20 -
W78E365
A
6.11 H/W Reboot Mode (Boot from LDROM)
By default, the W78E365 boots from APROM program after a power on reset. On some occasions,
user can force the W78E365 to boot from the LDROM program via following settings. The possible
situation that you need to enter H/W REBOOT mode when the APROM program can not run properly
and device can not jump back to LDROM to execute in-system programming function. Then you can
use this H/W REBOOT mode to force the W78E365 jumps to LDROM and executes in-system
programming procedure. When you design your system, you may reserve the pins P2.6, P2.7 to
switches or jumpers. For example in a CD-ROM system, you can connect the P2.6 and P2.7 to PLAY
and EJECT buttons on the panel. When the APROM program fails to execute the normal application
program. User can press both two buttons at the same time and then turn on the power of the
personal computer to force the W78E365 to enter the H/W REBOOT mode. After power on of
personal computer, you can release both buttons and finish the in-system programming procedure to
update the APROM code.
PSEN pin value at reset to prevent from accidentally activating the programming mode or H/W
and
REBOOT mode. It is necessary to add 10K resistor on these P2.6, P2.7 and P4.3 pins.
H/W Reboot Mode
P4.3 P2.7 P2.6 MODE
X L L REBOOT
L X X REBOOT
In application system design, user must take care of the P2, P3, ALE,
E
The Reset Timing For Entering
F04KBOOT Mode
P2.7
P2.6
RST
30 mS
10 mS
Hi-Z
Hi-Z
Publication Release Date: April 20, 2005
- 21 - Revision A5
The Algorithm of In-System Programming
Part 1:32KB APROM
START
In-System Programming Mode
W78E365
procedure of entering
Enter In-System
Programming Mode ?
(conditions depend on
user's application)
Yes
Setting control registers
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#03H
Setting Timer (about 1.5 us)
and enable timer interrupt
Start Timer and enter idle Mode.
(CPU will be wakened from idle mode
by timer interrupt, then enter In-System
Programming mode)
No
Execute the normal application
program
END
CPU will be wakened by interrupt and
re-boot from 4KB LDROM to execute
the loader program.
Go
- 22 -
W78E365
Go
Timer Interrupt Service Routine:
Stop Timer & disable interrupt
Is F04KBOOT Mode?
(CHPCON.7=1)
No
Setting Timer and enable Timer
interrupt for wake-up .
(15 ms for erasing operation)
Setting erase operation mode:
MOV SFRCN,#22H
(Erase 32KB APROM)
Start Timer and enter IDLE
Mode.
(Erasing...)
Yes
Reset the CHPCON Register:
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#03H
PGM
End of Programming ?
No
Setting Timer and enable Timer
interrupt for wake-up .
(50us for program operation)
Get the parameters of new code
(Address and data bytes)
through I/O ports, UART or
other interfaces.
Setting control registers for
programming:
MOV SFRAH,#ADDRESS_H
MOV SFRAL,#ADDRESS_L
MOV SFRFD,#DATA
MOV SFRCN,#21H
Part 2: 4KB LDROM
Procedure of Updating
the 32KB APROM
Yes
Is currently in the
F04KBOOT Mode ?
No
Software reset CPU and
re-boot from the 32KB
APROM.
MOV CHPENR,#87H
MOV CHPENR,#59H
MOV CHPCON,#83H
Yes
Hardware Reset
to re-boot from
new 32 KB APROM.
(S/W reset is
invalid in F04KBOOT
Mode)
End of erase
operation. CPU will
be wakened by Timer
interrupt.
PGM
END
Executing new code
from address
00H in the 32KB APROM.
Publication Release Date: April 20, 2005
- 23 - Revision A5
W78E365
r
6.12 Security
During the on-chip ROM programming mode, the ROM can be programmed and verified repeatedly.
Until the code inside the ROM is confirmed OK, the code can be protected. The protection of ROM
and those operations on it are described below.
The W78E365 has a Security Register that can be accessed in programming mode. Those bits of the
Security Registers can not be changed once they have been programmed from high to low. They can
only be reset through erase-all operation. The Security Register is located at the 0FFFFH of the
LDROM space.
0000h
0FFFh
7FFFh
FFFFh
32KB On-chip ROM
Program Memory
APROM
Reserved
B7
B0: Lock bit, logic 0: active
B1: MOVC inhibit,
logic 0: the MOVC instruction in external memory
cannot access the code in internal memory.
logic 1: no restriction.
B2: Encryption
logic 0: the encryption logic enable
logic 1: the encryption logic disable
B07: Osillator Control
logic 0: 1/2 gain
logic 1: Full gain
Default 1 for all security bits.
Reserved bits must be kept in logic 1.
B2
Security Bits
B0B1
Special Setting Registe
4KB On-chip ROM
Program Memory
LDROM
Reserved
Reserved
Security Register
Lock bit
This bit is used to protect the customer's program code in the W78E365. It may be set after the
programmer finishes the programming and verifies sequence. Once this bit is set to logic 0, both the
ROM data and Security Register can not be accessed again.
MOVC Inhibit
This bit is used to restrict the accessible region of the MOVC instruction. It can prevent the MOVC
instruction in external program memory from reading the internal program code. When this bit is set to
logic 0, a MOVC instruction in external program memory space will be able to access code only in the
external memory, not in the internal memory. A MOVC instruction in internal program memory space
will always be able to access the ROM data in both internal and external memory. If this bit is logic 1,
there are no restrictions on the MOVC instruction.
Encryption
This bit is used to enable/disable the encryption logic for code protection. Once encryption feature is
enabled, the data presented on port 0 will be encoded via encryption logic. Only whole chip erase will
reset this bit.
- 24 -
W78E365
A
Oscillator Control
W78E365/E516 allow user to diminish the gain of on-chip oscillator amplifier by using programmer to
set the bit B7 of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may
improperly affect the external crystal operation at high frequency above 24 MHz. The value of R and
C1, C2 may need some adjustment while running at lower gain.
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
PARAMETER SYMBOL MIN. MAX. UNIT
DC Power Supply
DD−VSS
V
Input Voltage VIN VSS -0.3 VDD +0.3 V
Operating Temperature TA 0 70
Storage Temperature TST -55 +150
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
-0.3 +6.0 V
°C
°C
7.2 D.C. Characteristics
(V
= 5V ±10%, TA = 25°C, Fosc = 20 MHz, unless otherwise specified.)
DD − VSS
SYMBOL PARAMETER
V
Operating Voltage 4.5 5.5 V RST = 1, P0 = VDD
DD
I
Operating Current - 20 mA
DD
I
Idle Current - 6 mA
IDLE
I
Power Down Current -
PWDN
I
IN1
I
IN2
Input Current
P1, P2, P3, P4
Input Current
RST
Input Leakage Current
I
LK
[*4]
I
TL
P0,
Logic 1 to 0 Transition Current
P1, P2, P3, P4
E
SPECIFICATION
MIN. MAX. UNIT
10
-50 +10
-10 +300
-10 +10
-500 -200
µA
µA
µA
µA
µA
TEST CONDITIONS
No load
= 5.5V
V
DD
Idle mode
= 5.5V
V
DD
Power-down mode
= 5.5V
V
DD
V
= 5.5V
DD
V
= 0V or V
IN
V
= 5.5V
DD
0<V
IN<VDD
= 5.5V
V
DD
0V<V
V
= 5.5V
DD
= 2.0V
V
IN
IN<VDD
DD
Publication Release Date: April 20, 2005
- 25 - Revision A5
D.C. Characteristics, continued
A
W78E365
SYMBOL PARAMETER
SPECIFICATION
TEST CONDITIONS
MIN. MAX. UNIT
Input Low Voltage
V
IL1
V
IL2
V
IL3
P0, P1, P2, P3, P4,
Input Low Voltage
RST
Input Low Voltage
XTAL1
[*4]
E
0 0.8 V V
0 0.8 V V
0 0.8 V V
= 4.5V
DD
= 4.5V
DD
= 4.5V
DD
Input High Voltage
V
IH1
V
IH2
V
IH3
V
OL1
P0, P1, P2,
Input High Voltage
RST
Input High Voltage
XTAL1
Output Low Voltage
P1, P2, P3, P4
P3, P4, EA
[*4]
2.4 V
3.5 V
3.5 V
- 0.45 V
Output Low Voltage
V
OL2
Isk1
P0, ALE,
PSEN
Sink current
P1, P3, P4
[*3]
- 0.45 V
4 8 mA
Sink current
Isk2
V
OH1
P0, P2, ALE,
Output High Voltage
P1, P2, P3, P4
PSEN
10 14 mA
2.4 - V
Output High Voltage
V
OH2
Isr1
P0, ALE,
Source current
P1, P2, P3, P4
PSEN
[*3]
2.4 - V
-120 -180
Source current
Isr2
P0, P2, ALE,
Notes:
*1. RST pin is a Schmitt trigger input.
*2. P0, ALE and
*3. XTAL1 is a CMOS input.
*4. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0.
PSEN are tested in the external access mode.
PSEN
-10 -14 mA
+0.2 V V
DD
+0.2 V
DD
+0.2 V
DD
µA
= 5.5V
D D
= 5.5V
V
DD
= 5.5V
V
DD
V
= 4.5V
DD
= +2 mA
I
OL
V
= 4.5V
DD
= +4 mA
I
OL
V
= 4.5V
DD
OL = 0.45V
V
V
=4.5V
DD
OL = 0.45V
V
= 4.5V
V
DD
I
= -100 µA
OH
= 4.5V
V
DD
I
= -400 µA
OH
V
= 4.5V
DD
V
OH = 2.4V
V
=4.5V
DD
V
OH = 2.4V
- 26 -
W78E365
7.3 A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the ratings
of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications
can be expressed in terms of multiple input clock periods (T
experience less than a ±20 nS variation.
Clock Input Waveform
CP), and actual parts will usually
XTAL1
T
CH
F
OP,
T
CL
T
CP
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
Operating Speed FOP 0 - 40 MHz 1
Clock Period TCP 25 - - nS 2
Clock High TCH 20 - - nS 3
Clock Low TCL 20 - - nS 3
Notes:
1. The clock may be stopped indefinitely in either state.
2. The T
3. There are no duty cycle requirements on the XTAL1 input.
CP specification is used as a reference in other specifications.
Publication Release Date: April 20, 2005
- 27 - Revision A5
8. TIMING WAVEFORMS
8.1 Program Fetch Cycle
S1
S2 S3 S4 S5 S6 S1 S2 S3 S4 S5 S6
XTAL1
ALE
PSEN
T
AAS
PORT 2
T
AAH
T
T
APL
T
PDA
PSW
T
ALW
T
PDH,TPDZ
W78E365
PORT 0
Code
A0-A7
Data
A0-A7
Code
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
Address Valid to ALE Low TAAS
Address Hold from ALE Low TAAH
APL
ALE Low to PSEN Low
PSEN Low to Data Valid
Data Hold after
Data Float after
PSEN
PSEN
High
High
T
T
PDA - - 2 TCP nS 2
PDH 0 - 1 TCP nS 3
T
T
PDZ 0 - 1 TCP nS
ALE Pulse Width TALW
T
Pulse Width
PSEN
Notes:
1. P0.0−P0.7, P2.0−P2.7 remain stable throughout entire memory cycle.
2. Memory access time is 3 T
3. Data have been latched internally prior to
4. "
∆" (due to buffer driving delay and wire loading) is 20 nS.
CP.
PSW
PSEN
1 TCP-∆
1 TCP-∆
1 TCP-∆
2 TCP-∆
3 TCP-∆
going high.
A0-A7
Data
A0-A7
- - nS 4
- - nS 1, 4
- - nS 4
2 TCP - nS 4
3 TCP - nS 4
- 28 -
Timing Waveforms, continued
8.2 Data Read Cycle
XTAL1
ALE
PSEN
W78E365
S2 S3S5 S6 S1S2 S3 S4S5 S6 S1S4
PORT 2
A0-A7
PORT 0
RD
PARAMETER SYMBOL MIN. TYP. MAX. UNIT NOTES
ALE Low to RD Low
Low to Data Valid
RD
Data Hold from RD High
Data Float from
Pulse Width
RD
Notes:
1. Data memory access time is 8 TCP.
2. "
∆" (due to buffer driving delay and wire loading) is 20 nS.
RD
High
A8-A15
DATA
T
DAR
T
DDA
T
DRD
DAR
T
T
DDA - - 4 TCP nS 1
DDH 0 - 2 TCP nS
T
DDZ 0 - 2 TCP nS
T
T
DRD
3 TCP-∆
6 TCP-∆
T
DDH,TDDZ
-
3 T
CP+∆
nS 1, 2
6 TCP - nS 2
Publication Release Date: April 20, 2005
- 29 - Revision A5
Timing Waveforms, continued
8.3 Data Write Cycle
XTAL1
ALE
PSEN
W78E365
S2 S3S5 S6 S1S2 S3 S4S1S5 S6S4
PORT 2
PORT 0
WR
A0-A7
T
DAW
A8-A15
T
DAD
DATA OUT
T
DWR
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
DAW
ALE Low to
WR
Low
Data Valid to WR Low
Data Hold from WR High
Pulse Width
WR
Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.
T
T
DAD
DWD
T
T
DWR
3 TCP-∆
1 TCP-∆
1 TCP-∆
6 TCP-∆
T
DWD
-
3 T
CP+∆
- - nS
- - nS
6 TCP - nS
nS
- 30 -
Timing Waveforms, continued
8.4 Port Access Cycle
XTAL1
ALE
W78E365
S5 S6 S1
T
T
PDHPDS
T
PDA
PORT
INPUT
SAMPLE
DATA OUT
PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Port Input Setup to ALE Low TPDS 1 TCP - - nS
Port Input Hold from ALE Low TPDH 0 - - nS
Port Output to ALE TPDA 1 TCP - - nS
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to
ALE, since it provides a convenient reference.
Publication Release Date: April 20, 2005
- 31 - Revision A5
9. TYPICAL APPLICATION CIRCUIT
9.1 External Program Memory and Crystal
V
8.2 K
DD
10 u
CRYSTAL
C1
C2
31
EA
19
XTAL1
R
18
XTAL2
9
RST
INT0
12
13
INT1
14
T0
15
T1
P1.0 1
P1.1
2
P1.2
3
P1.3
4
P1.4
5
P1.5
6
P1.6
7
P1.7
8
W78E365
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
PSEN
ALE
TXD
RXD
RD
WR
AD0
39
AD1
38
AD2
37
AD3
36
AD4
35
AD5
34
AD6
33
32
AD7
21
A8
22
A9
23
A10
24
A11
25
A12
26
A13
27
A14
28
A15
17
16
29
30
11
10
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
W78E365
3
4
7
8
13
14
17
18
1
11
74LS373
2
D0
Q0
5
D1
Q1
6
D2
Q2
9
D3
Q3
12
D4
Q4
15
D5
Q5
16
D6
Q6
19
D7
Q7
OC
G
A0
GND
A10
A11
A12
A13
A14
A15
10
A0
A1
9
A1
A2
8
A2
A3
7
A3
A4
6
A4
A5
5
A5
A6
4
A6
A7
3
A7
A8
25
A8
A9
24
A9
21
A10
23
A11
2
A12
26
A13
27
A14
1
A15
20
CE
22
OE
27512
A0
A1
A2
A3
A4
A5
A6
A7
11
O0
O1
O2
O3
O4
O5
O6
O7
AD0
12
AD1
13
AD2
15
AD3
16
AD4
17
AD5
18
AD6
19
AD7
Figure A
CRYSTAL C1 C2 R
6 MHz 47P 47P -
16 MHz 30P 30P -
24 MHz 15P 10P -
Above table shows the reference values for crystal applications.
Notes:
1. C1, C2, R components refer to Figure A
2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board.
Typical Application Circuit, continued
- 32 -
9.2 Expanded External Data Memory and Oscillator
V
DD
31
EA
19
XTAL1
18
XTAL2
9
RST
INT0
12
13
INT1
14
T0
15
T1
1
P1.0
2
P1.1
3
P1.2
4
P1.3
5
P1.4
6
P1.5
7
P1.6
8
P1.7
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
WR
PSEN
ALE
TXD
RXD
39
38
37
36
35
34
33
32
21
22
23
24
25
26
27
28
RD
17
16
29
30
11
10
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
A8
A9
A10
A11
A12
A13
A14
AD0
AD1
AD2
AD3
AD4
AD5
AD6
AD7
GND
3
D0
4
D1
7
D2
8
D3
13
D4
14
D5
17
D6
18
D7
1
OC
11
G
74LS373
W78E58B
Figure B
8.2 K
V
DD
OSCILLATOR
10 u
W78E365
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
GND
10
A0
9
8
7
6
5
4
3
25
24
21
23
2
26
1
20
22
27
D0
A1
D1
A2
D2
A3
D3
A4
D4
A5
D5
A6
D6
A7
D7
A8
A9
A10
A11
A12
A13
A14
CE
OE
WR
A0
2
Q0
5
A1
Q1
A2
6
Q2
9
A3
Q3
12
A4
Q4
15
A5
Q5
16
A6
Q6
A7
19
Q7
20256
AD0
11
AD1
12
AD2
13
15
AD3
AD4
16
AD5
17
AD6
18
AD7
19
10. PACKAGE DIMENSIONS
10.1 40-pin DIP
40
1
E
1
S
2
A
A
L
D
B
e
1
B
1
Dimension in inch Dimension in mm
Symbol
A
A
A
B
B
c
21
20
Base Plane
1
A
Seating Plane
E
e
A
a
D
E
E
e
L
a
e
S
Notes:
1. Dimension D Max. & S include mold flash or
tie bar burrs.
c
2. Dimension E1 does not include interlead flash.
3. Dimension D & E1 include mold mismatch and
are determined at the mold parting line.
4. Dimension B1 does not include dambar
protrusion/intrusion.
5. Controlling dimension: Inches.
6. General appearance spec. should be based on
final visual inspection spec.
Nom.
Min.
0.010
1
0.155
0.150
2
0.016
0.018
0.050 1.27
1
0.010
0.008
2.055 2.070
0.6000.590
0.540
0.545
1
1
0.120
0.130
015
0.630 16.00
0.650
A
0.254
3.81
0.406
0.203
14.986
13.72
2.286 2.54 2.7940.090 0.100
3.048
Min.
Nom.
3.937
0.457
0.254
52.20
15.24
13.84
3.302
16.51
5.334
4.064
0.559
1.3721.219
0.356
52.58
15.494
13.97
3.556
17.01
Max. Max.
0.210
0.160
0.022
0.0540.048
0.014
0.610
0.550
0.110
0.140
0.670
0.090
.
150
2.286
Publication Release Date: April 20, 2005
- 33 - Revision A5
Package Dimensions, continued
10.2 44-pin PLCC
D
H
61
7
17
L
θ
Seating Plane
D
e
G
D
44 40
b
b
1
W78E365
Dimension in inch
39
H
E
E
29
2818
2
A
A
1
A
y
GE
c
A
A
A
b
b
c
D
E
e
G
G
H
H
L
y
Notes:
1. Dimension D & E do not include interlead
flash.
2. Dimension b1 does not include dambar
protrusion/intrusion.
3. Controlling dimension: Inches
4. General appearance spec. should be based
on final visual inspection spec.
Symbol
Nom.
Min.
0.020
1
0.150
0.145
2
0.028
0.026
1
0.018
0.016
0.010
0.008
0.653
0.648
0.653
0.648
0.050
0.590
0.610
D
0.590
E
0.680
0.690
D
0.680
0.690
E
0.100
0.090
Dimension in mm
0.508
3.683
0.66
0.406
0.203
16.46
16.46
14.99
17.27
17.27
2.296
Min.
1.27
Nom.
3.81
0.711
0.457
0.254
16.59
16.59
15.49
15.4914.99
17.53
2.54
Max. Max.
0.185
0.155
0.032
0.022
0.014
0.658
0.658
BSC
0.630
0.6300.610
0.700
0.700
0.110
0.004
BSC
4.699
3.937
0.813
0.559
0.356
16.71
16.71
16.00
16.00
17.78
17.7817.53
2.794
0.10
10.3 44-pin PQFP
H
D
44
1
11
12
Seating Plane
D
e
See Detail F
Dimension in inch
34
Symbol
A
A
33
A
b
c
D
E
EH
E
e
H
H
L
1
L
22
b
c
A
A
2
A
1
y
θ
L
1
L
Detail F
y
θ
Notes:
1. Dimension D & E do not include interlead
flash.
2. Dimension b does not include dambar
protrusion/intrusion.
3. Controlling dimension: Millimeter
4. General appearance spec. should be based
on final visual inspection spec.
Nom.
Min.
--- ---
---
0.002
1
2
D
E
0.01 0.02 0.25
0.081
0.075
0.01
0.014
0.006 0.152
0.394
0.390
0.390
0.025
0.031
0.510 13.45
0.520
0.520
0.510
0.025
0.031
0.063
0.051
0
Dimension in mm
Max. Max.
---
0.087
0.018
0.0100.004
0.398
0.3980.394
0.036
0.530
0.530
0.037
0.075 1.295
0.003
Nom.
Min.
---
0.05
1.90
0.25
9.9
9.9
0.635
12.95
12.95
0.65
7
0
2.05
0.35
10.00
10.00
0.80
13.2
13.2
0.5
2.20
0.45
0.2540.101
10.1
10.1
0.952
13.45
0.8
0.95
1.6
1.905
0.08
---
7
- 34 -
W78E365
11. APPLICATION NOTE
11.1 In-system Programming Software Examples
This application note illustrates the in-system programmability of the Winbond W78E365 ROM
microcontroller. In this example, microcontroller will boot from 64KB APROM bank and waiting for a
key to enter in-system programming mode for re-programming the contents of 64KB APROM. While
entering in-system programming mode, microcontroller executes the loader program in 4KB LDROM
bank. The loader program erases the 64KB APROM then reads the new code data from external
SRAM buffer (or through other interfaces) to update the 64KB APROM.
Example 1:
;*******************************************************************************************************************
;* Example of 64K APROM program: Program will scan the P1.0. if P1.0 = 0, enters in-system
;* programming mode for updating the content of APROM code else executes the current ROM code.
;* XTAL = 16 MHz
;*******************************************************************************************************************
.chip 8052
.RAMCHK OFF
.symbols
CHPCON EQU BFH
CHPENR EQU F6H
SFRAL EQU C4H
SFRAH EQU C5H
SFRFD EQU C6H
SFRCN EQU C7H
ORG 0H
LJMP 100H ; JUMP TO MAIN PROGRAM
;************************************************************************
;* TIMER0 SERVICE VECTOR ORG = 000BH
;************************************************************************
ORG 00BH
CLR TR0 ; TR0 = 0, STOP TIMER0
MOV TL0, R6
MOV TH0, R7
RETI
;************************************************************************
;* 64K APROM MAIN PROGRAM
;************************************************************************
ORG 100H
MAIN_64K:
MOV A,P1 ; SCAN P1.0
ANL A, #01H
CJNE A, #01H,PROGRAM_64K ; IF P1.0 = 0, ENTER IN-SYSTEM PROGRAMMING MODE
JMP NORMAL_MODE
PROGRAM_64K:
MOV CHPENR, #87H ; CHPENR = 87H, CHPCON REGISTER WRTE ENABLE
Publication Release Date: April 20, 2005
- 35 - Revision A5
W78E365
MOV CHPENR, #59H ; CHPENR = 59H, CHPCON REGISTER WRITE ENABLE
MOV CHPCON, #03H ; CHPCON = 03H, ENTER IN-SYSTEM PROGRAMMING MODE
MOV TCON, #00H ; TR = 0 TIMER0 STOP
MOV IP, #00H ; IP = 00H
MOV IE, #82H ; TIMER0 INTERRUPT ENABLE FOR WAKE-UP FROM IDLE MODE
MOV R6, #F0H ; TL0 = F0H
MOV R7, #FFH ; TH0 = FFH
MOV TL0, R6
MOV TH0, R7
MOV TMOD, #01H ; TMOD = 01H, SET TIMER0 A 16-BIT TIMER
MOV TCON, #10H ; TCON = 10H, TR0 = 1,GO
MOV PCON, #01H ; ENTER IDLE MODE FOR LAUNCHING THE IN-SYSTEM
; PROGRAMMING
;********************************************************************************
;* Normal mode 64KB APROM program: depending user's application
;********************************************************************************
NORMAL_MODE:
. ; User's application program
.
.
.
Example 2:
;******************************************************************************************************************************
Example of 4 KB LDROM program: This loader program will erase the 64KB APROM first, then reads the new ;*
code from external SRAM and program them into 32 KB APROM bank. XTAL = 16 MHz
;*****************************************************************************************************************************
.chip 8052
.RAMCHK OFF
.symbols
CHPCON EQU BFH
CHPENR EQU F6H
SFRAL EQU C4H
SFRAH EQU C5H
SFRFD EQU C6H
SFRCN EQU C7H
ORG 000H
LJMP 100H ; JUMP TO MAIN PROGRAM
;************************************************************************
;* 1. TIMER0 SERVICE VECTOR ORG = 0BH
;************************************************************************
ORG 000BH
CLR TR0 ; TR0 = 0, STOP TIMER0
MOV TL0, R6
MOV TH0, R7
RETI
- 36 -
W78E365
;************************************************************************
;* 4KB LDROM MAIN PROGRAM
;************************************************************************
ORG 100H
MAIN_4K:
MOV SP, #C0H
MOV CHPENR, #87H ; CHPENR = 87H, CHPCON WRITE ENABLE.
MOV CHPENR, #59H ; CHPENR = 59H, CHPCON WRITE ENABLE.
MOV CHPCON, #03H ; CHPCON = 03H, ENABLE IN-SYSTEM PROGRAMMING.
MOV CHPENR, #00H ; DISABLE CHPCON WRITE ATTRIBUTE
MOV TCON, #00H ; TCON = 00H, TR = 0 TIMER0 STOP
MOV TMOD, #01H ; TMOD = 01H, SET TIMER0 A 16BIT TIMER
MOV IP, #00H ; IP = 00H
MOV IE, #82H ; IE = 82H, TIMER0 INTERRUPT ENABLED
MOV R6, #F0H
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
MOV TCON, #10H ; TCON = 10H, TR0 = 1, GO
MOV PCON, #01H ; ENTER IDLE MODE
UPDATE_64K:
MOV TCON, #00H ; TCON = 00H, TR = 0 TIM0 STOP
MOV IP, #00H ; IP = 00H
MOV IE, #82H ; IE = 82H, TIMER0 INTERRUPT ENABLED
MOV TMOD, #01H ; TMOD = 01H, MODE1
MOV R6, #E0H ; SET WAKE-UP TIME FOR ERASE OPERATION, ABOUT 15 mS. DEPENDING
; ON USER'S SYSTEM CLOCK RATE.
MOV R7, #B1H
MOV TL0, R6
MOV TH0, R7
ERASE_P_4K:
MOV SFRCN, #22H ; SFRCN(C7H) = 22H ERASE 64K
MOV TCON, #10H ; TCON = 10H, TR0 = 1,GO
MOV PCON, #01H ; ENTER IDLE MODE (FOR ERASE OPERATION)
;*********************************************************************
;* BLANK CHECK
;*********************************************************************
MOV SFRCN, #0H ; READ 64KB APROM MODE
MOV SFRAH, #0H ; START ADDRESS = 0H
MOV SFRAL, #0H
MOV R6, #FEH ; SET TIMER FOR READ OPERATION, ABOUT 1.5 µS.
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
BLANK_CHECK_LOOP:
SETB TR0 ; ENABLE TIMER 0
MOV PCON, #01H ; ENTER IDLE MODE
MOV A, SFRFD ; READ ONE BYTE
Publication Release Date: April 20, 2005
- 37 - Revision A5
W78E365
CJNE A, #FFH, BLANK_CHECK_ERROR
INC SFRAL ; NEXT ADDRESS
MOV A, SFRAL
JNZ BLANK_CHECK_LOOP
INC SFRAH
MOV A, SFRAH
CJNE A, #80H, BLANK_CHECK_LOOP ; END ADDRESS = 7FFFH
JMP PROGRAM_64KROM
BLANK_CHECK_ERROR:
MOV P1, #F0H
MOV P3, #F0H
JMP $
;*******************************************************************************
;* RE-PROGRAMMING 64KB APROM BANK
;*******************************************************************************
PROGRAM_64KROM:
MOV DPTR, #0H ; THE ADDRESS OF NEW ROM CODE
MOV R2, #00H ; TARGET LOW BYTE ADDRESS
MOV R1, #00H ; TARGET HIGH BYTE ADDRESS
MOV DPTR, #0H ; EXTERNAL SRAM BUFFER ADDRESS
MOV SFRAH, R1 ; SFRAH, TARGET HIGH ADDRESS
MOV SFRCN, #21H ; SFRCN(C7H) = 21 (PROGRAM 64K)
MOV R6, #BEH ; SET TIMER FOR PROGRAMMING, ABOUT 50 µS.
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
PROG_D_64K:
MOV SFRAL, R2 ; SFRAL(C4H) = LOW BYTE ADDRESS
MOVX A, @DPTR ; READ DATA FROM EXTERNAL SRAM BUFFER. BY ACCORDING USER?
; CIRCUIT, USER MUST MODIFY THIS INSTRUCTION TO FETCH CODE
MOV SFRFD, A ; SFRFD(C6H) = DATA IN
MOV TCON, #10H ; TCON = 10H, TR0 = 1,GO
MOV PCON, #01H ; ENTER IDLE MODE (PRORGAMMING)
INC DPTR
INC R2
CJNE R2, #0H, PROG_D_64K
INC R1
MOV SFRAH, R1
CJNE R1, #80H, PROG_D_64K
;*****************************************************************************
; * VERIFY 64KB APROM BANK
;*****************************************************************************
MOV R4, #03H ; ERROR COUNTER
MOV R6, #FEH ; SET TIMER FOR READ VERIFY, ABOUT 1.5 µS.
MOV R7, #FFH
MOV TL0, R6
MOV TH0, R7
MOV DPTR, #0H ; The start address of sample code
MOV R2, #0H ; Target low byte address
MOV R1, #0H ; Target high byte address
MOV SFRAH, R1 ; SFRAH, Target high address
- 38 -
W78E365
MOV SFRCN, #00H ; SFRCN = 00 (Read ROM CODE)
READ_VERIFY_64K:
MOV SFRAL, R2 ; SFRAL(C4H) = LOW ADDRESS
MOV TCON, #10H ; TCON = 10H, TR0 = 1,GO
MOV PCON, #01H
INC R2
MOVX A, @DPTR
INC DPTR
CJNE A, SFRFD, ERROR_64K
CJNE R2, #0H, READ_VERIFY_64K
INC R1
MOV SFRAH, R1
CJNE R1, #80H, READ_VERIFY_64K
;******************************************************************************
;* PROGRAMMING COMPLETLY, SOFTWARE RESET CPU
;******************************************************************************
MOV CHPENR, #87H ; CHPENR = 87H
MOV CHPENR, #59H ; CHPENR = 59H
MOV CHPCON, #83H ; CHPCON = 83H, SOFTWARE RESET.
ERROR_64K:
DJNZ R4, UPDATE_64K ; IF ERROR OCCURS, REPEAT 3 TIMES.
. ; IN-SYSTEM PROGRAMMING FAIL, USER'S PROCESS TO DEAL WITH IT.
.
.
.
Publication Release Date: April 20, 2005
- 39 - Revision A5
W78E365
12. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A1 May, 2003 - Initial Issued
A2 August, 2004 32 Revise title of 9.1
A3 Sep. 14, 2004 2 Remove P4.4 ~ P4.7
A4 Dec. 23, 2004 2, 15 Add PWM in feature list and modify PWM block diagram
A5 April 20, 2005 40 Add Important Notice
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
Headquarters
No. 4, Creation Rd. III,
Science-Based Industrial Park,
Hsinchu, Taiwan
TEL: 886-3-5770066
FAX: 886-3-5665577
http://www.winbond.com.tw/
Taipei Office
9F, No.480, Rueiguang Rd.,
Neihu District, Taipei, 114,
Taiwan, R.O.C.
TEL: 886-2-8177-7168
FAX: 886-2-8751-3579
Please note that all data and specifications are subject to change without notice.
All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Winbond Electronics Corporation America
2727 North First Street, San Jose,
CA 95134, U.S.A.
TEL: 1-408-9436666
FAX: 1-408-5441798
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18
Shinyokohama Kohoku-ku,
Yokohama, 222-0033
TEL: 81-45-4781881
FAX: 81-45-4781800
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai,
200336 China
TEL: 86-21-62365999
FAX: 86-21-62365998
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City,
No. 378 Kwun Tong Rd.,
Kowloon, Hong Kong
TEL: 852-27513100
FAX: 852-27552064
- 40 -
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