winbond W78E365 Technical data
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W78E365 Data Sheet
8-BIT MICROCONTROLLER
Table of Contents-
1. GENERAL DESCRIPTION.................................................................................................................. 2
2. FEATURES ......................................................................................................................................... 2
3. PIN CONFIGURATIONS ..................................................................................................................... 3
4. PIN DESCRIPTION ............................................................................................................................. 4
5. BLOCK DIAGRAM............................................................................................................................... 5
6. FUNCTIONAL DESCRIPTION ............................................................................................................ 6
6.1 RAM...................................................................................................................................................6
6.2 Timers 0, 1, and 2..............................................................................................................................7
6.3 Clock..................................................................................................................................................7
6.4 Power Management...........................................................................................................................7
6.5 Reset .................................................................................................................................................8
6.6 Port 4.................................................................................................................................................9
6.7 Pulse Width Modulated Outputs (PWM) ..........................................................................................14
6.8 Watchdog Timer ..............................................................................................................................17
6.9 In-System Programming (ISP) Mode ...............................................................................................19
6.10 Software Reset ................................................................................................................................20
6.11 H/W Reboot Mode (Boot from LDROM) ..........................................................................................21
6.12 Security............................................................................................................................................24
7. ELECTRICAL CHARACTERISTICS ................................................................................................. 25
7.1 Absolute Maximum Ratings .............................................................................................................25
7.2 D.C. Characteristics.........................................................................................................................25
7.3 A.C. Characteristics.........................................................................................................................27
8. TIMING WAVEFORMS .....................................................................................................................28
8.1 Program Fetch Cycle.......................................................................................................................28
8.2 Data Read Cycle..............................................................................................................................29
8.3 Data Write Cycle..............................................................................................................................30
8.4 Port Access Cycle............................................................................................................................31
9. TYPICAL APPLICATION CIRCUIT ................................................................................................... 32
9.1 External Program Memory and Crystal............................................................................................32
9.2 Expanded External Data Memory and Oscillator .............................................................................33
10. PACKAGE DIMENSIONS .................................................................................................................33
10.1 40-pin DIP........................................................................................................................................33
10.2 44-pin PLCC....................................................................................................................................34
10.3 44-pin PQFP....................................................................................................................................34
11. APPLICATION NOTE........................................................................................................................ 35
11.1 In-system Programming Software Examples ...................................................................................35
12. REVISION HISTORY ........................................................................................................................40
Publication Release Date: April 20, 2005
- 1 - Revision A5
W78E365
1. GENERAL DESCRIPTION
The W78E365 is an 8-bit microcontroller which has an in-system programmable Flash EPROM for
firmware updating. The instruction set of the W78E365 is fully compatible with the standard 8052. The
W78E365 contains a 64K bytes of main Flash APROM and a 4K bytes of auxiliary Flash LDROM
which allows the contents of the 64KB main APROM to be updated by the loader program located at
the LDROM; 256+1K bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O ports; an
additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are supported by a
eight sources two-level interrupt capability. To facilitate programming and verification, the ROM inside
the W78E365 allows the program memory to be programmed and read electronically. Once the code
is confirmed, the user can protect the code for security.
The W78E365 microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
2. FEATURES
• Fully static design 8-bit CMOS microcontroller
• 64K bytes of in-system programmable Flash EPROM for Application Program (APROM)
• 4K bytes of auxiliary ROM for Loader Program (LDROM)
• 256+1K bytes of on-chip RAM. (Including 1K bytes of AUX-RAM, software selectable)
• Four 8-bit bi-directional ports
• One 4-bit multipurpose programmable port (I/O, interrupt, Chip select function)
• Three 16-bit timer/counters
• One full duplex serial port
• Watchdog timer
• 5 channel PWM
• Software Reset
• P1.0 T2 programmable clock out
• Eight-sources, two-level interrupt capability
• Built-in power management
• Code protection
• Packaged in
− DIP 40: W78E365-40
− PLCC 44: W78E365P-40
− QFP 44: W78E365F-40
- 2 -
3. PIN CONFIGURATIONS
40-Pin DIP (W78E365)
T2, P1.0
T2EX, P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
RST
RXD, P3.0
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
WR, P3.6
RD, P3.7
XTAL2
XTAL1
VSS
W78E365
VDD1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
P0.0, AD0
P0.1, AD1
38
P0.2, AD2
37
P0.3, AD3
36
P0.4, AD4
35
P0.5, AD5
34
P0.6, AD6
33
P0.7, AD7
32
31
EA
ALE
30
29
PSEN
P2.7, A15
28
P2.6, A14
27
P2.5, A13
26
P2.4, A12
25
P2.3, A11
24
P2.2, A10
23
P2.1, A9
22
P2.0, A8
21
44-Pin PLCC (W78E365P)
P
1
.
4
6543
7
P1.5
8
P1.6
9
P1.7
10
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
11
12
13
14
15
16
17
P
3
.
6
,
/
W
R
P
1
.
3
P
3
.
7
,
/
R
D
T
2
E
X
,
P
P
1
1
.
.
1
2
X
X
T
T
A
A
L
L
2
1
/
I
A
N
T
D
T
2
0
3
,
,
,
P
P
P
1
V
0
4
.
D
.
.
0
D
0
2
2 1 44 43 42
V
P
P
P
S
2
2
4
S
.
.
.
0
1
0
,
,
A
A
8
9
44-Pin QFP (W78E365F)
/
T
I
2
N
E
T
A
A
A
D
D
D
3
1
2
,
,
,
P
P
P
0
0
0
.
.
.
3
1
2
40
41
39
P0.4, AD4
38
P0.5, AD5
37
P0.6, AD6
36
P0.7, AD7
35
EA
34
P4.1
33
ALE
32
PSEN
31
P2.7, A15
30
P2.6, A14
29
P2.5, A13
2827262524232221201918
P
P
P
2
2
2
.
.
.
3
4
2
,
,
,
A
A
A
1
1
1
1
2
0
P1.5
P1.6
P1.7
RST
RXD, P3.0
INT2, P4.3
TXD, P3.1
INT0, P3.2
INT1, P3.3
T0, P3.4
T1, P3.5
P
P
1
1
.
.
3
4
43 42 41
44
1
2
3
4
5
6
7
8
9
10
11
12
P
P
3
3
.
.
6
7
,
,
/
/
W
R
R
D
X
2
,
,
P
P
P
1
1
1
.
.
.
1
0
2
403938 37 36 35
V
X
X
S
T
T
S
A
A
L
L
2
1
T
3
,
P
V
4
D
.
D
2
P
P
2
4
.
.
0
0
,
A
8
A
A
A
A
D
D
D
D
3
1
2
0
,
,
,
,
P
P
P
P
0
0
0
0
.
.
.
.
3
1
2
0
34
33
P0.4, AD4
32
P0.5, AD5
31
P0.6, AD6
30
P0.7, AD7
29
EA
28
P4.1
27
ALE
26
PSEN
25
P2.7, A15
24
P2.6, A14
23
P2.5, A13
22212019181716151413
P
P
P
P
2
2
2
2
.
.
.
.
3
1
4
2
,
,
,
,
A
A
A
A
1
9
1
1
1
2
0
Publication Release Date: April 20, 2005
- 3 - Revision A5
4. PIN DESCRIPTION
A
SYMBOL TYPE DESCRIPTIONS
EXTERNAL ACCESS ENABLE: This pin forces the processor to execute the
external ROM. The ROM address and data will not be presented on the bus if
E
I
the
pin is high.
EA
W78E365
PROGRAM STORE ENABLE:
PSEN
ALE O H
RST I L
XTAL1 I
XTAL2 O CRYSTAL 2: This is the crystal oscillator output. It is the inversion of XTAL1.
VSS I GROUND: ground potential.
VDD I POWER SUPPLY: Supply voltage for operation.
P0.0 − P0.7
P1.0 − P1.7
P2.0 − P2.7
P3.0 − P3.7
P4.0 − P4.7
O H
I/O D PORT 0: Function is the same as that of standard 8052.
I/O H PORT 1: Function is the same as that of standard 8052.
I/O H
I/O H PORT 3: Function is the same as that of the standard 8052.
I/O H
Port 0 address/data bus. When internal ROM access is performed, no PSEN
strobe signal outputs originate from this pin.
ADDRESS LATCH ENABLE: ALE is used to enable the address latch that
separates the address from the data on Port 0. ALE runs at 1/6th of the
oscillator frequency.
RESET: A high on this pin for two machine cycles while the oscillator is
running resets the device.
CRYSTAL 1: This is the crystal oscillator input. This pin may be driven by an
external clock.
PORT 2: Port 2 is a bi-directional I/O port with internal pull-ups. This port also
provides the upper address bits for accesses to external memory. The P2.6
and P2.7 also provide the alternate function
from LD flash.
PORT 4: A bi-directional I/O. The P4.3 also provides the alternate function
REBOOT which is H/W reboot from LD flash.
PSEN enables the external ROM data in the
REBOOT
which is H/W reboot
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
- 4 -
5. BLOCK DIAGRAM
W78E365
P1.0
P1.7
P3.0
P3.7
P4.0
P4.3
Port
1
Port
Port
Port 1
Latch
ACC
Interrupt
Timer
2
Timer
0
Timer
1
UART
3
4
Port 3
Latch
Port 4
Latch
XTAL1
Oscillator
PSW
Instruction
Decoder
&
Sequencer
Bus & Clock
Controller
ALE
ALU
256+1K bytes
Reset Block
PSEN
T2T1
SFR RAM
Address
RAM & SFR
B
Stack
Pointer
Power control
Temp Reg.
Incrementor
Addr. Reg.
VssVCCRSTXTAL2
Port 0
Latch
DPTR
PC
64KB
Flash APROM
4KB
Flash LDROM
Port 2
Latch
Port
0
Port
2
P0.0
P0.7
P2.0
P2.7
Publication Release Date: April 20, 2005
- 5 - Revision A5
W78E365
6. FUNCTIONAL DESCRIPTION
The W78E365 architecture consists of a core controller surrounded by various registers, four general
purpose I/O ports, one special purpose programmable 4-bits I/O port, 256+1K bytes of RAM, three
timer/counters, a serial port. The processor supports 111 different opcodes and references both a 64K
program address space and a 64K data storage space.
6.1 RAM
The internal data RAM in the W78E365 is 256+1K bytes. It is divided into two banks: 256 bytes of
scratchpad RAM and 1K bytes of AUX-RAM. These RAMs are addressed by different ways.
• RAM 0H − 7FH can be addressed directly and indirectly as the same as in 8051. Address pointers
are R0 and R1 of the selected register bank.
• RAM 80H − FFH can only be addressed indirectly as the same as in 8051. Address pointers are R0,
R1 of the selected registers bank.
• AUX-RAM 0H − 3FFH is addressed indirectly as the same way to access external data memory with
the MOVX instruction. Address pointer are R0 and R1 of the selected register bank and DPTR
register. An access to external data memory locations higher than 3FFH will be performed with the
MOVX instruction in the same way as in the 8051. The AUX-RAM is enable after a reset. Setting the
bit 4 in CHPCON register will enable the access to AUX-RAM. When executing from internal
program memory, an access to AUX-RAM will not affect the Ports P0, P2,
WR and RD .
Example:
CHPENR REG F6H
CHPCON REG BFH
XRAMAH REG A1H
MOV CHPENR , #87H
MOV CHPENR, #59H
ORL CHPCON, #00010000B ; enable AUX-RAM
MOV CHPENR, #00H
MOV XRAMAH, #01H ; internal high address
MOV R0, #23H
MOV A, #55H
MOVX @R0, A ; Write 55h data to 0123h AUX-RAM address.
MOV XRAMAH, #02H
MOV R1, #FFH ; Read data from 02FFh AUX-RAM address.
MOVX A, @R1
MOV DPTR, #0134H
MOV A, #78H
MOVX @DPTR, A ; Write 78h data to 0134h AUX-RAM address.
MOV DPTR, #7FFFH
MOVX A, @DPRT ; Read data from the external 7FFFh address SRAM
- 6 -
W78E365
6.2 Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0,
TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide
control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H
and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1
are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by
the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or
as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating
modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload
mode is the same as that of Timers 0 and 1.
6.2.1 Timer 2 Output
If set T2OE (T2MOD.1) bit and clear C/T2 (T2CON.1) bit at auto-reload mode, P1.0 will be toggled
once overflow.
TIMER 2 Mode
Bit: 7 6 5 4 3 2 1 0
T2OE
Mnemonic: T2MOD Address: C9H
T2OE: Enable this bit to toggle P1.0 pin while Timer2 has been overflowed.
6.3 Clock
The W78E365 is designed with either a crystal oscillator or an external clock. Internally, the clock is
divided by two before it is used by default. This makes the W78E365 relatively insensitive to duty
cycle variations in the clock.
6.3.1 Crystal Oscillator
The W78E365 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be
connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each
pin to ground.
6.3.2 External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The
XTAL1 input is a CMOS-type input, as required by the crystal oscillator.
6.4 Power Management
6.4.1 Idle Mode
Setting the IDL bit in the PCON register enters the idle mode. In the idle mode, the internal clock to the
processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor
will exit idle mode when either an interrupt or a reset occurs.
Publication Release Date: April 20, 2005
- 7 - Revision A5
W78E365
6.4.2 Power-down Mode
When the PD bit in the PCON register is set, the processor enters the power-down mode. In this mode
all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a hardware
reset or external interrupts
INT0 to
6.4.3 Reduce EMI Emission
The W78E365 allows user to diminish the gain of on-chip oscillator amplifier by using programmer to
clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must be
taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect the
external crystal operating improperly at high frequency. The value of C1 and C2 may need some
adjustment while running at lower gain.
ALE Off Function
Auxiliary Register
Bit: 7 6 5 4 3 2 1 0
- - - - - - - ALEOFF
ALEOFF: Set this bit to disable ALE output.
INT1
when enabled and set to level triggered.
Mnemonic: AUXR Address: 8EH
6.5 Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E365 is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
6.5.1 W78E365 Special Function Registers (SFRs) and Reset Values
F8
F0
E8
E0
D8
D0
C8
C0
+B
00000000
+ACC
00000000
+P4
11111111
+PSW
00000000
+T2CON
00000000
+XICON
00000000
PWMP
00000000
T2MOD
00000000
PWM0
00000000
RCAP2L
00000000
P4CONA
00000000
PWM1
00000000
RCAP2H
00000000
P4CONB
00000000
PWMCON1
00000000
TL2
00000000
SFRAL
00000000
PWM2
00000000
TH2
00000000
SFRAH
00000000
CHPENR
00000000
PWM3
00000000
PWMCON2
00000000
SFRFD
00000000
PWM4
00000000
SFRCN
00000000
- 8 -
Continued
B8
B0
A8
A0
98
90
88
80
Notes:
1. The SFRs marked with a plus sign(+) are both byte- and bit-addressable.
2. The text of SFR with bold type characters are extension function registers.
+IP
00000000
+P3
00000000
+IE
00000000
+P2
11111111
+SCON
00000000
+P1
11111111
+TCON
00000000
+P0
11111111
XRAMAH
00000000
SBUF
xxxxxxxx
TMOD
00000000
SP
00000111
P43AL
00000000
P42AL
00000000
TL0
00000000
DPL
00000000
P41AL
00000000
TL1
00000000
DPH
00000000
TH0
00000000
P40AL
00000000
P43AH
00000000
P42AH
00000000
P41AH
00000000
TH1
00000000
P40AH
00000000
W78E365
CHPCON
0xx00000
P4CSIN
00000000
AUXR
00000000
POR
00000000
WDTC
00000000
PCON
00110000
6.6 Port 4
Port 4, address D8H, is a 8-bit multipurpose programmable I/O port. Each bit can be configured
individually by software. The Port 4 has four different operation modes.
Mode 0: P4.0
Mode 1: P4.0
addresses. These signals can be used as chip-select signals for external peripherals.
Mode 2: P4.0
addresses. These signals can be used as chip-select signals for external peripherals.
Mode 3: P4.0
specified addresses. These signals can be used as chip-select signals for external
peripherals.
When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range
depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH
and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the
control bits to configure the Port 4 operation mode.
−P4.3 is a bi-directional I/O port which is same as port 1. P4.2 and P4.3 also serve as
external interrupt
−P4.3 are read strobe signals that are synchronized with
PSEN
and
INT2
if enabled.
signal at specified
RD
−P4.3 are write strobe signals that are synchronized with WR signal at specified
−P4.3 are read/write strobe signals that are synchronized with
or WRsignal at
RD
Publication Release Date: April 20, 2005
- 9 - Revision A5
W78E365
6.6.1 Port Options Register
Bit: 7 6 5 4 3 2 1 0
- - - - - - - P0UP
Mnemonic: POR Address: 86H
P0UP: Enable Port 0 weak up. The pins of Port 0 can be configured with either the open drain or
standard port with internal pull-up. By the default, Port 0 is an open drain bi-directional I/O port. When
the P0UP bit in the POR register is set, the pins of port 0 will perform a bi-directional I/O port with
internal pull-up that is structurally the same Port2.
6.6.2
Two additional external interrupts, INT2 and INT3 , whose functions are similar to those of external
interrupt 0 and 1 in the standard 80C52. The functions/status of these interrupts are
determined/shown by the bits in the XICON (External Interrupt Control) register. The XICON register is
bit-addressable but is not a standard register in the standard 80C52. Its address is at 0C0H. To
set/clear bits in the XICON register, one can use the "SETB (
"SETB 0C2H" sets the EX2 bit of XICON.
XICON - external interrupt control (C0H)
PX3 EX3 IE3 IT3 PX2 EX2 IE2 IT2
PX3: External interrupt 3 priority high if set
EX3: External interrupt 3 enable if set
IE3: If IT3 = 1, IE3 is set/cleared automatically by hardware when interrupt is detected/serviced
IT3: External interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software
PX2: External interrupt 2 priority high if set
EX2: External interrupt 2 enable if set
IE2: If IT2 = 1, IE2 is set/cleared automatically by hardware when interrupt is detected/serviced
IT2: External interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software
INT2
/ INT3
) bit" instruction. For example,
CLR
- 10 -
Eight-source interrupt information:
A
W78E365
INTERRUPT SOURCE
External Interrupt 0 03H 0 (highest) IE.0 TCON.0
Timer/Counter 0 0BH 1 IE.1 -
External Interrupt 1 13H 2 IE.2 TCON.2
Timer/Counter 1 1BH 3 IE.3 -
Serial Port 23H 4 IE.4 -
Timer/Counter 2 2BH 5 IE.5 -
External Interrupt 2 33H 6 XICON.2 XICON.0
External Interrupt 3 3BH 7 (lowest) XICON.6 XICON.3
VECTOR
ADDRESS
POLLING SEQUENCE
WITHIN PRIORITY
LEVEL
ENABLE
REQUIRED
SETTINGS
INTERRUPT TYPE
EDGE/LEVEL
P4CONB (C3H)
BIT NAME FUNCTION
7, 6 P43FUN1
P43FUN0
5, 4 P43CMP1
P43CMP0
3, 2 P42FUN1
P42FUN0
1, 0 P42CMP1
P42CMP0
00: Mode 0. P4.3 is a general purpose I/O port which is the same as Port1.
01: Mode 1. P4.3 is a Read Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
10: Mode 2. P4.3 is a Write Strobe signal for chip select purpose. The address
range depends on the SFR P43AH, P43AL, P43CMP1 and P43CMP0.
11: Mode 3. P4.3 is a Read/Write Strobe signal for chip select purpose. The
address range depends on the SFR P43AH, P43AL, P43CMP1, and
P43CMP0.
Chip-select signals address comparison:
00: Compare the full address (16 bits length) with the base address register
P43AH, P43AL.
01: Compare the 15 high bits (A15
register P43AH, P43AL.
10: Compare the 14 high bits (A15
register P43AH, P43AL.
11: Compare the 8 high bits (A15
register P43AH, P43AL.
The P4.2 function control bits which are the similar definition as P43FUN1,
P43FUN0.
The P4.2 address comparator length control bits which are the similar definition
as P43CMP1, P43CMP0.
−A1) of address bus with the base address
−A2) of address bus with the base address
−
8) of address bus with the base address
Publication Release Date: April 20, 2005
- 11 - Revision A5
W78E365
P4CONA (C2H)
BIT NAME FUNCTION
7, 6
5, 4
3, 2
1, 0
P4CSIN (AEH)
BIT NAME FUNCTION
P41FUN1
P41FUN0
P41CMP1
P41CMP0
P40FUN1
P40FUN0
P40CMP1
P40CMP0
7 P43CSINV
6 P42CSINV The similarity definition as P43SINV.
5 P41CSINV The similarity definition as P43SINV.
4 P40CSINV The similarity definition as P43SINV.
3 - Reserve
2 - Reserve
1 - 0
0 - 0
6.6.3 Port 4 Base Address Registers
P40AH, P40AL:
The Base address register for comparator of P4.0. P40AH contains the high-order byte of address,
P40AL contains the low-order byte of address.
The P4.1 function control bits which are the similar definition as P43FUN1,
P43FUN0.
The P4.1 address comparator length control bits which are the similar definition
as P43CMP1, P43CMP0.
The P4.0 function control bits which are the similar definition as P43FUN1,
P43FUN0.
The P4.0 address comparator length control bits which are the similar definition
as P43CMP1, P43CMP0.
The active polarity of P4.3 when pin P4.3 is defined as read and/or write strobe
signal.
= 1: P4.3 is active high when pin P4.3 is defined as read and/or write strobe signal.
= 0: P4.3 is active low when pin P4.3 is defined as read and/or write strobe signal.
P41AH, P41AL:
The Base address register for comparator of P4.1. P41AH contains the high-order byte of address,
P41AL contains the low-order byte of address.
P42AH, P42AL:
The Base address register for comparator of P4.2. P42AH contains the high-order byte of address,
P42AL contains the low-order byte of address.
P43AH, P43AL:
The Base address register for comparator of P4.3. P43AH contains the high-order byte of address,
P43AL contains the low-order byte of address.
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