White Electronic Designs WED9LC6416V2012BI, WED9LC6416V2012BC, WED9LC6416V2010BI, WED9LC6416V2010BC, WED9LC6416V1612BI Datasheet
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WED9LC6416V
128Kx32 SSRAM/4Mx32 SDRAM
Advanced*
External Memory Solution for Texas Instruments TMS320C6000 DSP
FEATURES
■ Clock speeds:
• SSRAM: 200, 166,150, and 133 MHz
• SDRAMs: 125 and 100 MHz
■ DSP Memory Solution
• Texas Instruments TMS320C6201
• Texas Instruments TMS320C6701
■ Packaging:
• 153 pin BGA, JEDEC MO-163
■ 3.3V Operating supply voltage
■ Direct control interface to both the SSRAM and SDRAM ports
on the “C6x”
■ Common address and databus
■ 65% space savings vs. monolithic solution
■ Reduced system inductance and capacitance
DESCRIPTION
The WED9LC6416VxxBC is a 3.3V, 128K x 32 Synchronous
Pipeline SRAM and a 4Mx32 Synchronous DRAM array constructed with one 128K x 32 SBSRAM and two 4Mx16 SDRAM die
mounted on a multilayer laminate substrate. The device is
packaged in a 153 lead, 14mm by 22mm, BGA.
The WED9LC6416VxxBC provides a total memory solution for the
Texas Instruments TMS320C6201 and the TMS320C6701 DSPs
The Synchronous Pipeline SRAM is available with clock speeds
of 200, 166,150, and 133 MHz, allowing the user to develop a fast
external memory for the SSRAM interface port .
The SDRAM is available in clock speeds of 125 and 100 MHz,
allowing the user to develop a fast external memory for the
SDRAM interface port .
The WED9LC6416V is available in both commercial and industrial
temperature ranges.
*This data sheet describes a product that may or may not be under development and
is subject to change or cancellation without notice.
FIG. 1 PIN CONFIGURATION
TOP VIEW
12 3456 789
A DQ19 DQ23 VCC VSS VSS VSS VCC DQ24 DQ28 A
B DQ18 DQ22 VCC VSS SDCE VSS VCC DQ25 DQ29 B
C VCCQ VCCQ VCC SDWE SDA10 NC VCC VCCQ VCCQ C
D DQ17 DQ21 VCC VSS VSS VSS VCC DQ26 DQ30 D
E DQ16 DQ20 VCC VSS SDCLK VSS VCC DQ27 DQ31 E
F VCCQ VCCQ VCC VSS VSS VSS VCC VCCQ VCCQ F
G NC NC NC SDRAS SDCAS VSS A2 A4 A5 G
H NC NC A8 VSS VSS NC A1 A3 A10 H
J A6 A7 A9 VSS VSS NC A0 A11 A12 J
K NC / A17 NC / A18 NC / A19 VSS VSS NC NC A13 A14 K
L NC NC NC BWE2 BWE3 NC NC A15 A16 L
M VCCQ VCCQ VCC BWE0 BWE1 NC VCC VCCQ VCCQ M
N DQ12 DQ11 VCC VSS VSS VSS VCC DQ4 DQ0 N
P DQ13 DQ10 VCC VSS SSCLK VSS VCC DQ5 DQ1 P
R VCCQ VCCQ VCC VSS VSS VSS VCC VCCQ VCCQ R
T DQ14 DQ9 VCC SSADC SSWE NC VCC DQ6 DQ2 T
15 DQ8 VCC SSOE SSCE NC VCC DQ7 DQ3 U
U DQ
12 3456 789
PIN DESCRIPTION
A0-16 Address Bus
DQ0-31 Data Bus
SSCLK SSRAM Clock
SSADC SSRAM Address Status Control
SSWE SSRAM Write Enable
SSOE SSRAM Output Enable
SDCLK SDRAM Clock
SDRAS SDRAM Row Address Strobe
SDCAS SDRAM Column Address Strobe
SDWE SDRAM Write Enable
SDA10 SDRAM Address 10/auto precharge
0-3 SSRAM Byte Write Enables
BWE
SSCE Chip Enable SSRAM Device
SDCE Chip Enable SDRAM Device
VCC Power Supply pins, 3.3V
CCQ Data Bus Power Supply pins,
V
VSS Ground
NC No Connect
SDRAM SDQM 0 - 3
3.3V (2.5V future)
January 20001
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WED9LC6416V
FIG. 2 BLOCK DIAGRAM
A
SSWE
BWE
BWE
BWE
BWE
SSCE
SSOE
SSADC
SSCLK
10
SDA
SDCE
SDRAS
SDCAS
SDWE
SDCLK
0
1
2
3
0-16
A
0
A
0
A
1
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
A
15
A
16
BWE
BW
BW
BW
BW
CE
OE
ADSC
DQ
DQ
1
2
3
4
2
DQ
DQ
9-16
17-24
25-32
DQ
0-7
1-8
DQ
8-15
DQ
16-23
DQ
24-31
CLK
DQ
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
11
A10/AP
A
12
BA
0
A
13
BA
1
LDQM
UDQM
CS
RAS
CAS
WE
CLK
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A
11
A10/AP
A
12
BA
0
A
13
BA
1
LDQM
UDQM
CS
RAS
CAS
WE
CLK
DQ
DQ
DQ
DQ
8-15
8-15
DQ
0-7
0-7
DQ
8-15
DQ
16-23
0-7
DQ
24-31
0-31
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January 2001
WED9LC6416V
OUTPUT FUNCTIONAL DESCRIPTIONS
Symbol Type Signal Polarity Function
SSCLK Input Pulse Positive Edge The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
SSADS
SSOE Input Pulse Active Low
SSWE
SSCE Input Pulse Active Low SSCE disable or enable SSRAM device operation.
SDCLK Input Pulse Positive Edge The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
SDCE Input Pulse Active Low SDCE disable or enable device operation by masking or enabling all inputs except SDCLK and BWE0-3.
SDRAS
SDCAS Input Pulse Active Low
SDWE
0-16,
A
SDA10 rising clock edge. In addition to the row address, SDA10 is used to invoke Autoprecharge operation at the
DQ
BWE
Input Level —
Input
0-31
Output
0-3 Input Pulse
Level — Data Input/Output are multiplexed on the same pins.
When sampled at the positive rising edge of the clock, SSADS, SSOE, and SSWE define the operation
to be executed by the SSRAM.
When sampled at the positive rising edge of the clock, SDCAS, SDRAS, and SDWE define the operation
to be executed by the SDRAM.
Address bus for SSRAM and SDRAM
0 and A1 are the burst address inputs for the SSRAM
A
During a Bank Active command cycle, A
0-11, SDA10 defines the row address (RA0-10) when sampled at the
rising clock edge.
During a Read or Write command cycle, A0-7 defines the column address (CA0-7) when sampled at the
end of the Burst Read or Write Cycle. If SDA10 is high, autoprecharge is selected and A12 and A13 define
the bank to be precharged. If SDA10 is low, autoprecharge is disabled.
During a Precharge command cycle, SDA
10 is used in conjunction with A12 and A13 to control which bank(s)
to precharge. If SDA10 is high, all banks will be precharged regardless of the state of A12 and A13. If
SDA10 is low, then A12 and A13 are used to define which bank to precharge.
0-3 perform the byte write enable function for the SSRAM and DQM function for the SDRAM. BWE0
BWE
is associated with DQ0-7, BWE1 with DQ8-15, BWE2 with DQ16-23 and BWE3 with DQ24-31.
Vcc, Vss Supply Power and ground for the input buffers and the core logic.
CCQ Supply Data base power supply pins, 3.3V (2.5V future).
V
January 20001
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WED9LC6416V
ABSOLUTE MAXIMUM RATINGS
Voltage on Vcc Relative to Vss -0.5V to +4.6V
Vin (DQx) -0.5V to Vcc +0.5V
Storage Temperature (BGA) -55°C to +125°C
Junction Temperature +175°C
Short Circuit Output Current 100 mA
*Stress greater than those listed under "Absolute Maximum Ratings" may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions greater than those indicated in operational
sections of this specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING CONDITIONS
(VCC = 3.3V -5% / +10% unless otherwise noted;
0°C ≤ T
A ≤ 70°C, Commercial; -40°C ≤ TA ≤ 85°C, Industrial)
Parameter Symbol Min Max Units
Supply Voltage (1) VCC 3.135 3.6 V
Input High Voltage (1,2) VIH 2.0 VCC +0.3 V
Input Low Voltage (1,2) VIL -0.3 0.8 V
Input Leakage Current IL
0 ≤ VIN ≤ Vcc
Output Leakage (Output Disabled) ILo -10 10 µA
0 ≤ VIN ≤ Vcc
Output High (IOH = -4mA) (1) VOH 2.4 — V
Output Low (I
OL = 8mA) (1) VOL — 0.4 V
I -10 10 µA
NOTES:
1. All voltages referenced to Vss (GND).
2. Overshoot: V
IH ≤ +6.0V for t ≤ tKC/2
Underershoot: VIL ≥ -2.0V for t ≤ tKC/2
DC ELECTRICAL CHARACTERISTICS
(VCC = 3.3V -5% / +10% unless otherwise noted; 0°C ≤ TA ≤ 70°C, Commercial; -40°C ≤ TA ≤ 85°C, Industrial)
Description Conditions Symbol Frequency Typ Max Units
Power Supply Current:
Operating (1,2,3)
Power Supply Current
Operating (1,2,3)
Power Supply Current
Operating (1,2,3)
SSRAM Active / DRAM Auto Refresh Icc
SSRAM Active / DRAM Idle Icc
SDRAM Active / SSRAM Idle Icc
SSCE and SDCE ≤ Vcc -0.2V,
CMOS Standby All other inputs at Vss +0.2 ≤ V
IN or mA
1
2
3 100MHz 235 250 mA
I
SB1 20.0 40.0
VIN ≤ VCC -0.2V, Clk frequency = 0
TTL Standby
SSCE and SDCE ≤ V
All other inputs at V
IH min
IL max ≤ VIN or mA
SB2 30.0 55.0
I
VIN ≤ VCC -0.2V, Clk frequency = 0
Auto Refresh Icc
5 190 250 mA
NOTES:
1. I
CC (operating) is specified with no output current. ICC (operating) increases with faster cycle times and greater output loading.
2. "Device idle" means device is deselected (CE ≥ VIH) Clock is running at max frequency and Addresses are switching each cycle.
3. Typical values are measured at 3.3V, 25°C. ICC (operating) is specified at specified frequency.
133MHz 400 550
150MHz 450 580
166MHz 500 625
200MHz 550 700
133MHz 300 450
150MHz 350 480
166MHz 400 525
200MHz 450 585
83MHz 220 240
125MHz 255 280
mA
mA
BGA CAPACITANCE
Description Conditions Symbol Typ Max Units
Address Input Capacitance (1) TA = 25°C; f = 1MHz CI 58pF
Input/Output Capacitance (DQ) (1) TA = 25°C; f = 1MHz CO 810pF
Control Input Capacitance (1) TA = 25°C; f = 1MHz CA 58pF
Clock Input Capacitance (1) TA = 25°C; f = 1MHz CCK 46pF
NOTE:
1.This parameter is sampled.
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January 2001
WED9LC6416V
(VCC = 3.3V -5% / +10% unless otherwise noted; 0°C ≤ TA ≤ 70°C, Commercial; -40°C ≤ TA ≤ 85°C, Industrial)
SSRAM AC CHARACTERISTICS
Parameter Min Max Min Max Min Max Min Max Units
Clock Cycle Time tKHKH 5678ns
Clock HIGH Time tKLKH 1.6 2.4 2.6 2.8 ns
Clock LOW Time tKHKL 1.6 2.4 2.6 2.8 ns
Clock to output valid tKHQV 2.5 3.5 3.8 4.0 ns
Clock to output invalid tKHQX 1.5 1.5 1.5 1.5 ns
Clock to output on Low-Z tKQLZ 0000ns
Clock to output in High-Z tKQHZ 1.5 3 1.5 3.5 1.5 3.8 1.5 4.0 ns
Output Enable to output valid tOELQV 2.5 3.5 3.8 4.0 ns
Output Enable to output in Low-Z tOELZ 0000ns
Output Enable to output in High-Z tOEHZ 3.0 3.5 3.5 3.8 ns
Address, Control, Data-in Setup Time to Clock tS 1.5 1.5 1.5 1.5 ns
Address, Control, Data-in Hold Time to Clock t
Symbol 200MHz 166MHz 150MHz 133MHz
H 0.5 0.5 0.5 0.5 ns
January 20001
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WED9LC6416V
SSRAM OPERATION TRUTH TABLE
Operation Address Used SSCE SSADS SSWE SSOE DQ
Deselected Cycle, Power Down None H L X X High-Z
WRITE Cycle, Begin Burst External L L L X D
READ Cycle, Begin Burst External L L H L Q
READ Cycle, Begin Burst External L L H H High-Z
READ Cycle, Suspend Burst Current X H H L Q
READ Cycle, Suspend Burst Current X H H H High-Z
READ Cycle, Suspend Burst Current H H H L Q
READ Cycle, Suspend Burst Current H H H H High-Z
WRITE Cycle, Suspend Burst Current X H L X D
WRITE Cycle, Suspend Burst Current H H L X D
NOTE:
1. X means “don’t care”, H means logic HIGH. L means logic LOW.
2. All inputs except SSOE must meet setup and hold times around the rising edge (LOW to HIGH) of SSCLK.
3. Suspending burst generates wait cycle
4. For a write operation following a read operation, SSOE must be HIGH before the input data required setup time plus High-Z time for SSOE and staying HIGH
though out the input data hold time.
5. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
SSRAM PARTIAL TRUTH TABLE
Function SSWE BWE0 BWE1 BWE2 BWE3
READ H X X X X
WRITE one Byte (DQ0-7) L L H H H
WRITE all Bytes L L L L L
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January 2001
WED9LC6416V
)
)
)
FIG. 3 SSRAM READ TIMING
SSCLK
t
SSADS
SSCE
ADDR
SSOE
SSWE
DQ
FIG. 4 SSRAM WRITE TIMING
SSCLK
SSADS
SSCE
ADDR
t
KHKL
t
KHKH
S
t
S
t
S
A2 A3 A4
t
H
t
OELQV
t
KQLZ
t
KHKH
t
S
t
H
t
S
A1
t
H
t
KLKH
t
H
t
KHQX
t
KHQV
Q(A1) Q(A2) Q(A3) Q(A4)
t
KHKL
t
KLKH
A2 A3
t
H
A5A1
t
OEHQZ
Q(A5)
t
H
t
H
A4
A5
January 20001
SSOE
SSWE
DQ
D(A1)
t
S
t
S
D(A2)D(A3
t
H
t
H
D(A4
7
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KHGW X
D(A5
WED9LC6416V
(VCC = 3.3V -5% / +10% unless otherwise noted; 0°C ≤ TA ≤ 70°C, Commercial; -40°C ≤ TA ≤ 85°C, Industrial)
SDRAM AC CHARACTERISTICS
Parameter Min Max Min Max Min Max Units
Clock Cycle Time (1)
CL = 3 t
CL = 2 tCC 10 1000 12 1000 15 1000
Clock to valid Output delay (1,2) tSAC 678ns
Output Data Hold Time (2) tOH 33 3ns
Clock HIGH Pulse Width (3) tCH 33 3ns
Clock LOW Pulse Width (3) tCL 33 3ns
Input Setup Time (3) tSS 22 2ns
Input Hold Time (3) tSH 11 1ns
CLK to Output Low-Z (2) tSLZ 22 2ns
CLK to Output High-Z tSHZ 778ns
Row Active to Row Active Delay (4) tRRD 20 20 24 ns
RAS\ to CAS\ Delay (4) tRCD 20 20 24 ns
Row Precharge Time (4) tRP 20 20 24 ns
Row Active Time (4) tRAS 50 10,000 50 10,000 60 10,000 ns
Row Cycle Time - Operation (4) tRC 70 80 90 ns
Row Cycle Time - Auto Refresh (4,8) tRFC 70 80 90 ns
Last Data in to New Column Address Delay (5) tCDL 1 1 1 CLK
Last Data in to Row Precharge (5) tRDL 1 1 1 CLK
Last Data in to Burst Stop (5) tBDL 1 1 1 CLK
Column Address to Column Address Delay (6) tCCD 1.5 1.5 1.5 CLK
Number of Valid Output Data (7) 2 2 2
NOTES:
1.Parameters depend on programmed CAS latency.
2.If clock rise time is longer than 1ns (t
3.Assumed input rise and fall time = 1ns. If t
rise/2 -0.5)ns should be added to the parameter.
rise of tfall are longer than 1ns. [(trise = tfall)/2] - 1ns should be added to the parameter.
4.The minimum number of clock cycles required is detemined by dividing the minimum time required by the clock cycle time and then rounding up to the
next higher integer.
5.Minimum delay is required to complete write.
6.All devices allow every cycle column address changes.
7.In case of row precharge interrupt, auto precharge and read burst stop.
8.A new command may be given t
RFC after self-refresh exit.
Symbol 125MHz 100MHz 83MHz
CC 8 1000 10 1000 12 1000
12 1
ns
ea
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January 2001
WED9LC6416V
CLOCK FREQUENCY AND LATENCY PARAMETERS - 125MHz SDRAM
(Unit = number of clock)
Frequency CAS tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL
125MHz (8.0ns) 3 9 6 3 2 3 1 1 1
100MHz (10.0ns) 3 7 5 2 2 2 1 1 1
83MHz (12.0ns) 2 6 4 2 2 2 1 1 1
Latency
70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns
CLOCK FREQUENCY AND LATENCY PARAMETERS - 100MHz SDRAM
(Unit = number of clock)
Frequency CAS tRC tRAS tRP tRRD tRCD tCCD tCDL tRDL
100MHz (12.0ns) 3 7 5 2 2 2 1 1 1
83MHz (12.0ns) 2 6 5 2 2 2 1 1 1
Latency
70ns 50ns 20ns 20ns 20ns 10ns 10ns 10ns
REFRESH CYCLE PARAMETERS
Parameter Symbol Min Max Min Max Units
Refresh Period (1,2) tREF —64 — 64ms
NOTES:
1.4096 cycles
2.Any time that the Refresh Period has been exceeded, a minimum of two Auto (CBR) Refresh commands must be given to "wake-up" the device.
-10 -12
SDRAM COMMAND TRUTH TABLE
Function
Mode Register Set L L L L X OP CODE
Auto Refresh (CBR) L L L H X X X
Precharge
Bank Activate L L H H X BA Row Address 2
Write L H L L X BA L 2
Write with Auto Precharge L H L L X BA H 2
Read L H L L X BA L 2
Read with Auto Precharge L H L H X BA H 2
Burst Termination L H H L X X X 3
No Operation L H H H X X X
Device Deselect H X X X X X X
Data Write/Output Disable X X X X L X X 4
Data Mask/Output Disable X X X X H X X 4
NOTES:
1. All of the SDRAM operations are defined by states of SDCE\, SDWE\, SDRAS\, SDCAS\, and BWE
2. Bank Select (BA), if A
3. During a Burst Write cycle there is a zero clock delay, for a Burst Read cycle the delay is equal to the CAS latency.
4. The BWE has two functions for the data DQ Read and Write operations. During a Read cycle, when BWE goes high at a clock timing the data outputs are disabled
and become high impedance after a two clock delay. BWE also provides a data mask function for Write cycles. When it activates, the Write operation at the clock is
prohibited (zero clock latency).
January 20001
Single Bank L L H L X BA L 2
Precharge all Banks L L H L X X H
12 (BA0) and A13 (BA1) select between different banks.
SDCE SDRAS SDCAS SDWE BWE A12, A13 SDA10
0-3 at the positive rising edge of the clock.
9
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A
11-0
Notes
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