Vishay IRLL014, SiHLL014 Data Sheet

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IRLL014, SiHLL014

Vishay Siliconix

Power MOSFET

PRODUCT SUMMARY

VDS (V) 60

R

()V

DS(on)

Q

max. (nC) 8.4

g

Q

(nC) 3.5

gs

Q

(nC) 6.0

gd

Configuration Single

= 5.0 V 0.20

GS

D

FEATURES

• Surface mount

• Available in tape and reel

• Dynamic dV/dt rating

• Logic-level gate drive

•R

DS(on)

• Fast switching

• Ease of paralleling

• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912

DESCRIPTION

SOT-223

D

Marking code: LA

G

S

D

G

S

N-Channel MOSFET

Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
cost-effectiveness.
The SOT-223 package is designed for surface-mounting
using vapor phase, infrared, or wave soldering techniques.
Its unique package design allows for easy automatic
pick-and-place as with other SOT or SOIC packages but
has the added advantage of improved thermal performance
due to an enlarged tab for heatsinking. Power dissipation of
greater than 1.25 W is possible in a typical surface mount
application.

ORDERING INFORMATION

Package SOT-223
Lead (Pb)-free and Halogen-free SiHLL014TR-GE3
Lead (Pb)-free IRLL014TRPbF

Note

a. See device orientation.

specified at VGS = 4 V and 5 V

Available

a

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT

Drain-Source Voltage V
Gate-Source Voltage V

= 25 °C

T

Continuous Drain Current V

Pulsed Drain Current

a

at 10 V

GS

C

= 100 °C 1.7

C

DS

± 10

GS

I

D

IDM 22
Linear Derating Factor 0.025
Linear Derating Factor (PCB mount)
Single Pulse Avalanche Energy
Repetitive Avalanche Current
Repetitive Avalanche Energy
Maximum Power Dissipation T
Maximum Power Dissipation (PCB mount)
Peak Diode Recovery dV/dt
Operating Junction and Storage Temperature Range T
Soldering Recommendations (Peak temperature)

e

b

a

a

= 25 °C

e

c

d

C

TA = 25 °C 2.0

for 10 s 300

E

AS

I

AR

E

AR

P

D

dV/dt 4.5 V/ns

, T

J

stg

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).

= 25 V, starting TJ = 25 °C, L = 16 mH, Rg = 25 , IAS = 2.7 A (see fig. 12).

b. V

DD

c. I

 10 A, dI/dt  90 A/μs, VDD  VDS, TJ  150 °C.

SD

d. 1.6 mm from case.
e. When mounted on 1" square PCB (FR-4 or G-10 material).

S16-0015-Rev. F, 18-Jan-16

1

For technical questions, contact: [e-mail]

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

60

2.7

0.017
100 mJ

2.7 A

0.31 mJ

3.1

-55 to +150

Document Number: 91319

V

AT

W/°C

W

°C

IRLL014, SiHLL014

D

S

G

www.vishay.com

THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT

Maximum Junction-to-Ambient 
(PCB mount)

a

Maximum Junction-to-Case (Drain) R

R

thJA

thJC

--60

--40

Note

a. When mounted on 1" square PCB (FR-4 or G-10 material).

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT

Static

Drain-Source Breakdown Voltage V

V

Temperature Coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.073 - V/°C

DS

Gate-Source Threshold Voltage V

Gate-Source Leakage I

Zero Gate Voltage Drain Current I

Drain-Source On-State Resistance R

Forward Transconductance g

DS

GS(th)

V

GSS

DSS

V

DS(on)

fs

V

Dynamic

Input Capacitance C

Reverse Transfer Capacitance C

Total Gate Charge Q

Gate-Drain Charge Q

Turn-On Delay Time t

Rise Time t

Turn-Off Delay Time t

Fall Time t

Internal Drain Inductance L

Internal Source Inductance L

iss

- 170 -

oss

-42-

rss

g

--3.5

gs

--6.0

gd

d(on)

r

-17-

d(off)

-26-

f

D

V

Between lead,
6 mm (0.25") from
package and center of

S

die contact

Drain-Source Body Diode Characteristics

Continuous Source-Drain Diode Current I

Pulsed Diode Forward Current

a

Body Diode Voltage V

Body Diode Reverse Recovery Time t

Body Diode Reverse Recovery Charge Q

Forward Turn-On Time t

S

I

SM

SD

rr

rr

on

MOSFET symbol
showing the 
integral reverse
p - n junction diode

TJ = 25 °C, IF = 10 A, dI/dt = 100 A/μs

Notes

a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11).
b. Pulse width  300 μs; duty cycle  2 %.

VGS = 0 V, ID = 250 μA 60 - - V

VDS = VGS, ID = 250 μA 1.0 - 2.0 V

= ± 10 V - - ± 100 nA

GS

VDS = 60 V, VGS = 0 V - - 25

= 48 V, VGS = 0 V, TJ = 125 °C - - 250

V

DS

= 5.0 V ID = 1.6 A

GS

= 4.0 V ID = 1.4 A

GS

b

b

VDS = 25 V, ID = 1.6 A 3.2 - - S

VGS = 0 V,

V

= 25 V,

DS

f = 1.0 MHz, see fig. 5

= 10 A, VDS = 48 V,

I

= 5.0 V

GS

V

R

= 12 , RD = 2.8 , see fig. 10

g

TJ = 25 °C, IS = 2.7 A, VGS = 0 V

D

see fig. 6 and 13

= 30 V, ID = 10 A,

DD

b

b

D

G

S

b

b

Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)

Vishay Siliconix

°C/W

- - 0.20

- - 0.28

- 400 -

--8.4

-9.3-

- 110 -

-4.0-

-6.0-

--2.7

--22

--1.6V

- 65 130 ns

-0.330.65μC

μA



pFOutput Capacitance C

nC Gate-Source Charge Q

ns

nH

A

S16-0015-Rev. F, 18-Jan-16

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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2

Document Number: 91319

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20 µs Pulse Width
T

C

= 25 °C

VDS, Drain-to-Source Voltage (V)

I

D

, Drain Current (A)

10

0

10

1

10

-1

2.25 V

Bottom

Top

V

GS

7.5 V

5.0 V

4.0 V

3.5 V

3.0 V

2.75 V

2.5 V

10

-2

10

-1

10

1

10

0

V

20 µs Pulse Width
T

C

= 150 °C

VDS, Drain-to-Source Voltage (V)

I

D

, Drain C

u

rrent (A)

10

0

10

1

10

-2

10

-1

2.25 V

Bottom

Top

GS

7.5 V

5.0 V

4.0 V

3.5 V

3.0 V

2.75 V

2.5 V

10

-1

10

1

10

0

20 µs Pulse Width
V

DS

= 25 V

10

1

10

-2

10

-3

I

D

, Drain Current (A)

V

GS

,

Gate-to-Source Voltage (V)

2.5 3 3.5 4 4.5 5

2

25 °C

150 °C

10

-1

10

0

I

D

= 10 A

V

GS

= 10 V

3.0

0.0

0.5

1.0

1.5

2.0

2.5

T

J

,

Junction Temperature (°C)

R

DS(on)

, Drain-to-Source On Resistance

(Normalized)

- 60 - 40 - 20 0 20 40 60 80 100 120 140 160

QG, Total Gate Charge (nC)

V

GS

, Gate-to-Source Voltage (V)

10

6

6

4

0

2

0

2

10

86

4

V

DS

= 30 V

V

DS

= 48 V

For test circuit
see figure 13

ID = 10 A

TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

IRLL014, SiHLL014

Vishay Siliconix

Fig. 1 - Typical Output Characteristics, TC = 25 °C

Fig. 2 - Typical Output Characteristics, T

= 150 °C

C

Fig. 4 - Normalized On-Resistance vs. Temperature

700

600

500

400

300

Capacitance (pF)

200

100

0

0

10

V

Drain-to-Source Voltage (V)

,

DS

V

= 0 V, f = 1 MHz

GS

= Cgs + Cgd, Cds Shorted

C

iss

= C

C

rss

gd

C

= Cds + C

oss

gd

C

iss

C

oss

C

rss

1

10

Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage

S16-0015-Rev. F, 18-Jan-16

Fig. 3 - Typical Transfer Characteristics

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

For technical questions, contact: [e-mail]

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage

3

Document Number: 91319

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VSD, Source-to-Drain Voltage (V)

I

SD

, Reverse Drain Current (A)

0.4

2.4

1.61.20.8

10

-1

10

0

10

1

TJ = 150 °C

T

J

= 25 °C

2.0

V

GS

= 0 V

VDS, Drain-to-Source Voltage (V)

I

D

, Drain Current (A)

TC = 25 °C
T

J

= 150 °C

Single Pulse

10

3

0.1

0.1

2

5

1

10

2

2

5

25

1

25

10

25

10

2

25

10

3

2

5

10

2

5

Operation in this area limited by R

DS(on)

100 µs

1 ms

10 ms

I

D

, Drain Current (A)

TC, Case Temperature (°C)

0.0

0.5

1.0

1.5

2.0

2.5

25 1501251007550

3.0

Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

R

D

V

GS

R

g

D.U.T.

10 V

+

-

V

DS

V

DD

V

DS

90 %

10 %

V

GS

t

d(on)

t

r

t

d(off)

t

f

Fig. 7 - Typical Source-Drain Diode Forward Voltage

IRLL014, SiHLL014

Vishay Siliconix

Fig. 10a - Switching Time Test Circuit

Fig. 8 - Maximum Safe Operating Area

Fig. 10b - Switching Time Waveforms

Fig. 9 - Maximum Drain Current vs. Case Temperature

S16-0015-Rev. F, 18-Jan-16

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

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Document Number: 91319

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R

g

I

AS

0.01 Ω

t

p

D.U.T

L

V

DS

+

-

V

DD

10 V

Var y t

p

to obtain

required I

AS

250

0

100

150

200

25 150

125

10075

50

Starting TJ, Junction Temperature (°C)

E

AS

, Single Pulse Avalanche Energy (mJ)

Bottom

To p

I

D

1.2 A

1.7 A

2.7 A

50

V

DD

= 25 V

2

10

IRLL014, SiHLL014

Vishay Siliconix

)

thJC

10

D = 0.50

0.20

0.10

0.05

1

0.02

0.01

-1

10

Thermal Response (Z

-2

10

-5

10

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

Single Pulse
(Thermal Response)

-4

10

P

DM

t

1

t

2

Notes:

1. Duty Factor, D = t

2. Peak Tj = PDM x Z

-3

10

-2

10

0.1 1 10

1

10

1/t2

+ T

thJC

C

2

10

3

t1, Rectangular Pulse Duration (s)

V

DS

t

p

V

DS

I

AS

V

DD

S16-0015-Rev. F, 18-Jan-16

Fig. 12a - Unclamped Inductive Test Circuit

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Fig. 12b - Unclamped Inductive Waveforms

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Document Number: 91319

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Q

GS

Q

GD

Q

G

V

G

Charge

V

GS

P.W.

Period

dI/dt

Diode recovery

dV/dt

Ripple ≤ 5 %

Body diode forward drop

Re-applied
voltage

Reverse
recovery
current

Body diode forward

current

V

GS

= 10 Va

I

SD

Driver gate drive

D.U.T. l

SD

waveform

D.U.T. V

DS

waveform

Inductor current

D =

P.W.

Period

+

-

+

+

+

-

-

-

Peak Diode Recovery dV/dt Test Circuit

V

DD

• dV/dt controlled by R

g

• Driver same type as D.U.T.

•

I

SD

controlled by duty factor “D”

• D.U.T. - device under test

D.U.T.

Circuit layout considerations

• Low stray inductance

• Ground plane

• Low leakage inductance

current transformer

R

g

Note

a. V

GS

= 5 V for logic level devices

V

DD

Current regulator

Same type as D.U.T.

0.2 µF

12 V

V

GS

IRLL014, SiHLL014

Vishay Siliconix

50 kΩ

0.3 µF

+

V

D.U.T.

3 mA

DS

-

I

G

Current sampling resistors

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

I

D

Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91319

S16-0015-Rev. F, 18-Jan-16

THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT

ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000

Fig. 14 - For N-Channel

.

6

For technical questions, contact: [e-mail]

Document Number: 91319

SOT-223 (HIGH VOLTAGE)

Package Information

Vishay Siliconix

3

B

B1

0.10 (0.004)

0.10 (0.004)

0.20 (0.008)

3 x B

0.10 (0.004)

H

D

3

A

4

3

E

1

2

e

e1

MILLIMETERS INCHES

DIM. MIN. MAX. MIN. MAX.

A 1.55 1.80 0.061 0.071

B 0.65 0.85 0.026 0.033

B1 2.95 3.15 0.116 0.124

C 0.25 0.35 0.010 0.014

D 6.30 6.70 0.248 0.264

E 3.30 3.70 0.130 0.146

e 2.30 BSC 0.0905 BSC

e1 4.60 BSC 0.181 BSC

H 6.71 7.29 0.264 0.287

L 0.91 - 0.036 -

L1 0.061 BSC 0.0024 BSC

θ - 10' - 10'

ECN: S-82109-Rev. A, 15-Sep-08
DWG: 5969

Notes

1. Dimensioning and tolerancing per ASME Y14.5M-1994.

2. Dimensions are shown in millimeters (inches).

3. Dimension do not include mold flash.

4. Outline conforms to JEDEC outline TO-261AA.

A

M

M

M

M

C

C B

M

M

C A

M

M

C B

C

L1

4 x L

θ

0.08 (0.003)

4 x C

Document Number: 91363 www.vishay.com
Revision: 15-Sep-08 1

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Revision: 13-Jun-16

1

Document Number: 91000