UTRON UT61256SC-15, UT61256LS-8, UT61256LS-15, UT61256LS-10, UT61256LS-12 Datasheet

UTRON

UT61256

Rev. 1.1

32K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80020
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

1



FEATURES



Fast access time : 8/10/12/15ns (max.)



Low operating power consumption:

80 mA (typical.)



Single5V power supply



All inputs and outputs are TTL compatible



Fully static operation



Three state outputs



Package : 28-pin 300 mil skinny PDIP

28-pin 300 mil SOJ
28-pin 330 mil SOP
28-pin 8mm×13.4 mm STSOP

FUNCTIONAL BLOCK DIAGRAM

COLUMN I/O

COLUMN DECODER

ROW

DECODER

I/O

CONTROL

LOGI C

CONTROL

A4

I/O1

VSS

VCC

WE

OE

CE

I/O8

.

.

.

.

.
.

. .

.

A3

A

12

A7

A6

A5

A8

A9 A2 A1 A0 A

11

.

.

.

.

.

.

MEMORY ARRAY

512 ROWS × 512 COLUMNS

A

10

A14

A13

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A14 Address Inputs

I/O1 - I/O8 Data Inputs/Outputs

CE

Chip Enable Input

WE

Write Enable Input

OE

Output Enable Input

VCC Power Supply
VSS Ground

GENERAL DESCRIPTION

The UT61256 is a 262,144-bit high speed CMOS
static random access memory organized as
32,768 words by 8 bits. It is fabricated using high
performance, high reliability CMOS technology.

The UT61256 is designed for high-speed system
application. It is particularly suited for use in high
speed and high density system applications.

The UT61256 operates from a signal 5V power
supply and all inputs and outputs are fully TTL
compatible

PIN CONFIGURATION

A12

A7

A6

A5

A4

A3

A2

A1

A0

I/O1

I/O2

Vcc

A8

A9

A11

A10

I/O8

I/O7

I/O6

I/O5

I/O4

I/O3

Vss

UT61256

PDIP/SOP/SOJ

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

17

16

15

20

19

18

22

23

24

25

26

27

21

CE

WE

OE

A13

A14

I/O4

A11

A9

A8

A13

I/O3

A10

A14

A12

A7

A6

A5

Vcc

I/O8

I/O7

I/O6

I/O5

Vss

I/O2

I/O1

A0

A1

A2

A4

A3

UT61256

STSOP

28

14

13

12

11

10

9

8

7

6

5

4

3

2

1

17

16

15

20

19

18

22

23

24

25

26

27

21

WE

OE

CE

UTRON

UT61256

Rev. 1.1

32K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80020
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

2



ABSOLUTE MAXIMUM RATINGS

*

PARAMETER SYMBOL RATING UNIT

Terminal Voltage with Respect to VSS V

TERM

-0.5 to +7.0 V

Operating Temperature TA 0 to +70

℃

Storage Temperature T

STG

-65 to +150

℃

Power Dissipation PD 1 W
DC Output Current I

OUT

50 mA

Soldering Temperature (under 10 sec) Tsolder 260

℃

*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a

stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections

of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device

reliability.

TRUTH TABLE

MODE

CE

OE

WE

I/O OPERATION SUPPLY CURRENT

Standby H X X High - Z ISB, ISB1

Output Disable L H H High - Z ICC

Read L L H D

OUT

I

CC

Write L X L DIN I

CC

Note: H = VIH, L=VIL, X = Don't care.

DC ELECTRICAL CHARACTERISTICS

(VCC = 5V±10%, TA = 0℃ to 70℃)

PARAMETER SYMBOL TEST CONDITION MIN. MAX. UNIT

Input High Voltage VIH 2.2 VCC+0.5 V
Input Low Voltage VIL -0.5 0.8 V
Input Leakage Current ILI

V

SS

≦VIN ≦VCC

- 1 1

µ

A

Output Leakage

Current

ILO

V

SS

≦V

I/O

≦V

CC

CE

=V

IH

or

OE

=V

IH

or

WE

= VIL

- 1 1

µ

A

Output High Voltage VOH IOH= - 4mA 2.4 - V
Output Low Voltage VOL IOL= 8mA - 0.4 V

- 8 - 190 mA

- 10 - 180 mA

- 12 - 160 mA

Operating Power

Supply Current

ICC

CE

= V

IL

,

I

I/O

= 0mA ,Cycle=Min.

- 15 - 140 mA

ISB

CE

=V

IH

- 30 mA

Standby Power
Supply Current

I

SB1

CE

≧

V

CC

-0.2V

- 5 mA

UTRON

UT61256

Rev. 1.1

32K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80020
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

3



CAPACITANCE

(TA=25℃, f=1.0MHz)

PARAMETER SYMBOL MIN. MAX UNIT

Input Capacitance C

IN

-

8 pF

Input/Output Capacitance C

I/O

-

10 pF

Note : These parameters are guaranteed by device characterization, but not production tested.

AC TEST CONDITIONS

Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 3ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF, IOH/IOL = -4mA/8mA

AC ELECTRICAL CHARACTERISTICS

(V

CC

= 5V±10%, TA = 0℃ to 70℃)

(1) READ CYCLE

PARAMETER

SYMBOL UT61256-8 UT61256-10 UT61256-12 UT61256-15 UNIT

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Read Cycle Time

tRC

8 - 10 - 12 - 15 - ns

Address Access Time

tAA

- 8 - 10 - 12 - 15 ns

Chip Enable Access Time

t

ACE

- 8 - 10 - 12 - 15 ns

Output Enable Access Time

tOE

- 4 - 5 - 6 - 7 ns

Chip Enable to Output in Low Z

t

CLZ*

2 - 2 - 3 - 4 - ns

Output Enable to Output in Low Z

t

OLZ*

0 - 0 - 0 - 0 - ns

Chip Disable to Output in High Z

t

CHZ*

- 4 - 5 - 6 - 7 ns

Output Disable to Output in High Z

t

OHZ*

- 4 - 5 - 6 - 7 ns

Output Hold from Address Change

tOH

3 - 3 - 3 - 3 - ns

(2) WRITE CYCLE
PARAMETER

SYMBOL UT61256-8 UT61256-10 UT61256-12 UT61256-15 UNIT

MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.

Write Cycle Time

tWC

8 - 10 - 12 - 15 - ns

Address Valid to End of Write

tAW

6.5 - 8 - 12 - 15 - ns

Chip Enable to End of Write

tCW

6.5 - 8 - 12 - 15 - ns

Address Set-up Time

tAS

0 - 0 - 0 - 0 - ns

Write Pulse Width

tWP

6.5 - 8 - 9 - 10 - ns

Write Recovery Time

tWR

0 - 0 - 0 - 0 - ns

Data to Write Time Overlap

tDW

5 - 6 - 7 - 8 - ns

Data Hold from End of Write Time

tDH

0 - 0 - 0 - 0 - ns

Output Active from End of Write

t

OW*

1.5 - 2 - 3 - 4 - ns

Write to Output in High Z

t

WHZ*

- 5 - 6 - 7 - 8 ns

*These parameters are guaranteed by device characterization, but not production tested.

UTRON

UT61256

Rev. 1.1

32K X 8 BIT HIGH SPEED CMOS SRAM

UTRON TECHNOLOGY INC. P80020
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

4



TIMING WAVEFORMS

READ CYCLE 1

(Address Controlled)

(1,2,4)

t

RC

Address

DOUT Data Valid

t

AA

t

OH

t

OH

READ CYCLE 2

(CE and

OE

Controlled)

(1,3,5,6)

D

OUT

Address

CE

OE

t

RC

t

AA

t

ACE

t

OE

t

CLZ

t

OLZ

High-z

t

OHZ

t

CHZ

Data valid

High-Z

t

OH

Notes :

1.

WE

is HIGH for read cycle.

2. Device is continuously selected

CE

=V

IL.

3. Address must be valid prior to or coincident with

CE

transition; otherwise t

AA

is the limiting parameter.

4.

OE

is LOW.

5. t

CLZ

, t

OLZ

, t

CHZ

and t

OHZ

are specified with CL = 5pF. Transition is measured ±500mV from steady state.

6. At any given temperature and voltage condition, t

CHZ

is less than t

CLZ

, t

OHZ

is less than t

OLZ.