UTRON UT61256CLS-8, UT61256CLS-15, UT61256CLS-12, UT61256CLS-10, UT61256CJC-15 Datasheet
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UTRON
UT61256C
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80031
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
FEATURES
Fast access time : 8/10/12/15 ns (max.)
Low operating power consumption :
80 mA (typical)
Single 5V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Package : 28-pin 300 mil SOJ
28-pin 8mm×13.4mm STSOP
FUNCTIONAL BLOCK DIAGRAM
DECODER
I/O DATA
CIRCUIT
CONTROL
CIRCUIT
32K ×8
MEMORY
ARRAY
COLUMN I/O
A0-A14
Vcc
Vss
I/O1-I/O8
CE
OE
WE
PIN DESCRIPTION
SYMBOL DESCRIPTION
A0 - A14 Address Inputs
I/O1 - I/O8 Data Inputs/Outputs
CE
Chip Enable Input
WE
Write Enable Input
OE
Output Enable Input
VCC Power Supply
VSS Ground
GENERAL DESCRIPTION
The UT61256C is a 262,144-bit high-speed
CMOS static random access memory organized
as 32,768 words by 8 bits. It is fabricated using
high performance, high reliability CMOS
technology.
The UT61256C is designed for high-speed
system applications. It is particularly suited for
use in high-density high-speed system
applications.
The UT61256C operates from a single 5V power
supply and all inputs and outputs are fully TTL
compatible.
PIN CONFIGURATION
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O1
I/O2
Vcc
A8
A9
A11
A10
I/O8
I/O7
I/O6
I/O5
I/O4
I/O3
Vss
UT61256C
SOJ
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
A13
A14
WE
OE
CE
I/O4
A11
A9
A8
A13
I/O3
A10
A14
A12
A7
A6
A5
Vcc
I/O8
I/O7
I/O6
I/O5
Vss
I/O2
I/O1
A0
A1
A2
A4
A3
UT61256C
STSOP
28
14
13
12
11
10
9
8
7
6
5
4
3
2
1
17
16
15
20
19
18
22
23
24
25
26
27
21
OE
WE
CE
UTRON
UT61256C
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80031
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
ABSOLUTE MAXIMUM RATINGS
*
PARAMETER SYMBOL RATING UNIT
Terminal Voltage with Respect to Vss V
TERM
-0.5 to +6.5 V
Operating Temperature TA 0 to +70
℃
Storage Temperature T
STG
-65 to +150
℃
Power Dissipation PD 1 W
DC Output Current I
OUT
50 mA
Soldering Temperature (under 10 sec) Tsolder 260
℃
*Stress greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may
affect device reliability.
TRUTH TABLE
MODE
CE
OE
WE
I/O OPERATION SUPPLY CURRENT
Standby H X X High - Z
I
SB
,
I
SB1
Output Disable L H H High - Z I
CC
Read L L H D
OUT
I
CC
Write L X L D
IN
I
CC
Note: H = VIH, L=VIL, X = Don't care.
DC ELECTRICAL CHARACTERISTICS
(VCC = 5V±10%, TA = 0℃ to 70℃)
PARAMETER SYMBOL TEST CONDITION MIN. MAX. UNIT
Input High Voltage
V
IH
2.2 VCC+0.5 V
Input Low Voltage V
IL
- 0.5 0.8 V
Input Leakage Current I
LI
V
SS
≦
V
IN
≦
VCC
- 1 1
µ
A
Output Leakage Current I
LO
V
SS
≦
V
I/O
≦
V
CC
CE
=V
IH
or
OE
=V
IH
or
WE
=VIL
- 1 1
µ
A
Output High Voltage V
OH
I
OH
= - 4mA 2.4 - V
Output Low Voltage V
OL
I
OL
= 8mA
- 0.4 V
- 8 - 190 mA
- 10 - 180 mA
- 12 - 160 mA
Operating Power
Supply Current
I
CC
Cycle time=Min.
CE
= V
IL , II/O
=
0mA
- 15 - 140 mA
Standby Current (TTL) I
SB
CE
= V
IH
- 30 mA
Standby Current (CMOS) I
SB1
CE
≧V
CC
-0.2V
- 5 mA
UTRON
UT61256C
Rev. 1.2
32K X 8 BIT HIGH SPEED CMOS SRAM
UTRON TECHNOLOGY INC. P80031
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
CAPACITANCE
(TA=25℃, f=1.0MHz)
PARAMETER SYMBOL MIN. MAX. UNIT
Input Capacitance
C
IN
-
8 pF
Input/Output Capacitance
C
I/O
-
10 pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 3ns
Input and Output Timing Reference Levels 1.5V
Output Load CL=30pF, IOH/IOL=-4mA/8mA
AC ELECTRICAL CHARACTERISTICS
(VCC = 5V±10% , TA = 0℃ to 70℃)
(1) READ CYCLE
UT61256C
-8
UT61256C
-10
UT61256C
-12
UT61256C
-15
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Read Cycle Time
tRC 8 - 10 - 12 - 15 - ns
Address Access Time
tAA - 8 - 10 - 12 - 15 ns
Chip Enable Access Time
t
ACE
- 8 - 10 - 12 - 15 ns
Output Enable Access Time
tOE - 4 - 5 - 6 - 7 ns
Chip Enable to Output in Low Z
t
CLZ*
2 - 2 - 3 - 4 - ns
Output Enable to Output in Low Z
t
OLZ*
0 - 0 - 0 - 0 - ns
Chip Disable to Output in High Z
t
CHZ*
- 4 - 5 - 6 - 7 ns
Output Disable to Output in High Z
t
OHZ*
- 4 - 5 - 6 - 7 ns
Output Hold from Address Change
tOH 3 - 3 - 3 - 3 - ns
(2) WRITE CYCLE
UT61256C
-8
UT61256C
-10
UT61256C
-12
UT61256C
-15
PARAMETER
SYMBOL
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
UNIT
Write Cycle Time
tWC 8 - 10 - 12 - 15 - ns
Address Valid to End of Write
tAW 6.5 - 8 - 10 - 12 - ns
Chip Enable to End of Write
tCW 6.5 - 8 - 10 - 12 - ns
Address Set-up Time
tAS 0 - 0 - 0 - 0 - ns
Write Pulse Width
tWP 6.5 - 8 - 9 - 10 - ns
Write Recovery Time
tWR 0 - 0 - 0 - 0 - ns
Data to Write Time Overlap
tDW 5 - 6 - 7 - 8 - ns
Data Hold from End of Write Time
tDH 0 - 0 - 0 - 0 - ns
Output Active from End of Write
t
OW*
1.5 - 2 - 3 - 4 - ns
Write to Output in High Z
t
WHZ*
5 - 6 - 7 - 8 ns
*These parameters are guaranteed by device characterization, but not production tested.
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