UTRON UT611024JC-10, UT611024LS-15, UT611024LS-12, UT611024LS-10, UT611024LC-12 Datasheet

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Rev. 1.5

UTRON

FEATURES

Fast access time : 10/12/15ns (max.)
Low operating power consumption:

Single5V power supply
All inputs and outputs are TTL compatible
Fully static operation
 Three state outputs
Package : 32-pin 288 mil skinny PDIP

FUNCTIONAL BLOCK DIAGRAM

A4
A5

A6

7
A8
A12

DECODER

A13
A14
A15

A16

I/O 1

.

.

.

.

.

CONTROL

.

I/O 8

1CE

CE2

CONTROL

WE

OE

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0 - A16 Address Inputs

I/O1 - I/O8 Data Inputs/Outputs

100 mA (typical.)

32-pin 300 mil SOJ
32-pin 8mm×20mm TSOP-1
32-pin 8mm×13.4mm STSOP

.

MEMORY AR RAY

.

ROW

1024 RO WS × 1024 C O LU M N S

.

.

. .

I/O

.

.

.

LOGIC

,CE2

1CE

WE

OE
VCC Power Supply
VSS Ground

NC No Connection

C O L UMN I/O

COLUMN DECODER

11

9

3

10

2 A1 A0

Chip Enable Inputs
Write Enable Input
Output Enable Input

VCC

VSS

UT611024

128K X 8 BIT HIGH SPEED CMOS SRAM

GENERAL DESCRIPTION

The UT611024 is a 1,048,576-bit high speed
CMOS static random access memory organized
as 131,072 words b y 8 bits. It is fabricated usi ng
high performance, high reliability CMOS
technology.

The UT611024 is designed for high-sp eed s ystem
application. It is particularly suited for use in high
speed and high density system applications.

The UT611024 operates from a signal 5 V power
supply and all inputs and outputs are fully TTL
compatible

PIN CONFIGURATION

A11

A9
A8

A13

WE

CE2
A15

Vcc

NC
A16
A14
A12

A7

A6

A5

A4 A3

NC

A16
A14

A12

A7
A6

A5
A4
A3
A2
A1

A0
I/O1
I/O2
I/O3
Vss

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

32

31

30

29

UT611024

28

27

26

25

24

23

22

21

20

19

18

1716

PDIP / SOJ

UT611024

STSOP / TSOP-1

A15
CE2

A13

A11

A10

I/O8
I/O7
I/O6
I/O5
I/O4

Vcc

WE

A8
A9

OE

1CE

32

OE

A10

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

1CE

I/O8

I/O7
I/O6
I/O5

I/O4

Vss
I/O3
I/O2
I/O1

A0
A1

A2

UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

1



Rev. 1.5

UTRON

128K X 8 BIT HIGH SPEED CMOS SRAM

UT611024

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL RATING UNIT

Terminal Voltage w ith Respect to VSS V
Operating Temperature TA 0 to +70
Storage Temperature T
Power Dissipation PD 1 W
DC Output Current I
Soldering Temperature (under 10 sec) Tsolder 260

*Stresses greater than those listed under “Absolute Maxim um Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device or any other conditions above those indicated in the operational sections
of this specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device
reliability.

TRUTH TABLE

MODE

Standby H X X X High - Z ISB, ISB1
Standby X L X X High - Z ISB, ISB1

Output Disable L H H H High - Z ICC

Read L H L H D

Write L H X L DIN I

Note: H = VIH, L=VIL, X = Don't care.

CE

1

DC ELECTRICAL CHARACTERISTICS

PARAMETER SYMBOL TEST CONDITION MIN. MAX. UNIT

Input High Voltage VIH 2.2 VCC+0.5 V
Input Low Voltage VIL -0.5 0.8 V
Input Leakage Current ILI
Output Leakage

Current

Output High Voltage VOH IOH= - 4mA 2.4 - V
Output Low Voltage VOL IOL= 8mA - 0.4 V

Operating Power
Supply Current

Standby Power
Supply Current

Notes : VIL = -3.0V for pulse width less than 10ns.

ILO

ICC Cycle time =Min., I

ISB

I

SB1

*

CE2

≦VIN ≦VCC

V

SS

V

≦V

SS

or

OE

1CE

1CE

≧

V

IN

1CE

≧

V

IN

-0.5 to + 7.0 V

TERM

-65 to +150

STG

50 mA

OUT

I/O OPERATION SUPPLY CURRENT

OE

WE

(VCC = 5V±10%, TA = 0℃ to 70℃)

- 1 1

≦V

= V

=V

V

IH

≧

V

CC

I/O

=V

IL

or V

V

CC,

or

WE

IH

,CE2= VIH

or CE2=V

IH

≦

V

IN

-0.2V or CE2≦0.2V

CC

-0.2V or V

= V

I/O

IL

IN

or CE2=VIL

=V

1CE

IH

IL

= 0mA ,

IL

≦

0.2V

℃
℃

℃

I

OUT

CC
CC

- 1 1

- 10 - 180 mA

- 12 - 160 mA

- 15 - 140 mA

- 30 mA

- 5 mA

A

µ

A

µ

UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

2



Rev. 1.5

CAPACITANCE

PARAMETER SYMBOL MIN. MAX UNIT

Input Capacitance C
Input/Output Capacitance C

Note : These parameters are guarant eed by devi ce characterization, but not production tested.

UTRON

(TA=25℃, f=1.0MHz)

128K X 8 BIT HIGH SPEED CMOS SRAM

I/O

IN

-

-

UT611024

8 pF

10 pF

AC TEST CONDITIONS

Input Pulse Levels 0V to 3.0V
Input Rise and Fall Times 3ns
Input and Output Timing Reference Levels 1.5V
Output Load CL = 30pF, IOH/IOL = -1mA/4 mA

AC ELECTRICAL CHARACTERISTICS

(1) READ CYCLE

PARAMETER

Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low Z
Output Enable to Output in Low Z
Chip Disable to Output in High Z
Output Disable to Output in High Z
Output Hold from Address Change

(2) WRITE CYCLE
PARAMETER

Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High Z

*These parameters are guaranteed by device characterization, but not production tested.

SYMBOL UT611024-10 UT611024-12 UT611024-15 UNIT

tRC
tAA
t

ACE1, tACE2

tOE
t

CLZ1*, tCLZ2*

t

OLZ*

t

CHZ*1,tCHZ*2

t

OHZ*

tOH

SYMBOL UT611024-10 UT611024-12 UT611024-15 UNIT

tWC
tAW
t

CW1, tCW2

tAS
tWP
tWR
tDW
tDH
t

OW*

t

WHZ*

(V

= 5V±10%, TA = 0℃ to 70℃)

CC

MIN. MAX. MIN. MAX. MIN. MAX.

10 - 12 - 15 - ns

- 10 - 12 - 15 ns

- 10 - 12 - 15 ns

- 5 - 6 - 7 ns
2 - 3 - 4 - ns
0 - 0 - 0 - ns

- 5 - 6 - 7 ns

- 5 - 6 - 7 ns
3 - 3 - 3 - ns

MIN. MAX. MIN. MAX. MIN. MAX.

10 - 12 - 15 - ns

8 - 10 - 12 - ns
8 - 10 - 12 - ns
0 - 0 - 0 - ns
8 - 9 - 10 - ns
0 - 0 - 0 - ns
6 - 7 - 8 - ns
0 - 0 - 0 - ns
2 - 3 - 4 - ns

- 6 - 7 - 8 ns

UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Indus t ri a l P ark, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

3



A

UTRON

Rev. 1.5

TIMING WAVEFO RMS

READ CYCLE 1

(Address Controlled)

ddress

t

OH

D

OUT

，

READ CYCLE 2

(

CE2

1CE

128K X 8 BIT HIGH SPEED CMOS SRAM

(1,2,4)

t

RC

t

AA

Data Valid

OE

Controlled)

t

(1,3,5,6)

RC

and

UT611024

t

OH

Address

AA

t

ACE1

CE1

CE2

OE

CLZ1

t

CLZ2

t

, t

OLZ

HIGH-Z

, t

CHZ1

Dout

Notes :

1.

2. Device is continuousl y selected

3. Address must be val i d pri o r t o or coincident with

4.

5. t

6. At any given temperature and voltage condition, t

is HIGH for read cycle.

WE

is low.

OE

, t

CLZ1

CLZ2

, t

CHZ2

t

and t

t

ACE2

t

OLZ

=V

and CE2=V

IL

CE

1

are specified with CL=5pF. Transition is measured ±500mV from st eady state.

OHZ

CHZ1

OE

t

t

Data Valid

IH.

and CE2 transit i on; otherwise tAA is the limiting parameter.

CE

1

is less than t

CHZ1

CLZ1

, t

CHZ2

t

OHZ

t

OH

is less than t

t

CHZ2

CLZ2

, t

OHZ

HIGH-Z

is less than t

OLZ.

UTRON TECHNOLOGY INC. P80048
1F, No. 11, R&D Rd. II, Science-Based Indus t ri a l P ark, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

4