UTRON UT51C164MC-60, UT51C164MC-50, UT51C164MC-40, UT51C164MC-35, UT51C164JC-60 Datasheet



Rev 1.4

UTRON

FEATURES













40 / 44 pin 400mil TSOP-Ⅱ






access time: 35, 40, 50, 60

RAS

2

CAS

RAS
Early write or output enable controlled write
Extended Data Out operation
Package : 40 pin 400mil SOJ

Single +5V+
TTL compatible inputs and outputs
512 refresh cycles /8ms

Byte/Word Read/Write operation

CAS

- before –

only and Hidden refresh capability

10% power supply

refresh capability

RAS

256K X 16 BIT EDO DRAM

Speed -35 -40 -50 -60

t
t

t

t

t

RAC

CAA

PC

CAC

RC

35ns 40ns 50ns 60ns
18ns 20ns 24ns 30ns
14ns 15ns 19ns 27ns
11ns 12ns 14ns 15ns
70ns 75ns 90ns 110ns

UT51C164

GENERAL DESCRIPTION

The UT51C164 is high speed 5V EDO DRAMs organized as 256K bit X 16 I/O and fabricated with
the CMOS process. The UT51C164 offers a combination of unique features including : EDO Page
Mode operation for higher bandwidth with Page Mode cycle time as short as 14ns. All inputs are
TTL compatible. Input and output capacitance is significantly lowered to increase performance and
minimize loading. These features make the UT51C164 suited for wide variety of high performance
computer systems and peripheral applications

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
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

Rev 1.4

UTRON

PIN DESCRIPTION

SYMBOL DESCRIPTION

A0-A8 Address Inputs

RAS

UCAS

LCAS

WE

OE

Row Address Strobe

Column Address Strobe / Upper Byte Control

Column Address Strobe / Lower Byte Control

Write enable
Output enable

DQ0-DQ15 Data Inputs, Data Outputs
VDD +5V Supply
Vss 0V Supply
NC No Connect

PIN CONFIGURATIONS

UT51C164

40- pin SOJ

256K X 16 BIT EDO DRAM

UT51C164

40- pin TSOP -

Ⅱ

UT51C164

V

DQ0

DQ1

DQ2

DQ3

V

DQ4

DQ5

DQ6

DQ7

NC

NC

WE

RAS

NC

A0

A1

A2

A3

V

DD

DD

DD

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

40

Vss

39

DQ15

38

DQ14

37

DQ13

36

DQ12

35

Vss

34

DQ11

33

DQ10

32

DQ9

31

DQ8

30

NC

29

LCAS

28

UCAS

27

OE

26

A8

25

A7

24

A6

23

A5

22

A4

21

Vss

V

DQ0

DQ1

DQ2

DQ3

DD

V

DQ4

DQ5

DQ6

DQ7

NC

NC

WE

RAS

NC

A0

A1

A2

A3

DD

V

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

1

DD

40

Vss

39

DQ15

38

DQ14

37

DQ13

36

DQ12

35

Vss

34

DQ11

33

DQ10

32

DQ9

31

DQ8

30

NC

29

LCAS

28

UCAS

27

OE

26

A8

25

A7

24

A6

23

A5

22

A4

21

Vss

UTRON TECHNOLOGY INC. P90005
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

Rev 1.4

UTRON

FUNCTION BLOCK DIAGRAM

A0

A1

.

.

.

9

Y0

–Y8

A8

A7

.

Address Buffers

&

Predecoders

256K X 16 BIT EDO DRAM

UCAS

WE

OE

Counter

Refresh

Control Circuit

X0 – X8

Row Control Circuit

LCAS

RAS

UT51C164

V

V

DD

SS

GENERATOR

V

BB

V

BB

Column Decoder

X512 CS

Row Decoder

512 x 512 x 16

Sense Amp

Cell Array

x16 x16

FSA & Write in Circuit

Input & Output Buffer

x16

DQ[0,15]

UTRON TECHNOLOGY INC. P90005
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

Rev 1.4

UTRON

256K X 16 BIT EDO DRAM

UT51C164

ABSOLUTE MAXIMUM RATINGS

PARAMETER SYMBOL VALUE UNIT

Voltage on any pin relative to Vss V
Supply voltage relative to VSS V

Short circuit output current I

Power dissipation PD 1.0 W

Operating temperature TA 0 to + 70 ºC

Storage temperature T

Notes: Permanent device damage may occur if absolute maximum ratings are exceed.

RECOMMENDED DC OPERATING CONDITIONS

PARAMETER SYMBOL

Supply voltage

Input high voltage VIH 2.4 VDD +1V V 1

Input low voltage VIL -0.3 0.8 V 1

Notes: 1. All Voltage referred to Vss

CAPACITANCE

PARAMETER SYMBOL TYP MAX UNIT

Input capacitance (A0-A8) CIN1 3 4 pF
Input Capacitance

(

RAS ,UCAS,LCAS

Output capacitance(DQ0-DQ15) CDQ 5 7 pF

(TA = 25ºC, VDD= 5V±0.5V，f=1MHz)

,

,

OE

WE

VDD 4.5 5.5 V 1

Vss 0 0 V -

)

-1.0 to +7 V

T

-1.0 to +7 V

DD

50 mA

OUT

-55 to +125 ºC

STG

(TA = 0℃ to 70ºC)

5.0V

MIN MAX

C

2 4 5 pF

IN

UNIT NOTES

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

Rev 1.4

UTRON

256K X 16 BIT EDO DRAM

UT51C164

DC CHARACTERISTICS

(TA = 0℃ to 70ºC, VDD = 5.0 V ± 0.5 V, Vss = 0 V)

SYMBOL PARAMETER

SPEED

)

(t

RAC

UT51C164

Min Max

UNIT TEST CONDITION

-35 - 190

I

DD1

Operating Current,
V

DD

Supply

-40 - 180

-50 - 170

mA t

RC

-60 - 160

I

DD2

Standby Current
(TTL Input)

- - 3 mA

RAS=UCAS=LCAS

=V

-35 - 190

I

DD3

Only Refresh

RAS
Current

-40 - 180

-50 - 170

mA t

RC

-60 - 160

-35 - 220

I

DD4

EDO Page Mode
Current

-40 - 200

-50 - 190

mA t

PC

-60 - 180

-35 - 190

I

CBR Refresh Current

DD5

-40 - 180

-50 - 170

mA t

RC

-60 - 160

RAS

CAS

I

DD6

Standby Current
(CMOS Input)

- - 2 mA

All other inputs≧ V

VDD Power Supply - 4.5 5.5 V

ILI Input Leakage Current - -10 10 uA

ILO

Output Leakage
Current

- -10 10 uA

V

SS

V

SS

RAS=CAS

VIL Input Low Voltage - -1 0.8 V

VIH Input High Voltage - 2.4

VOL Output Low Voltage - - 0.4 V I

VDD +1

V

OI

= 2mA

VOH Output High Voltage - 2.4 - V IOH = 2mA

Notes: I
open. I

RAS

, I

, I

, I

DD1

DD3

is specified as an average current. In I

DD

=V

In I

IL.

DD4

are dependent on output loading and cycle rates. Specified values are obtained with the output

DD4

DD5

, address can be changed maximum once within one EDO page cycle time, tPC.

DD1

, I

DD3

, and I

address can be changed maximum once while

DD5

= tRC (min.)

IH

= tRC (min.)

= tPC (min.)

= tRC (min.)

≧

V

-0.2V

DD

≧

V

-0.2V

DD

≦

V

≦VDD

IN

≦

V

≦VDD

OUT

= V

SS

IH

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

Rev 1.4

UTRON

AC CHARACTERISTICS

Test condition: V

SYMBOL PARAMETER

1

t

RAS

2

tRC

3

tRP

4

t

CSH

5

t

CAS

6

t

RCD

7

t

RCS

8

t

ASR

9

t

RAH

10

t

ASC

11

t

CAH

12

t

RSH

13

t

CRP

14

t

RCH

15

t

RRH

16

t

ROH

17

t

Access Time from

OAC

18

t

Access Time from

CAC

19

t

Access Time from

RAC

20

t

CAA

21

tLZ

22

tHZ

23

tAR

24

t

RAD

25

26

27

28

29

tT

t

CWL

t

WCS

t

WCH

tWP

= 5.0V±0.5V, V

DD

Pulse Width

RAS

Read or Write Cycle Time 70 75 90 110 ns

Precharge Time

RAS

Hold Time

CAS

Pulse Width

CAS

to

RAS

Read Command Setup Time 0 0 0 0 ns
Row Address Setup Time 0 0 0 0 ns
Row Address Hold Time 6 7 9 10 ns
Column Address Setup Time 0 0 0 0 ns
Column Address Hold Time 6 7 9 10 ns

to

RAS

to

CAS

Time
Read Command Hold Time

Reference
Read Command Hold Time
Reference

Hold Time Referenced

RAS

to

OE

Access Time From Column
Address

or

OE

or

OE

Output
Column Address Hold Time

from

RAS

to Column Address

RAS

Delay Time
Transition Time 1.5 50 1.5 50 1.5 50 1.5 50 ns

Write Command to
Lead Time
Write Command Setup Time 0 0 0 0 ns
Write Command Hold time 5 6 7 10 ns
Write Pulse Width 5 6 7 10 ns

Delay

CAS

Hold Time

CAS

Precharge

RAS

CAS

RAS

to Low-Z Output

CAS

to High-Z

CAS

(TA = 0℃ to 70°C)

/ VIL=3V / 0V, V

IH

35 40 50 60

Min. Max. Min. Max. Min. Max. Min. Max.

35 75K 40 75K 50 75K 60 75K ns

25 25 30 40 ns

35 40 50 60 ns

8 8 10 10 ns

13 24 17 28 19 36 20 45 ns

10 12 14 15 ns

5 5 5 5 ns

0 0 0 0 ns

0 0 0 0 ns

7 8 10 10 ns

OE

CAS

RAS

CAS

11 12 14 15 ns

11 12 14 15 ns

35 40 50 60 ns

18 20 24 30 ns

0 0 0 0 ns

0 5 0 6 0 8 0 10 ns

25 30 40 50 ns

10 17 12 20 14 26 15 30 ns

8 10 10 10 ns

256K X 16 BIT EDO DRAM

/ VOL=2.0 / 0.8)

OH

UT51C164

NOTE

UNIT

*1

*2

*2

*9

*3,4,11

*3,5,6

*3,4,7

*13

*13

*8

*12

*9,10

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

Rev 1.4

UTRON

AC CHARACTERISTICS (

SYMBOL PARAMETER

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

t

t

t

t
t

t

t

t

t

t

t

t

t

t

t

Write Command Hold Time

WCR

from

Write Command to

RWL

Lead Time
Data in Setup Time 0 0 0 0 ns

tDS

Data in Hold Time 5 6 7 10 ns

tDH

Write to

WOH

OE

OED

Read-Modify-Write Cycle Time 105 110 130 170 ns

RWC

Read-Modify-Write Cycle Time

RRW

RAS

CAS

CWD

Modify-Write Cycle

RAS

RWD

Modify-Write Cycle

CAS

CRW

Column Address to

AWD

Time
EDO Page Mode Read or

tPC

Write Cycle Time

tCP

CAS

Column Address to

t

CAR

RAS

Access Time from Column

t

CAP

Precharge
Data in Hold Time Referenced

DHR

to

RAS

t

t

t

t
t

CAS

CSR

Refresh

RAS

RPC

Time

CAS

CHR

Refresh
EDO Page Mode Cycle Time

PCM

in RMW

Output Hold After

COH

OE

OES

Time

OE

OEH

RMW Cycle

OE

OEP

Refresh Interval (512 Cycles) 8 8 8 8 ms

REF

RAS

RAS

Hold time

OE

to Data Delay Time

Pulse Width

to

to

pulse Width in RMW

Precharge Time

Setup Time

Setup Time in CBR

to

Hold Time in CBR

Delay in Read-

WE

Delay in Read-

WE

Precharge

CAS

CAS

Low to

Hold Time from

Pulse Width

CAS

High Setup

continued )

Delay

WE

Low

in

WE

UT51C164

256K X 16 BIT EDO DRAM

35 40 50 60

Min. Max. Min. Max. Min. Max. Min. Max.

25 30 40 50 ns

11 12 14 15 ns

5 6 8 10 ns

5 6 8 10 ns

70 75 85 105 ns

28 30 34 40 ns

54 58 68 85 ns

46 48 52 65 ns

35 38 42 58 ns

14 15 19 27 ns

4 5 7 10 ns

18 20 24 30 ns

20 23 27 34 ns *4

25 30 40 50 ns

8 10 10 10 ns

0 0 0 0 ns

8 9 12 15 ns

55 60 70 85 ns

3 3 3 3 ns

3 4 6 8 ns

5 6 8 10 ns

8 10 14 18 ns

UNIT

NOTE

*11

*11

*11

*11

*9

*9

*9

*14

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

Rev 1.4

UTRON

256K X 16 BIT EDO DRAM

UT51C164

Notes:

t

(Max.) is specified for reference only. Operation within

1.

RCD

(Max.) and

t

CAA

time is controlled by

t

2. Either

RRH

or

t

(Max.) can be met. If

t

CAA

must be satisfied for Read Cycle to occur.

RCH

and

t

CAC.

t

is greater than the specified

RCD

t

(Max.) limits insures that

RCD

t

(Max.), the access

RCD

t

RAC

3. Measured with a load equivalent to one TTL input and 50pF.

4. Access time is determined by the longest of

≦

t

RCD

t

RAD

t

t

t

RAD

5. Assumes that
amount that

6. Assumes that
amount that

7. Assumes that

8. Operation within the
reference point only. If

t

by

CAA

t

9.

,

WCS

t

10.

WCS

t

11.

and

DS

t

12.

is measured between

T

t

and

CAC.

t

t

,

RWD

AWD

(min.) must be satisfied in an Early Write Cycle.

t

are referenced to the latter occurrence of

DH

t

RAD

exceeds

≦

t

RCD

exceeds

≧

t

RAD

t

RAD

t

t

and

CWD

(Max.). If

RAD

t

RCD

(Max.). If

RCD

t

RAD

(Max.)

(Max.)

t

t

RCD

RCD

(Max.).

(Max.) limits ensures that

is greater than the specified

RAD

are not restrictive operating parameters.

V

(min.) and

IH

V

IL

t

,

CAA

CAC

is greater than

is greater than

(max.). AC-measurements assume

t

and

CAP

t

t

t

can be met.

RA

t

RAD

or

CAS

.

(Max.),

RCD

(Max.),

RCD

t

will increase by the

RAC

t

will increase by the

RAC

t

(Max.) is specified as a

RAD

(Max.), the access time is controlled

.

WE

t

= 3ns.

T

t

13. Assumes a tri-state test load (5pF and a 500Ohm Thevenin equivalent).

14.An initial pause of 200us is required after power-up followed by any 8 CBR or ROR cycles
before device operation is achieved.

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

Rev 1.4

UTRON

256K X 16 BIT EDO DRAM

UT51C164

TRUTH TABLE

FUNCTION

Standby H H H X X X High-Z High-Z
Read: Word L L L H L ROW/COL DQ-OUT
Read: Lower Byte L L H H L ROW/COL DQ-OUT High-Z
Read: Upper Byte L H L H L ROW/COL High-Z DQ-OUT
Write: Word
(Early-Write)
Write: Lower Byte
(Early-Write)
Write: Upper Byte
(Early-Write)
Read-Write

EDO Page-Mode
Read
EDO Page-Mode
Write
EDO Page –Mode
Read-Write
Hidden Refresh
Read

Only

RAS
Refresh
CBR Refresh

Notes:

1. Byte Write cycles

2. Byte Read cycles

RAS LCAS UCAS

L L L L X

L L H L X

L H L L X

L L L

L

L

L

L→H→L

L H H X X

H→L

LCAS

LCAS

H→L H→L

H→L H→L

H→L H→L H→L L→H

L L H L

L L X X

or

or

UCAS

UCAS

active.

active.

WE

H→L L→H

H L

L X

ADDRESS DQ(0-7) DQ(8-15) NOTE

OE

ROW/COL DQ-IN

ROW/COL DQ-IN High-Z

ROW/COL High-Z DQ-IN

ROW/COL DQ-OUT,DQ-IN *1,2
COL DQ-OUT *2

COL DQ-IN *2

COL DQ-OUT,DQ-IN *1,2

ROW/COL DQ-OUT *2

ROW High-Z

X High-Z

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

Rev 1.4

UTRON

UTRON EDO Mode, X16 (2CAS) Device Timing Diagram

―

Waveforms of Read Cycle

t

RAS(1)

V

V

－

－

IH

IH

RAS

UCAS,

UCAS,
LCAS

LCAS

Address

WE

WE

OE

OE

V

V

－

－

IL

IL

t

CRP(13)

ROW

ADDRESS

t

RAH(9)

t

RAD(24)

t

RCS

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

ASR(8)

V

－

IH

V

－

IL

V

V

－

－

IH

IH

V

V

－

－

IL

IL

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

ASC(10)

(7)

t

AR(23)

t

RCD(6)

COLUMN ADDRESS

t

RAC(19)

t

CSH(4)

t

t

t

CAH(11)

CAA(20)

CAC(18)

t

CAR(24)

UT51C164

256K X 16 BIT EDO DRAM

RC(2)

t

t

RSH(12)

t

CAS(5)

t

ROH(16)

t

OAC(17)

t

OES(52)

t

RP(3)

t

CRP(13)

t

RCH(14)

t

RRH(15)

t

t

HZ(22)

HZ(22)

V

－

OH

DQ

V

－

OL

t

LZ(21)

VALID DATA - OUTVALID DATA - OUT

Don't care

Undefined

UTRON TECHNOLOGY INC. P90005
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

Rev 1.4

UTRON

UTRON EDO Mode, X16 (2CAS) Device Timing Diagram

―

Waveforms of Early Write Cycle

t

RAS(1)

V

V

－

－

IH

IH

RAS

RASRAS

UCAS,

UCAS,
LCAS

LCAS

Address

WE

WEWE

V

V

－

－

IL

IL

t

CRP(13)

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

ASR(8)

V

－

IH

V

－

IL

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

RAH(9)

ROW ADDRESS

t

RAD(24)

t

AR(23)

t

RCD(6)

COLUMN ADDRESS

t

(27)

WCS

t

CSH(4)

t

ASC(10)

t

WP(29)

t

WCR

t

CAH(11)

t

WCH(28)

t

CWL(26)

(30)

t

RC(2)

t

UT51C164

256K X 16 BIT EDO DRAM

t

RP(3)

RSH(12)

t

CAS(5)

t

t

RWL

CAR(44)

(31)

t

CRP(13)

V

V

－

－

IH

IH

OE

OE

V

V

－

－

IL

DQ

IL

t

DS(32)

V

－

IH

V

－

IL

t

DHR(46)

t

DH(33)

VALID DATA INVALID DATA -

HIGH-Z

Don't

Care

Undefined

UTRON TECHNOLOGY INC. P90005
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

Rev 1.4

UTRON

UTRON EDO Mode, X16 (2CAS) Device Timing Diagram

Waveforms of OE-Contrilled Write Cycle

t

t

ASC(10)

t

CSH(4)

RAS(1)

t

CAH(11)

RAS

RASRAS

UCAS,

UCAS,
LCAS

LCAS

Address

WE

WEWE

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

CRP(13)

ROW

ADDRESS

t

RAH(9)

t

RAD(24)

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

ASR(8)

V

－

IH

V

－

IL

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

RCD(6)

t

AR(23)

COLUMN ADDRESS

UT51C164

256K X 16 BIT EDO DRAM

t

RC(2)

t

RP(3)

t

t

t

WOH

RSH(12)

CAS(5)

t

CAR(44)

t

CWL(26)

t

WP

(34)

t

RWL

(31)

(29)

t

CRP(13)

V

V

－

－

IH

IH

OE

OE

V

V

－

－

IL

DQ

IL

V

－

IH

V

－

IL

t

(35)

OED

t

DS

(32)

t

DH(33)

VALID DATA-IN

Don' t Care

Undefined

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

12



Rev 1.4

UTRON

UTRON EDO Mode, X16 (2CAS) Device Timing Diagram

―

Waveforms of Read -Modify-Write Cycle

V

V

IH

IH

RAS

RASRAS

V

V

IL

IL

V

V

UCAS,

UCAS,
LCAS

LCAS

Address

WE

WEWE

OE

OE

DQ

IH

IH

V

V

IL

IL

V

IH

V

IL

V

V

IH

IH

V

V

IL

IL

V

V

IH

IH

V

V

IL

IL

VIHV
VILV

-

t

RRW(37)

－

－
－

－

t

CRP(13)

－

－
－

－

－
－

－

－
－

－

－

－
－

－

－

OH

－

OL

t

ASR(8)

ROW

ADDRESS

t

ACS

t

RAH(9)

t

RAD(24)

t

RCD(6)

t

t

RAC(19)

AR(23)

t

CSH(4)

t

CAH(11)

t

ASC(10)

COLUMN ADDRESS

t

(39)

RWD

t

(20)

CAA

t

(17)

OAC

t

(18)

CAC

t

LZ(21)

t

RWC(36)

t

CRW(40)

t

CWD

(38)

VALID

DATA-OUT

UT51C164

256K X 16 BIT EDO DRAM

t

RP(3)

t

RSH(12)

t

AWD

(41)

t

OED

(35)

t

(22)

HZ

t

CWL(26)

t

WP(29)

t

OEH

(53)

t

(32)

DS

VALID

DATA-IN

t

CRP(13)

t

RWL(31)

t

(33)

DH

Don't Care

Undefined

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

13



Rev 1.4

UTRON

UTRON EDO Mode, X16 (2CAS) Device Timing Diagram

―

EDO Page Mode Read Cycle

t

COLUMN

COLUMN
ADDRESS

ADDRESS

t

COH(5)

VALID

DATA OUT

RAS(1)

t

RAS

RASRAS

UCAS,

UCAS,
LCAS

LCAS

Address

WE

WEWE

OE

OE

DQ

t

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

CRP(13)

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

ASR(8)

V

－

IH

V

－

IL

V

V

－

－

IH

IH

V

V

－

－

IL

IL

V

V

－

－

IH

IH

V

V

－

－

IL

IL

V

－

OH

V

－

OL

t

RAH(9)

ROW

ADDRESS

t

t

RCD(6)

RCS(7)

t

t

RAC(19)

ASC(10)

t

AR(23)

CSH(4)

COLUMN
ADDRESS

t

CAA(20)

t

OAC(17)

t

CAC(18)

t

LZ(21)

t

CAH(11)

t

t

CAS(5)

t

RCH(14)

t

PC(42)

OES(52)

CP(43)

t

t

CAH(11)

RCS(7)

t

CAP(45)

t

CAC(18)

t

CAS(5)

UT51C164

256K X 16 BIT EDO DRAM

t

RP(3)

⌇⌇⌇⌇

t

ASC(10)

⌇⌇⌇⌇

⌇⌇⌇⌇

⌇⌇⌇⌇

t

HZ(22)

VALID

DATA OUT

⌇⌇⌇⌇

COLUMN

COLUMN
ADDRESS

ADDRESS

⌇⌇⌇⌇

⌇⌇⌇⌇

t

OEP(54)

t

RSH(12)

t

CAS(5)

t

CAR(44)

t

CAH(11)

t

RCS(7)

t

CAA(20)

t

OAC(17)

t

CAC(18)

t

LZ

t

RCH(14)

t

t

RRH(15)

t

HZ(22)

t

HZ(22)

t

HZ(22)

VALID

DATA OUT

CRP(13)

Don' t Care

Undefined

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

14



Rev 1.4

UTRON

UTRON EDO Mode, X16 (2CAS) Device Timing Diagram

―

EDO Page Mode Write Cycle

t

AR(23)

t

PC(42)

t

CAS(5)

(11)

CWL(26)

t

WCH(28)

t

DS(32)

OPEN

t

CP(43)

RAS(1)

COLUMN
ADDRESS

VALID

VALID

DATA IN

DATA IN

RAS

UCAS,

LCAS

Address

WE

OE

DQ

V

V

－

－

IH

IH

V

V

－

－

IL

IL

COLUMN
ADDRESS

t

WP(29)

VALID

VALID

DATA IN

DATA IN

t

t

CAH

t

t

CRP(13)

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

ASR(8)

V

－

IH

V

－

IL

V

V

－

－

IH

IH

V

V

－

－

IL

IL

V

V

－

－

IH

IH

V

V

－

－

IL

IL

－

V

IH

V

－

IL

t

RAH(9)

ROW

ADDRESS

t

t

RAD(24)

RCD(6)

t

WCS(27)

t

CSH(4)

t

DS (32)tDH (33)

t

ASC

t

CAH(11)

t

WCS(27)

t

t

t

CAS(5)

(10)

t

WCH(28)

WP(29)

UT51C164

256K X 16 BIT EDO DRAM

t

CWL(26)

t

DH

t

t

DS (32)

(33)

⌇⌇⌇⌇

⌇⌇⌇⌇

WCS(27)

⌇⌇⌇⌇

⌇⌇⌇⌇

⌇⌇⌇⌇

⌇⌇⌇⌇

⌇⌇⌇⌇

⌇⌇⌇⌇

t

COLUMN
ADDRESS

VALID

VALID

DATA IN

DATA IN

ASC

t

t

WP(29)

t

t

t

(10)

WCH(28)

RSH(12)

CAS(5)

CAR(44)

t

CWL(26)

t

DH

t

t

(11)

CAH

t

RWL(31)

(33)

OPEN

RP(3)

CRP(13)



Don't care

Undefined

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

15



Rev 1.4

UTRON

UTRON EDO Mode, X16 (2CAS) Device Timing Diagram

―

EDO Page Mode Read-Write Cycle

t

t

DH(33)

t

DS(32)

t

OEH(35)

RAS(1)

t

CP(43)

t

COLUMN
ADDRESS

t

CAP (45)

t

RAS

RASRAS

UCAS,

UCAS,
LCAS

LCAS

Address

WE

WEWE

OE

OE

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

CAH

COLUMN

ADDRESS

t

CAA

t

t

CAC

t

CSH(4)

(11)

RWD(39)

t

CWD(38)

t

AWD(41)

(20)

t

OED(35)

t

HZ(22)

(18)

t

CAS(5)

t

t

PCM(50)

t

CWL(26)

WP

t

OAC(17)

(29)

t

RCD(6)

t

t

ASR(8)tASR(8)

ROW

ADD

RAH(9)

t

RAD(24)

t

t

RAC(19)

ASC(10)

V

V

－

－

IH

IH

V

V

－

－

IL

IL

V

－

IH

V

－

IL

V

V

－

－

IH

IH

V

V

－

－

IL

IL

V

V

－

－

IH

IH

V

V

－

－

IL

IL

ASC(10)

t

CAH

t

CAA

t

CAC

(11)

t

CWD(38)

AWD(41)

(20)

t

OED(35)

t

HZ(22)

(18)

t

UT51C164

256K X 16 BIT EDO DRAM

t

RSH(12)

t

ASC(10)

t

CAH

COLUMN

COLUMN

ADDRESS

ADDRESS

t

CAP(45)

t

CAA(20)

t

OED(35)

t

HZ(22)

t

CAC

t

CWD(38)

t

AWD(41)

(18)

(11)

t

CAS(5)

t

t

CAR(44)

CWL

t

t

OAC(17)

t

(26)

WP

(29)

t

DS

CAS(5)

t

CWL(26)

t

WP(29)

t

OAC(17)

t

DH(33)

t

(32)

DS

t

RP(3)

t

CRP(13)

(31)

RWL

t

DH(33)

(32)

V

－

I/OH

DQ

OUT

V

－

I/OL

t

LZ(21)

IN

OUT

t

LZ(21)

IN

OUT

t

LZ(21)

IN

Don' t Care

Undefined

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

16



Rev 1.4

UTRON

UTRON EDO Mode, X16 (2CAS) Device Timing Diagram

―

―

Waveforms of RAS - Only Refresh Cycle

t

RAS(1)

RAS

RASRAS

UCAS,

UCAS,
LCAS

LCAS

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

CRP(13)

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

ASR(8)

t

RAH(9)

UT51C164

256K X 16 BIT EDO DRAM

t

RC(2)

t

RP(3)

Address

V

－

IH

V

－

IL

Note:

Note:

WE, OE = Don't care

ROW ADD

Don't care

Undefined

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

17



Rev 1.4

UTRON

UTRON

―

RAS

RASRAS

UCAS,

UCAS,
LCAS

LCAS

Address

WE

WE

WEWE

I/O

WE

WEWE

EDO Mode, X16 (2CAS) Device Timing Diagram

Waveforms of CAS - before - RAS Refresh Counter Test Cycle

t

t

CHR(49)

RAS(1)

t

t

RCS(7)

V

V

V

V

V

V

V

V

V

V

V

V

V

IH

IH

IH

V

V

V

IL

IL

IL

V

OH

V

OL

V

V

IH

IH

V

V

IL

IL

－

－

IH

IH

－

－

IL

IL

－

－

IH

IH

－

－

IL

IL

－

IH

－

IL

Read Cycle

－

－

－
－

－

－

－
－

Write Cycle

－

－
－

－

t

CSR(47)

CP(43)

t

WCS(27)

t

t

RWL(31)

LZ(21)

UT51C164

256K X 16 BIT EDO DRAM

t

RP(3)

t

RSH(12)

t

CAS(5)

t

RRH(15)

t

RCH(14)

t

HZ(22)

D

OUT

t

t

WCH(28)

CWL(26)

V

V

－

－

IH

IH

OE

OE

V

V

－

－

IL

DQ

IL

V

－

IH

V

－

IL

t

DS(32)

t

DH(33)

D

IN

Don't Care

Undefined

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

18



Rev 1.4

UTRON

UTRON EDO Mode, X16 (2CAS) Device Timing Diagram

―

―

Waveforms of CAS - before - RAS Refresh Cycle

RAS

RASRAS

UCAS,

UCAS,
LCAS

LCAS

DQ

t

RP(3)

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

RPC(48)

t

CP(43)

t

CSR(47)

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

HZ(22)

V

－

OH

V

－

OL

t

CHR(49)

t

RAS(1)

UT51C164

256K X 16 BIT EDO DRAM

t

RC(2)

t

RP(3)

Note: WE, OE = A0-A8= Don't care

Don't care

Undefined

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

19



Rev 1.4

UTRON

UTRON EDO Mode, X16 (2CAS) Device Timing Diagram

―

Waveforms of Hidden Refresh Cycle (Read)

t

RAS

RASRAS

UCAS,

UCAS,
LCAS

LCAS

Address

WE

WEWE

OE

OE

DQ

RC(2)

t

t

t

RCD(6)

RAH(9)

t

RAC(19)

RAS(1)

t

AR(23)

COLUMN
ADDRESS

t

RCS(7)

t

t

CAH(11)

t

RSH(12)

CAA(20)

t

LZ(21)

t

CAC(18)

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

CRP(13)

V

V

－

－

IH

IH

V

V

－

－

IL

IL

t

ASR(8)

V

－

IH

V

－

IL

V

V

－

－

IH

IH

V

V

－

－

IL

IL

V

V

－

－

IH

IH

V

V

－

－

IL

IL

V

－

OH

V

－

OL

ROW

ADD

t

RAD(24)

t

ASC(10)

t

RRH(15)

t

RP(3)

t

OAC(17)

VALID DATA

UT51C164

256K X 16 BIT EDO DRAM

t

t

CHR(49)

t

RAS(1)

t

RC(2)

HZ(22)

t

HZ(22)

t

t

CRP(13)

RP(3)

Don't Care

Undefined

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

20



Rev 1.4

UTRON

UTRON EDO Mode, X16 (2CAS) Device Timing Diagram

―

Waveforms of Hidden Refresh Cycle (Write)

t

RAS

UCAS,
LCAS

Address

WE

RC(2)

t

t

t

RAH(9)

RCD(6)

t

AR(23)

RAS(1)

t

t

COLUMN

ADDRESS

RSH(12)

CAH(11)

t

－

－

V

V

IH

IH

－

－

V

V

IL

IL

t

CRP(13)

－

－

V

V

IH

IH

－

－

V

V

IL

IL

t

ASR(8)

－

V

IH

－

V

IL

－

－

V

V

IH

IH

－

－

V

V

IL

IL

ROW

ADD

t

t

t

WCS(27)

RAD(24)

ASC(10)

WCH(28)

t

RP(3)

UT51C164

256K X 16 BIT EDO DRAM

t

t

CHR(49)

t

RC(2)

RAS(1)

t

CRP(13)

t

RP(3)

－

V

IH

OE

－

V

IL

t

DQ

DS(32)

－

V

IH

－

V

IL

t

DH(33)

VALID DATA -IN

t

DHR(46)

don't care



Undefined

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

21



Rev 1.4

UTRON

UTRON EDO Mode, X16 (2CAS) Device Timing Diagram

Waveforms of EDO-Page-Mode Read-Early-Write Cycle

―

(Pseudo Read-Modify-Write)

－

－

V

V

IH

IH

RAS

UCAS

LCAS

Address

WE

WE

OE

－

－

V

V

IL

IL

t

t

CRP

－

－

V

V

IH

IH

－

－

V

V

IL

IL

t

ASR

－

V

IH

－

V

IL

－

－

V

V

IH

IH

－

－

V

V

IL

IL

－

－

V

V

IH

IH

－

－

V

V

IL

IL

ROW

ADD

CSH

t

RCD

t

AR

t

RAD

t

t

ASC

RAH

t

RCS

t

RAC

COLUMN

ADDRESS

t

CAS

t

CAH

t

CAA

t

CAC

t

t

PC

t

CP

t

ASC

COLUMN

ADDRESS

t

CAP

OE

UT51C164

256K X 16 BIT EDO DRAM

t

RAS

t

t

t

CAH

t

CAA

t

COH

PC

CAS

t

CAC

CP

t

t

ASC

COLUMN

ADDRESS

t

RCH

t

WCS

t

DS

t

RSH

t

CAS

t

CAR

t

CAH

t

WCH

t

DH

t

RP

t

CP

DQ

V

OH

－

V

OL

VALID

DATA -OUT

VALID

VALID

DATA -OUT

DATA -OUT

VALID

VALID

DATA - IN

DATA - IN

Don't care

Undefined

－

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

22



Rev 1.4

UTRON

PACKAGE OUTLINE DIMENSION

40 pin 400mil SOJ Package Outline Dimension

UT51C164

256K X 16 BIT EDO DRAM

UNIT：MIL

SYMBOLS MIN. NOR. MAX.

A 130 134 138
A1 0.24 - ­A2 106 110 114

D 1025 BSC.

E 400 BSC.

H 430 440 450

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

23



UTRON

Rev 1.4

40 pin 400mil TSOP-Ⅱ Package Outline Dimension

256K X 16 BIT EDO DRAM

UT51C164

MM(BASE)

A 1.20(MAX)
A1 0.10±0.05
A2 1.00±0.05

b 0.30~0.45

t 0.13(TYP)

D 18.41±0.10

E1 10.16±0.10

E 11.76±0.20

e 0.80(TYP)

L 0.50±0.10

L1 0.80(REF)

θ

0° ~8°

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

24



Rev 1.4

UTRON

256K X 16 BIT EDO DRAM

UT51C164

ORDERING INFORMATION

PART NO.

UT51C164JC-35 35 40-PIN SOJ
UT51C164JC-40 40 40-PIN SOJ
UT51C164JC-50 50 40-PIN SOJ
UT51C164JC-60 60 40-PIN SOJ
UT51C164MC-35 35

UT51C164MC-40 40
UT51C164MC-50 50
UT51C164MC-60 60

ACCESS TIME

(ns)

PACKAGE

40-PIN TSOP-Ⅱ
40-PIN TSOP-Ⅱ
40-PIN TSOP-Ⅱ
40-PIN TSOP-Ⅱ

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

25



Rev 1.4

UTRON

256K X 16 BIT EDO DRAM

UT51C164

REVISION HISTORY

REVISION DESCRIPTION DATE

Rev. 1.0 Original. Apr 30 ,1999
Rev. 1.1 Add 40 pin TSOP-II Package. Jun 7 ,1999
Rev. 1.2 Add 3.3V range. Jul 30,1999
Rev. 1.3 Revised Datasheet name to be UT51C164/UT51L164. Sep 22,2000
Rev. 1.4 1. Separated VDD=5V and VDD=3.3V version.

2. Revise symbols “RAS#、CAS#、OE#、WE#” to be

、

“

RAS、CAS、OE

WE

”.

Jan 23,2002

UTRON TECHNOLOGY INC. P90005
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: [phone] FAX: [phone]

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