Toshiba TX79 Series, TX7901, TMPR7901 User Manual

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TX System RISC

TX79 Family

TMPR7901

(Symmetric 2-way superscalar

64-bit CPU)

The information contained herein is subject to change without notice.

The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others.

TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..

The Toshiba products listed in this document are intended for usage in general electronics applications ( computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of Toshiba products listed in this document shall be made at the customer’s own risk.

The products described in this document may include products subject to the foreign exchange and foreign trade laws.

Table Of Contents

TABLE OF CONTENTS

CHAPTER 1. INTRODUCTION........................................................................................................1-1

1.1 O

1.2 T

VERVIEW

ERMINOLOGY

................................................................................................................................1-1

.........................................................................................................................1-1

1.2.1 Abbreviations used...............................................................................................................1-1

1.2.2 Other Terminology...............................................................................................................1-3

1.3 C

ONVENTIONS

..........................................................................................................................1-3

CHAPTER 2. FEATURES...................................................................................................................2-1

CHAPTER 3. CONFIGURATION..................................................................................................... 3-1

3.1 RESET

ONFIGURATION

...........................................................................................................3-4

CHAPTER 4. ADDRESS MAPS......................................................................................................... 4-1

4.1 M

4.2 R

EMORY MAP

EGISTER MAP

..........................................................................................................................4-1

.........................................................................................................................4-2

CHAPTER 5. C790 PROCESSOR CORE......................................................................................... 5-1

5.1 F

5.2 B

EATURES

LOCK DIAGRAM AND FUNCTIONAL BLOCK DESCRIPTIONS

5.3 C790 R

5.4 FPU R

5.5 M

5.6 C

5.7 F

5.8 P

5.9 D

EMORY MANAGEMENT

ACHE MEMORY LOATING POINT UNIT ERFORMANCE MONITOR

EBUG FUNCTIONS

.................................................................................................................................5-1

....................................................5-2

EGISTERS

......................................................................................................................5-4

.......................................................................................................................5-4

..........................................................................................................5-4

......................................................................................................................5-4

.............................................................................................................5-5

.........................................................................................................5-5

...................................................................................................................5-6

CHAPTER 6. SDRAM MEMORY CONTROLLER........................................................................ 6-1

6.1 O

6.2 F

6.3 A

6.4 T

VERVIEW

EATURES

DDRESS SPACE DECODING

WO-STAGE DECODING PROCESS

................................................................................................................................6-1

.................................................................................................................................6-1

.....................................................................................................6-1

............................................................................................6-1

6.4.1 Default Memory Map........................................................................................................... 6-6

6.4.2 Example connection of DIMMs ...........................................................................................6-6

6.5 R

EGISTERS

................................................................................................................................6-7

6.5.1 Parameters register............................................................................................................. 6-9

6.5.2 Operation Mode Register (0x1E00_0040) R/W.................................................................6-12

6.5.3 ECC Mode Register (0x1E00_0050) R/W..........................................................................6-15

6.5.4 ECC Error Status Register (read only) (0x1E00_0060)....................................................6-16

6.5.5 ECC Error Address Register (read only) (0x1E00_0070)................................................. 6-17

6.5.6 Refresh Register (0x1E00_0090) R/W...............................................................................6-17

6.5.7 SDRAM Interface Output Drive-Strength Control Register (0x1E00_00A0) R/W.............6-18

6.5.8 DIMM 0 LOW Address Decode (0x1E00_0100) ...............................................................6-18

6.5.9 DIMM 0 HIGH Address Decode (0x1E00_0110).............................................................. 6-19

6.5.10 DIMM 1 LOW Address Decode (0x1E00_0120)............................................................... 6-19

6.5.11 DIMM1 HIGH Address Decode (0x1E00_0130)............................................................... 6-19

6.5.12 DIMM 2 LOW Address Decode (0x1E00_0140)............................................................... 6-20

6.5.13 DIMM 2 HIGH Address Decode (0x1E00_0150).............................................................. 6-21

6.5.14 DIMM 3 LOW Address Decode (0x1E00_0160)............................................................... 6-21

6.5.15 DIMM 3 HIGH Address Decode (0x1E00_0170).............................................................. 6-21

6.6 A

6.7 D

DDRESS MAPPING

ECC G

ATA

................................................................................................................6-22

ENERATION

.......................................................................................................6-23

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

6.8 SDRAM I

NITIALIZATION

.......................................................................................................6-25

CHAPTER 7. C790 BUS / G-BUS BRIDGE...................................................................................... 7-1

7.1 I

7.2 A

7.3 B

7.4 E

7.5 B

7.6 R

NTRODUCTION

DDRESS SPACE DECODE AND TRANSLATION

US TRANSACTIONS NDIANNESS

US ERRORS

EGISTERS

.........................................................................................................................7-1

..........................................................................7-2

.................................................................................................................7-2

.............................................................................................................................7-3

.............................................................................................................................7-4

................................................................................................................................7-5

7.6.1 System Configuration Register ............................................................................................ 7-6

7.6.2 C790 Bus Control Register..................................................................................................7-6

7.6.3 C790 Bus Status Register.....................................................................................................7-8

7.6.4 C790 Bus Bad Address Register..........................................................................................7-9

7.6.5 CG Upper Internal Register Address (UIRA)......................................................................7-9

7.6.6 CG Lower Internal Register Address (LIRA).....................................................................7-10

7.6.7 CG Upper ROM Address Register (UROMA) ................................................................... 7-10

7.6.8 CG Lower ROM Address Register (LROMA)....................................................................7-11

7.6.9 CG Upper PCI Address Register (CGUPA0, CGUPA1, CGUPA2, CGUPA3)................. 7-11

7.6.10 CG Lower PCI Address Register (CGLPA0, CGLPA1, CGLPA2, CGLPA3) ...................7-12

7.6.11 GC Upper Internal Register Address Register (GCUIRA) ................................................7-12

7.6.12 GC Lower Internal Register Address Register (GCLIRA).................................................7-13

7.6.13 GC Upper Memory Address Register (GCUMAx)............................................................. 7-13

7.6.14 GC Lower Memory Address Register (GCLMAx) .............................................................7-14

7.6.15 Interrupt Status Register (IRSTAT)....................................................................................7-14

7.6.16 Interrupt Mask Register (IRMSK)......................................................................................7-16

7.6.17 C790 Bus Latency Timer (LT)............................................................................................7-16

7.6.18 NMI Status Register (NRSTAT)..........................................................................................7-17

7.6.19 G-Bus Master Latency Timer............................................................................................. 7-17

7.6.20 G- Bus Broken Master Latency Timer............................................................................... 7-18

7.6.21 G- Bus Slave Latency Timer ..............................................................................................7-18

7.6.22 G-Bus Retry Timer.............................................................................................................7-19

7.6.23 GC Control Register.........................................................................................................7-20

7.6.24 G-Bus Status Register........................................................................................................7-21

7.6.25 G-Bus Bad Address Register..............................................................................................7-22

7.6.26 G-Bus Arbiter Request Status Register..............................................................................7-22

7.6.27 G-Bus Arbiter Granted Status Register............................................................................. 7-23

7.6.28 G-Bus Arbiter Master Status Register.............................................................................. 7-24

7.6.29 G-Bus Arbiter Control Register.........................................................................................7-24

CHAPTER 8. PCI/G-BUS BRIDGE...................................................................................................8-1

8.1 PCI/G-B

US BRIDGE

(“PGB”)................................................................................................... 8-1

8.1.1 Overview..............................................................................................................................8-1

8.1.2 PCI / G-Bus Bridge Interface Signals..................................................................................8-4

8.2 T

HEORY OF OPERATION

............................................................................................................8-5

8.2.1 G-Bus Write to PCI (Bridge Master Write)......................................................................... 8-5

8.2.2 G-Bus Master Reading from PCI (Bridge Master Read).....................................................8-6

8.2.3 PCI Master Writing to G-Bus Slave (Bridge Target Write)................................................. 8-9

8.2.4 PCI Master Reading from G-Bus Slave (Bridge Target Read).......................................... 8-10

8.2.5 Doorbell Feature............................................................................................................... 8-11

8.2.6 PCI Transaction Commands Supported. ...........................................................................8-11

8.2.7 Lower Address Bits............................................................................................................8-12

8.2.8 G-Bus to PCI Address Mapping, Addition method............................................................8-12

8.2.9 PCI to G-Bus Address Mapping........................................................................................ 8-13

8.2.10 Bus Error Handling Policies ............................................................................................. 8-13

8.2.11 PCI Bus Arbiter ................................................................................................................. 8-15

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

Table Of Contents

8.2.12 Reset...................................................................................................................................8-16

8.2.13 Retry requests .................................................................................................................... 8-17

8.3 PGB M

EMORY MAP

...............................................................................................................8-18

8.3.1 PCI Configuration Registers..............................................................................................8-18

8.3.2 PGB G-Bus Registers.........................................................................................................8-20

8.4 R

EGISTER DUAL-PORTING

......................................................................................................8-30

8.4.1 pgbCSR[1] Dual Porting...................................................................................................8-30

8.4.2 p2gBase[3] Dual Porting.................................................................................................. 8-30

8.4.3 Protection Strategy............................................................................................................ 8-30

8.5 PCI C

............................................................................................................................... 8-31

ORE

8.5.1 Overview............................................................................................................................8-31

8.5.2 Features.............................................................................................................................8-31

8.6 A

RCHITECTURE

......................................................................................................................8-32

8.6.1 Major Internal Modules.....................................................................................................8-32

8.6.2 I/O Signals for PCI Core...................................................................................................8-34

8.6.3 TRDY_TIMEOUT .............................................................................................................. 8-36

8.6.4 RETRY_TIMEOUT ............................................................................................................8-36

8.6.5 PCI Target Delayed Read Handling.................................................................................. 8-36

8.7 C

ONFIGURATION REGISTER DESCRIPTIONS

............................................................................8-37

8.7.1 PCI Vendor ID Register.....................................................................................................8-37

8.7.2 PCI Device ID Register .....................................................................................................8-37

8.7.3 PCI Command Register..................................................................................................... 8-37

8.7.4 PCI Status Register............................................................................................................ 8-38

8.7.5 Device Revision Identification Register.............................................................................8-38

8.7.6 Class Code Register...........................................................................................................8-39

8.7.7 Cache-Line Size Register...................................................................................................8-39

8.7.8 Master Latency Timer Register.......................................................................................... 8-40

8.7.9 Header Type.......................................................................................................................8-40

8.7.10 Subsystem Vendor ID......................................................................................................... 8-40

8.7.11 Subsystem ID Register....................................................................................................... 8-41

8.7.12 Interrupt Line Register.......................................................................................................8-41

8.7.13 Interrupt Pin Register........................................................................................................8-41

8.7.14 MIN_GNT Register............................................................................................................8-42

8.7.15 MAX_LAT Register............................................................................................................8-42

8.7.16 TRDY Timeout Value......................................................................................................... 8-42

8.7.17 Retry Timeout Value .......................................................................................................... 8-43

CHAPTER 9. DMA CONTROLLER................................................................................................. 9-1

9.1 M

ODES OF OPERATION

.............................................................................................................9-2

9.1.1 DMA Channel Priority.........................................................................................................9-2

9.1.2 Source and Destination........................................................................................................9-3

9.1.3 Block Transfers....................................................................................................................9-3

9.1.4 Slice Transfers..................................................................................................................... 9-4

9.1.5 C790 Cycle Stealing ............................................................................................................9-4

9.1.6 Chain Mode .........................................................................................................................9-6

9.1.7 Appending to The End of a Chain........................................................................................9-6

9.1.8 Bus Error............................................................................................................................. 9-6

9.1.9 32-/64-bit G-Bus I/O............................................................................................................ 9-7

9.1.10 Memory Byte Alignment Support.........................................................................................9-7

9.1.11 Restarting a Disabled Channel............................................................................................9-8

9.1.12 Reprogramming an Active Channel..................................................................................... 9-8

9.1.13 Restrictions.......................................................................................................................... 9-8

9.2 R

EGISTERS

................................................................................................................................9-9

9.2.1 Channel Control Registers (CCR0 - CCR7)...................................................................... 9-10

9.2.2 Channel Status Register (CSR0 – CSR7)...........................................................................9-13

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

iii

Table Of Contents

9.2.3 Source Address Registers (SAR0 - SAR7)..........................................................................9-14

9.2.4 Destination Address Register (DAR0 - DAR7)..................................................................9-15

9.2.5 Byte Count Register (BCR0 – BCR7).................................................................................9-15

9.2.6 Next Record Pointer Registers (NRPR0 – NRPR7)........................................................... 9-16

9.2.7 Global Control and Status Register (GCSR) ..................................................................... 9-16

9.2.8 C790 Bus Error Address Register (CBEADDR)................................................................9-17

9.2.9 G-Bus Error Address Register (GBEADDR)..................................................................... 9-18

CHAPTER 10. PROGRAMMABLE TIMER/COUNTERS............................................................. 10-1

10.1 F

EATURES

............................................................................................................................... 10-1

10.1.1 Interval Timer Mode..........................................................................................................10-1

10.1.2 Pulse Generator Mode....................................................................................................... 10-1

10.1.3 Watchdog Timer Mode.......................................................................................................10-1

10.1.4 Internal or External Clock Division ..................................................................................10-1

10.2 B

10.3 S

10.4 C

LOCK DIAGRAMS

IGNALS

ONFIGURATION REGISTERS

.................................................................................................................................10-4

..................................................................................................................10-2

..................................................................................................10-5

10.4.1 Timer Control Registers TMTCR0, TMTCR1, TMTCR2................................................... 10-6

10.4.2 Interval Timer Mode Registers TMITMR0, TMITMR1, TMITMR2................................... 10-7

10.4.3 Divider Registers TMCCDR0, TMCCDR1, TMCCDR2....................................................10-8

10.4.4 Pulse Generator Mode Registers TMPGMR1, TMPGMR2...............................................10-9

10.4.5 Watchdog Timer Mode Register (TMWTMR) Fields.......................................................10-10

10.4.6 Timer Interrupt Status Registers TMTISR0, TMTISR1, TMTISR2...................................10-11

10.4.7 Fields for Timer Compare Registers A (TMCPRAx) and B (TMCPRBx)........................10-13

10.4.8 Timer Read Registers (TMTRR0, TMTRR1, TMTRR2)....................................................10-14

10.5 P

ROGRAMMABLE TIMER/COUNTER OPERATION

...................................................................10-14

10.5.1 Interval Timer Mode Operation....................................................................................... 10-14

10.5.2 Pulse Generator Mode Operation ...................................................................................10-18

10.5.3 Watchdog Timer Mode Operation...................................................................................10-20

10.5.4 Examples of Timer/Counter Timing.................................................................................10-21

CHAPTER 11. INTERRUPT CONTROLLER................................................................................. 11-1

11.1 I

11.2 O

11.3 R

NTRODUCTION

PERATION

EGISTERS

.......................................................................................................................11-1

.............................................................................................................................11-1

..............................................................................................................................11-2

11.3.1 Interrupt Status Register (IRSTAT)...................................................................................11-2

11.3.2 Interrupt Mask Register (IRMASK).................................................................................. 11-3

CHAPTER 12. 10/100 IEEE802.3 MEDIA ACCESS CONTROLLER........................................... 12-1

12.1 O

VERVIEW

..............................................................................................................................12-1

12.1.1 C790 and MAC DMA.........................................................................................................12-2

12.1.2 MAC and MII ..................................................................................................................... 12-3

12.2 MII (M

12.3 MAC R

EDIUM INDEPENDENT INTERFACE

EGISTERS AND COUNTERS

).............................................................................. 12-4

..........................................................................................12-5

12.3.1 Register Functionality and Field Descriptions..................................................................12-8

12.3.2 Counters...........................................................................................................................12-28

12.3.3 MIIM (Media Independent Interface Management)........................................................ 12-33

12.3.4 Address Filtering ........................................................................................................ ..... 12-34

12.3.5 FIFO Addresses...............................................................................................................12-36

12.4 M

EMORY ORGANIZATION (FRAME DESCRIPTOR

).................................................................12-37

12.4.1 Descriptor Lists and Data Buffers...................................................................................12-37

12.4.2 Receive Descriptors.........................................................................................................12-38

12.4.3 Transmit Descriptors.......................................................................................................12-39

12.5 F

UNCTIONAL DESCRIPTION

..................................................................................................12-42

12.5.1 DMA................................................................................................................................. 12-42

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

Table Of Contents

12.5.2 FIFO Operation............................................................................................................... 12-45

12.5.3 MII Interface............................................................................................................ ........ 12-49

12.5.4 Interrupt........................................................................................................................... 12-49

12.5.5 Reset.................................................................................................................................12-49

CHAPTER 13. REMOVED.................................................................................................................13-1

CHAPTER 14. UARTS WITH FIFOS ............................................................................................... 14-1

14.1 O

VERVIEW

..............................................................................................................................14-1

14.1.1 Key Features......................................................................................................................14-2

14.1.2 Introduction....................................................................................................................... 14-2

14.2 F

UNCTIONAL DESCRIPTION

....................................................................................................14-2

14.2.1 Transmit Operation............................................................................................................14-2

14.2.2 Receive Operation ............................................................................................................. 14-3

14.2.3 Modem Control Lines........................................................................................................ 14-3

14.3 I

NTERFACE SIGNALS

14.4 UART D

EVICE REGISTER DESCRIPTION

...............................................................................................................14-3

.................................................................................14-4

14.4.1 UART Device Register Addressing....................................................................................14-4

14.4.2 Receive Buffer Register (RBR0, RBR1).............................................................................14-6

14.4.3 Transmit Holding Registers (THR0, THR1).......................................................................14-6

14.4.4 Line Control Registers (LCR0, LCR1)............................................................................... 14-6

14.4.5 Line Status Registers (LSR0,LSR1).................................................................................... 14-8

14.4.6 FIFO Control Registers (FCR0, FCR1).......................................................................... 14-10

14.4.7 Interrupt Identification Registers (IIR0, IIR1).................................................................14-11

14.4.8 Interrupt Enable Registers (IER0, IER1).........................................................................14-13

14.4.9 Modem Control Registers (MCR0, MCR1)..................................................................... 14-13

14.4.10 Modem Status Registers (MSR0, MSR1).........................................................................14-14

14.4.11 Scratch Registers (SCR0, SCR1).................................................................................... 14-15

14.4.12 Pre-scalar Register......................................................................................................... 14-15

14.4.13 Divisor Latch LS and MS Registers (DLL, DLM)........................................................... 14-16

14.5 S

PECIAL FEATURES

...............................................................................................................14-17

14.5.1 Transmit Machine Timing................................................................................................ 14-17

14.5.2 THR Empty Interrupt Timing...........................................................................................14-17

14.5.3 FIFO Reset Timing .......................................................................................................... 14-17

14.5.4 Rx Line Status Interrupt Timing....................................................................................... 14-17

14.5.5 Timeout interrupt timing..................................................................................................14-17

14.6 I

MPLEMENTED RESTRICTIONS

...............................................................................................14-18

14.6.1 Package pins....................................................................................................................14-18

CHAPTER 15. SERIAL PORT INTERFACE................................................................................... 15-1

15.1 O

15.2 B

VERVIEW

OOT MEMORY SEQUENCER FOR WORD ACCESS

..............................................................................................................................15-1

(BM/W).................................................... 15-3

15.2.1 Boot ROM (64 KB) ............................................................................................................15-5

15.3 TSEI O

15.4 TSEI

TRANSFERS

VERVIEW

....................................................................................................................15-7

...................................................................................................................15-8

15.4.1 TSEI Clock Phase and Polarity Controls .......................................................................... 15-8

15.4.2 TSEI Data and Clock Timing............................................................................................. 15-8

15.5 TSEI S

IGNALS AND PINS

........................................................................................................15-8

15.5.1 SCLK Pin........................................................................................................................... 15-8

15.5.2 SDMISO and SDMOSI.......................................................................................................15-9

15.5.3 SS_N...................................................................................................................................15-9

15.6 TSEI T

RANSFER FORMATS

.....................................................................................................15-9

15.6.1 CPHA Equals 0 Format..................................................................................................... 15-9

15.6.2 CPHA EQUALS 1 FORMAT ........................................................................................... 15-10

15.7 MCU I

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

NTERFACE

.................................................................................................................15-11

Table Of Contents

15.7.1 Read Access..................................................................................................................... 15-11

15.7.2 Write Access.....................................................................................................................15-11

15.8 TSEI REGISTERS............................................................................................................... 15-12

15.8.1 Control Register (SECR)..................................................................................................15-12

15.8.2 TSEI STATUS REGISTER (SESR)...................................................................................15-13

15.8.3 TSEI Data Register (SEDR)............................................................................................. 15-16

15.8.4 TSEI Data Direction Register (DDCR) ........................................................................... 15-16

15.9 TSEI S

15.10 I

NTERRUPT GENERATION

YSTEM ERRORS

.........................................................................................................15-17

......................................................................................................15-17

15.10.1 Compatibility Mode........................................................................................................ 15-17

15.10.2 Toshiba Mode.................................................................................................................15-18

15.10.3 Interrupt Generation on TSIC0 ......................................................................................15-18

CHAPTER 16. CLOCKS.....................................................................................................................16-1

16.1 O

16.2 F

16.3 O

16.4 P

VERVIEW

EATURES

PERATION

ERIPHERAL MODULE CLOCK

..............................................................................................................................16-1

............................................................................................................................... 16-2

.............................................................................................................................16-5

................................................................................................16-6

16.4.1 MAC Clock.........................................................................................................................16-6

16.4.2 UART Clock.......................................................................................................................16-6

16.4.3 SPI Clock........................................................................................................................... 16-7

16.4.4 PCI Clock...........................................................................................................................16-7

16.4.5 Timer Clock .......................................................................................................................16-7

CHAPTER 17. PINS............................................................................................................................. 17-1

17.1 JTAG B

OUNDARY SCAN EXTERNAL TEST CHAIN CONFIGURATION

.........................................17-5

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

TABLE OF FIGURES

Table Of Contents

IGURE

3-1 TX7901 B 3-2 A

TYPICAL SYSTEM UTILIZING

4-1 M

EMORY MAP

5-1 C790 B 6-1 TWO6-2 I

NITIAL SETTING AFTER RESET

6-3 E

XAMPLE CONNECTION OF SINGLE-SIDED

6-4 E

XAMPLE CONNECTION OF DOUBLE-SIDED

6-5 SDRAM R 6-6 E

XAMPLE TIMING PARAMETERS

6-7 C

HECK MATRIX FO R DATA

6-8 R

EAD MODIFY WRITE TRANSACTION BY THE

7-1 C790 B 7-2 G-B 7-3 BI-E 8-1 T

OP LEVEL BLOCK DIAGRAM

8-2 PGB S 8-3 W

RITE TO

8-4 G-B 8-5 S

TATE DIAGRAM FOR

8-6 PCI M 8-7 PCI M 8-8 G-B 8-9 PCI 8-10 T

RANSACTIONS WITH A

8-11 PCI A 8-12 H

IGH LEVEL ARCHITECTURE OF

8-13 PCI 9-1 R

OUND-ROBIN PRIORITY SCHEME

9-2 DMA C 9-3 C790 B 9-4 C790 B 9-5 C790 B 9-6 DMAC O 10-1 T

IMER MODULE CONNECTIONS INSIDE THE

10-2 T

IMER

10-3 I

NTERVAL TIMER OPERATION USING INTERNAL CLOCK

10-4 I

NTERVAL TIMER OPERATION USING EXTERNAL CLOCK

10-5 P

ULSE GENERATOR MODE OPERATION

10-6 W 10-7 I

NTERVAL TIMING EXAMPLE USING INTERNAL CLOCK

10-8 I

NTERVAL TIMING EXAMPLE USING EXTERNAL INPUT CLOCK

10-9 P

ULSE GENERATOR MODE TIMING EXAMPLE

10-10 W

LOCK DIAGRAM

..........................................................................................................................4-1

LOCK DIAGRAM

STAGE DECODING

EGISTERS

/ G-B

RIDGE ADDRESS TRANSLATION

NDIAN SUPPORT

IGNALS

US MASTER READ FROM

ASTER WRITING TO THE ASTER READING FROM

US TO

G-B

RBITER IMPLEMENTATION

AND APPLICATION SIGNALS FOR

HANNEL US OPERATIONS WITH CYCLE STEALING US OPERATIONS WITHOUT CYCLE STEALING US UNALIGNED ADDRESS CYCLE BREAK DOWN

0, T

ATCHDOG TIMER MODE OPERATION OF TIMER/COUNTER

ATCHDOG TIMER TIMING EXAMPLE

US BRIDGE BLOCK DIAGRAM

...........................................................................................................................8-3

PCI

FROM

PCI A

DDRESS MAPPING

US ADDRESS MAPPING

5 ....................................................................................................................9-5

PERATION

IMER

12-1 TX7901 10/100 MAC B 12-2 MAC M 12-3 F 12-4 F 12-5 I 12-6 D 12-7 R 12-8 T 14-1 UART B

EMORY SHARING WITH IELDS OF IELDS OF

MPERFECT FILTERING OF INCOMING FRAMES

ESCRIPTOR RING AND CHAIN STRUCTURE ECEIVE DESCRIPTOR FORMAT RANSMIT DESCRIPTOR FORMAT

MIIM C MIIM D

LOCK DIAGRAM

.......................................................................................................3-1

TX7901.................................................................................... 3-3

.............................................................................................................5-2

............................................................................................................6-2

.................................................................................................6-3

DIMMS..................................................................6-4

DIMMS................................................................6-5

................................................................................................................6-8

.............................................................................................6-10

ECC C

..................................................................................6-23

ODE

SDRAM C

.........................................................................7-1

.........................................................................................7-2

................................................................................................................7-3

...................................................................................................8-2

G-BUS.....................................................................................................8-6

PCI.............................................................................................8-8

G-B

US MASTER READ FROM

G-BUS...................................................................................8-10

G-BUS.....................................................................................8-11

, A

DDITION METHOD

........................................................................................8-13

G-B

US MASTER

...............................................................................8-14

..........................................................................................8-16

PCI

..........................................................................8-33

CORE

PCI C

ORE

...........................................................................................9-3

..................................................................................................................9-8

TX7901............................................................ 10-2

AND TIMER

2 C

ONNECTIONS

..............................................................................10-19

....................................................................10-22

..............................................................................10-22

LOCK DIAGRAM

.............................................................................12-1

C790.................................................................................. 12-2

ONTROL REGISTER

ATA REGISTER

...............................................................................12-33

......................................................................................12-34

....................................................................12-34

.......................................................................12-37

..........................................................................................12-38

.......................................................................................12-40

.....................................................................................................14-1

ONTROLLER

...................................6-24

PCI ..........................................................8-8

........................................................8-12

...................................................................8-34

.....................................................................9-5

...............................................................9-5

..........................................................9-7

..................................................................10-3

.....................................................10-16

....................................................10-16

..............................................10-20

......................................................10-21

..........................................10-21

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

Table Of Contents

IGURE

15-1 SPI M 15-2 TSEI B

EMORY MAP

LOCK DIAGRAM

15-3 CPHA E 15-4 CPHA E 15-5 MCU I 15-6 TSIC0

NTERFACE SIGNALING

BEHAVIOR

16-1 TX7901 C 16-2 TX7901 C

...............................................................................................................15-2

........................................................................................................15-7

0 T

QUALS QUALS

RANSFER FORMAT

1 T

RANSFER FORMAT

.............................................................................................15-11

, C

OMPATIBILITY MODE LOCK DOMAIN DIAGRAM LOCK DISTRIBUTION DIAGRAM

..................................................................................15-9

................................................................................15-10

.........................................................................15-19

.....................................................................................16-3

...........................................................................16-4

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

TABLE OF TABLES

Table Of Tables

ABLE

4-1 L 6-1 I 6-2 E 6-3 L 6-4 SDRAM M 7-1 L 7-2 S 7-3 C790 B 7-4 C790 B 7-5 C790 B 7-6 CG U 7-7 CG L 7-8 CG U 7-9 CG L 7-10 CG U 7-11 CG U 7-12 GC U 7-13 GC L 7-14 GC U 7-15 GC L 7-16 C790 I 7-17 G-B 7-18 C790 I 7-19 C790 B 7-20 NMI S 7-21 G-B 7-22 G-B 7-23 G-B 7-24 G-B 7-25 T 7-26 G-B 7-27 C790 B 7-28 G-B 7-29 G-B 7-30 G-B 7-31 G-B 7-32 G-B 8-1 S 8-2 G-B 8-3 S 8-4 PGB PCI C 8-5 PCI W 8-6 PGB R 8-7 PGB C 8-8 G2PU 8-9 G2PL 8-10 G2PB 8-11 G2PC 8-12 IA A 8-13 P2GB 8-14 G2PS 8-15 P2GS 8-16

7901 D

IST OF

NITIAL VALUES AFTER RESET

XAMPLE VALUES FOR FOUR

SDRAM M

IST OF

G-B

IST OF YSTEM CONFIGURATION REGISTER FIELDS

US CONTROL REGISTER FIELDS US STATUS REGISTER FIELDS US BAD ADDRESS REGISTER FIELDS

PPER

OWER INTERNAL REGISTER ADDRESS REGISTER FIELDS

PPER

OWER

PPER PPER LOWER PPER INTERNAL REGISTER ADDRESS REGISTER FIELDS

OWER INTERNAL REGISTER ADDRESS REGISTER FIELDS

PPER MEMORY ADDRESS REGISTER FIELDS

OWER MEMORY ADDRESS REGISTER FIELDS

NTERRUPT STATUS REGISTER FIELDS

US INTERRUPT SOURCE TABLE

NTERRUPT MASK REGISTER FIELDS

TATUS REGISTER US MASTER LATENCY TIMER US BROKEN MASTER LATENCY TIMER US SLAVE LATENCY TIMER RIDGE RETRY TIMER FIELDS

GC C

RIDGE STATUS REGISTER FIELDS

US ARBITER REQUEST STATUS REGISTER FIELDS US ARBITRATION REQUEST TABLE US ARBITER GRANTED REGISTER FIELDS US ARBITER MASTER STATUS REGISTER FIELDS US ARBITER GRANTED REGISTER FIELDS

IGNAL DESCRIPTION

US BURST SIZES

UPPORTED

INDOW SIZES

EGISTER ADDRESS MAP ONTROL AND STATUS REGISTER FIELD DESCRIPTIONS

PPER ADDRESS REGISTER FIELD DEFINITIONS

OWER ADDRESS REGISTER FIELD DESCRIPTIONS

ASE ADDRESS REGISTER FIELD DESCRIPTIONS

YCLETYPE REGISTER FIELD DEFINITIONS

DDRESS REGISTER FIELD DEFINITIONS

ASE ADDRESS REGISTER FIELD DESCRIPTIONS WAPCTRL REGISTER FIELD DESCRIPTIONS WAPCTRL REGISTER FIELD DESCRIPTIONS

REGSWAPCTRL REGISTER FIELD DESCRIPTIONS

EVICE REGISTERS

EMORY CONTROLLER REGISTERS

ODE REGISTER SETTINGS

US BRIDGE REGISTERS (BASE ADDRESS

I/O A

DDRESS REGISTER FIELDS

ROM A

DDRESS REGISTER FIELDS

ROM A

DDRESS REGISTER FIELDS

PCI A

DDRESS REGISTER FIELDS

PCI A

US LATENCY TIMER

.........................................................................................................7-17

ONTROL REGISTER FIELDS

US STATUS REGISTER FIELDS

.................................................................................................................8-4

..................................................................................................................8-9

PCI

TRANSAC TIO N TYP E S

ONFIGURATION REGISTER MAP

.................................................................................................................8-19

..............................................................................................4-3

...................................................................................................6-6

DIMMS......................................................................................6-6

DDRESS REGISTER FIELDS

...................................................................................................7-16

..........................................................................................7-17

.............................................................................................7-18

...........................................................................................7-19

................................................................................................8-20

...............................................................6-7

......................................................................................6-14

= 0X1E00_2000) .................................... 7-5

.............................................................................7-6

.....................................................................................7-7

........................................................................................7-8

..............................................................................7-9

...............................................................................7-9

................................................7-10

.........................................................................7-10

........................................................................7-11

............................................................7-12

................................................7-12

..............................................7-13

.................................................................7-13

................................................................7-14

.........................................................................7-14

........................................................................................7-15

............................................................................7-16

...........................................................................7-18

....................................................................................7-20

....................................................................................7-21

....................................................................................7-22

...........................................................7-22

.................................................................................7-23

.......................................................................7-23

............................................................7-24

.......................................................................7-24

.....................................................................................8-11

.............................................................................8-18

.................................................8-21

................................................................8-23

............................................................8-23

.............................................................8-24

.....................................................................8-24

..........................................................................8-25

.............................................................8-26

.....................................................................8-27

.....................................................................8-28

....................................................................8-29

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

8-17 P

ABLE

8-18 E

ABLE

8-19 C

ABLE

8-20 C

ABLE

8-21 C

ABLE

8-22 C

ABLE

8-23 C

ABLE

8-24 C

ABLE

8-25 C

ABLE

8-26 C

ABLE

8-27 C

ABLE

8-28 C

ABLE

8-29 H

ABLE

8-30 S

ABLE

8-31 S

ABLE

8-32 I

ABLE

8-33 I

ABLE

8-34 MIN_GNT R

ABLE

8-35 MAX_LAT R

ABLE

8-36 C

ABLE

8-37 C

ABLE

9-1 B

ABLE

9-2 DMAC R

ABLE

9-3 C

ABLE

9-4 C

ABLE

9-5 S

ABLE

9-6 D

ABLE

9-7 C

ABLE

9-8 N

ABLE

9-9 G

ABLE

9-10 C790 B

ABLE

9-11 G-B

ABLE

10-1 T

ABLE

10-2 TX7901 P

ABLE

10-3 T

ABLE

10-4 F

ABLE

10-5 F

ABLE

10-6 F

ABLE

10-7 F

ABLE

10-8 W

ABLE

10-9 F

ABLE

10-10 F

ABLE

10-11 F

ABLE

10-12 I

ABLE

10-13 D

ABLE

11-1 M

ABLE

11-2 I

ABLE

11-3 I

ABLE

11-4 I

ABLE

12-1 MII I

ABLE

12-2 MAC C

ABLE

12-3 MAC C

ABLE

12-4 MIIM (M

ABLE

12-5 MAC “P

ABLE

12-6 MAC H

ABLE

Table Of Tables

ROTECTION LEVELS

NABLES FROM

ONTROL AND DATA FROM

ONTROL ONFIGURATION ONFIGURATION

ONFIGURATION

ONFIGURATION DEVICE REVISION IDENTIFICATION REGISTER ONFIGURATION CLASS CODE REGISTER ONFIGURATION CACHE-LINE SIZE REGISTER

ONFIGURATION MASTER LATENCY TIMER REGISTER

EADER TYPE REGISTER

UBSYSTEM VENDOR

UBSYSTEM NTERRUPT LINE REGISTER NTERRUPT PIN REGISTER

ONFIGURATION ONFIGURATION RETRY TIMEOUT VALUE

LOCK A N D SLICE TRANSFER TYPES

HANNEL CONTROL REGISTER FIELD DESCRIPTIONS HANNEL STATUS REGISTER FIELD DESCRIPTIONS

OURCE ADDRESS REGISTER FIELD DEFINITIONS

ESTINATION ADDRESS REGISTER FIELD DEFINITIONS

URRENT BYTE COUNT REGISTER FIELD DEFINITIONS

EXT RECORD POINTER REGISTER FIELD DEFINITIONS LOBAL CONTROL AND STATUS REGISTER FIELD DESCRIPTIONS

IMER MODES AND CHANNELS

IMER/COUNTER CONFIGURATION REGISTERS IELD DESCRIPTIONS FOR TIMER CONTROL REGISTERS IELDS DESCRIPTIONS OF INTERVAL TIMER MODE REGISTERS IELD DESCRIPTIONS FOR DIVIDER REGISTERS IELD DESCRIPTIONS FOR PULSE GENERATOR MODE REGISTERS

ATCHDOG TIMER MODE REGISTER

IELD DESCRIPTIONS FOR TIMER INTERRUPT STATUS REGISTERS

IELD DESCRIPTIONS FOR TIME COMPARE REGISTERS IELD DESCRIPTIONS OF TIMER READ REGISTERS

NTERRUPT CONTROL WITH THE

ASKABLE INTERRUPT SOURCES NTERRUPT CONTROLLER REGISTERS NTERRUPT STATUS REGISTER FIELD DESCRIPTION NTERRUPT MASK REGISTER FIELD DESCRIPTION

& D

ID R

EGISTER

EGISTERS

US ERROR ADDRESS REGISTER FIELD DESCRIPTIONS

ROGRAMMABLE TIMER/COUNTER SIGNALS

IVIDER VALUES AND COUNTER FREQUENCIES GENERATED

NTERFACE SIGNALS

ONFIGURATION REGISTERS OUNTERS

EDIA INDEPENDENT INTERFACE MANAGEMENT

ERFECT TABLE

ASH TABLE V ALUES

.............................................................................................................8-30

PGB C

ORE TO

ATA SIGNALS FROM CORE TO

PCI V

ENDOR

PCI D

EVICE

PCI C PCI S

TATUS REGISTER

I/O P

ID R

OMMAND REGISTER

, L

ADS

ADS TO CORE

EGISTER

...............................................................................8-38

ISTED ALPHABETICALLY

, L

ISTED ALPHABETICALLY

I/O P

, L

ADS

ISTED ALPHABETICALLY

.........................................................................8-37

...........................................................................8-37

..........................................................................8-37

...............................................................................8-39

.......................................................................8-39

.........................................................8-40

.......................................................................................................8-40

ID R

EGISTER

.....................................................................................................8-41

.......................................................................................8-40

...................................................................................................8-41

......................................................................................................8-41

............................................................................................................8-42

EGISTER

...........................................................................................................8-42

TRDY T

IMEOUT VALUE

............................................................................8-42

............................................................................8-43

.........................................................................................9-4

....................................................................................................................9-9

..............................................................9-11

.................................................................9-13

....................................................................9-14

...........................................................9-15

..........................................................9-16

................................................9-17

.....................................................9-18

.............................................................................................10-1

..........................................................10-4

......................................................................10-5

TMTCRX........................................10-6

TMCCDR0, TMCCDR1, TMCCDR2........ 10-8

(TMWTMR) F

IELD DESCRIPTIONS

TMCPRAX, TMCPRBX..............10-13

TMTRRX............................................10-14

TIIE

AND

TZCE

......................................................10-15

BITS

..........................................................................................11-1

....................................................................................11-2

...............................................................11-2

.................................................................11-3

.......................................................................................................12-4

.......................................................................................12-5

...................................................................................................................12-6

) R

EGISTERS

” V

.........................................................................................12-7

ALUES

...................................................................................................12-7

....................................8-35

.........................8-35

..............8-35

...........................................8-38

...........................................9-16

TMITMRX..........................10-7

TMPGMRX.....................10-9

...........................10-10

TMTISRX.....................10-11

............................................10-17

..................................12-7

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

12-7 CCR

ABLE

12-8 TFCR

ABLE

12-9 RFCR

ABLE

12-10 R

ABLE

12-11 TSR

ABLE

12-12 RSR

ABLE

12-13 TIMR

ABLE

12-14 TIR

ABLE

12-15 RIMR

ABLE

12-16 RIR

ABLE

12-17 S

ABLE

12-18 S

ABLE

12-19 B

ABLE

12-20 TPFTR

ABLE

12-21 VLAN T

ABLE

12-22 TDPR

ABLE

12-23 RDPR

ABLE

12-24 CDPR

ABLE

12-25 TCDR

ABLE

12-26 RCDR

ABLE

12-27 IPGR

ABLE

12-28 I

ABLE

12-29 NBTBR

ABLE

12-30 IPGT

ABLE

12-31 MIIM C

ABLE

12-32 MIIM D

ABLE

12-33 P

ABLE

12-34 R

ABLE

12-35 T

ABLE

14-1 S

ABLE

14-2 D

ABLE

14-3 D

ABLE

14-4 L

ABLE

14-5 T

ABLE

14-6 L

ABLE

14-7 FIFO C

ABLE

14-8 R

ABLE

14-9 F

ABLE

14-10 I

ABLE

14-11 F

ABLE

14-12 M

ABLE

14-13 M

ABLE

14-14 P

ABLE

14-15 C

ABLE

15-1 SPI R

ABLE

15-2 TSEI S

ABLE

16-1 TX7901 C

ABLE

16-2 PLL S

ABLE

16-3 C

ABLE

16-4 E

ABLE

16-5 SPI C

ABLE

17-1 TX7901 P

ABLE

17-2 TX7901 P

ABLE

Table Of Tables

EG REGISTER FIELD DESCRIPTIONS

EG REGISTER FIELD DESCRIPTIONS EG REGISTER FIELD DESCRIPTIONS

ECEIVE MODES WHEN RXALL IS 1 OR

EG REGISTER FIELD DESCRIPTIONS EG REGISTER FIELD DESCRIPTIONS

EG REGISTER FIELD DESCRIPTIONS

EG REGISTER FIELD DESCRIPTIONS TATION ADDRESS TATION ADDRESS

US ERROR ADDRESS REGISTER FIELD DESCRIPTIONS

EG REGISTER FIELD DESCRIPTIONS

AG REGISTER FIELD DESCRIPTIONS

EG REGISTER FIELD DESCRIPTIONS

EG REGISTER FIELD DESCRIPTIONS EG REGISTER FIELD DESCRIPTIONS EG REGISTER FIELD DESCRIPTIONS

EG REGISTER FIELD DESCRIPTIONS

NTER PACKET GAP T VALUES FOR

EG REGISTER FIELD DESCRIPTIONS

VALUES FOR

ONTROL REGISTER FIELD DESCRIPTIONS

ATA REGISTER FIELD DESCRIPTIONS

ERFECT TABLE FIELD DESCRIPTIONS

ECEIVE DESCRIPTOR FIELD DESCRIPTIONS

RANSMIT DESCRIPTOR FIELD DESCRIPTIONS

I/O S

ERIAL

EVICE REGISTER ADDRESSING FOR

EVICE REGISTER ADDRESSING FOR INE CONTROL REGISTER FIELD DESCRIPTIONS RANSMIT AND RECEIVE CHARACTER SIZE

INE STATUS REGISTER FIELDS

ONTROL REGISTER FIELD DESCRIPTIONS

FIFO T

ECEIVE IELDS OF INTERRUPT IDENTIFICATION REGISTERS

NTERPRETATION OF THE FIELDS OF THE INTERRUPT IDENTIFICATION REGISTERS

IELD S OF INTERRUPT ENABLE REGISTERS

ODEM CONTROL REGISTER FIELDS

ODEM STATUS REGISTER FIELDS

RESCALER OUTPUT AND DIVIDE VALUES FOR VARIOUS

LOCK FREQUENCY AND PERCENT ERROR

EGISTER ADDRESSES (FOR

PECIFICATIONS

LOCKS

ELECTION

LOCK GEAR RATIO XAMPLE FREQUENCY RELATIONSHIP

LOCK FREQUENCY

IN FUNCTIONALITY IN POSITIONS

I R

EGISTER FIELD DESCRIPTIONS

II R

EGISTER FIELD DESCRIPTIONS

100 M

B AND

IGNAL DESCRIPTIONS

..............................................................................................14-8

RIGGER LEVELS

...........................................................................................................15-3

...................................................................................................................16-1

....................................................................................................................16-5

..............................................................................................................16-5

........................................................................................................16-7

.................................................................................................17-1

..........................................................................................................17-4

.................................................................................12-8

..............................................................................12-9

...........................................................................12-12

0 ........................................................................... 12-13

............................................................................12-14

............................................................................12-16

..........................................................................12-17

.............................................................................12-18

.........................................................................12-19

.............................................................................12-20

........................................................12-21

......................................................12-21

.....................................................12-22

........................................................................12-22

.....................................................................12-23

.........................................................................12-23

.........................................................................12-24

.........................................................................12-25

..........................................................................12-26

100 MB / 10 MB.........................................................12-26

......................................................................12-27

10 MB............................................................................12-27

..............................................................12-33

....................................................................12-34

...............................................................................12-35

......................................................................12-38

...................................................................12-40

........................................................................................14-3

UARTS 0 & 1: L UARTS 0 & 1: B

ITTLE ENDIAN MODE

IG ENDIAN MODE

........................14-5

.............................14-5

....................................................................14-6

...........................................................................14-6

.................................................................14-10

.........................................................................................14-11

.............................................................14-11

.........................................................................14-13

..................................................................................14-13

....................................................................................14-14

CPU & G-B

US CLOCKS

.........................................................................14-16

TSEI) ................................................................................. 15-1

..................................................................................16-6

.............14-11

..............14-16

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

iii

Handling Precautions

1 Using Toshiba Semiconductors Safely

1. Using Toshiba Semiconductors Safely

TOSHIBA are continually working to improve the quality and the reliability of their products.

Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to observe standards of safety, and to avoid situations in which a malfunction or failure of a TOSHIBA product could cause loss of human life, bodily injury or damage to property.

In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent products specifications. Also, please keep in mind the precautions and conditions set forth in the TOSHIBA Semiconductor Reliability Handbook.

1-1

1 Using Toshiba Semiconductors Safely

1-2

2. Safety Precautions

This section lists important precautions which users of semiconductor devices (and anyone else) should observe in order to avoid injury and damage to property, and to ensure safe and correct use of devices.

Please be sure that you understand the meanings of the labels and the graphic symbol described below before you move on to the detailed descriptions of the precautions.

[Explanation of labels]

[Explanation of labels][Explanation of labels]

Indicates an imminently hazardous situation which will result in death or serious injury if you do not follow instructions.

Indicates a potentially hazardous situation which could result in death or serious injury if you do not follow instructions.

Indicates a potentially hazardous situation which if not avoided, may result in minor injury or moderate injury.

2 Safety Precautions

[Explanation of graphic symbol]

[Explanation of graphic symbol][Explanation of graphic symbol]

Graphic symbol Meaning

Indicates that caution is required (laser beam is dangerous to eyes).

2-1

2 Safety Precautions

2.1 General Precautions regarding Semiconductor Devices

Do not use devices under conditions exceeding their absolute maximum ratings (e.g. current, voltage, power dissipation or

temperature).

This may cause the device to break down, degrade its performance, or cause it to catch fire or explode resulting in injury.

Do not insert devices in the wrong orientation.

Make sure that the positive and negative terminals of power supplies are connected correctly. Otherwise the rated maximum

current or power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to

catch fire or explode and resulting in injury.

When power to a device is on, do not touch the device’s heat sink.

Heat sinks become hot, so you may burn your hand.

Do not touch the tips of device leads.

Because some types of device have leads with pointed tips, you may prick your finger.

When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment’s electrodes or probes to

the pins of the device under test before powering it on.

Otherwise, you may receive an electric shock causing injury.

Before grounding an item of measuring equipment or a soldering iron, check that there is no electrical leakage from it.

Electrical leakage may cause the device which you are testing or soldering to break down, or could give you an electric shock.

Always wear protective glasses when cutting the leads of a device with clippers or a similar tool.

If you do not, small bits of metal flying off the cut ends may damage your eyes.

2-2

2 Safety Precautions

2.2 Precautions Specific to Each Product Group

2.2.1 Optical semiconductor devices

When a visible semiconductor laser is operating, do not look directly into the laser beam or look through the optical system.

This is highly likely to impair vision, and in the worst case may cause blindness.

If it is necessary to examine the laser apparatus, for example to inspect its optical characteristics, always wear the appropriate

type of laser protective glasses as stipulated by IEC standard IEC825-1.

Ensure that the current flowing in an LED device does not exceed the device’s maximum rated current.

This is particularly important for resin-packaged LED devices, as excessive current may cause the package resin to blow up,

scattering resin fragments and causing injury.

When testing the dielectric strength of a photocoupler, use testing equipment which can shut off the supply voltage to the

photocoupler. If you detect a leakage current of more than 100 µA, use the testing equipment to shut off the photocoupler’s

supply voltage; otherwise a large short-circuit current will flow continuously, and the device may break down or burst into flames,

resulting in fire or injury.

When incorporating a visible semiconductor laser into a design, use the device’s internal photodetector or a separate

photodetector to stabilize the laser’s radiant power so as to ensure that laser beams exceeding the laser’s rated radiant power

cannot be emitted.

If this stabilizing mechanism does not work and the rated radiant power is exceeded, the device may break down or the

excessively powerful laser beams may cause injury.

2.2.2 Power devices

Never touch a power device while it is powered on. Also, after turning off a power device, do not touch it until it has thoroughly

discharged all remaining electrical charge.

Touching a power device while it is powered on or still charged could cause a severe electric shock, resulting in death or serious

injury.

When conducting any kind of evaluation, inspection or testing, be sure to connect the testing equipment’s electrodes or probes to

the device under test before powering it on.

When you have finished, discharge any electrical charge remaining in the device.

Connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causing

injury.

2-3

2 Safety Precautions

Do not use devices under conditions which exceed their absolute maximum ratings (current, voltage, power dissipation,

temperature etc.).

This may cause the device to break down, causing a large short-circuit current to flow, which may in turn cause it to catch fire or

explode, resulting in fire or injury.

Use a unit which can detect short-circuit currents and which will shut off the power supply if a short-circuit occurs.

If the power supply is not shut off, a large short-circuit current will flow continuously, which may in turn cause the device to catch

fire or explode, resulting in fire or injury.

When designing a case for enclosing your system, consider how best to protect the user from shrapnel in the event of the device

catching fire or exploding.

Flying shrapnel can cause injury.

When conducting any kind of evaluation, inspection or testing, always use protective safety tools such as a cover for the device.

Otherwise you may sustain injury caused by the device catching fire or exploding.

Make sure that all metal casings in your design are grounded to earth.

Even in modules where a device’s electrodes and metal casing are insulated, capacitance in the module may cause the

electrostatic potential in the casing to rise.

Dielectric breakdown may cause a high voltage to be applied to the casing, causing electric shock and injury to anyone touching it.

When designing the heat radiation and safety features of a system incorporating high-speed rectifiers, remember to take the

device’s forward and reverse losses into account.

The leakage current in these devices is greater than that in ordinary rectifiers; as a result, if a high-speed rectifier is used in an

extreme environment (e.g. at high temperature or high voltage), its reverse loss may increase, causing thermal runaway to occur.

This may in turn cause the device to explode and scatter shrapnel, resulting in injury to the user.

A design should ensure that, except when the main circuit of the device is active, reverse bias is applied to the device gate while

electricity is conducted to control circuits, so that the main circuit will become inactive.

Malfunction of the device may cause serious accidents or injuries.

When conducting any kind of evaluation, inspection or testing, either wear protective gloves or wait until the device has cooled

properly before handling it.

Devices become hot when they are operated. Even after the power has been turned off, the device will retain residual heat which

may cause a burn to anyone touching it.

2.2.3 Bipolar ICs (for use in automobiles)

If your design includes an inductive load such as a motor coil, incorporate diodes or similar devices into the design to prevent

negative current from flowing in.

The load current generated by powering the device on and off may cause it to function erratically or to break down, which could in

turn cause injury.

Ensure that the power supply to any device which incorporates protective functions is stable.

If the power supply is unstable, the device may operate erratically, preventing the protective functions from working correctly. If

protective functions fail, the device may break down causing injury to the user.

2-4

3 General Safety Precautions and Usage Considerations

3. General Safety Precautions and Usage Considerations

This section is designed to help you gain a better understanding of semiconductor devices, so as to ensure the safety, quality and reliability of the devices which you incorporate into your designs.

3.1 From Incoming to Shipping

3.1.1 Electrostatic discharge (ESD)

When handling individual devices (which are not yet mounted on a printed circuit board), be sure that the environment is protected against electrostatic electricity. Operators should wear anti-static clothing, and containers and other objects which come into direct contact with devices should be made of anti-static materials and should be grounded to earth via an 0.5- to 1.0-MΩ protective resistor.

Please follow the precautions described below; this is particularly important for devices which are marked “Be careful of static.”.

(1) Work environment

•

When humidity in the working environment decreases, the human body and other insulators can easily become charged with static electricity due to friction. Maintain the recommended humidity of 40% to 60% in the work environment, while also taking into account the fact that moisture-proof-packed products may absorb moisture after unpacking.

•

Be sure that all equipment, jigs and tools in the working area are grounded to earth.

•

Place a conductive mat over the floor of the work area, or take other appropriate measures, so that the floor surface is protected against static electricity and is grounded to earth. The surface resistivity should be 10

Ω

•

Cover the workbench surface also with a conductive mat (with a surface resistivity of 104 to

Ω/sq, for a resistance between surface and ground of 7.5 × 105 to 10

10 is to disperse static electricity on the surface (through resistive components) and ground it to earth. Workbench surfaces must not be constructed of low-resistance metallic materials that allow rapid static discharge when a charged device touches them directly.

•

Pay attention to the following points when using automatic equipment in your workplace:

(a) When picking up ICs with a vacuum unit, use a conductive rubber fitting on the end of the

pick-up wand to protect against electrostatic charge.

(b) Minimize friction on IC package surfaces. If some rubbing is unavoidable due to the device’s

mechanical structure, minimize the friction plane or use material with a small friction coefficient and low electrical resistance. Also, consider the use of an ionizer.

to 108 Ω/sq and the resistance between surface and ground, 7.5 × 105 to

Ω) . The purpose of this

dissipates static electricity.

(d) Ensure that no statically charged bodies (such as work clothes or the human body) touch

the devices.

3-1

3 General Safety Precautions and Usage Considerations

(e) Make sure that sections of the tape carrier which come into contact with installation

devices or other electrical machinery are made of a low-resistance material.

(f) Make sure that jigs and tools used in the assembly process do not touch devices.

(g) In processes in which packages may retain an electrostatic charge, use an ionizer to

neutralize the ions.

•

Make sure that CRT displays in the working area are protected against static charge, for example by a VDT filter. As much as possible, avoid turning displays on and off. Doing so can cause electrostatic induction in devices.

•

Keep track of charged potential in the working area by taking periodic measurements.

•

Ensure that work chairs are protected by an anti-static textile cover and are grounded to the floor surface by a grounding chain. (Suggested resistance between the seat surface and grounding chain is 7.5 × 10

to 10

Ω.)

•

Install anti-static mats on storage shelf surfaces. (Suggested surface resistivity is 104 to 10

Ω/sq; suggested resistance between surface and ground is 7.5 × 10

•

For transport and temporary storage of devices, use containers (boxes, jigs or bags) that are made of anti-static materials or materials which dissipate electrostatic charge.

•

Make sure that cart surfaces which come into contact with device packaging are made of materials which will conduct static electricity, and verify that they are grounded to the floor surface via a grounding chain.

•

In any location where the level of static electricity is to be closely controlled, the ground resistance level should be Class 3 or above. Use different ground wires for all items of equipment which may come into physical contact with devices.

(2) Operating environment

•

Operators must wear anti-static clothing and conductive shoes (or a leg or heel strap).

•

Operators must wear a wrist strap grounded to earth via a resistor of about 1 MΩ.

•

Soldering irons must be grounded from iron tip to earth, and must be used only at low voltages (6 V to 24 V).

to 108 Ω.)

•

If the tweezers you use are likely to touch the device terminals, use anti-static tweezers and in particular avoid metallic tweezers. If a charged device touches a low-resistance tool, rapid discharge can occur. When using vacuum tweezers, attach a conductive chucking pat to the tip, and connect it to a dedicated ground used especially for anti-static purposes (suggested resistance value: 10

•

Do not place devices or their containers near sources of strong electrical fields (such as above a CRT).

to 108 Ω).

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3 General Safety Precautions and Usage Considerations

•

When storing printed circuit boards which have devices mounted on them, use a board container or bag that is protected against static charge. To avoid the occurrence of static charge or discharge due to friction, keep the boards separate from one other and do not stack them directly on top of one another.

•

Ensure, if possible, that any articles (such as clipboards) which are brought to any location where the level of static electricity must be closely controlled are constructed of anti-static materials.

•

In cases where the human body comes into direct contact with a device, be sure to wear antistatic finger covers or gloves (suggested resistance value: 10

•

Equipment safety covers installed near devices should have resistance ratings of 109 Ω or less.

•

If a wrist strap cannot be used for some reason, and there is a possibility of imparting friction to devices, use an ionizer.

•

The transport film used in TCP products is manufactured from materials in which static charges tend to build up. When using these products, install an ionizer to prevent the film from being charged with static electricity. Also, ensure that no static electricity will be applied to the product’s copper foils by taking measures to prevent static occuring in the peripheral equipment.

Ω or less).

3.1.2 Vibration, impact and stress

Handle devices and packaging materials with care. To avoid damage to devices, do not toss or drop packages. Ensure that devices are not subjected to mechanical vibration or shock during transportation. Ceramic package devices and devices in canister-type packages which have empty space inside them are subject to damage from vibration and shock because the bonding wires are secured only at their ends.

Plastic molded devices, on the other hand, have a relatively high level of resistance to vibration and mechanical shock because their bonding wires are enveloped and fixed in resin. However, when any device or package type is installed in target equipment, it is to some extent susceptible to wiring disconnections and other damage from vibration, shock and stressed solder junctions. Therefore when devices are incorporated into the design of equipment which will be subject to vibration, the structural design of the equipment must be thought out carefully.

If a device is subjected to especially strong vibration, mechanical shock or stress, the package or the chip itself may crack. In products such as CCDs which incorporate window glass, this could cause surface flaws in the glass or cause the connection between the glass and the ceramic to separate.

Furthermore, it is known that stress applied to a semiconductor device through the package changes the resistance characteristics of the chip because of piezoelectric effects. In analog circuit design attention must be paid to the problem of package stress as well as to the dangers of vibration and shock as described above.

Vibration

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3.2 Storage

3.2.1 General storage

•

Avoid storage locations where devices will be exposed to moisture or direct sunlight.

•

Follow the instructions printed on the device cartons regarding transportation and storage.

•

The storage area temperature should be kept within a temperature range of 5°C to 35°C, and relative humidity should be maintained at between 45% and 75%.

•

Do not store devices in the presence of harmful (especially corrosive) gases, or in dusty conditions.

•

Use storage areas where there is minimal temperature fluctuation. Rapid temperature changes can cause moisture to form on stored devices, resulting in lead oxidation or corrosion. As a result, the solderability of the leads will be degraded.

•

When repacking devices, use anti-static containers.

3 General Safety Precautions and Usage Considerations

Humidity:

Temperature:

•

Do not allow external forces or loads to be applied to devices while they are in storage.

•

If devices have been stored for more than two years, their electrical characteristics should be tested and their leads should be tested for ease of soldering before they are used.

3.2.2 Moisture-proof packing

Moisture-proof packing should be handled with care. The handling procedure specified for each packing type should be followed scrupulously. If the proper procedures are not followed, the quality and reliability of devices may be degraded. This section describes general precautions for handling moisture-proof packing. Since the details may differ from device to device, refer also to the relevant individual datasheets or databook.

(1) General precautions

Follow the instructions printed on the device cartons regarding transportation and storage.

•

Do not drop or toss device packing. The laminated aluminum material in it can be rendered ineffective by rough handling.

•

The storage area temperature should be kept within a temperature range of 5°C to 30°C, and relative humidity should be maintained at 90% (max). Use devices within 12 months of the date marked on the package seal.

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3 General Safety Precautions and Usage Considerations

•

If the 12-month storage period has expired, or if the 30% humidity indicator shown in Figure 1 is pink when the packing is opened, it may be advisable, depending on the device and packing type, to back the devices at high temperature to remove any moisture. Please refer to the table below. After the pack has been opened, use the devices in a 5°C to 30°C. 60% RH environment and within the effective usage period listed on the moisture-proof package. If the effective usage period has expired, or if the packing has been stored in a high-humidity environment, bake the devices at high temperature.

Packing Moisture removal

Tray If the packing bears the “Heatproof” marking or indicates the maximum temperature which it can

withstand, bake at 125°C for 20 hours. (Some devices require a different procedure.)

Tube Transfer devices to trays bearing the “Heatproof” marking or indicating the temperature which they

can withstand, or to aluminum tubes before baking at 125°C for 20 hours.

Tape Deviced packed on tape cannot be baked and must be used within the effective usage period after

unpacking, as specified on the packing.

•

When baking devices, protect the devices from static electricity.

•

Moisture indicators can detect the approximate humidity level at a standard temperature of 25°C. 6-point indicators and 3-point indicators are currently in use, but eventually all indicators will be 3-point indicators.

HUMIDITY INDICATOR

60%

50%

40%

30%

20%

10%

READ AT LAVENDER BETWEEN PINK & BLUE

(a) 6-point indicator (b) 3-point indicator

DANGER IF PINK

HUMIDITY INDICATOR

CHANGE DESICCANT

READ AT LAVENDER BETWEEN PINK & BLUE

Figure 1 Humidity indicator

DANGER IF PINK

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3 General Safety Precautions and Usage Considerations

3.3 Design

Care must be exercised in the design of electronic equipment to achieve the desired reliability. It is important not only to adhere to specifications concerning absolute maximum ratings and recommended operating conditions, it is also important to consider the overall environment in which equipment will be used, including factors such as the ambient temperature, transient noise and voltage and current surges, as well as mounting conditions which affect device reliability. This section describes some general precautions which you should observe when designing circuits and when mounting devices on printed circuit boards.

For more detailed information about each product family, refer to the relevant individual technical datasheets available from Toshiba.

3.3.1 Absolute maximum ratings

Do not use devices under conditions in which their absolute maximum ratings (e.g. current, voltage, power dissipation or temperature) will be exceeded. A device may break down or its performance may be degraded, causing it to catch fire or explode resulting in injury to the user.

The absolute maximum ratings are rated values which must not be exceeded during operation, even for an instant. Although absolute maximum ratings differ from product to product, they essentially concern the voltage and current at each pin, the allowable power dissipation, and the junction and storage temperatures.

If the voltage or current on any pin exceeds the absolute maximum rating, the device’s internal circuitry can become degraded. In the worst case, heat generated in internal circuitry can fuse wiring or cause the semiconductor chip to break down.

If storage or operating temperatures exceed rated values, the package seal can deteriorate or the wires can become disconnected due to the differences between the thermal expansion coefficients of the materials from which the device is constructed.

3.3.2 Recommended operating conditions

The recommended operating conditions for each device are those necessary to guarantee that the device will operate as specified in the datasheet. If greater reliability is required, derate the device’s absolute maximum ratings for voltage, current, power and temperature before using it.

3.3.3 Derating

When incorporating a device into your design, reduce its rated absolute maximum voltage, current, power dissipation and operating temperature in order to ensure high reliability. Since derating differs from application to application, refer to the technical datasheets available for the various devices used in your design.

3.3.4 Unused pins

If unused pins are left open, some devices can exhibit input instability problems, resulting in malfunctions such as abrupt increase in current flow. Similarly, if the unused output pins on a device are connected to the power supply pin, the ground pin or to other output pins, the IC may malfunction or break down.

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Since the details regarding the handling of unused pins differ from device to device and from pin to pin, please follow the instructions given in the relevant individual datasheets or databook.

CMOS logic IC inputs, for example, have extremely high impedance. If an input pin is left open, it can easily pick up extraneous noise and become unstable. In this case, if the input voltage level reaches an intermediate level, it is possible that both the P-channel and N-channel transistors will be turned on, allowing unwanted supply current to flow. Therefore, ensure that the unused input pins of a device are connected to the power supply (Vcc) pin or ground (GND) pin of the same device. For details of what to do with the pins of heat sinks, refer to the relevant technical datasheet and databook.

3.3.5 Latch-up

Latch-up is an abnormal condition inherent in CMOS devices, in which Vcc gets shorted to ground. This happens when a parasitic PN-PN junction (thyristor structure) internal to the CMOS chip is turned on, causing a large current of the order of several hundred mA or more to flow between Vcc and GND, eventually causing the device to break down.

Latch-up occurs when the input or output voltage exceeds the rated value, causing a large current to flow in the internal chip, or when the voltage on the Vcc (Vdd) pin exceeds its rated value, forcing the internal chip into a breakdown condition. Once the chip falls into the latch-up state, even though the excess voltage may have been applied only for an instant, the large current continues to flow between Vcc (Vdd) and GND (Vss). This causes the device to heat up and, in extreme cases, to emit gas fumes as well. To avoid this problem, observe the following precautions:

3 General Safety Precautions and Usage Considerations

(1) Do not allow voltage levels on the input and output pins either to rise above Vcc (Vdd) or to

fall below GND (Vss). Also, follow any prescribed power-on sequence, so that power is applied gradually or in steps rather than abruptly.

(2) Do not allow any abnormal noise signals to be applied to the device.

(3) Set the voltage levels of unused input pins to Vcc (Vdd) or GND (Vss).

(4) Do not connect output pins to one another.

3.3.6 Input/Output protection

Wired-AND configurations, in which outputs are connected together, cannot be used, since this short-circuits the outputs. Outputs should, of course, never be connected to Vcc (Vdd) or GND (Vss).

Furthermore, ICs with tri-state outputs can undergo performance degradation if a shorted output current is allowed to flow for an extended period of time. Therefore, when designing circuits, make sure that tri-state outputs will not be enabled simultaneously.

3.3.7 Load capacitance

Some devices display increased delay times if the load capacitance is large. Also, large charging and discharging currents will flow in the device, causing noise. Furthermore, since outputs are shorted for a relatively long time, wiring can become fused.

Consult the technical information for the device being used to determine the recommended load capacitance.

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3.3.8 Thermal design

The failure rate of semiconductor devices is greatly increased as operating temperatures increase. As shown in Figure 2, the internal thermal stress on a device is the sum of the ambient temperature and the temperature rise due to power dissipation in the device. Therefore, to achieve optimum reliability, observe the following precautions concerning thermal design:

(1) Keep the ambient temperature (Ta) as low as possible.

(2) If the device’s dynamic power dissipation is relatively large, select the most appropriate

circuit board material, and consider the use of heat sinks or of forced air cooling. Such measures will help lower the thermal resistance of the package.

(3) Derate the device’s absolute maximum ratings to minimize thermal stress from power

dissipation.

θja = θjc + θca θja = (Tj–Ta) / P θjc = (Tj–Tc) / P θca = (Tc–Ta) / P in which θja = thermal resistance between junction and surrounding air (°C/W)

θjc = thermal resistance between junction and package surface, or internal thermal

resistance (°C/W)

θca = thermal resistance between package surface and surrounding air, or external

thermal resistance (°C/W) Tj = junction temperature or chip temperature (°C) Tc = package surface temperature or case temperature (°C) Ta = ambient temperature (°C) P = power dissipation (W)

3 General Safety Precautions and Usage Considerations

3.3.9 Interfacing

When connecting inputs and outputs between devices, make sure input voltage (VIL/VIH) and output voltage (V connecting devices operating at different supply voltages, such as in a dual-power-supply system, be aware that erroneous power-on and power-off sequences can result in device breakdown. For details of how to interface particular devices, consult the relevant technical datasheets and databooks. If you have any questions or doubts about interfacing, contact your nearest Toshiba office or distributor.

OL/VOH

θca

θjc

Figure 2 Thermal resistance of package

) levels are matched. Otherwise, the devices may malfunction. When

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3.3.10 Decoupling

Spike currents generated during switching can cause Vcc (Vdd) and GND (Vss) voltage levels to fluctuate, causing ringing in the output waveform or a delay in response speed. (The power supply and GND wiring impedance is normally 50 Ω to 100 Ω.) For this reason, the impedance of power supply lines with respect to high frequencies must be kept low. This can be accomplished by using thick and short wiring for the Vcc (Vdd) and GND (Vss) lines and by installing decoupling capacitors (of approximately 0.01 µF to 1 µF capacitance) as high-frequency filters between Vcc (Vdd) and GND (Vss) at strategic locations on the printed circuit board.

For low-frequency filtering, it is a good idea to install a 10- to 100-µF capacitor on the printed circuit board (one capacitor will suffice). If the capacitance is excessively large, however, (e.g. several thousand µF) latch-up can be a problem. Be sure to choose an appropriate capacitance value.

An important point about wiring is that, in the case of high-speed logic ICs, noise is caused mainly by reflection and crosstalk, or by the power supply impedance. Reflections cause increased signal delay, ringing, overshoot and undershoot, thereby reducing the device’s safety margins with respect to noise. To prevent reflections, reduce the wiring length by increasing the device mounting density so as to lower the inductance (L) and capacitance (C) in the wiring. Extreme care must be taken, however, when taking this corrective measure, since it tends to cause crosstalk between the wires. In practice, there must be a trade-off between these two factors.

3 General Safety Precautions and Usage Considerations

3.3.11 External noise

Printed circuit boards with long I/O or signal pattern lines are vulnerable to induced noise or surges from outside sources. Consequently, malfunctions or breakdowns can result from overcurrent or overvoltage, depending on the types of device used. To protect against noise, lower the impedance of the pattern line or insert a noise-canceling circuit. Protective measures must also be taken against surges.

For details of the appropriate protective measures for a particular device, consult the relevant databook.

3.3.12 Electromagnetic interference

Widespread use of electrical and electronic equipment in recent years has brought with it radio and TV reception problems due to electromagnetic interference. To use the radio spectrum effectively and to maintain radio communications quality, each country has formulated regulations limiting the amount of electromagnetic interference which can be generated by individual products.

Electromagnetic interference includes conduction noise propagated through power supply and telephone lines, and noise from direct electromagnetic waves radiated by equipment. Different measurement methods and corrective measures are used to assess and counteract each specific type of noise.

Input/Output

Signals

Difficulties in controlling electromagnetic interference derive from the fact that there is no method available which allows designers to calculate, at the design stage, the strength of the electromagnetic waves which will emanate from each component in a piece of equipment. For this reason, it is only after the prototype equipment has been completed that the designer can take measurements using a dedicated instrument to determine the strength of electromagnetic interference waves. Yet it is possible during system design to incorporate some measures for the prevention of electromagnetic interference, which can facilitate taking corrective measures once the design has been completed. These include installing shields and noise filters, and increasing

3-9

the thickness of the power supply wiring patterns on the printed circuit board. One effective method, for example, is to devise several shielding options during design, and then select the most suitable shielding method based on the results of measurements taken after the prototype has been completed.

3.3.13 Peripheral circuits

In most cases semiconductor devices are used with peripheral circuits and components. The input and output signal voltages and currents in these circuits must be chosen to match the semiconductor device’s specifications. The following factors must be taken into account.

(1) Inappropriate voltages or currents applied to a device’s input pins may cause it to operate

erratically. Some devices contain pull-up or pull-down resistors. When designing your system, remember to take the effect of this on the voltage and current levels into account.

(2) The output pins on a device have a predetermined external circuit drive capability. If this

drive capability is greater than that required, either incorporate a compensating circuit into your design or carefully select suitable components for use in external circuits.

3.3.14 Safety standards

Each country has safety standards which must be observed. These safety standards include requirements for quality assurance systems and design of device insulation. Such requirements must be fully taken into account to ensure that your design conforms to the applicable safety standards.

3 General Safety Precautions and Usage Considerations

3.3.15 Other precautions

(1) When designing a system, be sure to incorporate fail-safe and other appropriate measures

according to the intended purpose of your system. Also, be sure to debug your system under actual board-mounted conditions.

(2) If a plastic-package device is placed in a strong electric field, surface leakage may occur due to

the charge-up phenomenon, resulting in device malfunction. In such cases take appropriate measures to prevent this problem, for example by protecting the package surface with a conductive shield.

(3) With some microcomputers and MOS memory devices, caution is required when powering on

or resetting the device. To ensure that your design does not violate device specifications, consult the relevant databook for each constituent device.

(4) Ensure that no conductive material or object (such as a metal pin) can drop onto and short the

leads of a device mounted on a printed circuit board.

3.4 Inspection, Testing and Evaluation

3.4.1 Grounding

Ground all measuring instruments, jigs, tools and soldering irons to earth. Electrical leakage may cause a device to break down or may result in electric shock.

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3.4.2 Inspection Sequence

c Do not insert devices in the wrong orientation. Make sure that the positive

and negative electrodes of the power supply are correctly connected. Otherwise, the rated maximum current or maximum power dissipation may be exceeded and the device may break down or undergo performance degradation, causing it to catch fire or explode, resulting in injury to the user.

d When conducting any kind of evaluation, inspection or testing using AC

power with a peak voltage of 42.4 V or DC power exceeding 60 V, be sure to connect the electrodes or probes of the testing equipment to the device under test before powering it on. Connecting the electrodes or probes of testing equipment to a device while it is powered on may result in electric shock, causing injury.

(1) Apply voltage to the test jig only after inserting the device securely into it. When applying or

removing power, observe the relevant precautions, if any.

(2) Make sure that the voltage applied to the device is off before removing the device from the

test jig. Otherwise, the device may undergo performance degradation or be destroyed.

(3) Make sure that no surge voltages from the measuring equipment are applied to the device.

3 General Safety Precautions and Usage Considerations

(4) The chips housed in tape carrier packages (TCPs) are bare chips and are therefore exposed.

During inspection take care not to crack the chip or cause any flaws in it. Electrical contact may also cause a chip to become faulty. Therefore make sure that nothing comes into electrical contact with the chip.

3.5 Mounting

There are essentially two main types of semiconductor device package: lead insertion and surface mount. During mounting on printed circuit boards, devices can become contaminated by flux or damaged by thermal stress from the soldering process. With surface-mount devices in particular, the most significant problem is thermal stress from solder reflow, when the entire package is subjected to heat. This section describes a recommended temperature profile for each mounting method, as well as general precautions which you should take when mounting devices on printed circuit boards. Note, however, that even for devices with the same package type, the appropriate mounting method varies according to the size of the chip and the size and shape of the lead frame. Therefore, please consult the relevant technical datasheet and databook.

3.5.1 Lead forming

c Always wear protective glasses when cutting the leads of a device with

clippers or a similar tool. If you do not, small bits of metal flying off the cut ends may damage your eyes.

d Do not touch the tips of device leads. Because some types of device have

leads with pointed tips, you may prick your finger.

Semiconductor devices must undergo a process in which the leads are cut and formed before the devices can be mounted on a printed circuit board. If undue stress is applied to the interior of a device during this process, mechanical breakdown or performance degradation can result. This is attributable primarily to differences between the stress on the device’s external leads and the stress on the internal leads. If the relative difference is great enough, the device’s internal leads, adhesive properties or sealant can be damaged. Observe these precautions during the leadforming process (this does not apply to surface-mount devices):

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3 General Safety Precautions and Usage Considerations

(1) Lead insertion hole intervals on the printed circuit board should match the lead pitch of the

device precisely.

(2) If lead insertion hole intervals on the printed circuit board do not precisely match the lead

pitch of the device, do not attempt to forcibly insert devices by pressing on them or by pulling on their leads.

(3) For the minimum clearance specification between a device and a

printed circuit board, refer to the relevant device’s datasheet and databook. If necessary, achieve the required clearance by forming the device’s leads appropriately. Do not use the spacers which are used to raise devices above the surface of the printed circuit board during soldering to achieve clearance. These spacers normally continue to expand due to heat, even after the solder has begun to solidify; this applies severe stress to the device.

(4) Observe the following precautions when forming the leads of a device prior to mounting.

•

Use a tool or jig to secure the lead at its base (where the lead meets the device package) while bending so as to avoid mechanical stress to the device. Also avoid bending or stretching device leads repeatedly.

•

Be careful not to damage the lead during lead forming.

•

Follow any other precautions described in the individual datasheets and databooks for each device and package type.

3.5.2 Socket mounting

(1) When socket mounting devices on a printed circuit board, use sockets which match the

inserted device’s package.

(2) Use sockets whose contacts have the appropriate contact pressure. If the contact pressure is

insufficient, the socket may not make a perfect contact when the device is repeatedly inserted and removed; if the pressure is excessively high, the device leads may be bent or damaged when they are inserted into or removed from the socket.

(3) When soldering sockets to the printed circuit board, use sockets whose construction prevents

flux from penetrating into the contacts or which allows flux to be completely cleaned off.

(4) Make sure the coating agent applied to the printed circuit board for moisture-proofing

purposes does not stick to the socket contacts.

(5) If the device leads are severely bent by a socket as it is inserted or removed and you wish to

repair the leads so as to continue using the device, make sure that this lead correction is only performed once. Do not use devices whose leads have been corrected more than once.

(6) If the printed circuit board with the devices mounted on it will be subjected to vibration from

external sources, use sockets which have a strong contact pressure so as to prevent the sockets and devices from vibrating relative to one another.

3.5.3 Soldering temperature profile

The soldering temperature and heating time vary from device to device. Therefore, when specifying the mounting conditions, refer to the individual datasheets and databooks for the devices used.

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3 General Safety Precautions and Usage Considerations

(1) Using a soldering iron

Complete soldering within ten seconds for lead temperatures of up to 260°C, or within three seconds for lead temperatures of up to 350°C.

(2) Using medium infrared ray reflow

•

Heating top and bottom with long or medium infrared rays is recommended (see Figure 3).

Medium infrared ray heater (reflow)

Product flow

Long infrared ray heater (preheating)

Figure 3 Heating top and bottom with long or medium infrared rays

•

Complete the infrared ray reflow process within 30 seconds at a package surface temperature of between 210°C and 240°C.

•

Refer to Figure 4 for an example of a good temperature profile for infrared or hot air reflow.

(°C) 240

210

160

140

Package surface temperature

60-120 s

30 s

or less

Time (s)

Figure 4 Sample temperature profile for infrared or hot air reflow

(3) Using hot air reflow

•

Complete hot air reflow within 30 seconds at a package surface temperature of between 210°C and 240°C.

•

For an example of a recommended temperature profile, refer to Figure 4 above.

(4) Using solder flow

•

Apply preheating for 60 to 120 seconds at a temperature of 150°C.

•

For lead insertion-type packages, complete solder flow within 10 seconds with the temperature at the stopper (or, if there is no stopper, at a location more than 1.5 mm from the body) which does not exceed 260°C.

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3 General Safety Precautions and Usage Considerations

•

For surface-mount packages, complete soldering within 5 seconds at a temperature of 250°C or less in order to prevent thermal stress in the device.

•

Figure 5 shows an example of a recommended temperature profile for surface-mount packages using solder flow.

(°C) 250

160

140

Package surface temperature

60-120 s

Time (s)

Figure 5 Sample temperature profile for solder flow

5 s

or less

3.5.4 Flux cleaning and ultrasonic cleaning

(1) When cleaning circuit boards to remove flux, make sure that no residual reactive ions such as

Na or Cl remain. Note that organic solvents react with water to generate hydrogen chloride and other corrosive gases which can degrade device performance.

(2) Washing devices with water will not cause any problems. However, make sure that no

reactive ions such as sodium and chlorine are left as a residue. Also, be sure to dry devices sufficiently after washing.

(3) Do not rub device markings with a brush or with your hand during cleaning or while the

devices are still wet from the cleaning agent. Doing so can rub off the markings.

(4) The dip cleaning, shower cleaning and steam cleaning processes all involve the chemical

action of a solvent. Use only recommended solvents for these cleaning methods. When immersing devices in a solvent or steam bath, make sure that the temperature of the liquid is 50°C or below, and that the circuit board is removed from the bath within one minute.

(5) Ultrasonic cleaning should not be used with hermetically-sealed ceramic packages such as a

leadless chip carrier (LCC), pin grid array (PGA) or charge-coupled device (CCD), because the bonding wires can become disconnected due to resonance during the cleaning process. Even if a device package allows ultrasonic cleaning, limit the duration of ultrasonic cleaning to as short a time as possible, since long hours of ultrasonic cleaning degrade the adhesion between the mold resin and the frame material. The following ultrasonic cleaning conditions are recommended:

Frequency: 27 kHz ∼ 29 kHz

Ultrasonic output power: 300 W or less (0.25 W/cm

or less)

Cleaning time: 30 seconds or less

Suspend the circuit board in the solvent bath during ultrasonic cleaning in such a way that the ultrasonic vibrator does not come into direct contact with the circuit board or the device.

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3 General Safety Precautions and Usage Considerations

3.5.5 No cleaning

If analog devices or high-speed devices are used without being cleaned, flux residues may cause minute amounts of leakage between pins. Similarly, dew condensation, which occurs in environments containing residual chlorine when power to the device is on, may cause betweenlead leakage or migration. Therefore, Toshiba recommends that these devices be cleaned. However, if the flux used contains only a small amount of halogen (0.05W% or less), the devices may be used without cleaning without any problems.

3.5.6 Mounting tape carrier packages (TCPs)

(1) When tape carrier packages (TCPs) are mounted, measures must be taken to prevent

electrostatic breakdown of the devices.

(2) If devices are being picked up from tape, or outer lead bonding (OLB) mounting is being

carried out, consult the manufacturer of the insertion machine which is being used, in order to establish the optimum mounting conditions in advance and to avoid any possible hazards.

(3) The base film, which is made of polyimide, is hard and thin. Be careful not to cut or scratch

your hands or any objects while handling the tape.

(4) When punching tape, try not to scatter broken pieces of tape too much.

(5) Treat the extra film, reels and spacers left after punching as industrial waste, taking care not

to destroy or pollute the environment.

(6) Chips housed in tape carrier packages (TCPs) are bare chips and therefore have their reverse

side exposed. To ensure that the chip will not be cracked during mounting, ensure that no mechanical shock is applied to the reverse side of the chip. Electrical contact may also cause a chip to fail. Therefore, when mounting devices, make sure that nothing comes into electrical contact with the reverse side of the chip. If your design requires connecting the reverse side of the chip to the circuit board, please consult Toshiba or a Toshiba distributor beforehand.

3.5.7 Mounting chips

Devices delivered in chip form tend to degrade or break under external forces much more easily than plastic-packaged devices. Therefore, caution is required when handling this type of device.

(1) Mount devices in a properly prepared environment so that chip surfaces will not be exposed to

polluted ambient air or other polluted substances.

(2) When handling chips, be careful not to expose them to static electricity.

In particular, measures must be taken to prevent static damage during the mounting of chips. With this in mind, Toshiba recommend mounting all peripheral parts first and then mounting chips last (after all other components have been mounted).

(3) Make sure that PCBs (or any other kind of circuit board) on which chips are being mounted do

not have any chemical residues on them (such as the chemicals which were used for etching the PCBs).

(4) When mounting chips on a board, use the method of assembly that is most suitable for

maintaining the appropriate electrical, thermal and mechanical properties of the semiconductor devices used.

* For details of devices in chip form, refer to the relevant device’s individual datasheets.

3-15

3.5.8 Circuit board coating

When devices are to be used in equipment requiring a high degree of reliability or in extreme environments (where moisture, corrosive gas or dust is present), circuit boards may be coated for protection. However, before doing so, you must carefully consider the possible stress and contamination effects that may result and then choose the coating resin which results in the minimum level of stress to the device.

3.5.9 Heat sinks

(1) When attaching a heat sink to a device, be careful not to apply excessive force to the device in

the process.

(2) When attaching a device to a heat sink by fixing it at two or more locations, evenly tighten all

the screws in stages (i.e. do not fully tighten one screw while the rest are still only loosely tightened). Finally, fully tighten all the screws up to the specified torque.

(3) Drill holes for screws in the heat sink exactly as specified. Smooth the

surface by removing burrs and protrusions or indentations which might interfere with the installation of any part of the device.

(4) A coating of silicone compound can be applied between the heat sink and

the device to improve heat conductivity. Be sure to apply the coating thinly and evenly; do not use too much. Also, be sure to use a non-volatile compound, as volatile compounds can crack after a time, causing the heat radiation properties of the heat sink to deteriorate.

3 General Safety Precautions and Usage Considerations

(5) If the device is housed in a plastic package, use caution when selecting the type of silicone

compound to be applied between the heat sink and the device. With some types, the base oil separates and penetrates the plastic package, significantly reducing the useful life of the device. Two recommended silicone compounds in which base oil separation is not a problem are YG6260 from Toshiba Silicone.

(6) Heat-sink-equipped devices can become very hot during operation. Do not touch them, or you

may sustain a burn.

3.5.10 Tightening torque

(1) Make sure the screws are tightened with fastening torques not exceeding the torque values

stipulated in individual datasheets and databooks for the devices used.

(2) Do not allow a power screwdriver (electrical or air-driven) to touch devices.

3.5.11 Repeated device mounting and usage

Do not remount or re-use devices which fall into the categories listed below; these devices may cause significant problems relating to performance and reliability.

(1) Devices which have been removed from the board after soldering

(2) Devices which have been inserted in the wrong orientation or which have had reverse current

applied

(3) Devices which have undergone lead forming more than once

3-16

3 General Safety Precautions and Usage Considerations

3.6 Protecting Devices in the Field

3.6.1 Temperature

Semiconductor devices are generally more sensitive to temperature than are other electronic components. The various electrical characteristics of a semiconductor device are dependent on the ambient temperature at which the device is used. It is therefore necessary to understand the temperature characteristics of a device and to incorporate device derating into circuit design. Note also that if a device is used above its maximum temperature rating, device deterioration is more rapid and it will reach the end of its usable life sooner than expected.

3.6.2 Humidity

Resin-molded devices are sometimes improperly sealed. When these devices are used for an extended period of time in a high-humidity environment, moisture can penetrate into the device and cause chip degradation or malfunction. Furthermore, when devices are mounted on a regular printed circuit board, the impedance between wiring components can decrease under highhumidity conditions. In systems which require a high signal-source impedance, circuit board leakage or leakage between device lead pins can cause malfunctions. The application of a moisture-proof treatment to the device surface should be considered in this case. On the other hand, operation under low-humidity conditions can damage a device due to the occurrence of electrostatic discharge. Unless damp-proofing measures have been specifically taken, use devices only in environments with appropriate ambient moisture levels (i.e. within a relative humidity range of 40% to 60%).

3.6.3 Corrosive gases

Corrosive gases can cause chemical reactions in devices, degrading device characteristics. For example, sulphur-bearing corrosive gases emanating from rubber placed near a device (accompanied by condensation under high-humidity conditions) can corrode a device’s leads. The resulting chemical reaction between leads forms foreign particles which can cause electrical leakage.

3.6.4 Radioactive and cosmic rays

Most industrial and consumer semiconductor devices are not designed with protection against radioactive and cosmic rays. Devices used in aerospace equipment or in radioactive environments must therefore be shielded.

3.6.5 Strong electrical and magnetic fields

Devices exposed to strong magnetic fields can undergo a polarization phenomenon in their plastic material, or within the chip, which gives rise to abnormal symptoms such as impedance changes or increased leakage current. Failures have been reported in LSIs mounted near malfunctioning deflection yokes in TV sets. In such cases the device’s installation location must be changed or the device must be shielded against the electrical or magnetic field. Shielding against magnetism is especially necessary for devices used in an alternating magnetic field because of the electromotive forces generated in this type of environment.

3-17

3 General Safety Precautions and Usage Considerations

3.6.6 Interference from light (ultraviolet rays, sunlight, fluorescent lamps and

incandescent lamps)

Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases the device can malfunction. This is especially true for devices in which the internal chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. This problem is not limited to optical semiconductors and EPROMs. All types of device can be affected by light.

3.6.7 Dust and oil

Just like corrosive gases, dust and oil can cause chemical reactions in devices, which will adversely affect a device’s electrical characteristics. To avoid this problem, do not use devices in dusty or oily environments. This is especially important for optical devices because dust and oil can affect a device’s optical characteristics as well as its physical integrity and the electrical performance factors mentioned above.

3.6.8 Fire

Semiconductor devices are combustible; they can emit smoke and catch fire if heated sufficiently. When this happens, some devices may generate poisonous gases. Devices should therefore never be used in close proximity to an open flame or a heat-generating body, or near flammable or combustible materials.

3.7 Disposal of Devices and Packing Materials

When discarding unused devices and packing materials, follow all procedures specified by local regulations in order to protect the environment against contamination.

3-18

4 Precautions and Usage Considerations

4. Precautions and Usage Considerations

This section describes matters specific to each product group which need to be taken into consideration when using devices. If the same item is described in Sections 3 and 4, the description in Section 4 takes precedence.

4.1 Microcontrollers

4.1.1 Design

(1) Using resonators which are not specifically recommended for use

Resonators recommended for use with Toshiba products in microcontroller oscillator applications are listed in Toshiba databooks along with information about oscillation conditions. If you use a resonator not included in this list, please consult Toshiba or the resonator manufacturer concerning the suitability of the device for your application.

(2) Undefined functions

In some microcontrollers certain instruction code values do not constitute valid processor instructions. Also, it is possible that the values of bits in registers will become undefined. Take care in your applications not to use invalid instructions or to let register bit values become undefined.

4-1

4 Precautions and Usage Considerations

4-2

TX7901 User’s Manual

Rev. 6.30T

November, 2001

DOCUMENT NUMBER M−99−00004−07

Chapter 1: Introduction

1. Introduction

1.1 Overview

The TX7901 MIPS RISC microcontroller is a highly integrated solution based on Toshiba’s dual-issue super-scalar pipeline Processor Core, the C790 (henceforth referred to as “the C790”). The C790 has a 128-bit internal architecture featuring MIPS ISA support and additional instruction enhancements specially developed for embedded applications.

The TX7901 is a new generation MIPS processor solution offering high performance, high bandwidth and high integration, utilizing Toshiba's Computer-On-Silicon concept. This class of product is targeted for applications that require a high-performance, cost-ef fective solution such as networking, printers, and set-top boxes.

1.2 Terminology

1.2.1 Abbreviations used

802.3x IEEE 802.3x standard for Ethernet based Local Area Networks b bits (e.g. 1 Mb = 1 Mega bit) B Bytes (e.g. 4 MB = 4 Mega Bytes)

Suffix for active low signals

BIU Bus Interface Unit BTAC Branch Target Address Cache COP0 Coprocessor 0 C790 High-performance MIPS CPU Core on which the TX7901 is based C790 Bus Main system bus that connects the C790 CPU to the rest of the system

devices such as the memory controller and G-bus bridge.

D$ Data Cache Memory DIMM DRAM chip module

Set of DRAM chips that are controlled by a chip selector signal. Double-sided DIMM in this case is considered to be two DIMMs.

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

1-1

Chapter 1: Introduction

DMA Direct Memory Access DMAC Direct Memory Access Controller DRAM Dynamic RAM DTLB Data Translation Look-aside Buffer F/B Feedback FIFO “First In First Out” Buffer Fiber Fiber Physical Medium Dependent

PMD (EMAC) FPU Floating Point Unit G-Bus Proprietary Toshiba On-chip Bus Interface intended for IP interfaces I$ Instruction Cache Memory IC Integrated Circuit IP I ntellectual Property – proprietary circuit implementations from multiple

vendors intended to be incorporated into a larger IC design

ISA Instruction Set Architecture ITLB Instruction Translation Look-aside Buffer JTLB Joint Translation Look-aside Buffer MAC Mult iply-Accumulator, CPU such as iMAC (integer MAC), fMAC (floating-point

MAC) Media Access Controller, Ethernet controller such as eMAC

MBPS Million(s of) bits per second MII Media-Independent Interface MIPS I, Instruction set capabilities of successive generations of MIPS series

II, III processors NMI Non-Maskable Interrupt PCI Peripher al Component Interconnect PHY Physical Layer

Chip on which a physical layer is implemented

PLL Phase-Locked Loop R/O Read-Only

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

1-2

Chapter 1: Introduction

R/W Read/Write Rx Receive S/C Self-Clearing TBD To Be Determined TP-PMD Twisted Pair-Physical Medium Dependent TS Time Slot Tx Transmit UCAB Un-cached Accelerated Buffer UART Universal Asynchronous Receiver/Transmitter VAddr Virtual Address WBB Write-Back Buffer W/O Write-Only

1.2.2 Other Terminology

To Assert a signal means to take it to its active level. An active high signal is “1” when asserted, and an active low signal is “0” when asserted.

1.3 Conventions

• Register values are expressed in this manual as base 16 (hexadecimal) numbers, and are prefixed by the characters “0x”, which are not part of the number, in keeping with Verilog (and C) Language Terminology. In order to improve legibility, the underscore character (_) separates numbers larger than four hex digits in length into four-digit groups.

• Internal signals start with a lower case module name, followed by suffixes with capitalized initial letter(s).

• Active Low internal signals are indicated by signal names ending with the letter B.

• Signals on external pins are always written completely in UPPER CASE, for example,

BOOT16.

• Active Low external signals are indicated by signal names ending with an asterisk (*).

• A bit field within a register is referred to by the terminology: Register[bit_field] when

referring to the bit field by name, or by its bit position.

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

1-3

Chapter 2: Features

2. Features

C790 integrated high-performance RISC processor core with 128-bit internal



architecture optimized for high data throughput

• 2-way super-scalar pipeline with 128-bit (2x64-bit) data path

• 200/266 MHz operation

• MIPS I, II, III compatible ISA with selected MIPS IV ISA (Pre-fetch and Move

Conditional Instructions)

• Additional multimedia instruction set support to provide SIMD operation

• 32 KB two-way set associative Instruction Cache, and 32 KB t wo-way set associative

Data Cache

• Line lockable Data cache, write back cache (WBB), non-blocking load, and data

cache Pre-fetch instruction to enhance performance

• 64-entry fully associative branch target address cache

• 48-entry fully associative JTLB supporting 4 KB –16 MB page size. WinCE profile II

recommended.

• IEEE754 Double Precision FPU tightly coupled with the CPU core. FPU is

compatible with the TX49.

• Bi-endian (Litt le Endian and Big Endian) operations supported

Dual 10/100 Mbps Ethernet Media Access Controller with scatter-gather DMA bus



master capability (“MAC”)

• Supports 10 or 100 Mbps MII-based PHY devices including 100BASE-TX, 100BASE-

FX & 100BASE-T4

• Media-Independent Interface (MII) Management feature

• Supports ENDEC, TP-PMD & Fiber PMD devices

• Supports Half and Full Duplex operation

• Scatter-Gather DMA bus master capability

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

2-1

Chapter 2: Features

PCI/G-Bus Bridge (“PGB”)



• Fully compliant with PCI Local Bus Specification Rev. 2.1

• 32-bit PCI bus interface

• 33 MHz or 66 MHz PCI operation

• Zer o-Latency Back to Back transfers

• Supports on-chip arbitration of up to 5 masters (supports a maximum of 2 - 4

external PCI devices)

• Dual Address cycle

• Supports all PCI specific configuration registers

SDRAM Memory Controller (“SDRAMC”)



The SDRAM Memory Controller has been designed and integrated into the TX7901 processor to take advantage of high memory bandwidth to external memories. The C790 and the DMA Controller can both access memory to perform Read / Write operations. The SDRAMC supports:

• 1 GB memory with four DIMMs (8M × 8B × 4) or two double-side DIMMs

(8M × 8B × 4 × 2)

• PC 100/133 DIMM/SO-DIMM

• Internal PLL for de-skewing clock and data between the TX7901 and SDRAM

DIMMs

• Four-bank interleaving for 64/128/256 Mb SDRAMs

• Two-bank interleaving for 16 Mb SDRAMs

• ECC, single-bit err or correction, double- bit erro r detection

• Aligned burst transactions

DMA Controller (“DMAC”)



Eight independent DMA channels have been implemented for external and internal peripherals that access memory. DMA operation provides the fastest access to memory while the C790 executes in parallel from internal caches. The DMAC supports:

• Eight independent DMA channels for both internal and external DMA requests

• Chaining via linked lists of records

• Block and Slice modes

• Memory to memory, memory to peripheral, and peripheral to memory transactions

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

2-2

Chapter 2: Features

Interrupt Controller



The Interrupt controller in the TX7901 supports both internal and external interrupts to the C790 core. It contains an interrupt source register to identify up to 22 different interrupt sources. In addition, there is an interrupt register mask that is used to mask interrupt sources to the C790. The supported Interrupts are:

• PCI Controller, MACs, DMAC, UARTs, Timers, SPI Interrupts, Bus errors and external interrupts

Non-Maskable Interrupt (NMI)



Non-Maskable Interrupts are used to indicate fatal conditions. ECC uncorrectable errors, the watchdog timer, and external NMI pins are sources of NMIs.

Triple Timer-Counters (“TMR”)



The three timer counters integrated into the TX7901 each have their own part icular 24-bit up counter and control registers for implementing each timer control “channel”.

• Timer 0 is an internal timer that uses the internal clock and operates in the Internal Timer Mode, which causes periodic interrupts.

• Timer 1 for Channel 1 operates in the Interval Timer Mode or Pulse Generator Mode, which generates waveforms of arbitrary frequencies and duty ratios.

• Timer 2 for Channel 2 operates in the Pulse Generator Mode and Watchdog Timer mode, monitoring system runaway conditions in the Interval Timer mode.

UART



• Dual UARTs

• Modem flow control (CTS/RTS)

• Baud rate generator

• Software-compatible with NSC NS16550A

SPI



• Master operation

• Supports Serial Boot ROM and RTC. Flash ROM and EEPROM are supported by

the Companion chip.

• Supports Atmel serial ROM as Boot ROM

HW JTAG Scan Test logic support



• JTAG external test mode for chip boundary tests facilitates board testing.

• Full SCAN design and direct memory test modes facilitat e chip testing.

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

2-3

Chapter 3: Configuration

The following is the block diagram of the TX7901:

3. Configuration

PLL

I$32K

IFU

PCU

D$32K

LSU

C790

BIU

DEBUG

FPU

64-Bit G-Bus

64-bit

Internal

G-Bus

C790 Bus

(128-bit Internal

System Bus)

Bridge

Test Logic

SDRAM

Controller

DMAC

INTC

SPI Serial

Boot R

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

Dual

UARTs

Figure 3-1 TX7901 Block Diagram

Dual

MACs

3-1

PCI

Bridge

Timers

C790



High performance MIPS RISC processor core with 128-bit internal system bus interface.

MAC



Dual 10/100Mbps Ethernet MAC with scatter-gather DMA bus master capability.

PCI Bridge



32-bit PCI bus interface compliance with PCI Local Bus Specification Rev. 2.1. PCI0 is 66 MHz/32-bit PCI. PCI1 is 33 MHz/32-bit PCI.

SDRAMC



SDRAM memory controller

DMAC



8-channel DMA controller

INTC



22 internal and external sources of interrupts, and interrupt controller for these interrupt sources.

Chapter 3: Configuration

Timers



3-channel 24-bit up counters work as the interval timer, pulse generator, and watchdog timer.

UART



2-channel serial I/Os, NS 16550 software compatible Channel 0 has full function. Channel 1 has two pins (SW, SOUT) only, and is used for the debug monitor.

SPI



Serial Peripheral Interface connects the serial Boot ROM and Real-time clock

64-Bit G-Bus Bridge



A bridge between the 128-bit internal system bus and the 64-bit G-Bus

PLL



Phase-Locked-Loop to generate the TX7901’s internal clocks from an external oscillator

Test Logic



Supports Scan and JTAG.

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

3-2

Chapter 3: Configuration

PLL

200/266 MHz*

I$ 32K

PCU

D$ 32K

IFU

SPI Dual

LSU

C790

64b/ 50 MHz 66 MHz

BIU

DEBUG

FPU

Dual

UART

MODEMS PHY

128b/ 100 MHz 133 MHz

64-Bit G-

Bus Bridge

MACs

INTC

Bridge

Test Logic

SDRAMC

DMAC

PCI

SDRAM Memory Devices

PC100/133 DIMM

Note: 266 MHz CPU and PC 133

SDRAM interfaces are being planned as premium products.

Timers

Serial ROM

Flash ROM

RTC

PCI Controller 1

e.g. USB i/f

Dial-Up

Lines

PCI Controller 2 e.g., EIDE

CDROM, HDD, etc

PCI Controller 3

e.g., IEEE1394

Figure 3-2 A typical system utilizing TX7901

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

3-3

Chapter 3: Configuration

3.1 Reset Configuration

C790: Pins define the endianness. SPI: 2 MHz (133)/1.56 MHz (100) of the bit rate accesses Boot ROM. SDRAM: 8 MB per DIMM (chip select) starting at physical address 0x0000_0000.

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

3-4

Chapter 4: Address Maps

4. Address Maps

4.1 Memory Map

The physical memory space of the TX7901 is 4 GB. The memory management unit (MMU) of the C790 manages the memory map of the TX7901. The TX7901 virtual and physical addresses are both 32 bits wide.

0xFFFF_FFFF

0x2100_0000

0x1F00_0000 0x1E00_1000

0x1E00_0000

C790 Bus G-Bus

PCI Memory

ROM

Registers

GCIRA

CGUPAn

CGLPAn

CGUPAm CGLPAm

UROMA

LROMA

UIRA

LIRA GCUIRA GCLIRA

PCI Memory

ROM

Registers

SPI

MAC DMA

PCI

0x1FC0_FFFF 0x1FC0_0000

Registers

SDRAM Memory

0x0000_0000

CGUMAn CGLMAn

CGUMAn

CGLMAn

Figure 4-1 Memory Map

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

Memory Window Memory Window

4-1

Chapter 4: Address Maps

TX7901 internal registers are mapped from 0x1E00_0000 to 0x1EFF_FFFF (16 MB). The ROM/SRAM addresses are mapped from 0x1F00_0000 to 0x20FF_FFFF (32 MB).

Main memory space (SDRAM) can be located anywhere except in the internal register range. This memory space is located on the C790 Bus. PCI memory space can also be located anywhere except in that range, and up to four segments (including one I/O space) are allowed. Note that all nine segments must be

non-overlapping

and are programmed by the user. For details, please refer to the chapters on the SDRAM memory controller and PCI controller.

4.2 Register Map

The following is the register map of the TX7901 built-in modules:

0x1E00_0000 - 0x1E00_0FFF SDRAM Memory Controller on the C790 Bus 0x1E00_1000 - 0x1E00_1FFF DMA Controller 0x1E00_2000 - 0x1E00_2FFF G-Bus Bridge and Interrupt Controller 0x1E00_3000 - 0x1E00_3FFF PCI Bridge (PGB) 0x1E00_4000 - 0x1E00_4FFF Timer/Counter 0x1E00_5000 - 0x1E00_5FFF MAC0 0x1E00_6000 - 0x1E00_6FFF MAC1 0x1E00_7000 - 0x1E00_7FFF UART0 0x1E00_8000 - 0x1E00_8FFF UART1 0x1E00_9000 - 0x1E00_9FFF SPI (TSEI) and GPIO 0x1E00_A000 - 0x1E00_AFFF PCI Bridge (PGB1): optional 0x1E00_B000 - 0x1E00_BFFF Reserved 0x1E00_C000 - 0x1E00_FFFF Reserved 0x1E01_0000 - 0x1EFF_FFFF Reserved

For more information, please refer to the chapter that pertains to the relevant module.

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

4-2

Chapter 4: Address Maps

The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information.

Table 4-1 List of 7901 Device Registers

Name Register Description Address R/W Size(b)

SDRAM Memory Controller, Base Address 0x1E00_0000

D0PR DIMM 0 Parameters Register 0x1E00_0000 R/W 128 D1PR DIMM 1 Parameters Register 0x1E00_0010 R/W 128 D2PR DIMM 2 Parameters Register 0x1E00_0020 R/W 128

D3PR DIMM 3 Parameters Register 0x1E00_0030 R/W 128 DOMR Operation Mode Register 0x1E00_0040 R/W 128 DEMR ECC Mode Register 0x1E00_0050 R/W 128

DEESR ECC Error Status Register 0x1E00_0060 R 128 DEEAR ECC Error Address Register 0x1E00_0070 R 128

– RESERVED 0x1E00_0080

DREFRESH Refresh Register 0x1E00_0090 R/W 128

DDRIVE SDRAM Interface Output Drive-Strength Control Register 0x1E00_00A0 R/W 128 D0LOW DIMM 0 LOW Address Decode 0x1E00_0100 R/W 128 D0HIGH DIMM 0 HIGH Address Decode 0x1E00_0110 R/W 128 D1LOW DIMM 1 LOW Address Decode 0x1E00_0120 R/W 128 D1HIGH DIMM 1 HIGH Address Decode 0x1E00_0130 R/W 128 D2LOW DIMM 2 LOW Address Decode 0x1E00_0140 R/W 128 D2HIGH DIMM 2 HIGH Address Decode 0x1E00_0150 R/W 128 D3LOW DIMM 3 LOW Address Decode 0x1E00_0160 R/W 128 D3HIGH DIMM 3 HIGH Address Decode 0x1E00_0170 R/W 128

DMA Controller, Base Address 0x1E0 0_ 100 0

CCR0 Channel 0 Control Register 0x1E00_1000 R/W 64 CSR0 Channel 0 Status Register 0x1E00_1010 R/W 64 SAR0 Channel 0 Source Address Register 0x1E00_1020 R/W 64 DAR0 Channel 0 Destination Address Register 0x1E00_1030 R/W 64 BCR0 Channel 0 Byte Count Register 0x1E00_104 0 R/W 64

NRPR0 Channel 0 Next Record Pointer Register 0x1E00_1050 R/W 64

-- RESERVED 0x1E00_1060 - 0x1E00_10F0

CCR1 Channel 1 Control Register 0x1E00_1100 R/W 64 CSR1 Channel 1 Status Register 0x1E00_1110 R/W 64 SAR1 Channel 1 Source Address Register 0x1E00_1120 R/W 64 DAR1 Channel 1 Destination Address Register 0x1E00_1130 R/W 64 BCR1 Channel 1 Byte Count Register 0x1E00_114 0 R/W 64

NRPR1 Channel 1 Next Record Pointer Register 0x1E00_1150 R/W 64

-- RESERVED 0x1E00_1160 - 0x1E00_11F0

CCR2 Channel 2 Control Register 0x1E00_1200 R/W 64 CSR2 Channel 2 Status Register 0x1E00_1210 R/W 64 SAR2 Channel 2 Source Address Register 0x1E00_1220 R/W 64 DAR2 Channel 2 Destination Address Register 0x1E00_1230 R/W 64 BCR2 Channel 2 Byte Count Register 0x1E00_124 0 R/W 64

NRPR2 Channel 2 Next Record Pointer Register 0x1E00_1250 R/W 64

- RESERVED 0x1E00_1260 - 0x1E00_12F0

CCR3 Channel 3 Control Register 0x1E00_1300 R/W 64 CSR3 Channel 3 Status Register 0x1E00_1310 R/W 64 SAR3 Channel 3 Source Address Register 0x1E00_1320 R/W 64 DAR3 Channel 3 Destination Address Register 0x1E00_1330 R/W 64 BCR3 Channel 3 Byte Count Register 0x1E00_134 0 R/W 64

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

4-3

Chapter 4: Address Maps

The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information.

Name Register Description Address R/W Size(b)

NRPR3 Channel 3 Next Record Pointer Register 0x1E00_1350 R/W 64

-- RESERVED 0x1E00_1360 -0x1E00_13F0

CCR4 Channel 4 Control Register 0x1E00_1400 R/W 64 CSR4 Channel 4 Status Register 0x1E00_1410 R/W 64 SAR4 Channel 4 Source Address Register 0x1E00_1420 R/W 64 DAR4 Channel 4 Destination Address Register 0x1E00_1430 R/W 64 BCR4 Channel 4 Byte Count Register 0x1E00_144 0 R/W 64

NRPR4 Channel 4 Next Record Pointer Register 0x1E00_1450 R/W 64

-- RESERVED 0x1E00_1460 -0x1E00_14F0

CCR5 Channel 5 Control Register 0x1E00_1500 R/W 64 CSR5 Channel 5 Status Register 0x1E00_1510 R/W 64 SAR5 Channel 5 Source Address Register 0x1E00_1520 R/W 64 DAR5 Channel 5 Destination Address Register 0x1E00_1530 R/W 64 BCR5 Channel 5 Byte Count Register 0x1E00_154 0 R/W 64

NRPR5 Channel 5 Next Record Pointer Register 0x1E00_1550 R/W 64

-- RESERVED 0x1E00_1560 -0x1E00_15F0

CCR6 Channel 6 Control Register 0x1E00_1600 R/W 64 CSR6 Channel 6 Status Register 0x1E00_1610 R/W 64 SAR6 Channel 6 Source Address Register 0x1E00_1620 R/W 64 DAR6 Channel 6 Destination Address Register 0x1E00_1630 R/W 64 BCR6 Channel 6 Byte Count Register 0x1E00_164 0 R/W 64

NRPR6 Channel 6 Next Record Pointer Register 0x1E00_1650 R/W 64

-- RESERVED 0x1E00_1660 -0x1E00_16F0

CCR7 Channel 7 Control Register 0x1E00_1700 R/W 64 CSR7 Channel 7 Status Register 0x1E00_1710 R/W 64 SAR7 Channel 7 Source Address Register 0x1E00_1720 R/W 64 DAR7 Channel 7 Destination Address Register 0x1E00_1730 R/W 64 BCR7 Channel 7 Byte Count Register 0x1E00_174 0 R/W 64

NRPR7 Channel 7 Next Record Pointer Register 0x1E00_1750 R/W 64

-- RESERVED 0x1E00_1760 -0x1E00_1FF0

G–Bus Bridge / Chip Configuration / Interrupt Controller, Base Address 0x1E00_2000

SCR System Configuration Register 0x1E00_2000 R 64 BCR C790 Bus Control Register 0x1E00_2008 R/W 64 BSR C790 Bus Status Register 0x1E00_2010 R/W 64

BBAR C790 Bus Bad Address Register 0x1E00_2018 R 64

UIRA CG Upper Internal Regist er Address 0x1E00_2020 R 64

LIRA CG Lower Internal Register Address 0x1E00_2028 R 64 UROMA CG Upper ROM Address Register 0x1E00_2030 R 64 LROMA CG Lower ROM Address Register 0x1E00_2038 R 64

CGUPA0 CG Upper PCI Address 0 0x1E00_2040 R/W 64

CGLPA0 CG Lower PCI Address 0 0x1E00_2048 R/W 64

CGUPA1 CG Upper PCI Address 1 0x1E00_2050 R/W 64

CGLPA1 CG Lower PCI Address 1 0x1E00_2058 R/W 64

CGUPA2 CG Upper PCI Address 2 0x1E00_2060 R/W 64

CGLPA2 CG Lower PCI Address 2 0x1E00_2068 R/W 64

CGUPA3 CG Upper PCI Address 3 0x1E00_2070 R/W 64

CGLPA3 CG Lower PCI Address 3 0x1E00_2078 R/W 64 GCUIRA GC Upper Internal Register Address 0x1E00_208 0 R 64

GCLIRA GC Lower Internal Register Address 0x1E00_2088 R 64

GCUMA0 GC Upper MEM Address 0 0x1E00_2090 R/W 64

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

4-4

Chapter 4: Address Maps

The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information.

Name Register Description Address R/W Size(b)

GCLMA0 GC Lower MEM Address 0 0x1E00_2098 R/W 64 GCUMA1 GC Upper MEM Address 1 0x1E00_20A0 R/W 64 GCLMA1 GC Lower MEM Address 1 0x1E00_20A8 R/W 64 GCUMA2 GC Upper MEM Address 2 0x1E00_20B0 R/W 64 GCLMA2 GC Lower MEM Address 2 0x1E00_20B8 R/W 64 GCUMA3 GC Upper MEM Address 3 0x1E00_20C0 R/W 64 GCLMA3 GC Lower MEM Address 3 0x1E00_20C8 R/W 64 GCUMA4 GC Upper MEM Address 4 0x1E00_20D0 R/W 64 GCLMA4 GC Lower MEM Address 4 0x1E00_20D8 R/W 64

IRSTAT Interrupt Status Register 0x1E00_20E0 R 64

IRMSK Interrupt Mask Register 0x1E00_20E8 R/W 64

LT C790 Bus Latency Timer 0x1E00_20F0 R/W 64

NRSTAT NMI Status Register 0x1E00_20F8 R 64

GBMLT G-Bus Master Latency Timer 0x1E00_2100 R/W 64

GBBMLT G-Bus Broken Master Timer 0x1E00_2108 R/W 64

GBSLT G-Bus Slave Latency Timer 0x1E00_2110 R/W 64

RTT G-Bus Retry Timer 0x1E00_2118 R/W 64

GCCR GC Control register 0x1E00_212 0 R/W 64

GBSTAT G-Bus Status Register 0x1E00_2128 R/W 64

GBBAR G-Bus Bad Address Regist er 0x1E00_2130 R 64 GBARSR G-Bus Arbiter Request Status Register 0x1E00_2138 R 64 GBAGSR G-Bus Arbiter Granted Status Regist er 0x1E00_2140 R 64 GBAMSR G-Bus Arbiter Master Status Register 0x1E00_2148 R/W 64

GBACR G-Bus Arbiter Control Register 0x1E00_2150 R/W 64

PCI / G-Bus Bridge / PCI Controller, Base Address 0x1E00_3000

Device & Vendor ID Register 0x1E00_3000 R 32

Status & Command Register 0x1E00_3004 R/W 32

Class Code, Revision ID Register 0x1E00_3008 R 32

PCI0

Configuration

Space

Master Latency Timer & Cache line Size

BIST, Header Type,

Memory Base Address[0] 0x1E00_301 0 R/W 32

Memory DAC Base Address[0] 0x1E00_3014 R/W 32

Memory Base Address[1] 0x1E00_301 8 R/W 32

Memory DAC Base Address[1] 0x1E00_301C R/W 32

Memory Base Address[2] 0x1E00_302 0 R/W 32

Memory DAC Base Address[2] 0x1E00_3024 R/W 32

Reserved 0x1E00_3028

Subsystem ID, Subsystem Vendor ID 0x1E00_302C R 32

XX,XX,XX,XX 0x1E00_3030 R/W 32

Reserved, 0xDC 0x1E00_3034 R 32

Reserved 0x1E00_3038

Max_Lat, Min_Gnt, Interrupt Pin, Interrupt Line 0x1E00_303C R 32

Reserved, Retry Time Value, TRDY Timeout 0x1E00_3040 R/W 32

I/O Base Address [0] 0x1E00_3044 R/W 32

Reserved 0x1E00_3048 - 0x1E00_30D8

Pre-existing features, 0xE401 0x1E00_30DC R/W 32

Pre-existing features 0x1E00_30E0 R/W 32

Reserved, p2gBase3[35:32], 0x0002 0x1E00_30E4 R/W 32

p2gBase3[31:0] 0x1E00_30E8 R/W 32

Reserved 0x1E00_30EC - 0x1E00_30FF

0x1E00_300C R/W 32

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

4-5

Chapter 4: Address Maps

The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information.

Name Register Description Address R/W Size(b)

PgbCSR PGB Control and Status Register 0x1E00_3100 R/W 64 g2pLower0 g2pwindow Lower Address Register 0 0x1E00_3108 R/W 64 g2pUpper0 g2pwindow Upper Address Register 0 0x1E00_3110 R/W 64 g2pLower1 g2pwindow Lower Address Register 1 0x1E00_3118 R/W 64 g2pUpper1 g2pwindow Upper Address Register 1 0x1E00_3120 R/W 64 g2pLower2 g2pwindow Lower Address Register 2 0x1E00_3128 R/W 64 g2pUpper2 g2pwindow Upper Address Register 2 0x1E00_3130 R/W 64 g2pLower3 g2pwindow Lower Address Register 3 0x1E00_3138 R/W 64 g2pUpper3 g2pwindow Upper Address Register 3 0x1E00_3140 R/W 64

g2pBase0 g2pwindow Base Address Register 0 0x1E00_314 8 R/W 64 g2pBase1 g2pwindow Base Address Register 1 0x1E00_315 0 R/W 64 g2pBase2 g2pwindow Base Address Register 2 0x1E00_315 8 R/W 64 g2pBase3 g2pwindow Base Address Register 3 0x1E00_316 0 R/W 64

g2pCycleType g2pwindow Cycle Type Register 0x1E00_316 8 R/W 64

p2gBase0 p2gwindow Base Address Register 0 0x1E00_317 0 R/W 64 p2gBase1 p2gwindow Base Address Register 1 0x1E00_317 8 R/W 64 p2gBase2 p2gwindow Base Address Register 2 0x1E00_318 0 R/W 64 p2gBase3 p2gwindow Base Address Register 3 0x1E00_318 8 R/W 64

Ia Failing Transaction Address Register 0x1E00_3190 R/W 64

-- Reserved 0x1E00_3198 - 0x1E00_3FFF

Programmable Timer / Counters, Base Address 0x1E00_4000

TMTCR0 Timer Control Register 0 0x1E00_4000 R/W 32

TMTISR0 Timer Interrupt Status Register 0 0x1E00_4004 R/W 32 TMCPRA0 Compare Register A 0 0x1E00_4008 R/W 32 TMCPRB0 Compare Register B 0 0x1E00_400C R/W 32

TMITMR0 Interval Timer Mode Register 0 0x1E00_4010 R/W 32

TMCCDR0 Divider Register 0 0x1E00_4020 R/W 32

- Reserved 0x1E00_4030

- Reserved 0x1E00_4040 TMTRR0 Timer Read Register 0 0x1E00_40F0 R/O 32 TMTCR1 Timer Control Register 1 0x1E00_4100 R/W 32

TMTISR1 Timer Interrupt Status Register 1 0x1E00_4104 R/W 32 TMCPRA1 Compare Register A 1 0x1E00_4108 R/W 32 TMCPRB1 Compare Register B 1 0x1E00_410C R/W 32

TMITMR1 Interval Timer Mode Register 1 0x1E00_4110 R/W 32 TMCCDR1 Divider Register 1 0x1E00_4120 R/W 32 TMPGMR1 Pulse Generator Mode Register 1 0x1E00_4130 R/W 32

- Reserved 0x1E00_4140 R/O 32 TMTRR1 Timer Read Register 1 0x1E00_41F0 R/W 32 TMTCR2 Timer Control Register 2 0x1E00_4200 R/W 32

TMTISR2 Timer Interrupt Status Register 2 0x1E00_4204 R/W 32 TMCPRA2 Compare Register A 2 0x1E00_4208 R/W 32 TMCPRB2 Compare Register B 2 0x1E00_420C R/W 32

TMITMR2 Interval Timer Mode Register 2 0x1E00_4210 R/W 32 TMCCDR2 Divider Register 2 0x1E00_4220 R/W 32 TMPGMR2 Pulse Generator Mode Register 2 0x1E00_4230 R/W 32

TMWTMR2 Watch Dog Timer Mode Register 2 0x1E00_4240 R/W 32

TMTRR2 Timer Read Register 2 0x1E00_42F0 R/W 32

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

4-6

Chapter 4: Address Maps

The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information.

Name Register Description Address R/W Size(b)

Dual Ethernet Media Access Controllers, Base Addresses 0x1E00_5000 and 0x1E00_6000

(Note: Counters start at offsets 0x200)

- Reserved 0x1E00_5000 R

CCReg0 Com mand & Configuration Register 0 0x1E00_5008 R/W 64

TFCReg0 Transmit Frame Configuration 0 0x1E00_5010 R/W 64

RFCReg0 Receive Frame Configuration 0 0x1E00_5018 R/W 64

TSReg0 Transmit Status Register 0 0x1E00_5020 R 64 RSReg0 Receive Status Register 0 0x1E00_5028 R 64

TIMReg0 Transmit Interrupt Mask Register 0 0x1E00_5030 R/W 64

TIReg0 Transmit Interrupt Register 0 0x1E00_5038 R 64

RIMReg0 Receive Interrupt Mask Register0 0x1E00_5040 R/W 64

RIReg0 Receive Interrupt Register0 0x1E00_5048 R 64

- Reserved 0x1E00_5050

- Reserved 0x1E00_5058

TPFTReg0 Transmit Pause Frame Timer Register0 0x1E00_5060 R/W 64

VLANReg0 VLAN Tag Register 0 0x1E00_5068 R/W 64

TDPReg0 Transmit Frame Descriptor Pointer Register 0 0x1E00_5070 R/W 64

RDPReg0 Rec ei ve Fram e Descri ptor Pointer Register 0 0x1E00_5078 R/W 64

CDPReg0 Current Frame Descriptor Pointer Register0 0x1E00_5080 R 64

BusErrReg0 Bus E rror A ddress Regi ster0 0x1E00_5088 R 64

TCDReg Transmit Frame Current Descriptor Pointer 0x1E00_5090 R 32 RCDReg Rec ei ve Fram e Current Desc ri ptor Pointer 0x1E00_5098 R 32

- Reserved 0x1E00_50A0 - 0x1E00_50FF peMACC0 Internal Test Register 0 (peMACC) 0x1E00_5100 R/W 64 peMACT0 Int ernal Test Register 0 (peMACT) 0x1E00_5108 R/W 64

IPGReg0 Back-to-Ba ck IPG gap0 0x1E00_5110 R/W 64

NBTBReg0 Non Back-to-Back IPG gap0 0x1E00_5118 R/W 64

peCLRT0 Internal Test Register0 (peCLRT) 0x1E00_5120 R/W 64 peMAXF0 Internal Test Register0 (peMAXF) 0x1E00_5128 R/W 64 pePNCT0 Internal Test Register0 (pePNCT) 0x1E00_5130 R/W 64

peTBCT0 Internal Test Register 0 (peTBCT) 0x1E00_5138 R/W 64

LSAII0 Local Station Addr II 0x1E00_51A8 R/W 64

LSAI0 Local Station Addr I 0x1E00_51B0 R/W 64

peVLTP0 Internal Test Register (peVLTP) 0x1E00_51C8 R/W 64

TBTCnt0 Total Bytes Transmitted Count Register 0x1E00_5200 R/W 64

TGFTCnt0 Total Good Frames Transmitted 0x1E00_5208 R/W 64

MFTCnt0 Multicast Frames Transmitted 0x1E00_5210 R/W 64

BFTCnt0 Broadcast Frames Transmitted 0x1E00_5218 R/W 64

TxFrame64_0 Frames Transmitted (TxFrame64) 0x1E00_5220 R/W 64 TxFrame127_0 Frames Transmitted (TxFrame127) 0x1E00_5228 R/W 64 TxFrame255_0 Frames Transmitted (TxFrame255) 0x1E00_5230 R/W 64 TxFrame511_0 Frames Transmitted (TxFrame511) 0x1E00_5238 R/W 64

TxFrame1K0 Frames Transmitted (TxFrame1K) 0x1E00_5240 R/W 64

TxFrameGt1K0 Frames Transmitted (TxFrameGt1K) 0x1E00_5248 R/W 64

MPFTCnt0 MAC Pause Frames Transmitted 0x1E00_5250 R/W 64

LFTCnt0 Long Frames Transmitted 0x1E00_5258 R/W 64

TCCnt0 Total Collisions 0x1E00_5260 R/W 64 LCCnt0 Late Collision 0x1E00_5268 R/W 64

MCCnt0 Multiple Collision 0x1E00_5270 R/W 64

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

4-7

Chapter 4: Address Maps

The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information.

Name Register Description Address R/W Size(b)

SCCnt0 Single Collision 0x1E00_5278 R/W 64

EDCnt0 Excessive Deferrals 0x1E00_5280 R/W 64 TRECnt0 Transmit Retry Errors 0x1E00_5288 R/W 64 TUECnt0 Transmit Underflow Errors 0x1E00_5290 R/W 64

- Reserved 0x1E00_5298

TBRCnt0 Total Bytes Received 0x1E00_52A0 R/W 64

TRFRCnt0 Total Readable Frames Received 0x1E00_52A8 R/W 64

MFRCnt0 Multicast Frames Received 0x1E00_52B0 R/W 64 BFRCnt0 Broadcast Frames Received 0x1E00_52B8 R/W 64

RxFrame64_0 Frames Received (RxFrame64) 0x1E00_52C0 R/W 64 RxFrame127_0 Frames Received (RxFrame127) 0x1E00_52C8 R/W 64 RxFrame255_0 Frames Received (RxFrame255) 0x1E00_52D0 R/W 64 RxFrame511_0 Frames Received (RxFrame511) 0x1E00_52D8 R/W 64

RxFrame1K0 Frames Received (RxFrame1K) 0x1E00_52E0 R/W 64

RxFrameGt1K0 Fram es Received (RxFrameGt1K) 0x1E00_52E8 R/W 64

MCFRCnt0 MAC Pause Frames Received 0x1E00_52F0 R/W 64

LFRCnt0 Long Frames Recei ved 0x1E00_52F8 R/W 64

RECnt0 Receive Errors 0x1E00_5300 R/W 64

FRBCCnt0 Frames Received with Bad CRC 0x1E00_5308 R/W 64

MFRCnt0 Misaligned Frames Received 0x1E00_531 0 R/W 64

UFCnt0 Undersized Frames 0x1E00_5318 R/W 64 FFCnt0 Fragm ented Frames 0x1E00_5320 R/W 64

JFRCnt0 Jabber Frames Received 0x1E00_5328 R/W 64

NRDMFCnt0 No RxDescriptor Missed Frames 0x1E00_5330 R/W 64

NRMFCnt0 No RxFIFO Missed Frames 0x1E00_5338 R/W 64

MIIMCR0 MIIM Control Register 0x1E00_5400 R/W 64 MIIMDR0 MIIM Data Register 0x1E00_5408 R/W 64

PhyAddr0_0 Physical Address 0 0x1E00_5600 R/W 64 PhyAddr1_0 Physical Address 1 0x1E00_5608 R/W 64 PhyAddr2_0 Physical Address 2 0x1E00_5610 R/W 64 PhyAddr3_0 Physical Address 3 0x1E00_5618 R/W 64 PhyAddr4_0 Physical Address 4 0x1E00_5620 R/W 64 PhyAddr5_0 Physical Address 5 0x1E00_5628 R/W 64 PhyAddr6_0 Physical Address 6 0x1E00_5630 R/W 64 PhyAddr7_0 Physical Address 7 0x1E00_5638 R/W 64 PhyAddr8_0 Physical Address 8 0x1E00_5640 R/W 64

PhyAddr9_0 Physical Address 9 0x1E00_5648 R/W 64 PhyAddrA_0 Physical Address A 0x1E00_5650 R/W 64 PhyAddrB_0 Physical Address B 0x1E00_5658 R/W 64 PhyAddrC_0 Physical Address C 0x1E00_5660 R/W 64 PhyAddrD_0 Physical Address D 0x1E00_5668 R/W 64 PhyAddrE_0 Physical Address E 0x1E00_5670 R/W 64 PhyAddrF_0 Physical Address F 0x1E00_5678 R/W 64

- Reserved 0x1E00_6000

CCReg1 Comm and & Conf i guration Regi ster 0x1E00_6008 R/W 64

TFCReg1 Transm it Frame Confi guration 0x1E00_6010 R/W 64

RFCReg1 Receive Frame Configuration 0x1E00_6018 R/W 64

TSReg1 Transmit Status Register 0x1E00_6020 R/W 64 RSReg1 Recei ve Status Register 0x1E00_6028 R/W 64

TIMReg1 Transmit Interrupt Mask Register 0x1E00_6030 R/W 64

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

4-8

Chapter 4: Address Maps

The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information.

Name Register Description Address R/W Size(b)

TIReg1 Transmit Interrupt Regi ster 0x1E00_6038 R/W 64

RIMReg1 Receive Interrupt Mask Register 0x1E00_6040 R/W 64

RIReg1 Receive Interrupt Register 0x1E00_6048 R/W 64

- Reserved 0x1E00_6050

- Reserved 0x1E00_6058

TPFTReg1 Transmit Pause Frame Timer Register 0x1E00_6060 R/W 64

VLANReg1 VLAN Tag Register 0x1E00_6068 R/W 64

TDPReg1 Transmit Frame Descri ptor Po i nter Register 0x1E00_6070 R/W 64 RDPReg1 Receive Frame Descriptor Pointer Register 0x1E00_6078 R/W 64 CDPReg1 Current Frame Descriptor Pointer Regist er 0x1E00_6080 R/W 64

BusErrReg1 Bus Error Address Register 0x1E00_6088 R/W 64

peMACC1 Internal Test Regist er (peMACC) 0x1E00_6100 R/W 64

peMACT1 Internal Test Register (peMACT) 0x1E00_6108 R/W 64

IPGReg1 Back-to-Ba ck IPG gap0 0x1E00_6110 R/W 64

NBTBReg1 Non Back-to-Back IPG gap0 0x1E00_6118 R/W 64

peCLRT1 Internal Test Register0 (peCLRT) 0x1E00_6120 R/W 64 peMAXF1 Internal Test Register0 (peMAXF) 0x1E00_6128 R/W 64 pePNCT1 Internal Test Register0(pePNCT) 0x1E00_6130 R/W 64

peTBCT1 Internal Test Register 0 (peTBCT) 0x1E00_6138 R/W 64

LSAII1 Local Station Addr II 0x1E00_61A8 R/W 64

LSAI1 Local Station Addr I 0x1E00_61B0 R/W 64

peVLTP1 Internal Test Register (peVLTP) 0x1E00_61C8 R/W 64

TBTCnt1 Total Bytes Transmitted Count Register 0x1E00_6200 R/W 64

TGFTCnt1 Total Good Frames Transmitted 0x1E00_6208 R/W 64

MFTCnt1 Multicast Frames Transmitted 0x1E00_6210 R/W 64

BFTCnt1 Broadcast Frames Transmitted 0x1E00_6218 R/W 64

TxFrame64_1 Frames Transmitted (TxFrame64) 0x1E00_6220 R/W 64 TxFrame127_1 Frames Transmitted (TxFrame127) 0x1E00_6228 R/W 64 TxFrame255_1 Frames Transmitted (TxFrame255) 0x1E00_6230 R/W 64 TxFrame511_1 Frames Transmitted (TxFrame511) 0x1E00_6238 R/W 64

TxFrame1K1 Frames Transmitted (TxFrame1K) 0x1E00_6240 R/W 64

TxFrameGt1K1 Frames Transmitted (TxFrameGt1K) 0x1E00_6248 R/W 64

MPFTCnt1 MAC Pause Frames Transmitted 0x1E00_6250 R/W 64

LFTCnt1 Long Frames Transmitted 0x1E00_6258 R/W 64

TCCnt1 Total Collisions 0x1E00_6260 R/W 64 LCCnt1 Late Collision 0x1E00_6268 R/W 64

MCCnt1 Multiple Collision 0x1E00_6270 R/W 64

SCCnt1 S i ngl e Col l is i on 0x1E00_6278 R/W 64

EDCnt1 Excessive Deferrals 0x1E00_6280 R/W 64 TRECnt1 Transmit Retry Errors 0x1E00_6288 R/W 64 TUECnt1 Transmit Underflow Errors 0x1E00_6290 R/W 64

- Reserved 0x1E00_6298

TBRCnt1 Total Bytes Received 0x1E00_62A0 R/W 64

TRFRCnt1 Total Readable Frames Received 0x1E00_62A8 R/W 64

MFRCnt1 Multicast Frames Received 0x1E00_62B0 R/W 64 BFRCnt1 Broadcast Frames Received 0x1E00_62B8 R/W 64

RxFrame64_1 Frames Received (RxFrame64) 0x1E00_62C0 R/W 64 RxFrame127_1 Frames Received (RxFrame127) 0x1E00_62C8 R/W 64 RxFrame255_1 Frames Received (RxFrame255) 0x1E00_62D0 R/W 64

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

4-9

Chapter 4: Address Maps

The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information.

Name Register Description Address R/W Size(b)

RxFrame511_1 Frames Received (RxFrame511) 0x1E00_62D8 R/W 64

RxFrame1K1 F rames Received (RxFrame1K) 0x1E00_62E0 R/W 64

RxFrameGt1K1 Fram es Received (RxFrameGt1K) 0x1E00_62E8 R/W 64

MCFRCnt1 MAC Pause Frames Received 0x1E00_62F0 R/W 64

LFRCnt1 Long Frames Recei ved 0x1E00_62F8 R/W 64

RECnt1 Receive Errors 0x1E00_6300 R/W 64

FRBCCnt1 Frames Received with Bad CRC 0x1E00_6308 R/W 64

MFRCnt1 Misaligned Frames Received 0x1E00_631 0 R/W 64

UFCnt1 Undersized Frames 0x1E00_6318 R/W 64 FFCnt1 Fragm ented Frames 0x1E00_6320 R/W 64

JFRCnt1 Jabber Frames Received 0x1E00_6328 R/W 64

NRDMFCnt1 No RxDescriptor Missed Frames 0x1E00_6330 R/W 64

NRMFCnt1 No RxFIFO Missed Frames 0x1E00_6338 R/W 64

MIIMCR1 MIIM Control Register 0x1E00_6400 R/W 64

MIIMDR1 MIIM Data Register 0x1E00_6408 R/W 64 PhyAddr0_1 Physical Address 0 0x1E00_6600 R/W 64 PhyAddr1_1 Physical Address 1 0x1E00_6608 R/W 64 PhyAddr2_1 Physical Address 2 0x1E00_6610 R/W 64 PhyAddr3_1 Physical Address 3 0x1E00_6618 R/W 64 PhyAddr4_1 Physical Address 4 0x1E00_6620 R/W 64 PhyAddr5_1 Physical Address 5 0x1E00_6628 R/W 64 PhyAddr6_1 Physical Address 6 0x1E00_6630 R/W 64 PhyAddr7_1 Physical Address 7 0x1E00_6638 R/W 64 PhyAddr8_1 Physical Address 8 0x1E00_6640 R/W 64 PhyAddr9_1 Physical Address 9 0x1E00_6648 R/W 64

PhyAddrA_1 Physical Address A 0x1E00_6650 R/W 64 PhyAddrB_1 Physical Address B 0x1E00_6658 R/W 64 PhyAddrC_1 Physical Address C 0x1E00_6660 R/W 64 PhyAddrD_1 Physical Address D 0x1E00_6668 R/W 64 PhyAddrE_1 Physical Address E 0x1E00_6670 R/W 64 PhyAddrF_1 Physical Address F 0x1E00_6678 R/W 64

UART0, UART1, Base Addresses 0x1E00_7000 and 0x1E00_8000

RBR0 Receive Buffer Register 0 0x1E00_7000 R/O 8 THR0 Transmit Holding Register 0 0x1E00_7000 W/O 8

DLL0 Divisor Latch 0 (LS) 0x1E00_7000 R/W 8

IER0 Interrupt Enable Regist er 0 0x1E00_7004 R/W 8

DLM0 Divisor Latch 0 (MS) 0x1E00_7004 R/W 8

IIR0 Interrupt Identification Register 0 0x1E00_7008 R/O 8

FCR0 FIFO Control Register 0 0x1E00_7008 W/O 8

LCR0 Line Control Register 0 0x1E00_700C R/W 8

MCR0 Modem Control Register 0 0x1E00_7010 R/W 8

LSR0 Line Status Register 0 0x1E00_7014 R/O 8 MSR0 Modem Status Register 0 0x1E00_7018 R/W 8 SCR0 Scratch Register 0 0x1E00_701C R/W 8 PSR0 Pre-scaler Register 0 0x1E00_7020 R/W 8 RBR1 Receive Buffer Register 1 0x1E00_8000 R/O 8 THR1 Transmit Holding Register 1 0x1E00_8000 W/O 8

DLL1 Divisor Latch 1 (LS) 0x1E00_8000 R/W 8

IER1 Interrupt Enable Regist er 1 0x1E00_8004 R/W 8

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

4-10

Chapter 4: Address Maps

The following table is a register map of the individual modules. Please note that this table is still under construction. See the tables in each relevant chapter for more information.

Name Register Description Address R/W Size(b)

DLM1 Divisor Latch 1 (MS) 0x1E00_8004 R/W 8

IIR1 Interrupt Identification Register 1 0x1E00_8008 R/O 8

FCR1 FIFO Control Register 1 0x1E00_8008 W/O 8

LCR1 Line Control Register 1 0x1E00_800C R/W 8 MCR1 Modem Control Register 1 0x1E00_8010 R/W 8

LSR1 Line Status Register 1 0x1E00_8014 R/O 8 MSR1 Modem Status Register 1 0x1E00_8018 R/W 8 SCR1 Scratch Register 1 0x1E00_801C R/W 8 PSR1 Pre-scaler Register 1 0x1E00_8020 R/W 8

SPI (TSEI) and GPIO Base Address 0x1E00_9000

GPIO_outreg General-purpose I/O Register 0x1E00_9000 R/W 8

GPIO_inreg General-purpose I/O Register 0x1E00_9004 R/O 8

GPIO_outenab General-purpose I/O Register 0x1E00_9008 R/W 8

- Reserved 0x1E00_900C

TSEI_SECR Control Register 0x1E00_9010 R/W 8

TSEI_SESR Status Register 0x1E00_9014 R/W 8 TSEI_SEDR Data Register 0x1E00_9018 R/W 8 TSEI_DDCR Data Direction Register 0x1E00_901C R/W 8

PGB1 (Optional) Base Address 0x1E00_A000

Device & Vendor ID Register 0x1E00_A000 R 32

Status & Command Register 0x1E00_A004 R/W 32

Class Code, Revision ID Register 0x1E00_A008 R 32

BIST, Header Type,

Master Latency Timer & Cache line Size

Memory Base Address[0] 0x1E00_A010 R/W 32

Memory DAC Base Address[0] 0x1E00_A014 R/W 32

Memory Base Address[1] 0x1E00_A018 R/W 32

Memory DAC Base Address[1] 0x1E00_A01C R/W 32

Memory Base Address[2] 0x1E00_A020 R/W 32

Memory DAC Base Address[2] 0x1E00_A024 R/W 32

PCI1

Configuration

Space

pgbCSR PGB Control and Status Register 0x1E00_A100 R/W 64 g2pLower0 g2pwindow Lower Address Register 0 0x1E00_A108 R/W 64 g2pUpper0 g2pwindow Upper Address Register 0 0x1E00_A110 R/W 64 g2pLower1 g2pwindow Lower Address Register 1 0x1E00_A118 R/W 64

Subsystem ID, Subsystem Vendor ID 0x1E00_A02C R 32

Max_Lat, Min_Gnt, Interrupt Pin, Interrupt Line 0x1E00_A03C R 32

Reserved, Retry Time Value, TRDY Timeout 0x1E00_A040 R/W 32

Pre-existing features, 0xE401 0x1E00_A0DC R/W 32

Reserved, p2gBase3[35:32], 0x0002 0x1E00_A0E4 R/W 32

Reserved 0x1E00_A028

XX,XX,XX,XX 0x1E00_A030 R/W 32

Reserved, 0xDC 0x1E00_A034 R 32

Reserved 0x1E00_A038

I/O Base Address [0] 0x1E00_A044 R/W 32

Reserved 0x1E00_A048 – 0x1E00_A0D8

Pre-existing features 0x1E00_A0E0 R/W 32

p2gBase3[31:0] 0x1E00_A0E8 R/W 32

Reserved 0x1E00_A0EC - 0x1E00_A0FF

0x1E00_A00C R/W 32

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4-11

Chapter 4: Address Maps

The following table is a register map of the individual modules. Please note that this table is

still under construction. See the tables in each relevant chapter for more information.

Name Register Description Address R/W Size(b)

g2pUpper1 g2pwindow Upper Address Register 1 0x1E00_A120 R/W 64 g2pLower2 g2pwindow Lower Address Register 2 0x1E00_A128 R/W 64 g2pUpper2 g2pwindow Upper Address Register 2 0x1E00_A130 R/W 64 g2pLower3 g2pwindow Lower Address Register 3 0x1E00_A138 R/W 64 g2pUpper3 g2pwindow Upper Address Register 3 0x1E00_A140 R/W 64

g2pBase0 g2pwindow Bas e A ddress Register 0 0x1E00_A148 R/W 64 g2pBase1 g2pwindow Bas e A ddress Register 1 0x1E00_A150 R/W 64 g2pBase2 g2pwindow Bas e A ddress Register 2 0x1E00_A158 R/W 64 g2pBase3 g2pwindow Bas e A ddress Register 3 0x1E00_A160 R/W 64

g2pCycleType g2pwindow Cycle Type Register 0x1E00_A168 R/W 64

p2gBase0 p2gwindow Bas e A ddress Register 0 0x1E00_A170 R/W 64 p2gBase1 p2gwindow Bas e A ddress Register 1 0x1E00_A178 R/W 64 p2gBase2 p2gwindow Bas e A ddress Register 2 0x1E00_A180 R/W 64 p2gBase3 p2gwindow Bas e A ddress Register 3 0x1E00_A188 R/W 64

Ia Failing Transaction Address Register 0x1E00_A190 R/W 64

- RESERVED 0x1E00_A198 - 0x1E00_AFFF

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Chapter 5: C790 Processor Core

5. C790 Processor Core

This chapter is an overview of the C790 Processor Core.

5.1 Features

The C790 is an integrated, high-performance, RISC processor core with 128-bit internal

data paths optimized for high data throughput.

Some of the C790 features are listed below:

 2-way super-scalar pipeline with 128-bit (2x64-bit) data path

 200/266 MHz operation

 MIPS I, II, III compatible ISA, with selected MIPS IV ISA (Pre-fetch and Move

Conditional Instruction)

 Additional multim edia instr uction set support to provide SIMD operation

 32 KB, 2-way set associative Instruction Cache and 32 KB, 2-way set associative Data

Cache

 Supports the data cache line lock, write back cache, and non-blocking load functions,

and the prefetch instruction.

 64-entry fully associative branch target address cache

 48-entry fully associative JTLB supporting 4 KB –16 MB page size

 Supports 32-bit physical address

 IEEE-754 compatible, double-precision FPU is coupled with the C790.

 Supports bi-Endian (Litt le Endian and Big Endian) operation

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Chapter 5: C790 Processor Core

5.2 Block Diagram and Functional Block Descriptions

This section shows a block diagram of the C790 and summarizes the modules’ functionality.

Instruction

PC Unit

PC Pipe &

BTAC

(64-entry

fully assoc.)

MMU

(JTLB)

48 entry TLB

Cop0 Registers

ITLB

2 entries

Virtual Address

(IVA)

Instruction

Physical Address

(IPA)

TLB Refill Bus

Instruction Cache (I-Cache)

Tag, BHT, Predecode, Inst RAMs

(32kB, 2-way set assoc.)

I-Cache Output

Issue Logical Staging Resigters

(2 Issue, In-order)

GPR

(32x128-bit wide registers)

Operand/Bypass Logic

Pipeline Control

LS Execution Pipe

Response

Buffer

Virtual Address

Computation Logic

Data Virtual Address

Data Cache

(D-Cache)

(32 KB, 2-way

set assoc.)

WBB

(DVA)

DTLB

(4 entries)

Data Physical Address

(DPA)

UCAB

128b

BR Execution Pipe

I1 Execution Pipe

Result and Move Buses

BIU Bus

(32x64-bit wide

registers)

I0 Execution Pipe

FPR

C1 COP1 (FPU) Pipe

128b

Figure 5-1 C790 Block Diagram

TX7901 User’s Manual (Rev. 6.30T – Nov, 2001)

Bus Interface Unit

128b

CPU Bus

5-2

Chapter 5: C790 Processor Core

 PC Unit: T he 32-bit Program Counter (PC) holds the address of the instruction that is

being executed. It also contains a 64-entry Branch Target Address Cache (BTAC) which stores branch target addresses used for branch prediction (to eliminate branch penalties).

 Issue Logic and Staging Registers: The issue logic controls the transfer of fetched

instructions to the appropriate execution pipes. It can issue a maximum of two instructions per cycle, and any instructions remaining that were fetched but could not be issued because of conflicts such as resource conflicts or hazards are held in staging registers until they can be issued.

 General Purpose Registers (GPRs): The width of the GPRs is extended from MIPS

III’s 64 bits, to a width of 128 bits. The upper 64 bits of the GPRs are accessible using the quad word Load/Store instructions, the quad word funnel shift instruction, and the parallel (multimedia) instructions.

 I0 and I1 Pipes: The two integer pipelines I0 and I1 each contain a complete 64-bit ALU,

Shifter, and Multiply-Accumulate (MAC) unit. The I0 pipeline additionally contains a Shift Amount (SA) register that is used for funnel shift operations, and the I1 pipeline contains a leading zero counter. The two 64-bit data paths can be configured dynamically, on an instruction-by-instruction basis, into a single 128-bit data-path when it is necessary to execute 128-bit wide multimedia, shift, ALU or Multiply-Accumulate instruct ions. The two 64-bit data paths share a single 128-bit multimedia shifter during 128-bit wide shift operations.

 Load / Store (LS) Pipe: The Load/Store (LS) pipe supports a single issue of Load and

Store instructions at widths ranging from one byte (8 bits), to one quad-word (128 bits).

 Memory Management Unit (MMU): The Memory Management Unit supports the

address translation functions of the C790. It contains a 48-entry fully associative JTLB, a 2-entry Instruction Translation Lookaside Buffer (ITLB), and a 4-entry Data Translation Lookaside Buffer (DTLB).

 Memory Caches: The C790 includes an Instruction Cache and a Data Cache. For each

branch instruction present in the instruction cache, two bits of branch history information are stored in a Branch History Table (BHT).

 Response and Write-back Buffer: The Write-back Buffer (WBB) is an 8-entry by 16-

byte (one quad-word) FIFO queues up stores prior to accessing the C790 bus. It increases C790 performance by isolating the processor from the latencies of the C790 bus. It is also used during the gathering operation of uncached accelerated stores. Sequential stores less than a quad-word in length are gathered in the WBB, thereby improving bus bandwidth usage.

 Uncached Accelerated Buffer (UCAB) : The Uncached Accelerated Buffer (UCAB) is a

2-entry by 4 quad-word buffer. It caches 128 sequential bytes of data during an uncached accelerated load miss. Subsequent loads from the uncached accelerated address space get their data from this buffer if the address hits in the UCAB, thereby eliminating bus latencies and providing higher performance.

 Bus Interface Unit (BIU) : The Bus Interface Unit (BIU) connects the core’s internal bus

to the C790 bus. It interfaces the core’s internal bus signals to the C790 Bus.

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Chapter 5: C790 Processor Core

The C790 extends the normal MIPS-compatible register set by extending the width of the general purpose registers (GPRs) from 64 bits to 128 bits. It also incorporates an additional pair of HI/LO registers for the I1 pipe, and the SA register for funnel shift instructions.

5.3 C790 Registers

The C790 has 128-bit wide GPRs. The upper 64 bits of the GPRs are only used by the C790-specific “Quad Load/Store”, and “Multimedia (Parallel)” instructions.

HI1 and LO1, which are the upper 64 bits of each of the 128-bit HI and LO registers, are also used by new multiply and divide instructions such as MULT1, MULTU1, DIV1, DIVU1, MADD1, MADDU1, MFHI1, MFLO1, MTHI1, and MTLO1, which are non-parallel I1 pipelinespecific instructions. They are also used by multimedia (parallel) multiply and divide instructions.

5.4 FPU Registers

The floating-point unit (COP1) has thirty-two 64-bit wide floating-point registers. It also contains two floating-point control registers.

5.5 Memory Management

The C790 provides a memory management unit (MMU) which uses an on-chip translation look-aside buffer (TLB) to translate virtual addresses into physical addresses.

Features

• MIPS III-compatible 32-bit MMU

• Operating Modes: User, Supervisor, and Kernel

• TLB: 48 entries of even/odd page pairs (96 pages)

Fully associative

• Page Size: 4 KB, 16 KB, 64 KB, 256 KB, 1 MB, 4 MB, 16 MB

• ITLB: 2 entries

• DTLB: 4 entries

• Address Sizes: Virtual Address Size = 32 bits

Physical Address Size = 32 bits

5.6 Cache Memory

The C790 contains an instruction cache and a separate data cache.

Features

• Separate Instruction Cache and Data Cache

• Caches are virtually indexed and physically tagged

• Write-back policy for the Data Cache

• Cache Size: Instruction Cache: 32 KB

Data Cache: 32 KB

• Line size: 64 Bytes

• Associativity: 2-way set-associative

• Write Policy: Write-back and write allocate

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Chapter 5: C790 Processor Core

• Data order for block reads: Sequential ordering

• Data order for block writes: Sequential ordering

• Instruction cache miss restart: After all data are received

• Data cache miss restart: Early restart on first quad-word

• Cache parity: No

• Cache Locking: Data Cache Line Lock

Controlled by CACHE instruction

• Cache Snooping: No

• Non-blocking load: Yes

• Hit Under Miss: Yes (Supports multiple hits under one miss)

• Data Cache Pre-fetch: Yes

5.7 Floating Point Unit

The floating-point unit implements double-precision and single-precision operations. The unit is IEEE-754 compatible.

Features:

• MIPS III floating point instr uctions

• High performance double-precision floating point unit tightly coupled to the C790

• Supports double-precision and single-precision formats as defined in the IEEE-

754 specifications

• Compatible with the TX49 FPU

• No hardware support for denormalized numbers

5.8 Performance Monitor

The performance monitor provides the means for gathering statistical information about the internal events of the C790 and its pipeline during program execution. The statistics gathered during program execution aid in tuning the performance of hardware and software systems based on the processor core.

The performance monitor consists of one control register and two counters. The control register controls the functions of the monitor while the counters count the number of events specified by the control register.

Features:

• Two performance counter registers

• Can count over twenty different events within the C790

• Counting can be selectively enabled in User, Supervisor, Kernel, and Exception

modes

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Chapter 5: C790 Processor Core

5.9 Debug Functions

The C790 supports ranged hardware break pointers with mask registers. This makes it possible to debug with less observational impact. Note that C790 debugging also supports software debugging using the BREAK instruction as defined in MIPS ISA.

Features:

• One Instruction Address Breakpoint register

• One Instruction Address Breakpoint Mask register

• One Data Address Breakpoint register

• One Data Address Breakpoint Mask register

• One Data Value Breakpoint register

• One Data Value Breakpoint Mask register

• Each breakpoint is individually enabled

• Breakpoint function can be selectively enabled in User, Supervisor, Kernel, and

Exception modes

• External Trigger signal can be generated when breakpoint occurs

• 11 signals are used to provide real-time PC tracing functionality

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Chapter 6: SDRAM Memory Controller

6. SDRAM Memory Controller

6.1 Overview

This SDRAM Controller is used to connect the C790 (128-bit MIPS CPU) to SDRAM. The SDRAM devices that can be connected are 64 Mb, 128 Mb, or 256 Mb with a 4-bank architecture. If 8M x 8 x 4 SDRAM chips are used, the TX7901 can support 1 GB memory with 4 physical memory banks.

6.2 Features

• Directly connected to a 128-bit C790 sysbus operating up to 133 MHz

• Supports PC100/133 DIMM

• Supports 4-bank interleaving for 64/128/256 Mbit SDRAMs, or 2-bank

interleaving for 16 Mbit

• ECC, single-bit error correction, double- bit error det ection

• Maximum access rate of 133 MHz

• Supports aligned (8 quad-word) burst transfers

6.3 Address Space Decoding

The SDRAM Controller has a fully programmable address map. It uses a two-stage decoding process where major device regions are decoded first, and then the individual devices are sub-decoded. Addresses for regions in 256 MB units are compared by exact matching, and individual device addresses are compared by size comparison. One device (DIMM) therefore cannot span across 256 MB boundaries.

6.4 Two-Stage Decoding Process

Physical space is divided into 16 regions. Each region can have 256 MBytes of address space. Memory space decoding starts with the sysAddr address being compared with the values in the four LOW and HIGH Registers. Device0, device1, device2, and device3 correspond to sdrCSB[0], sdrCSB[1], sdrCSB[2], sdrCSB[3.]

Address decoding is performed as follows:

• sysAddr[31:28] are compared against region field [31:28] in the LOW Decoder

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Chapter 6: SDRAM Memory Controller

registers. This value must match exactly. This value effectively sets a 256 MB region.

• sysAddr[27:20] are compared against bits [27:20] in the LOW Decoder registers. This value of sysAddr must be greater than or equal to the LOW decode value. This describes the low boundary for the region.

• sysAddr[27:20] are compared against bits [27:20] in the HIGH Decoder registers. The value of sysAddr must be less than or equal to the HIGH decode value. This describes the high boundary for the region.

• If all of the above are true, then the device region is selected and the corresponding chip select signal is activated.

Any device region can be disabled by setting the value of the “LOW” decoder to be higher than that of the “HIGH” decoder.

The LOW and HIGH Decode Registers cannot be programmed in the region from 0x_1E00_0000 to 0x_20FF_FFFF. This is reserved for TX7901 registers and Boot Devices. It is important to note that devices never span across region boundaries. This is detected by reading a HIGH Register after a write. Two devices may be put in one region, but they must not overlap.

Examples of the two-stage decoding process are shown in Figure 6-1 and Figure 6-2.

Physical address space

sysAddr[31:0]

LOW

HIGH

[31:28] [27:20]

•

31 28 27 20 19 0

•

Region Boundary

31 28 27 20 19 0

Region Boundary

Can read the same value as LOW[31:28]

≥

•

≤

•

0 -------------------------- 0

1 ------------------------- 1

0xFFFF_FFFF

Region 15

DIMM

Region 1

0x1000_0000

Region 0

0x0000_0000

•

Figure 6-1 Two-stage Decoding

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6-2

0xFFFF_FFFF

Chapter 6: SDRAM Memory Controller

0x0FFF_FFFF

0x1000_0000

0x0200_0000

DIMM3 (8 MB)

0x0180_0000

DIMM2 (8 MB)

0x0100_0000

DIMM1 (8 MB)

0x0080_0000

DIMM0 (8 MB)

0x0000_0000

D3 HIGH D3 LOW

D2 HIGH D2 LOW

D1 HIGH D1 LOW

D0 HIGH D0 LOW

Region0

0x0000_0000

Figure 6-2 Initial Setting after Reset

Programming note It is okay to place multiple DIMMs into a region. It is okay to place two DIMMs into

consecutive physical addresses. However, it is not okay to place a DIMM across two regions. In other words, placing a DIMM across region boundaries is not permitted. This violation can be detected by reading the HIGH register again after LOW and HIGH are written. If the HIGH register is read the same as it was written, then it is okay. If it is diff erent because the HIGH region field is the same as that of LOW, then it is okay to place a DIMM across the 256 MB region boundary.

la r4, <LOW of DIMM0> la r5, <HIGH of DIMM1> la r7, <SDRAM base address>

sq r4, D0LOW (r7) sq r5, D0HIGH (r7) lq r6, D0HIGH (r7) bne r5, r6, crossing DIMM

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Chapter 6: SDRAM Memory Controller

BankAddr[1:0] Address[12:0] RAS, CAS, WE

sdmCSB[0]

sdmCSB[1]

sdmCSB[2]

sdmCSB[3]

data [63:0] check bits[7:0] DQM[7:0]

DIMM0

•

DIMM1

•

DIMM2

•

DIMM3

•

8b 8b 8b 8b 8b 8b 8b 8b 8b

72b

RefClk

TX7901

100/133 MHz

Clock

Distribution

Figure 6-3 Example Connection of Single-sided DIMMs

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Chapter 6: SDRAM Memory Controller

BankAddr[1:0] Address[12:0] RAS, CAS, WE

sdmCSB[0]

sdmCSB[1]

sdmCSB[2]

sdmCSB[3]

data [63:0] check bits[7:0] DQM[7:0]

RefClk

72b

DIMM0,2

•

DIMM1,3

•

8b 8b 8b 8b 8b 8b 8b 8b 8b

TX7901

100/133 MHz

Clock

Distribution

Figure 6-4 Example Connection of Double-sided DIMMs

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Chapter 6: SDRAM Memory Controller

6.4.1 Default Memory Map

After sysResetB is active, the default memory map is as shown in Table 6-1.

Table 6-1 Initial Values after Reset

Device CS LOW HIGH

DIMM0 sdrCSB[0] D0LOW (0x0 000_0000) D0HIGH (0x0 07F_FFFF) 8 MB

DIMM1 sdrCSB[1] D1LOW (0x0 080_0000) D1HIGH (0x0 0FF_FFFF) 8 MB

DIMM2 sdrCSB[2] D2LOW (0x0 100_0000) D2HIGH (0x0 17F_FFFF) 8 MB

DIMM3 sdrCSB[3] D3LOW (0x0 180_0000) D3HIGH (0x0 1FF_FFFF) 8 MB

Table 6-2 below shows an example of four 64 MB DIMMs.

Table 6-2 Example Values for Four DIMMs

Device CS LOW HIGH

0 000_ 0000)

DIMM0 sdrCSB[0] D0LOW

DIMM1 sdrCSB[1] D1LOW (0x0 400_0000) D1HIGH (0x0 7FF_FFFF) 64 MB

DIMM2 sdrCSB[2] D2LOW (0x0 800_0000) D2HIGH (0x0 BFF_FFFF) 64 MB

DIMM3 sdrCSB[3] D3LOW (0x0 C00_0000) D3HIGH (0x0 FFF_FFFF) 64 MB

(0x

D0HIGH

(0x0 3FF_FFFF)

Initial

Size

Initial

Size

64 MB

6.4.2 Example connection of DIMMs

It is possible to connect up to four single-sided DIMMs. See Figure 6-3 above. It is possible to connect up to two double-sided DIMMs. See Figure 6-4 above. Double-sided DIMM is considered as two DIMMs since it has two Chip Select inputs. See

the Application Notes (to be released) for more information regarding the clocking.

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Chapter 6: SDRAM Memory Controller

6.5 Registers

The following table is a register map of the SDRAM Memory Controller Module.

Table 6-3 List of SDRAM Memory Controller Registers

Name Register Description Address R/W Size(b)

SDRAM Memory Controller, Base Address 0x1E00_0000

D0PR DIMM 0 Parameters Register 0x1E00_0000 R/W 128 D1PR DIMM 1 Parameters Register 0x1E00_0010 R/W 128 D2PR DIMM 2 Parameters Register 0x1E00_0020 R/W 128 D3PR DIMM 3 Parameters Register 0x1E00_0030 R/W 128

DOMR Operation Mode Register 0x1E00_0040 R/W 128

DEMR ECC Mode Register 0x1E00_0050 R/W 128 DEESR ECC Error St atus Register 0x1E00_0060 R 128 DEEAR ECC E rror Address Regis ter 0x1E00_0070 R 128

– RESERVED 0x1E00_0080

DREFRESH Refresh Register 0x1E00_0090 R/W 128

DDRIVE

D0LOW DIMM 0 LOW Address Decode 0x1E00_0100 R/W 128

D0HIGH DIMM 0 HIGH Address Dec ode 0x1E00_0110 R/W 128

D1LOW DIMM 1 LOW Address Decode 0x1E00_0120 R/W 128

D1HIGH DIMM 1 HIGH Address Dec ode 0x1E00_0130 R/W 128

D2LOW DIMM 2 LOW Address Decode 0x1E00_0140 R/W 128

D2HIGH DIMM 2 HIGH Address Dec ode 0x1E00_0150 R/W 128

D3LOW DIMM 3 LOW Address Decode 0x1E00_0160 R/W 128

D3HIGH DIMM 3 HIGH Address Dec ode 0x1E00_0170 R/W 128

SDRAM Interface Output Drive- Strength

Control Register

0x1E00_00A0 R/W 128

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Chapter 6: SDRAM Memory Controller

General Control

DOMR

DREFRESH

DDRIVE

ECC

DEMR

DEESR DEEAR

SDRAMC

sdmCSB[0]

D0PR

D0LOW D0HIGH

sdmCSB[1]

D1PR

D1LOW D1HIGH

sdmCSB[2]

D2PR

D2LOW D2HIGH

sdmCSB[3]

D3PR

D3LOW D3HIGH

Physical Address

DIMM0

DIMM1

DIMM2

DIMM3

Figure 6-5 SDRAM Registers

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Chapter 6: SDRAM Memory Controller

All of the following registers are 128 bits wide and are aligned to 16 Byte boundaries. In order to facilitate Bi-Endian programming, it is stro ngly recommended to use lq/sq to access these registers.

6.5.1 Parameters register

127 32

31 30 29 28 26 25 24 23 21 20 18 17 16 15 2 1 0

13 23 3 2 14 2

C A S

This register contains parameters that are used for each of the physical memory devices. All memory devices share the same timing parameters (bits[29:16]) in the Device Region 0 Parameters Register.

 DIMM 0 Parameters Register (0x1E00_0000) R/W

D S L

Field Bit(s) Description

Device Select (01)

DSL 1:0

– 15:2 Reserved –

CAS 17:16

A2RWI 20:18

P2AI 23:21

WRT 25:24

00: 16 Mb SDRAM 01: 64/128 Mb SDRAM 10: 256 Mb SDRAM 11: Reserved

CAS Latency (11) These bits specify the timing for the first read data after

SDRAM samples a column address. 00, 01: Reserved

10: 2 clock cycles 11: 3 clock cycles

Active to Read/Write Interval (011) Specifies the earliest timing for a READ/WRITE command

after an ACTIVE command. 000, 001 : Reserved

010 : 2 clock cycles 011 : 3 clock cycles 100 - 111 : Reserved

Precharge to active interval (011) These bits specify the earliest timing for a new command

after a PRECHARGE command. 000, 001 : Reserved

010 : 2 clock cycles 011 : 3 clock cycles 100 - 111 : Reserved

Write recovery time (10) These bits specify the earliest timing for a PRECHARGE

command after the last data were written to the SDRAM. 01 : 1 clock cycle 10 : 2 clock cycl es 00, 11 : Reserved

Timing

Symbol

–

tCAS

tRCD

tRP

tWR

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Chapter 6: SDRAM Memory Controller

Field Bit(s) Description

Refresh Recovery Time (110) These bits specify the earliest timing for a new command

after a Refresh command. 001 : 5 cl ock cycles

RRT 28:26

A2P 29

– 31:30 Reserved –

010 : 6 cl ock cycles 011 : 7 cl ock cycles 100 : 8 cl ock cycles 101 : 9 cl ock cycles 110 : 10 clock cycles 111 : 16 clock cycles 000 : Reserved

Activate to Precharge (1) This bit specifies the earliest timing for a PRECHARGE

command after an ACTIVE command. 0 : 5 clock cycles 1 : 6 clock cycles

The following figure shows example timing parameters.

Figure 6-6 Example Timing Parameters

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

≥tRAS

COMMAND

ACTIVE

READ PRE

tRCD

Timing

Symbol

tRFC

tRAS

tPR

Any

command

Address

COMMAND

ddress

OMMAND

ROW COL

tCAS

Read data Read data

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

≥tRAS

ACTIVE WRITE

Any

command

tRCD

ROW COL

≥tWR

Write

data

Write

data

T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10

REFRESH

Any

command

≥tRFC

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Chapter 6: SDRAM Memory Controller

 DIMM 1 Parameters Register (0x1E00_0010) R/W

127 32

31 2 1 0

30 2

Field Bit Description

Device Select (01)

DSL 1:0

– 31:2 Reserved

Other parameters use the same values as DIMM 0.

 DIMM 2 Parameters Register (0x1E00_0020) R/W

00: 16 Mb SDRAM 01: 64/128 Mb SDRAM 10: 256 Mb SDRAM 11: Reserved

D S L

127 32

31 2 1 0

30 2

Field Bit Description

Device Select (01)

DSL 1:0

– 31:2 Reserved

Other parameters use the same values as DIMM 0.

00: 16 Mb SDRAM 01: 64/128 Mb SDRAM 10: 256 Mb SDRAM 11: Reserved

D S L

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 DIMM 3 Parameters Register (0x1E00_0030) R/W

127 32

31 2 1 0

30 2

Field Bit Description

Device Select (01)

DSL 1:0

– 31:2 Reserved

Other parameters use the same values as DIMM 0.

00: 16 Mb SDRAM 01: 64/128 Mb SDRAM 10: 256 Mb SDRAM 11: Reserved

D S L

6.5.2 Operation Mode Register (0x1E00_0040) R/W

127 32

31 13 12 10 9 3 2 0

19 3 7 3

This register is used to execute commands other than standard memory reads and writes to the SDRAM. Bits [12:10] are used to check the current state of the SDRAM Controller.

Field Bit(s) Description

Operation Mode (001) 000 : Normal SDRAM Mode (Read/Write)

001 : NOP Commands

OPM 2:0

– 9:3 Reserved (0)

Stat 12:10

– 31:13 Reserved (0)

010 : Precharge All Banks 011 : Writing to the SDRAM Mode Register. Each DIMM could have a different Mode. 100 : Force a Refresh Cycle Others : Reserved

Status (read only) 000 : Idle 001 : Page Activation 010 : Precharge 011 : Write Mode Register 100 : Refresh 101 : Read 110 : Write 111 : Reserved

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In order to execute one of the above commands on the SDRAM, the following procedure should occur:

1. The corresponding value should be written to the SDRAM Operation Mode Register.

2. OMR Write should be followed by a dummy write to the corresponding SDRAM. For Mode Register Write, the RAS address [12:0] will be put in the Mode Register. To map sysADDR into the RAS address, please see 6.6 Address Mapping.

3. SDRAM and SDRAM Controller initialization should be complete before writing 000 to this register in order to place it back into the Normal SDRAM mode. Normal SDRAM operation can then start.

6.5.2.1 Normal SDRAM Mode

0x0 should be written to the SDRAM Operation Mode Register to enable normal reading and writing to the SDRAM.

Note: SDRAM and SDRAM Controller must be complete before entering this mode.

6.5.2.2 NOP Commands

NOP commands are used to issue NOPs to SDRAM when the DIMM is accessed. This prevents unwanted commands from being registered during idle or wait states of the initialization sequence.

6.5.2.3 Precharge All Banks

The Precharge All Banks command is used to deactivate the open row. The Precharge All Banks command is the first command called after reset. In this mode, any write to a particular DIMM causes the Precharge command to be issued. Once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. This sequence will be performed by the hardware sequencer.

6.5.2.4 Writing to the SDRAM Mode Register

Each DIMM has its own Mode Register. The Mode Register is used to define the specific mode of operation for the SDRAM. This definition includes the selection of a burst length, sdrCAS* latency, burst type, operating mode, etc. (Please see your SDRAM data sheet for more information about this register.) Typically, the Mode Register of each SDRAM is initialized during system boot-up and is kept static.

The parameter that the SDRAM Controller can change is the CAS lat ency. The burst length must be programmed to 2. The bust type is Sequential. The Write Burst Mode is the Programmed Burst Length. In order to change this parameter in the SDRAM’s Mode Register:

1. The DIMM Parameter Registers are updated properly. DIMMs are precharged, deactivated.

2. The SDRAM Operation Mode Register should be written to 0x3 to indicate a Write Command to the SDRAM Mode Register.

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Chapter 6: SDRAM Memory Controller

3. Store dummy data (32-bit) to a location. The address of this store instruction is saved in the Mode Register as data. The address is shuffled by address mapping. The corresponding address bit may vary according to the SDRAM chip and DIMM connection. SDRAMC uses RA[12:0] of sysAddr as a Mode Register value.

Table 6-4 SDRAM Mode Register Settings

Burst Length 2 Burst Type Sequential Write burst mode Programmed burst length CAS Latency 2 or 3

6.5.2.5 Force Refresh

The Force Refresh Command is used to execute a refresh cycle. In this mode, any write to a DIMM causes the Auto Refresh command to be called. The lower address and data are ignored because the Auto Refresh command uses a refresh counter internal to the SDRAM chip. At least eight Auto Refresh commands are required for the power on sequence.

6.5.2.6 Initialization sequence

Intel’s “PC SDRAM Specification” Rev. 1.7, November 1999 recommends the sequence described below.

Following the initialization sequence, the device must be ready for f ull functionality. SDRA M devices are initialized by the following sequence:

1. At least one NOP cycle will be issued after the 1msec device deselect.

2. A m inim um pause of 200 µsec will be provided after the NOP.

3. A pr echarge all command will be issued to the SDRAM.

4. Eight Auto Refresh (CBR) refresh cycles will be provided.

5. A mode register set cycle will be issued to program the SDRAM parameters (e.g., Burst

length, CAS# latency, etc.).

6.5.2.7 Important programming note

Program codes that change any SDRAM/SDRAMC parameters should be located in a memory device other than SDRAM memory (boot ROM, for example). Otherwise, such program codes may cause a deadlock.

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Chapter 6: SDRAM Memory Controller

6.5.3 ECC Mode Register (0x1E00_0050) R/W

127 32

31 16 15 8 7 5 4 3 2 0

16 8 3 1 1 3

Field Bit(s) Description

Error Correction Check Mode (000) 000 : ECC Disable Mode, no check bit generation

001 : Detect mode. Performs check bit generation during

memory writes and error detection only during memory

ECCM 2:0

SEIE(3) 3 Single ECC Error Interrupt Enable (0)

MEIE(4) 4

– 7:5 Reserved (0)

Check 15:8 Check bits [7:0] to write (Diagnostic Mode)

– 31:16 Reserved (0)

reads.

010 : ECC Enable Mode. Performs check bit generation

during memory writes and error detection and correction during memory reads.

011 : Diagnostic Mode for verifying the ECC function. All

check bits are forced to check bits in this register during memory writes.

Multiple ECC Error Interrupt Enable (0) Interrupt occurs when an ECC error is detected and this bit is

set to “1.”

Check 0

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6.5.4 ECC Error Status Register (read only) (0x1E00_0060)

127 32

31 24 23 16 15 8 7 2 1 0

888611

Syndr Check

When there is an ECC Error (single or double bit error), the failing status is stored in this register and an interrupt is generated.

After an ECC Error, the ECC Error Status Register and the ECC Error Address Register keep the status and address of the latest error until it has been read. SBE and MBE are cleared after it is read. Regardless of the ECC Interrupt Enable Bit in the ECC Mode Register, these registers are updated when an ECC error is detected.

Field Bit(s) Description

SBE 0 Single Bit Error (SBE)

MBE 1 Multiple Bit Error (MBE)

–7:2Reserved

Check 15:8 Check bits [7:0]

Syndr 23:16 Syndrome bits [7:0]

– 31:24 Reserved

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6.5.5 ECC Error Address Register (read only) (0x1E00_0070)

127 32

31 4 3 0

ErrAddr 0

28 4

When there is an ECC Error, the failing address is stored in this register. This register keeps the error address of the latest ECC error.

Field Bits Description

ErrAddr 31:4 Error Address [31:4]

–3:0Reserved

6.5.6 Refresh Register (0x1E00_0090) R/W

127 32

31 18 17 16 15 14 13 0

14 1 1 2 14

R F

This register contains parameters that are used for all SDRAMs with the SDRAM controller.

Field Bit(s) Description

Refresh Interval Count Value (0x0400) Implements standard CAS before refreshing RAS. Refresh

RIC 13:0

– 15:14 Reserved (0)

NSRF 16

RFE 17

– 31:18 Reserved (0)

rates for all banks can be programmed in this register. RefIntCnt is a 14-bit counter. If the default value is 0x400 for example and if the clock is 100 MHz, then a refresh sequence will occur every 10 µs. (10 ns × 1024) = 10.24 µs

Non-Staggered Refresh (0) In the non-staggered refresh mode, this bit is set and

sdrCSB[3:0] will be active to simultaneously refresh all banks. Staggered refresh is used to refresh banks in order sequentially.

Refresh Enable (0) SDRAM refresh will be enabled when this bit is set, and will

be disabled when this bit is reset. This bit defaults to 0 (reset) after chip reset. This bit should be enabled after BIOS finishes the SDRAM initialization and initializes all other control registers in the SDRAM controller.

RIC

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Chapter 6: SDRAM Memory Controller

6.5.7 SDRAM Interface Output Drive-Strength Control Register (0x1E00_00A0) R/W

127 32

31 6 5 4 3 2 1 0

D M

26 2 2 2

D S L

This register contains parameters which are used to select the SDRAM interface control/address (i.e. CSB[3:0], CKE, RASB, CASB, WEB, BA[1:0], and AD[12:0]) and data/data-mask (i.e. CB[7:0], DQ[127:0], and DQM[15:0]) output drive-strength.

C A D S

Field Bits Description

Control/Address output drive-strength select (11)

CADSL 1:0

– 2:3 Reserved (0)

DMDSL* 5:4

– 31:6 Reserved

00 : 8 mA 01 : 16 mA 10 : 24 mA 11 : 32 mA

Data/Data-mask output drive-strength select (10) 00 : 8 mA

01 : 16 mA 10 : 24 mA 11 : 32 mA

Note: * Currently 16 mA fixed drivers are implemented for Data/Data-

mask output due to I/O area limitation. DMDSL doesn’t affect drive-strength of Data/Data-mask output drivers.

6.5.8 DIMM 0 LOW Address Decode (0x1E00_0100)

127 32

31 28 27 20 19 0

DIMM 0 LOW boundary 0 -----------------------------------------------------------0

4 (R/W) 8 20

Bits R/W Description

31:28 R/W DIMM 0 27:20 R/W LOW boundary

19:0 R/O 0

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Chapter 6: SDRAM Memory Controller

6.5.9 DIMM 0 HIGH Address Decode (0x1E00_0110)

127 32

31 28 27 20 19 0

DIMM 0 HIGH boundary 1 ------------------------------------------------------------1

4 (R/O) 8 20

Bits R/W Description

31:28 R/O DIMM 0 27:20 R/W HIGH Boundary

19:0 R/O 1

6.5.10 DIM M 1 LOW Address Decode (0x1E00_0120)

127 32

31 28 27 20 19 0

DIMM 1 LOW boundary 0 -----------------------------------------------------------0

4 (R/W) 8 20

Bits R/W Description

31:28 R/W DIMM1 27:20 R/W LOW boundary

19:0 R/O 0

6.5.11 DIM M 1 HIGH Address Decode (0x1E00_0130)

127 32

31 28 27 20 19 0

DIMM1 HIGH boundary 1 ------------------------------------------------------------1

4 (R/O) 8 20

Bits R/W Description

31:28 R/O DIMM1 27:20 R/W HIGH Boundary

19:0 R/O 1

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Chapter 6: SDRAM Memory Controller

6.5.12 DIM M 2 LOW Address Decode (0x1E00_0140)

127 32

31 28 27 20 19 0

DIMM 2 LOW boundary 0 -----------------------------------------------------------0

4 (R/W) 8 20

Bits R/W Description

31:28 R/W DIMM 2 27:20 R/W LOW boundary

19:0 R/O 0

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Chapter 6: SDRAM Memory Controller

6.5.13 DIM M 2 HIGH Address Decode (0x1E00_0150)

127 32

31 28 27 20 19 0

DIMM 2 HIGH boundary 1 ------------------------------------------------------------1

4 (R/O) 8 20

Bits R/W Description

31:28 R/O DIMM 2 27:20 R/W HIGH Boundary

19:0 R/O 1

6.5.14 DIM M 3 LOW Address Decode (0x1E00_0160)

127 32

31 28 27 20 19 0

DIMM 3 LOW boundary 0 -----------------------------------------------------------0

4 (R/W) 8 20

Bits R/W Description

31:28 R/W DIMM 3 27:20 R/W LOW boundary

19:0 R/O 0

6.5.15 DIM M 3 HIGH Address Decode (0x1E00_0170)

127 32

31 28 27 20 19 0

DIMM 3 HIGH boundary 1 ------------------------------------------------------------1

4 (R/O) 8 20

Bits R/W Description

31:28 R/O DIMM3 27:20 R/W HIGH Boundary

19:0 R/O 1

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Chapter 6: SDRAM Memory Controller

6.6 Address Mapping

sysPAddr[27:0] is assorted into bank, row, and column addresses. This section describes the mapping of address bits for performance analysis purposes.

Address range

Device size

sysPAddr

256 MB

128 MB

64 MB

16 MB

31 28 27 26 25 24 23 12 11 ---------6 5 4 3 2 1 0

64 B

16 B = 128b

8 B = 64 b

System elements

256 MB Region Size

Device Type Bank address

BA[1:0]

Row Address

RA[12:0]

12 11 10 … 0 16 Mb – 6 – – 22 …12 64 Mb

128 Mb

76 76

– 24 22 …12 – 24 22 …12

256 Mb 7 6 27 24 22 …12

– : No pins in this device × : Don’t care

AP: Auto Precharge: Assign a constant of 1 to this bit. Number: bit number of sysPAddr [27:3]

4 KB Page Size

SDRAM bus size

sysBus size

Cache line size

Column Address

CA[12:0]

12 11 10 9 8 7 6 … 3 2 …0

––××7 23 11… 8 5 …3 – × AP × 25 23 11… 8 5 …3 – × AP 26 25 23 11…8 5 …3 ××AP 26 25 23 11…8 5 …3

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Chapter 6: SDRAM Memory Controller

6.7 Data ECC Generation

Each of the 64 data bits and 8 check bits has a unique 8-bit SECDED ECC check code; this check code is generated by taking the even parity of the ECC check code for a selected group of data bits. As Figure 6-3 shows, bit locations are numbered from right to left in ascending order, from data bit 0 (furthest right) to data bit 63 (furthest left). For example, data bit 0, in the far right column of the figure, has an 8-bit check value of 0001_0011 are represented in this figure by periods, (.), because they are not used in the calculations).

Figure 6-7 also gives values for the 8 check bits, 7:0. For instance, the 8-bit SECDED ECC code for check bit 6 is in column 6, near the right hand edge of the figure.

(0s

Figure 6-7 Check Matrix for Data ECC Code

Note: * This row indicates the total number of 1s in the generated

syndrome for each data bit in an error.

The SDRAM Controller supports ECC detection and correction of 64-bit (72-bit) SDRAMs. If ECC is enabled and there is an ECC error in the read, an interrupt will be asserted to the CPU and the ECC Error Status Register will be set to indicate that bad data were returned.

For 64-bit (72-bit) SDRAMS, if ECC is enabled, check bits will be generated and written to the sdrCB[7:0] lines during the same cycle that the data are written.

ECC will be generated for partial writes via the read-modify-write protocol. Since most SDRAMs come in 8-bit granularities, ECC checking and generation require an additional SDRAM chip to store the ECC information. In order to generat e the ECC to this extr a device during partial writes, the current ECC bits must first be r ead and then modified during the partial write. The protocol for the read-modify-write transaction is as follows:

1. Read the existing data. On this read, all sdrDQM lines are asserted LOW. This means that the BE (byte enable) for the ECC byte can be connected to ANY of the

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Chapter 6: SDRAM Memory Controller

[6]

sdrDQM[7:0]* outputs. The ECC data are read on the sdrCB[7:0] inputs.

2. Modify the ECC information based on the data that are to be written. The ECC nibble is modified in the SDRAM Controller.

3. Write the new data and new ECC byte.

Figure 6-8 illustrates the procedure that the SDRAM Controller uses to generate ECC in a partial write to SDRAM.

1. READ All Data and Check Bits

x72

SDRAM

Data[7:0]

SDQM[0]*

SSERTED

Data[15:8]

SDQM[1]*

ASSERTED

Data[55:48]

SDQM

SSERTED

Data[63:56]

SDQM[7]*

ASSERTED

CB[7:0]

SDQM[X]*

ASSERTED

2. Modify Check Byte in TX7901

Existing Check Bits

X X X X X X X X

3. Write New Data and Modified Check Byte

x72

Data[7:0]

NEW

SDQM[0]*

ASSERTED

SDRAM

Data[15:8]

NEW

SDQM[1]*

Y Y Y Y Y Y Y Y

MODIFIED Check Bits

SSERTED

Data[55:48]

EXISTING

SDQM[6]*

ASSERTED

SDRAM

Data[63:56]

EXISTING

SDQM[7]*

ASSERTED

SDRAM

CB[7:0]

SDRAM Check

SDQM[X]*

ASSERTED

SDRAM

Figure 6-8 Read Modify Write Transaction by the SDRAM Controller

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Chapter 6: SDRAM Memory Controller

6.8 SDRAM Initialization

Following below is an example of the code used during SDRAM initialization.

/* SDRAMC register definition */ #define SDRAMC 0xbe00_0000 /* SDRAMC base address(virtual) */ #define D0PR 0x0000 /* DIMM0 Parameter Register */ #define D1PR 0x0010 /* DIMM1 Parameter Register */ #define D2PR 0x0020 /* DIMM2 Parameter Register */ #define D3PR 0x0030 /* DIMM3 Parameter Register */

#define DOMR 0x0040 /* Operation Mode Register */ #define DOMR_NORMAL 0 /* Normal Operation Mode */ #define DOMR_NOP 1 /* NOP mode */ #define DOMR_PRECHARGE 2 /* Precharge All Banks */ #define DOMR_WR_MODEREG 3 /* Write SDRAM mode register*/ #define DOMR_REFRESH 4 /* Force a Refresh Cycle */ #define DEMR 0x0050 /* ECC Mode Register */ #define DEESR 0x0060 /* ECC Error Status Register */ #define DEEAR 0x0070 /* ECC Error Address Register */ #define DREFRESH 0x0090 /* Refresh Register */ #define DDRIVE 0x00a0 /* Output Driver Strength */

#define D0LOW 0x0100 /* DIMM0 LOW address */ #define D0HIGH 0x0110 /* DIMM0 HIGH address */ #define D1LOW 0x0120 /* DIMM1 LOW address */ #define D1HIGH 0x0130 /* DIMM1 HIGH address */ #define D2LOW 0x0140 /* DIMM2 LOW address */ #define D2HIGH 0x0150 /* DIMM2 HIGH address */ #define D3LOW 0x0160 /* DIMM3 LOW address */ #define D3HIGH 0x0170 /* DIMM3 HIGH address */

/* configuration for single 32MB DIMM on DIMM0 * consist of five 64Mbit chips with ECC check bit * start end size * DIMM0 0x0000_0000 0x01ff_ffff 32MB * DIMM1 0x0200_0000 0x01ff_ffff 0MB * DIMM2 0x0400_0000 0x03ff_ffff 0MB * DIMM3 0x0600_0000 0x05ff_ffff 0MB */

#define RAMBASE 0x0000_0000 /* start physical address */ #define RAM32MB 0x0200_0000 /* size of 32MB memory */ #define DIMM0ADDR 0xa000_000 /* dummy write address(virtual) for DIMM0 */ #define DPR_CL3 \ 1 /* 1:0 DSL 64/128Mb */\ | 3 << 16 /* 17:16 CAL CL=3 cycle */\ | 3 << 18 /* 20:18 A2RWI Active to Write = 3 cycle */\ | 3 << 21 /* 23:21 P2AI Precharge to active = 3 cycle */\ | 2 << 24 /* 25:24 WRT Write recovery = 2 cycle */\ | 6 << 26 /* 28:26 RRT Refresh Recovery = 10 cycle */\ | 1 << 29 /* 29 A2P Active to Precharge = 6 cycle */

#define SDRM_CL3 /* RA Paddr description */\ 1 << 12 /* 2:0 14:12 Burst Length = 2 */\

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| 0 << 15 /* 3 15 Burst Type = Sequential */\ | 3 << 16 /* 6:4 18:16 CAS Latency = 3 */\ | 0 << 19 /* 8:7 20:19 OpMode = Standard Op */\ | 0 << 21 /* 9 21 Write Burst Mode = programmed */\ | 0xa000_0000 /* UnCached UnMapped area for DIMM0 */

#define SDR_RFSH /* Refresh Register's value */\ 1500 /* RIC: 64ms/4096 >15,000 ns @ 100 MHz */\

| 0<<16 /* NSRF: Staggered refresh */\ | 1<<17 /* RFE: Refresh enable */\

# initialize registers and force NOP mode la k1, SDRAMC # SDRAMC base address la t1, DIMM0ADDR # address of dummy write for DIMM0 li t0, DOMR_NOP sq t0, DOMR(k1) # force NOP mode to prevent unnecessary access

# specify SDRAM parameter li t0, DPR_CL3 sq t0, D0PR(k1) sq t0, D1PR(k1) sq t0, D2PR(k1) sq t0, D3PR(k1)

# set up SDRAM address windows li t0, RAMBASE # start address of DIMM0 li t2, RAMBASE + RAM 32MB-1 # end address of DIMM0 sq t0, D0LOW(k1) # store DIMM0 LOW reg (starting 0x0000_0000) sq t2, D0HIGH(k1) # store DIMM0 HIGH reg (32MB)

li t0, RAMBASE + RAM32MB

li t2, RAMBASE + RAM32MB*2-1 sq t0, D1LOW(k1) # store DIMM1 LOW reg (starting 0x0200_0000) sq t2, D1HIGH(k1) # store DIMM1 HIGH reg (0MB)

li t0, RAMBASE + RAM32MB*2 li t2, RAMBASE + RAM32MB*3-1 sq t0, D2LOW(k1) # store DIMM2 LOW reg (starting 0x0400_0000) sq t2, D2HIGH(k1) # store DIMM2 HIGH reg (0MB)

li t0, RAMBASE + RAM32MB*3 li t2, RAMBASE + RAM32MB*4-1 sq t0, D3LOW(k1) # store DIMM3 LOW reg (starting 0x0600_0000) sq t2, D3HIGH(k1) # store DIMM3 HIGH reg (0MB)

#Precharge All Bank li t0, DOMR_PRECHARGE sq t0, DOMR(k1) # mode set to precharge all bank sw $0, 0(t1) # issue command

# two Auto Refresh cycles li t0, DOMR_REFRESH sq t0, DOMR(k1) sw $0, 0(t1) # issue command sw $0, 0(t1) # issue command twice

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# write SDRAM chip's Mode Register li t0, DOMR_WR_MODEREG sq t0, DOMR(k1) # write SDRAM Mode Register la t2, SDRM_CL3 sw $0, 0(t2) # write address goes to MODE register lw t0, DOMR(k1) # read DOMR to make sure Write Mode Reg # It takes more than 2 x sysBusClk

# start Refresh

li t0, SDR_RFSH

sq t0, DREFRESH (k1)

# return to Normal mode of SDRAMC access li t0, DOMR_NORMAL sq t0, DOMR(k1) sync.l lw t0, DOMR(k1) # read DOMR to make sure Normal mode sync.l

# Now SDRAM is ready for access

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Chapter 7: C790 Bus/G-Bus Bridge

7. C790 Bus / G-Bus Bridge

7.1 Introduction

The C790 Bus/ G-Bus Bridge provides an efficient interface between the C790 bus (and its attached C790 CPU and Main Memory), and the G-Bus (and its attached peripheral devices.) The bridge supports C790 accesses to devices on the G-Bus, and G-Bus Mastering devices’ access to the main memory on the C790 Bus.

Figure 7-1 shows the block diagram of the G-bridge.

C790 Read Command

(Addr, BE, TSize)

C790 Bus

Receiver Interface

C790 Bus

Transmitter

Interface

C790 Bus

Monitors

C790 Bus

Master

State

C790 Bus

Slave State

Machine

CGFIFO (8x1QW)

GCFIFO (9x1QW)

G-Bridge

Registers

G-Bus

Master State

Machine

G-Bus

Slave State

Machine

G-Bus Transmit Interface

G-Bus

Arbiter

Figure 7-1 C790 Bus / G-Bus Bridge Block Diagram

G-Bus

G-Bus Receiver Interface

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7.2 Address Space Decode and Translation

The C790 accesses G-Bus devices through one CG internal register window, one ROM window and four PCI windows. The upper 28-bit address pAddr[31:4] seen on the C790 bus is copied directly onto the G-Bus while the lower 2–bit address is derived from the byte enable bits. G-Bus Masters access the main memory through the memory controller on the C790 Bus via one GC internal register window and five memory windows. The upper 28-bit address seen on the G-Bus is copied directly into the C790 Bus while the lower 2 address bits on the G-Bus are used to specify the location of the word/double-word in a quad-word. (See Figure 7-2.)

C790 Bus Addr

31 4

31 4 3 2 1 0

ByteEnable

Encode Reduce

Byte En.

Figure 7-2 G-Bridge Address Translation

7.3 Bus Transactions

The C790 can issue either a single quad-word operation or 4 quad-word burst operations on the C790 bus. When the C790 initiates a bus cycle to a G-Bus device, the bridge detects the address and posts the written data into the CGFIFO if it is a write transaction, or initiates a G-Bus read transaction. Such transactions are called CG (C790 to G-Bus) transactions.

The masters on the G-Bus can initiate a single double-word operation or a burst operat ion of up to 8 quad-words (16 double words). When G-Bus masters initiate a bus cycle to main memory, the bridge detects the address and posts the written data into the GCFIFO if it is a write transaction, or initiates a C790 Bus read transaction. Such transactions are called GC (G-Bus to C790) transactions.

The C790 Bus supports the Wrap-Around addressing mode while the G-Bus supports the linearly-incrementing addressing mode. 4-quad-word burst operation on the C790 Bus is translated into 4-quad-word aligned burst transaction on the G-Bus.

The C790 and G-Bus Masters can issue their transactions independently and the bridge can handle and arbitrate their concurrent transactions correctly.

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Toshiba TX79 Series, TX7901, TMPR7901 User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Table Of Contents

Table Of Tables

1 Using Toshiba Semiconductors Safely

2 Safety Precautions

3 General Safety Precautions and Usage Considerations

3.5.2 Socket mounting

4 Precautions and Usage Considerations