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TMP88CS34/CP34
CMOS 8-Bit Microcontroller
TMP88CS34N/F, TMP88CP34N/F
The TMP88CS34/CP34 is the high speed and high performance 8-bit single chip microcomputers. This
MCU contain CPU core, ROM, RAM, input/output ports, four Multi-function timer/counters, serial bus
interface, on-screen display, PWM output, 8-bit AD converter, and remote control signal preprocessor on
chip.
Product No. ROM RAM Package OTP MCU
TMP88CS34N/F 64 K u 8-bit
TMP88CP34N/F 48 K u 8-bit
1.5 K u 8-bit
P-SDIP42-600-1.78
P-QFP44-1414-0.80D
TMP88PS34N/F
Features
ٟ 8-bit single chip microcomputer TLCS-870/X Series
ٟ Instruction execution time: 0.25 Ps (at 16 MHz)
ٟ 842 basic instructions
x Multiplication and Division (8 bits u 8 bits, 16 bits u 8 bits, 16 bits/8 bits)
x Bit manipulations (Set/Clear/Complement/Move/Test/Exclusive or)
x 16-bit data and 20-bit data operations
x 1-byte jump/subroutine-call (Short relative jump/Vector call)
ٟ I/O ports: Maximum 33 (High current output: 4)
ٟ 15 interrupt sources: External 6, Internal 10
x All sources have independent latches each, and nested interrupt control is available.
x Edge-selectable external interrupts with noise reject
x High-speed task switching by register bank changeover
ٟ ROM corrective function
ٟ Two 16-bit timer/counters: TC1, TC2
x Timer, Event-counter, Pulse width measurement, External trigger timer, Window modes
ٟ Two 8-bit timer/counters: TC3, TC4
x Timer, Event counter, Capture (Pulse width/duty measurement) mode
000707EBP1
xFor a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Qualit
and Reliability Assurance / Handling Precautions.
xTOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general
can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer,
when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid
situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage t
property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the mos
recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the “Handling Guide fo
Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability Handbook” etc..
xThe TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal
equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are
neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction o
failure of which may cause loss of human life or bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made
at the customer’s own risk.
xThe products described in this document are subject to the foreign exchange and foreign trade laws.
xThe information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed b
TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its
use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION o
others.
xThe information contained herein is subject to change without notice.
Purchase of TOSHIBA I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I
S
ecification as defined by Philips.
2
C system, provided that the system conforms to the I2C Standard
88CS34-1
2003-03-25
TMP88CS34CP34
ٟ Time base timer (Interrupt frequency: 0.95 Hz to 31250 Hz)
ٟ Watchdog timer
x Interrupt source/reset output
ٟ Serial bus interface
ٟ On-screen display circuit
ٟ Jitter elimination
ٟ DA conversion (Pulse Width Modulation) outputs
ٟ 8-bit successive approximate type AD converter with sample and hold
ٟ High current output: 1 pin (typ. 20 mA)
ٟ Remote control signal preprocessor
ٟ Two power saving operating modes
2
x I
C bus, 8-bit SIO mode (Selectable two I/O channels)
x Font ROM characters: Mono font 383 characters, color font 96 characters or mono font 447
characters, color font 64 characters
x Characters display: 32 columns u 12 lines
x Composition: 16 u 18 dots
x Size of character: 4 kinds (line by line)
x Color of character: 8 or 27 kinds (character by character)
x Variable display position: Horizontal 256 steps, Vertical 625 steps
x Fringing, Smoothing, Slant, Underline , Blinking function
x 14/12-bit resolution (2 channels)
x 12-bit resolution (2 channels)
x STOP mode: Oscillation stops. Battery/Capacitor back-up. Port output hold/high-impedance.
x IDLE mode: CPU stops, and Peripherals operate using high-frequency clock. Release by
interrupts.
ٟ Operating voltage: 4.5 to 5.5 V at 16 MHz
ٟ Emulation POD: BM88CS34N0A-M15
88CS34-2
2003-03-25
TMP88CS34CP34
Pin Assignments
P-SDIP42-600-1.78
Package
P-QFP44-1414-0.80D
Package
TMP88CS34N
TMP88CP34N
TMP88PS34N
TMP88CS34F
TMP88CP34F
TMP88PS34F
P-SDIP42-600-1.78
/
/INT2/TC1/AIN0) P53
0KWU
VVSS
) P40
0PWM
) P41
1PWM
) P42
2PWM
) P43
3PWM
(
P32
N.C.
VDD
VSS
1SCK
4KWU
(
(
P-QFP44-1414-0.80D
(SDA0) P35
(TC4) P33
(
(
(
(
88CS34-3
VSS
) P40
(
0PWM
(
) P41
1PWM
(
) P42
2PWM
) P43
(
3PWM
P44
P45
P46
P47
) P50
(TC2/
(SO1/SDA1) P52
(
(
(
/Y/BLIN/AIN4) P60
5KWU
0INT
(SI1/SCL1) P51
/AIN1) P54
1KWU
/AIN2) P55
2KWU
/AIN3) P56
3KWU
/BIN/AIN5) P61
(GIN) P62
(RIN) P63
(I) P57
P30 (INT3/RXIN)
P34 (SCL0)
P31 (INT4/TC3)
31
33
32
34
35
36
37
38
39
40
41
42
43
44
3
1
2
P46
P44
P45
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17 26
18
19
20
21
)
STOP
/
INT5
P20 (
XIN
TEST
RESET
XOUT
30
27
29
26
28
4
7
8
5
6
P47
) P50
) P51
NT0
SCL1
(SI1/
(TC2/I
(SO1/SDA1) P52
/INT2/TC1/AIN0) P53
SCK1
/
KWU0
(
OSC2
25
/AIN1) P54
KWU1
(
OSC1
24
/AIN2) P55
KWU2
(
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
25
24
23
22
)
VD
P71 (
23
22
21
20
19
18
17
16
15
14
13
12
11 9 10
/AIN3) P56
KWU3
(
VDD
P33 (TC4)
P32
VVSS
P35 (SDA0)
P34 (SCL0)
P31 (INT4/TC3)
P30 (INT3/RXIN)
5INT/STOP
P20 (
RESET
XOUT
XIN
TEST
OSC2
OSC1
P71 (
P70 (
P67 (Y/BL)
P66 (B)
P65 (G)
P64 (R)
)
VD
)
HD
P70 (HD)
P67 (Y/BL)
P66 (B)
P65 (G)
P64 (R)
N.C.
P57
P63 (RIN)
P62 (GIN)
P61 (BIN//AIN5/
P60 (Y/BLIN/AIN4/
2003-03-25
)
KWU5
)
)
4KWU
TMP88CS34CP34
Pin Functions (1/2)
Pin Name I/O Function
1-bit input/output port with latch.
P20 (
INT5/STOP
P35 (SDA0) I/O (Input/Output) I2C bus serial data input/output 0
P34 (SCL0) I/O (Input/Output) I2C bus serial clock input/output 0
P33 (TC4) I/O (Input)
P32 I/O
P31 (INT4/TC3) I/O (Input)
P30 (INT3/RXIN) I/O (Input)
P47 I/O
P46 I/O
P45 I/O
P44 I/O
P43 (
PWM3
P42 (
PWM2
P41 (
PWM1
P40 (
PWM0
P57 (I) I/O (Output) Translucent signal output
P56 (
KWU3
P55 (
KWU2
P54 (
KWU1
P53
(
/AIN0/TC1
KWU0
/INT2/
SCK1
P52 (SDA1/SO1)
P51 (SCL1/SI1)
P50 (TC2/
P67 (Y/BL) I/O (Output) Y or BL output
P66 (B) I/O (Output)
P65 (G) I/O (Output)
P64 (R) I/O (Output)
P63 (RIN) I/O (Input) R input
P62 (GIN) I/O (Input) G input
P61
/BIN/AIN5)
(
KWU5
P60
(
/YBLIN/AIN4)
KWU4
) I/O (Input)
) I/O (Output)
) I/O (Output)
) I/O (Output)
) I/O (Output)
/AIN3) I/O (Input)
/AIN2) I/O (Input)
/AIN1) I/O (Input)
I/O
)
INT0
)
(Input/Input/Input
/Input/Output)
I/O
(Input/Output/Output)
I/O
(Input/Output/Input)
I/O
(Input/Input)
I/O (Input)
I/O (Input)
When used as an input port, the
latch must be set to “1”.
6-bit programmable input/output
port. Each bit of these ports can be
individually configured as an input or
an output under software control.
During reset, all bits are configured
as inputs. When used as a serial bus
interface input/output, the latch must
be set to “1”.
8-bit programmable input/output
port. Each bit of these ports can be
individually configured as an input or
an output under software control.
During reset, all bits are configured
as inputs.
8-bit programmable input/output
port. Each bit of these ports can be
individually configured as an input or
an output under software control.
During reset, all bits are configured
as inputs. When used as a serial bus
interface input/output, the latch must
be set to “1”.
8-bit programmable input/output
port. (P67 to 61: Tri-State, P60: High
current output) Each bit of these
ports can be individually configured
as an input or an output under
software control. During reset, all
bits are configured as inputs. When
used P64 to P67 as port, each bit of
the P6 port data selection register
(bit 7 to 4 in ORP6S) must be set to
“1”.
P63 to P61 output 0 after a reset.
When these dual-function pins are
used as ports, be sure to set
ORP6S2 to “1”.
External interrupt input 5 or STOP
mode release signal input
Video signal input 1 or Composite
sync input
External interrupt input 4 or
Timer/Counter input 3
External interrupt input 3 or Remote
control signal preprocessor input
12-bit DA conversion (PWM) outputs
14/12-bit DA conversion (PWM)
outputs
Key on wake-up inputs or AD
converter analog inputs
Key on wake-up input or AD
converter analog input or
Timer/counter input 1 or External
interrupt input 2 or SIO serial clock
input/output 1
2
I
C bus serial data Input/Output 1 or
SIO serial data output 1
2
I
C bus serial data Input/Output 1 or
SIO serial data input 1
Timer/Counter input 2 or External
interrupt input 0
R/G/B outputs
Key on wake-up input 5 or B input or
AD converter analog input 5
Key on wake-up input 4 or Y/BL
input or AD converter analog input 4
88CS34-4
2003-03-25
TMP88CS34CP34
Pin Functions (2/2)
Pin Name I/O Function
P71 ( VD ) I/O (Input) Vertical synchronous signal input
P70 (HD) I/O (Input)
XIN, XOUT Input, Output
RESET I/O
TEST Input Test pin for out-going test. Be tied to low.
OSC1, OSC2 Input, Output Resonator connecting pins for on-screen display circuitry
VDD, VSS, VVSS Power Supply 5 V, 0 V (GND)
2-bit programmable input/output
port. Each bit of these ports can be
individually configured as an input or
an output under software control.
During reset, all bits are configured
as inputs.
Resonator connecting pins. For inputting external clock, XIN is used and
XOUT is opened.
Reset signal input or watchdog timer output/address-trap-reset
output/system-clock-rest output
Horizontal synchronous signal input
88CS34-5
2003-03-25
TMP88CS34CP34
Block Diagram
OSC Connecting
Pins for On-Screen
Display
OSC1
OSC2
Power
VDD
Supply
VSS
VVSS
Reset I/O Test Pin
RESET
TEST
Resonator
Connecting Pins
XIN
XOUT
TLCS-870/X
CPU core
System Controller
Standby Controller
Timing Generator
High
frequency
Clock
Generator
Display
Memory
Data Memory
(RAM)
Time Base
Watchdog
Timer
Timer
Character
ROM
On-screen display circuit
R, G, B,
Y/BL
Interrupt Controller
16-bit
Timer
TC1 TC2
Jitter
Elimination
Timer/Counter
TC3 TC4
8-bit
VD
HD
I/O Ports
P64 to P67 P70, 71 P 57
I
P6 P7 P5
ROM corrective circuit
Program Counter
Program Memo ry
(ROM)
Inst. Register
Inst. Decoder
P4 P2
DA Converter
(PWM)
P5
8-bit
AD
Key on
wake up
I/O Ports
Remote
control signal
P60 to P63 P50 to P56 P40 to P47 P20
P3 P6
P30 to P35
Serial Bus
Interface
Y/BLIN
RIN
GIN
BIN
88CS34-6
2003-03-25
Operational Description
TMP88CS34/CP34
1.
CPU Core Functions
The CPU core consists of a CPU, a system clock controller, and an interrupt controller.
This section provides a description of the CPU core, the program memory, the data memory, the
external memory interface, and the reset circuit.
1.1 Memory Address Map
The TMP88CS34/CP34 memory consists of four blocks: ROM, RAM, SFR (Special Function
Register), and DBR (Data Buffer Register). They are all mapped to a 1-Mbyte address space.
Figure 1.1.1 shows the TMP88CS34/CP34 memory address map. There are 16 banks of the
general-purpose register. The register banks are also assigned to the RAM address space.
SFR
RAM
DBR
ROM
ROM: Read Only Memory includes
RAM: Random Access Memory includes
SFR: Special Function Register includes
DBR: Data Buffer Register includes
00000H
0003FH
00040H
000BFH
000C0H
006BFH
00F80H
00FFFH
04000H
13EFFH
FFF00H
FFF3FH
FFF40H
FFF7FH
FFF80H
FFFFFH
Program memory, Character data memory for OSD
Data memory, Stack, General-purpose register banks
I/O ports, Peripheral hardware control registers, Peripheral hardware status registers
System control registers, Interrupt control registers, Program status word
Control register for on-screen display (OSD)
Remote-control-receive control/status registers, ROM correction control registers
Test video signal control registers
64 bytes
128 bytes
1536 bytes
128 bytes
65280 bytes
64 bytes
64 bytes
128 bytes
TMP88CS34
00000H
0003FH
00040H
000BFH
000C0H
006BFH
00F80H
00FFFH
04000H
0FEFFH
FFF00H
FFF3FH
FFF40H
FFF7FH
FFF80H
FFFFFH
64 bytes
128 bytes
1536 bytes
128 bytes
48896 bytes
64 bytes
64 bytes
128 bytes
TMP88CP34
Figure 1.1.1 Memory Address Map
88CS34-7
2003-03-25
TMP88CS34/CP34
Electrical Characteristics
Absolute maximum ratings
Parameter Symbol Pins Ratings Unit
Supply Voltage VDD 0.3 to 6.5
Input Voltage VIN 0.3 to VDD 0.3
Output Voltage V
Output Current (Per 1 pin)
Output Current (Total)
Power Dissipation [Topr 70 qC] PD
Soldering Temperature (time) Tsld 260 (10 s)
Storage Temperature Tstg 55 to 125
Operating Temperature Topr 30 to 70
Note: The abs olute maximum ratings are rated va lues which must not be exceeded during operation,
even for an instant. Any one of the ratings must not be exceeded. If any absolute maximum rating is
exceeded, a device may break down or its performance may be degraded, causing it to catch fire or
explode resulting in i njury to the user. Thus, when designing products whic h include this device,
ensure that no absolute maximum rating value will ever be exceeded.
Recommended operating conditions
Parameter Symbol Pins Conditions Min Max Unit
Supply Voltage VDD
V
Except hysteresis input VDD u 0.70
IH1
Input High Voltage
Input Low Voltage
Clock Frequency
V
Hysteresis input VDD u 0.75
IH2
Key-on Wake-up input
V
IH3
V
Except hysteresis input VDD u 0.30
IL1
V
Hysteresis input
IL2
Key-on Wake-up input VDD 4.5 to 5.5V
V
IL3
fc XIN, XOUT VDD 4.5 to 5.5V 8.0 16.0
Internal clock VDD 4.5 to 5.5V
f
OSC
(VSS 0 V)
0.3 to VDD 0.3
OUT1
I
Ports P2, P3, P4, P5, P61 to P67, P7 3.2
OUT1
I
Ports P60 30
OUT2
Ports P2, P3, P4, P5, P64 to P67, P7 30
6 I
OUT1
Ports P60 30
6 I
OUT2
(VSS 0 V, Topr 30 to 70 qC)
fc 16 MHz NORMAL mode
fc 16 MHz IDLE mode
STOP mode
V
4.5 to 5.5V
DD
V
4.5 to 5.5V
V
DD
fc 8 MHz 8.0 12.0
fc 16 MHz 16.0 24.0
400
4.5 5.5
V
DD
u 0.90
DD
0
V
u 0.25
DD
VDD u 0.65
V
mA
mW
qC
V
MHz
Note 1: The recommended operating conditions for a device are operating conditions under which it can be
guaranteed that the device will operate as specified. If the device is used under operating conditions
other than the recomm ended operating conditions (supply voltage, operat ing temperature range,
specified AC /DC values e tc.), malfunct ion may occur . Thus, when design ing product s which incl ude
this device, ensure that t he recomm ended oper atin g cond itions f or the de vice are alwa ys adhere d
to.
Note 2: Clock frequency fc: Supply voltage range is specified in NORMAL mode and IDLE mode.
Note 3: Smaller value is alternatively specified as the maximum value.
88CS34-208
2003-03-25
TMP88CS34/CP34
Hysteresis voltage VHS Hysteresis inputs 0.9 V
Input current
Input resistance R
Output leakage
current
Output high voltage V
Output low voltage VOL
Output low current I
Supply current in
NORMAL mode
Supply current in
IDLE mode
Supply current in
STOP mode
DC Characteristics
Parameter Symbol Pins Conditions Min Typ. Max Unit
I
TEST VDD 5.5 V, VIN 5.5 V/0 V r 2
IN1
I
Open drain ports VDD 5.5 V, VIN 5.5 V/0 V r 2
IN2
I
Tri-state ports VDD 5.5 V, VIN 5.5 V/0 V r 2
IN3
I
I
LO1
I
LO2
OL3
I
IN4
IN2
OH2
DD
RESET, STOP
RESET
Sink open drain ports VDD 5.5 V, V
Tri-state ports VDD 5.5 V, V
Tri-state ports VDD 4.5 V, IOH 0.7 mA 4.1
Except XOUT and
ports P60
Port P60 VDD 4.5 V, IOL 1.0 V 20
(VSS 0 V, Topr 30 to 70 qC)
V
V
5.5 V, VIN 5.5 V/0 V r 2
DD
5.5 V, VIN 0 V 100 220 450 k:
DD
5.5 V 2
OUT
5.5 V/0 V r 2
OUT
VDD 4.5 V, IOL 1.6 mA 0.4
V
5.5 V
DD
fc 16 MHz (Note3)
5.3 V/0.2 V
V
IN
5.5 V
V
DD
V
5.3 V/0.2 V
IN
PA
PA
V
25 30
20 25
0.5 10 PA
mA
Note 1: Typical values show those at Topr 25 qC, VDD 5 V.
Note 2: Input Current I
Note 3: Supply Current I
; The current through resistor is not included.
IN3
; The current (Typ. 0.5 mA) through ladder resistors of ADC is included in
DD
NORMAL mode and IDLE mode.
AD Conversion Characteristics
Parameter Symbol Conditions Min Typ. Max Unit
Analog reference voltage
Analog reference voltage range ǻV
Analog input voltage V
Nonlinearity error r1
Zero point error r2
Full scale error r2
Total error
V
V
(VSS 0 V, VDD 4.5 V t o 5.5 V, Topr 30 to 70 qC)
supplied from VDD pin. V
AREF
supplied from VSS pin. 0
ASS
VDD VSS V
AREF
VSS V
AIN
V
5.0 V
DD
r3
DD
DD
Note: The total error means all error except quanting error.
DD
V
LSB
88CS34-209
2003-03-25
Machine cycle time tcy
High level clock pulse width t
Low level clock pulse width t
AC characteristics
Parameter Symbol Conditions Min Typ. Max Unit
WCH
WCL
Recommended oscillating conditions
Parameter Oscillator
High-frequency
oscillation
Ceramic resonator
TMP88CS34/CP34
(VSS 0 V, VDD 4.5 V to 5.5 V, Topr 30 to 70 qC)
In NORMAL mode
In IDLE mode
For external clock operation
(XIN input), fc 16 MHz
(VSS 0 V, VDD 4.5 V to 5.5 V, Topr 30 to 70 qC)
Oscillation
Frequency
8 MHz Murata CSA 8.00MTZ 30 pF 30 pF
16 MHz Murata CSA 16.00MXZ040 5 pF 5 pF
XIN XOUT
High-frequency Oscillation
Recommended Oscillator
C2 C1
0.5 1.0 Ps
31.25 ns
Recommended Constant
C
1
C
2
Note 1: To keep reliable operation, shield the de vice electric ally with the m etal plate on its package m old
surface against the high electric field, for example, by CRT (Cathode Ray Tube) .
Note 2: The product num bers and specif ications of the res onators by Murat a Manufacturing C o., Ltd. are
subject to change. For up-to-date information, please refer to the following URL;
http://www.murata.co.jp/search/index.html
88CS34-210
2003-03-25
Recommended oscillating conditions
Item Resonator
Oscillation for OSD LC resonator
The frequency generated in LC oscillation can be obtained using the following equations.
1
f
Ǒ
LC2
is not fixed at a constant value. It can be changed to tune into the desired frequency.
C
1
㨯
C,
TMP88CS34/CP34
(VSS 0 V, VDD 4.5 V to 5.5 V, Topr 30 to 70 qC)
Oscillation
Frequency
8 MHz 33 5 to 30 10
12 MHz 15 5 to 30 10
16 MHz 10 5 to 30 10
20 MHz 6.8 5 to 25 10
24 MHz 4.7 5 to 25 10
OSC1 OSC2
C
1
CC
21
CC
21
L
Oscillation for OSD
C2
Recommended parameter value
L (PH) C
(pF) C2 (pF)
1
Note 1: Toshiba’s OSD circuit determines a horizontal display start position by counting clock pulses
generated in LC oscillation. For this reason, the OSD circuit may fail to detect clock pulses normally,
resulting in the hori zontal start position becom ing unstable, at the beginning of oscillation, if the
oscillation amplitude is low.
Changing L and C
from the values reco mmended for a spec ific frequency m ay hamper a stable
2
OSD display.
If the LC oscillati on frequency is the same as a h igh-frequency cloc k value, the oscillation of the
high-frequency oscil lator may cause the LC osc illation frequency to fluctua te, thus making OSD
displays flicker.
When determining t hese parameters, please chec k the oscillation frequenc y and the stability of
oscillation on your TV sets.
Also check the deter mined parameters on your fin al products, because the opt imum parameter
values may vary from one product to another.
Note 2: W hen using the LSI package in a stro ng electric field, suc h as near a CRT, elect rically sh ield the
package so that its normal operation can be maintained.
88CS34-211
2003-03-25
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