Toshiba TMP87CP24AF User Manual

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TOSHIBA

CMOS 8-Bit Microcontroller

TMP87CM24A/P24A

TMP87CM24AF, TMP87CP24AF

The TMP87CM24A/P24A are the high speed and high performance 8-bit single chip microcomputers. These

MCU contain, large ROM, RAM, input/output ports, LCD driver, a 8-bit AD converter, four multi-function

timer/counters, two serial interfaces, and two clock generators on chip.

Product No. TMP87CM24A TMP87CP24A

ROM RAM 32 Kx8 bits 48 K X 8 bits

2Kx8bits P-LQFP100-1414-0.50C

Features

♦8-bit single chip microcomputer TLCS-870 Series ♦ instruction execution time: 0.5 jjs (at 8 MHz), 122 jjs (at 32 kHz) ♦ 129 types and 412 basic instructions

• Multiplication and Division (8 bitsx 8 bits, 16 bits -r 8 bits): Execution time 3.5 /js (at 8 MHz)

• Bit manipulations (Set/Clear/Complement/Load/Store/Test/Exclusive OR)

• 16-bit data operations

• 1-byte jump/call (Short relative jumpA/ector call)

♦ l4 interruptsources(External: 5, Internal: 9)

• All sources have independent latches each, and nested interrupt control is available

• 4 edge-selectable external interruptswith noise reject

• High-speed task switching by register bank changeover

♦ lO-input/output ports (Max 69 pins)

♦two 16-bit timer^ounters

• Timer, Event counter. External trigger timer. Window, PPG output Pulse width measurement modes

♦Two 8-bit timer/counters

• Timer, Eventcounter, Capture (Pulse width/duty measurement), PWM output, PDO modes

♦Time Base Timer (Interrupt frequency: 1 Hz to 16384 kHz) ♦ Divider output function (frequency: 1 kHz to 8 kHz) ♦watchdog Timer

♦two 8-bit Serial Interfaces

• Each 8 bytes transmit/receive data buffer

• Internal/external serial clock, and 4-/8-bit mode

Package

OTP MCU

TMP87PP24A

000707EBP1

I For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled

Quality and Reliability Assurance / Handling Precautions.

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc..

• The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk.

• The products described in this document are subject to the foreign exchange and foreign trade laws.

• The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others.

• The information contained herein is subject to change without notice.

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♦ LCD driver

• Built-in voltage booster for LCD driver

• With display memory (20 bytes)

• LCD direct drive capability (Max 40 seg x 4 com)

• 1/4,1/3,1/2 duty or static drive are programmably selectable

♦8-bit successive approximate type AD converter with sample and hold

• 8 analog inputs

• Conversion time:23 /^s/92 fxs (at 8 MHz) ♦ Dual clock operation (optional) ♦ Five Power saving operating modes

• STOP mode: Oscillation stops. Battery/Capacitor back-up. Port output hold/high-impedance.

• SLOW mode: Low power consumption operation using

low-frequency clock (32.768 kHz).

• IDLE1 mode: CPU stops, and Peripherals operate using

high-frequency clock. Release by interrupts.

• IDLE2 mode: CPUstops,and Peripheralsoperate using high and lowfrequency clock.

Release by interrupts.

• SLEEP mode: CPU stops, and Peripherals operate using low-frequency clock.

Release by interrupts.

♦Operating Voltage: 2.2 to 5.5 V at 4.2 MHz/32.768 kHz, 4.5 to 5.5 V at 8 MHz/32.768 kHz

• Emulation Pod: BM87CP24F0A

TMP87CM24A/P24A

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(XTOUT) P22

(XT I N) P21

_____ ______

(INT5/STOP) P20

(INT3/TC3) P40

(PWM/PDO) P41

(SCK1) P42

(501) P44

(SCK2) P45

(502) P47

vss

XOUT

X I N

RESET

TEST

(S I 1) P43

(S I 2) P46

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TOSHIBA

Block Diagram

Power Supply

LCD drive [em power supply 1

Reset I/O Test Pin

Resonator

or r

Connecting

Pins

ing-j

RESET

TEST

XIN -

XOUT"

V3-

Voltage booster

for LCD driver

System Controller

Standby Controller

Timing Generator

High frequ.

Lowfrequ.

Common outputs

COM3 to COMO

1Í

1 LCD Driver

Clock

Generator

______

i M:

PSV\

Flags RBS

Time Base

Timer

Watchdog

Timer

Segment outputs

SEG11 toSEGO

Stack Pointer

Interrupt Controller

16-Bit Timer/ Counter

TCI 1 TC2

8-Bit

Timer/Counter

TMP87CM24A/P24A

I/O Port(Segment outputs)

__________A___________

P67 P77 P87

to to to to

P60 P70 P80 P90

____

^ ^ ^

Data Memory

(RAM)

Serial

Interfaces

SI01 SI02

P8 P9

Program Counter

Program

Memory (ROM)

Inst. Register

Inst. Decoder

P93

O a:): O ÍI

8bit

A/D converter

VAREE

VASS

Analog

reference

voltage

P57 (AI N7) P07

to to to

V^PSO (AINO) POO

(Analog inputs)

P17

to to to

P10 P30 P40

P35

I/O ports

P47

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TMP87CM24A/P24A

Pin Functions

Pin Name Input/Output

P07 to POO P17, P16 P15(TC2) P14(P^) P13(DVO)

P12(INT2/TC1)

P11 (INTI) P10(TÑTÜ) External interrupt 0 input

P22 (XTOUT) P21 (XTIN)

P20(INT5/STOP) P35 to P30 I/O

P47 (S02) P46 (SI 2) P45 (SCK2) P44 (SOI) I/O (Output) SI01 serial data output P43 (SI1) I/O (Input) SI01 serial data input P42 (SCK1)

P41 (PWM/PDO) I/O (Output)

P40(INT3/TC3) I/O (Input)

P57(AIN07) to

PSO(AINOO)

SEG39 (P80) to

SEG32 (P87)

SEG31 (P70)to

SEG24 (P77)

SEG23 (P60) to

SEG16(P67)

SEG15(P90) to

SEG12(P93)

SEG11 toSEGO

COM3 to COMO XIN, XOUT

RESET TEST VDD, VSS VAREE, VASS C0,C1, VI, V2, V3

I/O

I/O (Input)

I/O (Output)

I/O (Input)

I/O (Output)

I/O (Input)

I/O (Output)

I/O (Input) SI02 serial data input

I/O (I/O) SI02 serial clock input/output

I/O (I/O) SI01 serial clock input/output

I/O (Input)

Output (I/O)

Output Output

Input, Output

I/O Reset signal input or watchdog timer output/address-trap-reset output

Input Test pin for out-going test. Be fixed to low.

Power Supply

LCD voltage

booster pin

8-bit programmable input/output ports (tri-state).

Each bit of these ports can be individually configured as an input or an output under software control.

When used as an input port, timer/counter

input or external interrupt input, the P0CR/P1CR must be set to "0". When used as timer/counter output or divider output,

the P0CR/P1CR must be set to "1" after

setting output latch to "1".

3-bit input/output port with latch.

When used as an input port, external interrupt input or STOP mode release input, the output latch must be set to "1".

6-bit input/output port with latch.

When used as inout oort. the outout latch must be set to "1". 8-bit input/output port with latch.

When used as serial interface output or timer/counter output, the P4CR1 must be

set to "1" after setting output latch to "1".

When used as an input port, serial

interface input or external interrupt input,

the P4CR1 must be set to "0".

8-bit programmable input/output port (tri state). Each bit of the port can be individually configured as an input or an output under software control.

When used as analog input, the P5CR must

be set to "0". 8-bit input/output port with latch.

When used as an input port, the segment

output control register must be set to "0" after setting output latch to "1".

4-bit input/output port with latch. When used as an input port, the segment output control register must be set to "0" after setting output latch to "1".

LCD segment outputs LCD common outputs

Resonator connecting pins for high-frequency clock. For inputting external clock, XIN is used and XOUT is ooened.

+ 5V, OV(GND)

Analog reference voltage inputs (High, Low)

LCD voltage booster pin. Capacitors are required between CO and Cl pin and between V1/V2/V3 pinandGND.

Function

Timer/Counter 2 input Programmable pulse generator output Divider output

External interrupt 2 input or Timer/Counter 1 input

External interrupt 1 input

Resonator connecting pins (32.768 kHz). For inputting external clock, XTIN is used and XTOUT is opened.

External interrupt 5 input or STOP mode release signal input

SI02 serial data output

8-bit PWM output, 8-bit programmable divider output External interrupt 3 input, Timer/Counter 3 input

AD converter analog inputs

LCD segment outputs. When used as segment output, the segment output control register must be set to "1".

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TMP87CM24A/P24A

Operational Description

1. CPU Core Functions

The CPU core consists of a CPU, a system clock controller, an interrupt controller, and a watchdog timer. This section provides a description of the CPU core, the program memory (ROM), the data memory (RAM), and the reset circuit.

1.1 Memory Address Map

TheTLCS-870 Series is capable of addressing 64K bytes of memory. Figure 1-1 shows the memory address mapsof theTMP87CM24A/P24A. In theTLCS-870 Series, the memory is organized 4 address spaces (ROM, RAM, SFR, and DBR). It uses a memory mapped I/O system, and all I/O registers are mapped in the SFR/DBR address spaces. There are 16 banks of general-purpose registers. The register banks are also assigned to the first 128 bytes of the RAM address space.

SFR

RAM

DBR

ROM

OOOOh

003F

^ 0040

OOBF OOCO

083 F

/ 0F80

k OFFF

4000

FFOO

FFBF FFCO

FFDF FFEO

\ FFFF

64 bytes

128 bytes

1920 bytes

48896 bytes

192 bytes

32 bytes 32 bytes

TMP87CP24A

OOOOh

003F 0040

OOBF OOCO

083 F

0F80

64 bytes

128 bytes

1920 bytes

TMP87CM24A

ROM: Read Only Memory includes:

RAM: Random Access Memory includes :

SFR: Special Function Register includes:

DBR: Data Buffer Register includes:

Program memory

Data memory Stack General-purpose register banks

I/O ports Peripheral control registers Peripheral status registers System control registers Interrupt control registers Program Status Word

SIO data buffer

Vector table for vector call instructions (16 vectors)

Vector table for interrupts/ reset (16 vectors)

Entry area for page call instructions

Figure 1-1. Memory Address Maps

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1.2 Program Memory (ROM)

The TMP87CM24A has a 32Kx8-bit (addresses 8000h to FFFFh), and the TMP87CP24A has a 48Kx8-bit (addresses 4000h to FFFFh) of program memory (mask programmed ROM). Addresses FFOOh to FFFFh in the program memory can also be used for special purposes.

(1) Interrupt/Reset vector table (addresses FFEOh to FFFFh)

This table consists of a reset vector and 15 interrupt vectors (2 bytes/vector). These vectors store a

reset start address and interrupt service routine entry addresses.

(2) Vector table for vector call instructions (addresses FFCOh to FFDFh)

This table stores call vectors (subroutine entry address, 2 bytes/vector) for the vector call instructions

[CALLV n]. There are 16 vectors. The CALLV instruction increases memory efficiency when utilized

for frequently used subroutine calls (called from 3 or more locations).

(3) Entry area (addresses FFOOh to FFFFh) for page call instructions

This is the subroutine entry address area for the page call instructions [CALLP n]. Addresses FFOOh-

FFBFh are normally used because address FFCOh to FFFFh are used for the vector tables.

Programs and fixed data are stored in the program memory. The instruction to be executed next is read from the address indicated by the current contents of the program counter (PC). There are relative jump and absolute jump instructions. The concepts of page or bank boundaries are not used in the program memory concerning any jump instruction.

Example: The relationship between the

jump instructions and the PC.

E8C4H: JRS T, $ + 2 + 08H

WhenJF = 1,thejump ismadeto E8CEh, which is 08h added to the contents of the

PC. (The PC contains the address of the instruction being executed+ 2;

therefore, in this case, the PC contents are E8C4h + 2 = E8C6h.)

@ 8-bit PC-relative jump [JR cc, $ + 2+d]

E8C4H : JR Z, $ + 2 + 80H

When ZF = 1, the jump is made to E846h, which is FF80h (-128) added to the current contents of the PC.

(3) 16-bitabsolute jump [JP a]

E8C4H : JP 0C235H

An unconditional jump is made to address C235h- The absolute jump

instruction can jump anywhere within

the entire 64-Kbyte space.

Address

4000h

(8000)

FFOO

FF7B FFBF

FFCO FFC1 FFC2

FFDF FFEO FFE1 FFE2

FFFD FFFE FFFF

call vector (L)

call vector (H)

interrupt vector (L)

interrupt vector (H)

reset vector (L)

reset vector (H)

Figure 1-2. Program Memory Map

TMP87CM24A/P24A

ROM contents

Example :

56 C8

3E CO

The relationship between ROM Contents and Call group instructions/Interrupt/ Reset

CALLP 7BH PC<-FF7B

CALLV OH ; PC<-C856h

INT5 PC D368

RESET PC<-C03E

In theTLCS-870 Series, the same instruction used to access the data memory (e.g. [LD A, (HL)]) is also used to read out fixed data (ROM data) stored in the program memory. The register-offset PC-relative addressing (PC + A) instructions can also be used, and the code conversion, table look-up and n-way multiple jump processing can easily be programmed.

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Example 1 : Loads the ROM contents at the address specified by the HL register pair

TMP87CM24A/P24A

contents into the accumulator (TMP87CM24A : HL^SOOOh):

LD A, (HL) ; A<-ROM (HL)

Example 2

TABLE : SNEXT

Converts BCD to 7-segment code (common anode LED). When A = 05h, 92h is output to port P6 after executing the following program:

ADD A, TABLE-$-4 ; P6<-ROM (TABLE + A)

LD (P6), (PC + A)

JRS T, SNEXT ; JumptoSNEXT ^f 9 f b

DB OCOH, 0F9H, 0A4H, OBOH, 99H, 92H, 82H, 0D8H, 80H, 98H

Notes: "$ " is a header address of ADD instruction.

DB is a byte data difinition instruction.

Example 3 N-way multiple jump in accordance with the contents of

accumulator (0^ A^ 3):

SHLC JP

A ; if A = 00h then PC<-C234h (PC + A) if A = 01H then PC<-C378h

if A = 02h then PC<-DA37h if A = 03h then PC<-E1B0h

0C234H, 0C378H, 0DA37H, 0E1B0H

I Note : DW is a word data definition instruction. Word=2bytes

SHLC A

- JP (PC + A) -

34 C2 78 C3 37

BO El

1.3 Program Counter (PC)

The program counter (PC) is a 16-bit register which indicates the program memory address where the instruction to be executed next is stored. After reset, the user defined reset vector stored in the vector table (addresses FFFFh and FFFEh) is loaded into the PC ; therefore, program execution is possible from any desired address. For example, when COh and 3Eh are stored at addresses FFFFh and FFFEh, respectively, the execution starts from address C03Eh after reset. The TLCS-870 Series utilizes pipelined processing (instruction pre-fetch); therefore, the PC always indicates 2 addresses in advance. For example, while a 1-byte instruction stored at address Cl 23h is being executed, the PC contains Cl 25h-

MSB LSB

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Program Counter (PC)

PCh

(a) Configuration

PCl

PC Contents

Instruction Execution

Figure 1-3. Program Counter

Z)C

(b) Timing chart of PC contents and Instruction Execution

ХЗЗЕОСЗЕПС

a + 1

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TMP87CM24A/P24A

1.4 Data Memory (RAM)

The TMP87CM24A/P24A have a 2Kx 8-bit (address 0040h to 083Fh) of data memory (static RAM). Figure 1 -4 shows the data memory map. Addresses OOOOh to OOFFh are used as a direct addressing area to enhance instructions which utilize this addressing mode; therefore, addresses 0040h to OOFFh in the data memory can also be used for user flags or user counters.

Example 1 : If bit 2 at data memory address OOCOh is "1", OOh is written to data memory at

address 00E3h; otherwise, FFh is written to the data memory at address 00E3h-

TEST (00C0H).2 JRS T,SZERO CLR (00E3H)

JRS SZERO : SNEXT:

Example 2 : Increments the contents of data memory at address OOFSh, and clears to OOh when

LD (00E3H),0FFH

T,SNEXT

IOh is exceeded.

INC (OOFSH) ; (OOFSh) (OOFSh) +1

AND (OOFSH), OFH ; (OOFSh) (OOFSh)aOFh

General-purpose register banks (8 registersx 16 banks) are also assigned to the 128 bytes of addresses

0040h-00BFh. Access as data memory is still possible even when being used for registers. For example,

when the contents of the data memory at address 0040h is read out, the contents of the accumulator in the bank 0 are also read out. The stack can be located anywhere within the data memory except the register bank area. The stack depth is limited only by the free data memory size. For more details on the stack, see section "1.7 Stack and Stack Pointer". With the TMP87CM24A/P24A, programs in data memory cannot be executed. If the program counter indicates a specific data memory address (addresses 0040h to 083Fh), an address-trap-reset is generated due to due to bus error. (Output from the RESET pin goes low.)

; if (OOCOh) 2 = 0 then jump

; (00E3h)^00h

; (00E3h)^FFh

Example Clears RAM to "OOh" except the bank 0

LD HL, 0048H

LD A, H

LD BC, 07F7H SRAMCLR

Note: The data memory contents become unstable when the power supply is turned on; therefore, the

data memory should be initialized by an initialization routine. Note that the general-purpuse registers are mapped in the RAM; therefore, do not clear RAM at the current bank addresses.

LD (HL + ), A

DEC BC

JRS

F, SRAMCLR

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; Sets start address to HL register pair ; Sets initial data (OOh) to A register

; Sets number of byte to BC register pair

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TMP87CM24A/P24A

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TMP87CM24A/P24A

1.5 General-purpose Register Banks

General-purpose registers are mapped into addresses 0040h to OOBFh in the data memory as shown in Figure 1-4. There are 16 register banks, and each bank contains 8-bit registers W, A, B, C, D, E, H, and L. Figure 1-5 shows the general-purpose register bank configuration.

w A

D E

H L

— bank 4 (0060to006?H)

—I banks (0058to005FH)

— bank 2 (0050to0057H)

cl (0048to004FH)

—' bank 15 (00B8 to OOBFh)

—I bank 14 (00B0to00B7H)

—' bank 13 (OOABtoOOAFH)

bank 12 (OOAO to 00A?h)

Example

(0041h) (0040h)

(0043h)

(0045h)

(0047h)

Bank 0

W A

(0042h)

D E

(0044h)

H L

(0046h)

bankO (0040to0047H)

(a) Configuration

Figure 1-5. General-purpose Register Banks

In addition to access in 8-bit units, the registers can also be accessed in 16-bit units as the register pairs WA, BC, DE, and HL. Besides its function as a general-purpose register, the register also has the following functions:

(b) Address assignments of registers

(1) A,WA

The A register functions as an 8-bit accumulator and WA the register pair functions as a 16-bit accumulator (W is high byte and A is low byte). Registers other than A can also be used as accumulators for 8-bit operations.

Examples: ® add a, B ; Adds B contents to a contents and stores the result into a.

® SUB WA, 1234H ; Subtracts 1234h from WA contents and stores the result into WA.

® SUB E, A ; Subtracts A contents from E contents, and stores the result into E.

(2) HL,DE

The HL and DE specify a memory address. The HL register pair functions as data pointer (HL) /index

register (HL + d) /base register (HL + C), and the DE register pair function as a data pointer (DE). The HL also has an auto-post- increment and auto-pre-decrement functions. This function simplifies

multiple digit data processing, software LIFO (last-in first-out) processing, etc.

Example 1 : ®

A, (HL)

LD A, (HL + 52H)

; Loads the memory contents at the address specified by HL into A. ; Loads the memory contents at the address specified by the value

obtained by adding 52h to HL contents into A.

(3)

A, (HL + C)

; Loads the memory contents at the address specified by the value

obtained by adding the register C contents to HL contents into A.

A, (HL + )

; Loads the memory contents at the address specified by HL into A.

Then increments HL.

A, (-HL)

; Decrements HL. Then loads the memory contents at the address

specified by new HL into A.

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The TLCS-870 Series can transfer data directly memory to memory, and operate directly between memory data and memory data. This facilitates the programming of block processing.

Example 2: Block transfer

(3) B, C, BC

Registers B and C can be used as 8-bit buffers or counters, and the BC register pair can be used as a

16-bit buffer or counter. addressing (refer to example 1 (3) above) and as a divisor register for the division instruction [DIV gg. C].

Example 1 : Repeat processing

LD B, m m = n - 1 (n : Number of bytes to transfer) LD HL, DSTA Sets destination address to HL LD DE, SRCA

SLOOP: LD

INC INC

DEC

JRS F, SLOOP

The C register functions as an offset register for register-offset index

SREPEAT: I processing :

DEC

JRS

Sets source address to DE (HL), (DE) HL<-DE HL HL<-HL+ 1 DE DE<-DE + 1 B B<-B- 1

if B S Othen loop

B, n

Sets n as the number of repetitions to B

(n + 1 times processing)

F, SREPEAT

TMP87CM24A/P24A

Example 2 : Unsigned integer division (16-bit-r 8-bit)

DIV WA, C

Divides the WA contents by the C contents, places the

quotient in A and the remainder in W.

The general-purpose register banks are selected by the 4-bit register bank selector (RBS). During reset, the RBS is initialized to "0". The bank selected by the RBS is called the current bank. Together with the flag, the RBS is assigned to address OOBFh in the SFR as the program status word (PSW). There are 3 instructions [LD RBS, n], [PUSH PSW], [POP PSW] to access the PSW. The PSW can be also operated by the memory access instruction.

Example 1 : Incrementing the RBS

INC (OOBFH)

Example 2 : Reading the RBS

LD A, (OOBFH)

Highly efficient programming and high-speed task switching are possible by using bank changeover to save registers during interrupt and to transfer parameters during subroutine processing. During interrupt, the PSW is automatically saved onto the stack. The bank used before the interrupt was accepted is restored automatically by executing an interrupt return instruction [RETI]/[RETN] ; therefore, there is no need for the RBS save/restore software processing. The TLCS-870 Series supports a maximum of 15 interrupt sources. One bank is assigned to the main program, and one bank can be assigned to each source. Also, to increase the efficiency of data memory usage, assign the same bank to interrupt sources which are not nested.

; RBS RBS + 1

; A <—RBS (AstoO ^ RBS, AytoA^FIags)

Example: Saving/restoring registers during interrupt task using bank changeover.

PINT1 : LD RBS, n ; RBS n (Bank changeover)

Interrupt processing

RETI ; Maskable interrupt return (Bank restoring)

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TMP87CM24A/P24A

1.6 Program Status Word (PSW)

The program status word (PSW) consists of a register bank selector (RBS) and four flags, and the PSW is assigned to address OOBFh in the SFR. The RBS can be read and written using the memory access instruction (e.g. [LD A, (003FH)], [LD (OOBFH), A], however the flags can only be read. When writing to the PSW, the change specified by the instruction is made without writing data to the flags. For example, when the instruction [LD (OOBFH), OSH] is executed, "5" is written to the RBS and the JF is set to "1", but the other flags are not affected. [PUSH PSW] and [POP PSW] are the PSW access instructions.

1.6.1 Register Bank Selector (RBS)

The register bank selector (RBS) is a 4-bit register used to select general-purpose register banks. For example, when RBS = 2, bank 2 is currently selected. During reset, the RBS

is initialized to "0". Figure 1-6. PSW (Flags, RBS) Configuration

1.6.2 Flags

The flags are configured with the upper 4 bits : a zero flag, a carry flag, a half carry flag and a jump status flag. The flags are set or cleared under conditions specified by the instruction. These flags except the half carry flag are used as jump condition "cc" for conditional jump instructions [JR cc, $ + 2 + d]/[JRS cc, $ + 2 + d]. After reset, the jump status flag is initialized to "1", other flags are not affected.

(1) Zero flag (ZF)

The ZF is set to "1" if the operation result or the transfer data is OOh (for 8-bit operations and data

transfers)/0000H (for 16-bit operations); otherwise the ZF is cleared to "0".

During the bit manipulation instructions [SET, CLR, and CPL], the ZF is set to "1" if the contents of the specified bit is "0"; otherwise the ZF is cleared to "0". This flag is set to "1" when the upper 8 bits of the product are OOh during the multiplication

instruction [MUL], and when OOh for the remainder during the division instruction [DIV]; otherwise it

is cleared to "0".

(2) Carry flag (CF)

The CF is set to "1" when a carry out of the MSB (most significant bit) of the result occurred during addition or when a borrow into the MSB of the result occurred during subtraction; otherwise the CF

is cleared to "0". During division, this flag is set to "1" when the divisor is OOh (divided by zero error), or when the quotient is IOOh or higher (overflow error); otherwise it is cleared. The CF is also affected during the shift/rotate instructions [SHLC, SHRC, ROLC, and RORC]. The data shifted out from a register is set to the CF. This flag isalsoa 1-bit register(a boolean accumulator) for the bit manipulation instructions. Set/clear/complement are possible with the CF manipulation instructions.

Examplel : Bit manipulation (The result of exclusive-OR between bit 5 content of address 0?h and

bit 0 content of address 9Ah is written to bit 2 of address 01 h )

LD CF, (0007H).5 ; (0001 h)2 {0007h)s V (009Ah)o XOR CF, (009AH). 0 LD (0001H).2, CF

(3) Half carry flag (HF)

The HF is set to "1" when a carry occurred between bits 3 and 4 of the operation result during an 8-

bit addition, or when a borrow occurred from bit 4 into bit 3 of the result during an 8-bit subtraction; otherwise the HF is cleared to "0". This flag is useful in the decimal adjustment for BCD operations (adjustments using the [DAA r], or [DAS r] instructions).

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Example: BCD operation

(The A becomes 4?H after executing the following program when A = 19h, B = 28h)

ADD A, B ; A<-41h, HF<-1,CF<-0 DAA A ; A 41H + 06h = 4?H (decimal-adjust)

TMP87CM24A/P24A

(4) Jump status flag (JF)

Zero or carry information is set to the JF after operation (e. g. INC, ADD, CMP, TEST). The JF provides the jump condition for conditional jump instructions [JRS T/F, $-F2-hd], [JR T/F, $ -F 2 -hd] (T or F is a condition code). Jump is performed if the JF is "1" for a true condition (T), or the JF is "0" for a false condition (F). The JF is set to "1" after executing the load/exchange/swap/nibble rotate/jump instruction, so that

[JRS T, $ -F 2 -F d] and [JR T, $ -f 2 -f d] can be regarded as an unconditional jump instruction.

Example : Jump status flag and conditional jump instruction

INC JRS

LD A,(HL) JRS

Example : The accumulator and flags become as shown below after executing the following instructions

when the WA register pair, the HL register pair, the data memory at address OOCSh, the carry flag

and the half carry flag contents being "219Ah", "OOCSh", "D7h", "1" and "0", respectively.

A T, SLABLE1

T, SLABLE2

; Jump when a carry is caused by the immediately

preceding operation instruction.

; JF is set to "1" by the immediately preceding

instruction, making it an unconditional jump instruction.

Instruction

ADDC A, (HL) SUBB CMP AND LD ADD A, 66H

A, (HL) A, (HL) A, (HL) A, (HL)

Acc. after

execution

72 1 C2 1 9A 92 D7 1

Flag after execution

JF ZF CF HF

1 1

0 0 0 0 0

1 1 1 1

1 1 1

Instruction

INC A 0 0 0 0

ROLC A 35

RORC A

ADD WA,0F508H 16A2 1

MUL W, A 13DA

SET A.5 BA 1 1 1

Acc. after execution

Flag after execution

JF ZF CF HF

0 0

0 0 0 0

0 0

1 1

1.7 Stack and Stack Pointer

1.7.1 Stack

The stack provides the area in which the return address or status, etc. are saved before a jump is performed to the processing routine during the execution of a subroutine call instruction or the acceptance of an interrupt. On a subroutine call instruction [CALL a]/[CALLP n]/[CALLV n], the contents of the PC (the return address) is saved; on an interrupt acceptance, the contents of the PC and the PSW are saved (the PSW is pushed first, followed by PCh and PCl). Therefore, a subroutine call occupies two bytes on the stack; an interrupt occupies three bytes. When returning from the processing routine, executing a subroutine return instruction [RET] restores the contents to the PC from the stack; executing an interrupt return instruction [RETI]/[RETN] restores the contents to the PC and the PSW (the PCl is popped first, followed by PCh and PSW). The stack can be located anywhere within the data memory space except the register bank area, therefore the stack depth is limited only by the free data memory size.

0 0

0 0 0

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TMP87CM24A/P24A

1.7.2 Stack Pointer (SP)

The stack pointer (SP) is a 16-bit register containing the address of the next free locations on the stack. The SP is post-decremented when a subroutine call or a push instruction is executed, or when an interrupt is accepted; and the SP is pre-incremented when a return or a pop instruction is executed. Figure 1-8 shows the stacking order.

The SP is not initialized hardware-wise but requires initialization by an initialize routine (sets the highest stack address). [LD SP, mn], [LD SP, gg] and [LD gg, SP] are the SP access instructions (mn; 16-bit immediate data, gg; register pair).

Example 1 :To initialize the SP

LD SP, 083FH

Example 2 : To read the SP

LD HL, SP

; SP<-083Fh

; HL<-SP

MSB LSB

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Stack Pointer (SP)

Figure 1-7. Stack Pointer

1.8 System Clock Controller

Figure 1-8. Stack

The system clock controller consists of a clock generator, a timing generator, and a stand-by controller.

Figure 1-9. System Clock Controller

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TMP87CM24A/P24A

1.8.1 Clock Generator

The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: one for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the system clock controller to low-power operation based on the low-frequency clock. The high-frequency (fc) and low-frequency (fs) clocks can be easily obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins, respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to the XIN/XTIN pin with the XOUT/XTOUT pin not connected. The TMP87CM24A/P24A are not provided an RC oscillation.

High-frequency clock

XIN

□

XOUT

□

XIN XOUT

□

(open)

(a) Crystal/Ceramic

resonator

A/oie; Accurate Adjustment of the Oscillation Frequency:

Although no hardware to externally and directly monitor the basic clock pulse is not provided,

the oscillation frequency can be adjusted by making the program to output fixed frequency pulses to the port while disabling all interrupts and monitoring this pulse. With a system requiring adjustment of the oscillation frequency, the adjusting program must be created beforehand.

(b) External oscillator

Figure 1-10. Examples of Resonator Connection

XTIN

□

Low-frequency clock

XTOUT

XTIN

□

(d) External oscillator

XTOUT

(open)

1.8.2 Timing Generator

The timing generator generates from the basic clock the various system clocks supplied to the CPU core and peripheral hardware. The timing generator provides the following functions :

□

Generation of divider output (DVO) pulses Generation of source clocks for time base timer Generation of source clocks for watchdog timer Generation of internal source clocks for timer/counters TCI -TC3, TC5 Generation of internal clocks for serial interfaces SI01 and SI02 Generation of warm-up clocks for releasing STOP mode

Generation of a clock for releasing reset output

Configuration of Timing Generator

(1)

The timing generator consists of a 21-stage divider with a divided-by-4 prescaler, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode and DV7CK (bit 4 in TBTCR) shown in Figure 1-11 as follows.

During reset and at releasing STOP mode, the divider is cleared to "0", however, the prescaler is not

cleared.

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TMP87CM24A/P24A

A divided-by-256 of high-frequency clock (fc/28) is input to the 7th stage of the divider. Do not set DVCKto "1" in the single-clock mode.

@ In the dual-clock mode

During NORMAL2 or IDLE2 mode (SYSCK = 0), an input clock to the 7th stage of the divider can be selected either "fc/28" or "fs" with DV7CK. During SLOW or SLEEP mode (SYSCK = 1), fs is automatically input to the 7th stage. To input clock to the 1st stage is stopped ; output from the 1st to 6th stages is also stopped.

MPX: Multiplexer

Figure 1-11. Configuration of Timing Generator

TBTCR

(0036h)

(DVOEN)

DV7CK

(DVOCK)

________1________

Selection of input clock to the 7th staqe of the divider

(TBTEN) (TBTCK)

DV7CK

_________1________1________

0 : fc/28 [Hz] 1 : fs

(Initial value: 0**0 0***)

Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], * : Don't care Note 2: Do not set DV7CK to "1" in the single-clock mode. Note 3: Do not set DV7CK to "1" before low-frequency clock is stable in the dual-clock mode.

Figure 1-12. Timing Generator Control Register

(2) Machine Cycle

Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution unit is called an "machine cycle". There are a total of 10 different types of instructions for the TLCS-870 Series: ranging from 1-cycle instructions which

require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (SO - S3), and each state consists of one main system clock.

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TMP87CM24A/P24A

1/fc or 1/fs [s]

Main System Clock

State

SO SI

-------

Machine cycle

-------------

S3 SO SI

0.5//S atfc=8MHz

122 //s at fs = 32.768 kHz

Figure 1-13. Machine Cycle

1.8.3 Stand-by Controller

The stand-by controller starts and stops the oscillation circuits for the high-frequency and low-frequency clocks, and switches the main system clock. There are two operating modes: single-clock and dual-clock. These modes are controlled by the system control registers (SYSCR1, SYSCR2). Figure 1-14 shows the operating mode transition diagram and Figure 1-15 shows the system control registers. Either the single-clock or the dual-clock mode can be selected by an option during reset. TMP87PP24 is only fixed on the single-clock after reset release. When using the dual-clock mode, turn on the oscillation circuits for low-frequency clocks at the beginning of program.

(1) Single-dock mode

Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. As main system clock is mode from high frequency clock, in the single-clock mode, the machine cycle time is4/fc [s] (0.5 jjs at fc = 8 MHz).

In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. In the case where the single-clock mode has been selected as an option, the TMP87CM24A/P24A are placed in this mode after reset.

® IDLE1 mode

In this mode, the internal oscillation circuit remains active, and the CPU and the watchdog timer are halted; however, on-chip peripherals remain active (operate using the highfrequency clock). IDLE1 mode is started by setting IDLE bit in the system control register 2 (SYSCR2), and IDLE1 mode is released to NORMAL1 mode by an interrupt request from onchip peripherals or external interrupt inputs. When IMF (interrupt master enable flag) is "1" (interrupt enable), the execution will resume upon acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. When IMF is "0" (interrupt disable), the execution will resume with the instruction which follows IDLE mode start instruction.

(3) STOP1 mode

In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with the lowest power consumption during this mode. The output status of all output ports can be set to either output hold or high-impedance under software control. STOP1 mode is started by setting STOP bit in the system control register 1 (SYSCR1), and STOP1 mode is released by an input (either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warming-up period is completed, the execution resumes with the next instruction which follows the STOP mode start instruction.

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(2) Dual-dock mode

Both high-frequency and low-frequency oscillation circuits are used in this mode. Pins P21 (XTIN) and P22 (XTOUT) cannot be used as input/output ports. The main system clock is obtained from the

high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock

in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] (0.5

IDLE2 modes, and 4/fs [s] (122 fxs at fs = 32.768 kHz) in SLOW and SLEEP modes. Note that the

TMP87PP24 is placed in the single-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on by executing [SET (SYSCR2).XTEN] instruction.

TMP87CM24A/P24A

fjs at fc = 8 MHz) in NORMAL2 and

In this mode, the CPU core operates using the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. In case that the dual clock mode has been selected by an option, the TMP87CM24A/P24A are placed in this mode after reset.

@ SLOW mode

This mode can be used to reduce power-consumption by turning off oscillation of the highfrequency clock. The CPU core and on-chip peripherals operate using the low-frequency clock. Switching back and forth between NORMAL2 and SLOW modes is performed by the system control register 2.

(3) IDLE2mode

In this mode, the internal oscillation circuits remain active. The CPU and the watchdog timer are halted; however, on-chip peripherals remain active (operate using the high-frequency clock and/or the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode, except that operation returns to NORMAL2 mode.

® SLEEP mode

In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (operate using the low-frequency clock). Starting and releasing of SLEEP mode is the same as for IDLE1 mode, except that operation returns to SLOW mode.

(D STOP2 mode

As in STOP1 mode, all system operations are halted in this mode.

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IDLE1

mode

r :

, Software

Interrupt

(a) Single-clock mode

RESETI

NORMALI

mode

Reset release

STOP Din inou t

Software

TMP87CM24A/P24A

STO PI

mode

Operating mode

RESETI

U 0

NORMALI

IDLE1

STORI

RESET2 NORMAL2

u 0

IDLE2

SLOW

SLEEP STOP2

IDLE2 mode

SLEEP

mode

Software

Interrupt

Software

Interrupt

(b) Dual-clock mode

Note 1: NORMAL1 and NORMAL2 m odes are generically called

Note 2: The TMP87PP24 doesn't have RESET2 mode.

High-frequency Low-frequency

NORMAL; STOP1 and STOP2 are called STOP; and IDLE1, IDLE2 and SLEEP are called IDLE.

Frequency

CPU core

Reset

Turning on

oscillation

Turning off

Operate

oscillation

Turning off

Halt

oscillation

Reset Reset

Turning on

oscillation

Turning on

oscillation

High-frequency

Halt

Low-frequency

Turning off

oscillation

Turning off

oscillation

Halt

On-chip

Peripherals

Reset

Operate

Halt

Operate

(High and/or Low)

Low-frequency

Halt

Machine cycle

time

4/fc [s]

—

4/fc [s]

4/fs [s]

—

Figure 1-14. Operating Mode Transition Diagram

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System Control Register 1

SYSCR1

(0038h)

STOP

RELM RETM OUTEN WUT

_______1______

TMP87CM24A/P24A

(Initial value: 0000 00**)

STOP

RELM

RETM

OUTEN

WUT

Note 1:

Note 2:

Note 3:

STOP mode start

Release method for STOP mode

Operating mode after STOP mode

Port output control during STOP mode

Warming-uptime at releasing STOP mode

Always set RETM to "0" when transiting from NORMAL1 mode to STOP1 mode and from NOMAL2 mode to STOP2 mode. Always set RETM to "1" when transiting from SLOW mode to STOP2 mode.

When STOP mode is released with RESET pin input, a return is made to NORMAL mode regardless

of the RETM contents.

fc: High-frequencyclocklHz] fs: Low-frequency clock [Hz]

*; Don't care

Note 4: Note 5:

Bits 1 and 0 in SYSCR1 are read in as undefined data when a read instruction is executed.

When the STOP mode is started by specifying OUTEN = "0", the internal input of port is fixed to

"0" and the interrupt of the falling edge may be set.

System Control Register 2

SYSCR2

(0039h) SYSCK IDLE

5 4

0 : CPU core and peripherals remain active 1 : CPU core and peripherals are halted

(start STOP mode)

Edge-sensitive release Level-sensitive release

Return to NORMAL mode Return to SLOW mode

High-impedance Remain unchanged

3 X 2’7fc or 3 X 2’Vfs

2’7fc or 2’Vfs

Reserved

[s]

(Initial value: 10/100 **** )

R/W

XEN

XTEN

SYSCK

IDLE

Note 1 Note 2 Note3 Note 4 Note 5

Note 6:

High-frequency oscillator control

Low-frequency oscillator control

Main system clock select (write)/main system clock monitor (read)

IDLE mode start

A reset is applied (RESET pin output goes low) if both XEN and XTEN are cleared to "0". Do not clear XEN to "0" when SYSCK = 0, and do not clear XTEN to "0" when SYSCK = 1.

WDT: watchdog timer, * : Don't care

Bits 3to0 in SYSCR2 are always read in as "1" when a read instruction is executed. An optional initial value can be selected for XTEN. Always specify when ordering ES (engineering sample).

0 : Turn off oscillation 1 : Turn on oscillation

0 : High-frequency clock 1 : Low-frequency clock

0 : CPU and watchdog timer remain active 1 : CPU and watchdog timer are stopped (start IDLE mode)

XTEN operating mode after reset

Single-clock mode (NORMAL1)

Dual-clock mode (NORMAL2)

The instruction for specifying Masking Option (Operating Mode) in ES Order Sheet is described in

ADDITIONAL INFORMATION "Notice for Masking Option of TLCS-870 series" section 8.

Figure 1-15. System Control Registers

R/W

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1.8.4 Operating Mode Control

(1) STOP mode (STORI, STOP2)

STOP mode is controlled by the system control register 1 (SYSCR1) and the STOP pin input. The STOP

pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is started

by setting STOP (bit 7 in SYSCR1) to "1". During STOP mode, the following status is maintained.

status in effect before STOP mode was entered. The port output can be select either output hold or high-impedance by setting OUTEN ( bit 4 in SYSCR1).

(3) The divider of the timing generator is cleared to "0".

@ The program counter holds the address of the instruction following the instruction which

started the STOP mode.

STOP mode includes a level-sensitive release mode and an edge-sensitive release mode, either of which can be selected with RELM (bit 6 in SYSCR1).

a. Level-sensitive release mode (RELM = 1)

In this mode, STOP mode is released by setting the STOP pin high. This mode is used for capacitor back-up when the main power supply is cut off and long term battery back-up. When the STOP pin input is high, executing an instruction which starts the STOP mode will not place in STOP mode but instead will immediately start the release sequence (warm-up). Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low. The following method can be used for confirmation:

• Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input).

TMP87CM24A/P24A

Example : Starting STOP mode with an INT5 interrupt.

TEST (P2). 0 JRS F, SINTS port P20 is at high LD (SYSCR1),01000000B SET (SYSCRD.7 LDW (IL), 1110011101010111B RETI

______

Confirm by program that the STOP pin input is low and start STOP mode.

STOP pin

XOUTpin

Note 1: Note 2:

PINTS :

SINT5 :

NORMAL

operation

After warm-up start, even /f STOP pin input is low again, STOP mode does not restart.

When changing to the level-sensitive release mode from the edge-sensitive release mode, the release mode is not switched until a rising edge of the STOP pin input is detected.

; To reject noise, the STOP mode does not start if

; Sets up the level-sensitive release mode. ; Starts STOP mode ; IL12, 11,7, S,3<-0

STOP

____________

operation

STOP mode is released by the hardware.

Figure 1-16. Level-sensitive Release Mode

Warm-up

/ Always released if the STOP \

V pin input is high.

NORMAL operation

__________

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b. Edge-sensitive release mode (RELM = 0)

Example : Starting STOP mode operation in the edge-sensitive release mode

TMP87CM24A/P24A

In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high.

LD (SYSCR1), 10000000B ; DI SET

(SYSCRI).STOP ; STOP <r-1 (activates stop mode)

LDW (IL),1110011101010111B ; IL12,11,7, 5,3<-0

OUTEN 0 (specifies high-impedance) IMF <-0 (disables interrupt service)

(clears interrupt latches)

; IMF<-1 (enables interrupt service)

STOP mode is released by the following sequence:

turned on ; when returning to SLOW mode, only the low-frequency clock oscillator is turned

on. When returning to NORMAL 1, only the high-frequency clock oscillator is turned on.

@ A warming-up period is inserted to allow oscillation time to stabilize. During warm-up, all

internal operations remain halted. Two different warming-up times can be selected with WUT (bits 2 and 3 in SYSCR1) as determined by the resonator characteristics.

(3) When the warming-up time has elapsed, normal operation resumes with the instruction

following the STOP mode start instruction (e.g. [SET (SYSCR1). 7]). The start is made after the divider of the timing generator is cleared to "

Table 1-1. Warming-up Time example

Return to NORMALI mode Return to SLOW mode

WUT At fc = 4.194304 MHz At fc = 8MHz WUT At fs = 32.768 kHz

3 X 2’7fc [s]

2’7fc

Note: The warming-up time is obtained by dividing the basic clock by the divider: therefore,

the warming-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warming-up time must be considered an approximate value.

STOP mode can also be released by setting the RESET pin low, which immediately performs the normal reset operation. In this case, even if the setting is to return to the SLOW mode, it starts from the NORMAL mode. (If the initial XTEN of TMP87CM24A/P24A are set to "1" by mask option, they start from the NORMAL2 mode. In case of TMP87PP24, starts from NORMAL1 mode.

375 [ms] 125

0".

196.6 [ms]

65.5

3 X 2’7fs [s]

2’7fs

750 [ms] 250

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H o

(/)

Oscillator circuit

Main system clock

Program counter

Instruction execution

Port output

Divider

STOP pin input

Oscillator circuit Turn off

Main system clock

Program counter

Instruction execution

Port output-

Divider

TjnjnjnjnjnjijnjijxnjijnjTJTjnjnjnjnjnjiJij^^

Z)C

-------

.Hiqh-Z

Turn on

ttI f

__________

i*“

Warming up

Turn on

a +2

(a) STOP Mode Start (Example : Start with SET (SYSCR1). 7 instruction located at address a)

n + 1

SET (SYSCR1). 7

n + 2

a + 3

n + 3

iJHJHJijnjijnjnjnjnjnjnjijnjnjnjx

a + 3

.. Count up

X X

(b) STOP Mode Release

a + 4

Instruction at addressa+ 2 X Instruction at address a+ 3 Xlrstruction at address a+ 4

n + 4

a + 5

Turn off

Halt

^ Hi gh-Z(whenOUTEN = 0)

a + 6

)€

DD >

■O

vl n

N> O

Figure 1-18. STOP Mode Start/Release

> N> >

TOSHIBA

Note: When STOP mode is released with alow hold voltage, the following cautions must be observed.

The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be high, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower rate than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting highlevel input voltage (hysteresis input).

(2) IDLE mode (IDLE1,IDLE2, SLEEP)

IDLE mode is controlled by the system control register

2 and maskable interrupts. The following status is

maintained during IDLE mode.

halted. On-chip peripherals continue to

operate.

@ The data memory, CPU registers and port

output latches are all held in the status in effect before IDLE mode was entered.

TMP87CM24A/P24A

(3) The program counter holds the address of

the instruction following the instruction which started IDLE mode.

Example : Starting IDLE mode.

SET (SYSCR2). 4

IDLE mode includes a normal release mode and an

interrupt release mode. Selection is made with the

interrupt master enable flag (IMF). Releasing the IDLE

mode returns from IDLE1 to NORMAL1, from IDLE2 to

NORMAL2, and from SLEEP to SLOW mode.

a. Normal release mode (IMF = "0")

IDLE mode is released by any interrupt source

enabled by the individual interrupt enable flag

(EF) or an external interrupt 0 (INTO pin) request. Execution resumes with the instruction following

the IDLE mode start instruction (e.g. [SET

(SYSCR2).4]).

The interrupt latch (IL) of the interrupt source for releasing the IDLE mode must be cleared to

"0" by load instruction.

b. Interrupt release mode (IMF = "1")

IDLE mode is released and interrupt processing is started by any interrupt source enabled with the individual interrupt enable flag (EF) or an external interrupt 0 (INTO pin) request. After the interrupt is processed, the execution resumes from the instruction following the instruction which started IDLE mode.

IDLE mode can also be released by setting the RESET pin low, which immediately performs the reset operation. After reset, the TMP87CM24A/P24A are placed in NORMAL2 mode (the TMP87PP24 is

placed in NORMAL1 mode).

IDLE<-1

Figure 1-19. IDLE Mode

Note: When a watchdog timer interrupt is generated immediately before the IDLE mode is

started, the watchdog timer interrupt will be processed but IDLE mode will not be started.

3-24-25 2002-10-03

N> O»

Main system clock

Interrupt request

Program counter

Instruction execution

Watchdog timer

Main system clock

Interrupt request

Program counter

Instruction execution ■

Watchdog timer

1 1 ! 1 1

1 1 II !

1 II 1 1 II 1

------------

Halt

a + 3

® Normal Release Mode

a + 2

SET (SYSCR2).4

Operate

(a) IDLE Mode Start (Example; starting with the SET instruction located at address a)

Operate

a +4

Instruction at address a + 2

■C

xzz

a + 3

-----

iislt

-----------

H o

(/)

DD >

1 1

N> O

Watchdog timer

Halt

(D Interrupt Release Mode (b) IDLE Mode Release

Figure 1-20. IDLE Mode Start/Release

Operate

■O

vl n

TOSHIBA

(3) SLOW mode

SLOW mode is controlled by the system control register 2 (SYSCR2) and the timer/counter 2 (TC2).

a. Switching from NORMAL2 mode to SLOW mode

Examplel : Switching from NORMAL2 mode to SLOW mode.

Example2 : Switching to SLOW mode after low-frequency clock oscillation has stabilized.

TMP87CM24A/P24A

First, set SYSCK (bit 5 in SYSCR2) to switch the main system clock to the low-frequency clock. Next, clear XEN (bit 7 in SYSCR2) to turn off high-frequency oscillation. When the low-frequency clock oscillation is unstable, wait until oscillation stabilizes before performing the above operations. The timer/counter 2 (TC2) can conveniently be used to confirm that low-frequency clock oscillation has stabilized.

Note: The high frequency clock can be continued oscillation in order to return to NORMAL2

mode from SLOW mode quickly. Always turn off oscillation of high frequency clock

when switching from SLOW mode to STOP mode.

SET (SYSCR2).5 ; SYSCK<-1

CLR (SYSCR2). 7

LDW (TREG2), 8000H

SET (EIRH). EF14 ; Enable INTTC2

(TC2CR), 14H ; Sets TC2 mode

(TC2CR), 34H

XEN<-0

(timer mode, source clock : fs)

; Sets warming-uptime

(according toXtal characteristics)

; Starts TC2

(Switches the main system clock to the low-frequency clock) (turns off high-frequency oscillation)

PINTTC2 : LD

SET (SYSCR2). 5 ; SYSCK<-1 CLR RETI

VINTTC2: DW PINTTC2

(TC2CR), 10H

(SYSCR2). 7

; Stops TC2

; XEN<-0

; INTTC2 vector table

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b. Switching from SLOW mode to NORMAL2 mode

Example : Switching from SLOW mode to NORMAL2 mode (fc = 8 MHz, warming-up time is about

TMP87CM24A/P24A

First, set XEN (bit 7 in SYSCR2) to turn on the high-frequency oscillation. When time for stabilization (warm-up) has been taken by the timer/counter 2 (TC2), clear SYSCK (bit 5 in SYSCR2) to switch the main system clock to the high-frequency clock. SLOW mode can also be released by setting the RESET pin low, which immediately performs the reset operation. After reset, the TMP87CM24A/P24A are placed in NORMAL mode.

7.9 ms).

SET (SYSCR2). 7 ; XEN<-1 (turns on high-frequency oscillation)

LD (TREG2+ 1), 0F8H

SET (EIRH). EF14 ; Enable INTTC2

(TC2CR), 10H ; Sets TC2 mode

(timer mode, source clock: fc)

; Sets the warming-up time

(according to frequency and resonator characteristics)

(TC2CR), ЗОН

; Starts TC2

PINTTC2 : LD

CLR

RETI

VINTTC2: DW PINTTC2

Note 1: After the SYSCK is cleared to "0", the CPU core operate using low frequency clock

when the main system clock is switching from low frequency clock to high frequency

clock.

Note 2: SLOW mode can also be released by setting the RESET pin low, which immediately

performs the reset operation. After reset, the TMP87CM24A/P24A are placed in NORMAL2 mode. (The TMP87PP24A is placed in NORMAL1 mode)

(TC2CR), ЮН (SYSCR2). 5

; Stops TC2 ; SYSCK<-0 (Switches the main system clock to the

high-frequency cicok)

; INTTC2 vector table

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H o

(/)

o o

mode

(a) Switching to the SLOW Mode

Figure 1-21. Switching between the NORMAL2 and SLOW Modes

■o

vl n

N) > N>

TOSHIBA

TMP87CM24A/P24A

1.9 Interrupt Controller

The TMP87CM24A/P24A each have a total of 14 interrupt sources: 5 externals and 9 internals. Nested interrupt control with priorities is also possible. Two of the internal sources are pseudo non-maskable interrupts; the remainder are all maskable interrupts. Interrupt latches (IL) that hold the interrupt requests are provided for interrupt sources. Each interrupt vector is independent. The interrupt latch is set to "1" when an interrupt request is generated and requests the CPU to accept the interrupt. The acceptance of maskable interrupts can be selectively enabled and disabled by the program using the interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). When two or more interrupts are generated simultaneously, the interrupt is accepted in the highest priority order as determined by the hardware. Figure 1-22 shows the interrupt controller.

Table 1-2. Interrupt Sources

Interrupt Source

Internal/

External

Internal Internal

(Reset) Non-Maskable INTSW INTWDT

(Software interrupt) Pseudo (Watchdog Timer interrupt) non-maskable

External INTO (External interrupt 0)

Internal INTTC1 (16-bitTCI interrupt)

External

Internal

External

INTI (External interrupt 2) IMF- EFs= 1 INTTBT

(Time Base Timer interrupt)

INT2 (External interrupt 2) IMF- EFy= 1 Internal INTTC3 (8-bit TC3 interrupt) Internal INTSI01 (Serial Interface 1 interrupt) Internal INTTC5 (8-bit TC5 interrupt)

External INT3 (External interrupts)

Reserved Internal Internal

INTSI02

(Serial Interface 2 interrupt)

INTTC2 (16-bit TC2 interrupt) IMF- EFi4= 1 ILi4

External INT5 (External interrupt 5)

Enable Condition

Interrupt

Latch

IMF= 1, INT0EN = 1 IMF- EF4= 1 IL

IMF- EFe= 1

IMF- EFs= 1 IMF- EFg= 1 IL

IMF- EFio= 1 IMF- EF11 = 1 IL

IMF- EFi2= 1

IMF- EFi3= 1

IMF- EFi5= 1

IL IL

ILi5 FFEOh

—

IL IL

IL iLe

ILs

10 11

12 13

2 3

4 5

Vector Table

Address

FFFEh FFFCh FFFAh

FFF

FFF4h

FFF2h FFFOh FFEEh

FFECh

FFEAh

FFE

FFE4h FFE2h

Priority

High 0

1 2

3 4 5

10 11 12

13 14

Low 15

(1) Interrupt Latches (IL 15to2)

Interrupt latches are provided for each source, except for a software interrupt. The latch is set to "1" when an interrupt request is generated, and requests the CPU to accept the interrupt. The latch is cleared to "0" just after the interrupt is accepted. All interrupt latches are initialized to "0" during

reset. The interrupt latches are assigned to addresses OOBCh and OOBDh in the SFR. Each latch can be cleared to "0" individually by an instruction; however, the read-mod ify-write instruction such as bit manipulation or operation instructions cannot be used (Do not clear the IL2 for a watchdog timer

interrupt to "0"). Thus, interrupt requests can be cancelled and initialized by the program. Note that interrupt latches cannot be set to "1" by any instruction. The contents of interrupt latches can be read out by an instruction. Therefore, testing interrupt

requests by software is possible.

Example 1 : Clears interrupt latches

Dl LDW El

(IL), 1110100000111111B

IMF<-0

ILi2# ILiotolL5<—0

IMF<-1

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TMP87CM24A/P24A

L-

_QJ "o

L-

■ *->

+->

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Example 2 : Reads interrupt latches

Examples: Tests an interrupt latch

(2) Interrupt Enable Register (EIR)

The interrupt enable registers (EIR) enable and disable the acceptance of interrupts except for the

pseudo non-maskable interrupts (software and watchdog timer interrupts). Pseudo non-maskable

interrupts are accepted regardless of the contents of the EIR; however, the pseudo non-maskable

interrupts cannot be nested more than once at the same time. The EIR consists of an interrupt master enable flag (IMF) and individual interrupt enable flags (EF). These registers are assigned to addresses 003Ah and 003Bh in the SFR, and can be read and written

by an instruction (including read-modify-write instructions such as bit manipulation instructions).

The interrupt master enable flag (IMF) enables and disables the acceptance of all interrupts, except for pseudo non-maskable interrupts. Clearing this flag to "0" disables the acceptance of all maskable interrupts. Setting to "1" enables the acceptance of interrupts. When an interrupt is accepted, this flag is cleared to "0" to temporarily disable the acceptance of maskable interrupts. After execution of the interrupt service program, this flag is set to "1" by the maskable interrupt return instruction [RETI] to again enable the acceptance of interrupts. If an interrupt request has already been occurred, interrupt service starts immediately after execution of the [RETI] instruction. Pseudo non-maskable interrupts are returned by the [RETN] instruction. In this case, the IMF is set to "1" only when pseudo non-maskable interrupt service is started with interrupt acceptance enabled (IMF = 1). Note that IMF remains "0" when cleared in the interrupt service program. The IMF is assigned to bit 0 at address 003Ah in the SFR, and can be read and written by an instruction. IMF is normally set and cleared by the [El] and [Dl] instructions, and the IMF is initialized to "0" during reset.

@ Individual interrupt Enable Flags (EFisto EF4)

These flags enable and disable the acceptance of individual maskable interrupts, except for an external interrupt 0. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of an interrupt, setting the bit to "0" disables acceptance.

Example 1 : Sets EF for individual interrupt enable, and sets IMF to "1".

Example 2 : Sets an individual interrupt enable flag to

LD WA, (IL)

TEST (IL).7 JR F,SSET

Dl LDW El

Dl SET (EIRH).4 El

(EIR), 1110100010100000B

; W<-ILh, A<-IL|_

; ifIl7= 1 thenjump

IMF<-0

EFisto EF13, EF11,

IMF<-1

IMF<-0

EFi2^1

IMF<-1

TMP87CM24A/P24A

EF7, EFc

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TMP87CM24A/P24A

(003C, 003Dh)

EIR

(003A, 003Bh)

ILi5

ILi4

; IL12 i IL

12 11

IL9

ILs

; IL5 ; IL4 ; IL3 ; IL2

iLe

ILh (003Dh)

(Initial Value : 00000000 000000**)

1EF N

____

EFi4

: EF12 : EFii

EF10EFg

EIRh (003Bh) EIRl (003Ah)

EF? 1

____

^ _________________________________/

; EFs ; EF4 1 1 IMF 1

EFe

(Initial Value : 00000000 0000***0)

Note 1: Do not use any read-modify-write instruction such as bit manipulation for clearing IL Note 2: Do not clear IL2 to "0 " by an instruction. Note 3: Do not set IMF to "1" during non-maskable interrupt service program. Note 4: When manipulating IL or EF, clear IMF (to disable interrupts ) beforehand. Note 5: Do not set IMF to "1" simultaneously with EF15 to EF4.

Figure 1-23. Interrupt Latch (IL) and Interrupt Enable Register (EIR)

5 4 3 2 1 0

ILl(003Ch)

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TMP87CM24A/P24A

1.9.1 Interrupt Sequence

An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 machine cycles (4 jus at fc = 8 MHz in NORMAL mode) after the completion of the current instruction execution. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for pseudo non-maskable interrupts).

(1) Interrupt acceptance processing

acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled.

@ The interrupt latch (IL) for the interrupt source accepted is cleared to "0".

(3) The contents of the program counter (PC) and the program status word are saved (pushed)

onto the stack. (Pushed down in order of PSW, PCh, PCl). The contents of stack pointer (SP) is decreased by 3.

@ The entry address of the interrupt service program is read from the vector table address

corresponding to the interrupt source, and the entry address is loaded to the program counter.

d) The instruction stored at the entry address of the interrupt service program is executed.

1-machine cycle

Interrupt I n signal I /1 I

Interrupt latch !

Instruction

execution

"Z)C

DOGXHOC

Interrupt service task

I I I I I I I I I I I I I I I I I I I I I

Ir-

Note 2

Interrupt acceptance

Instruction \X\

A execution Ajj A

b+lXb + 2Xb + 3,

RETI instruction execution

)OOC )OEK

Note 1: a: return address, b: entry address, c: address when the RETI instruction is stored Note 2: The maximum response time from when an IL is set until an interrupt acceptance processing starts is

Figure 1-24. Timing Chart of Interrupt Acceptance and Interrupt Return Instruction

Example : Correspondence between vector table address for INTTBT and the entry address of the

interrupt service program.

Vector table address Entry address

38/fc to 38/fs[s]. It equals to setting the IL on the first machine cycle in 10 cycles instruction execution.

yzz

FFF2h FFF3h

A maskable interrupt is not accepted until the IMF is set to "1" even if a maskable interrupt of higher priority than that of the current interrupt being serviced. When nested interrupt service is necessary, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags.

03l

D2,

D203h D204h

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06h

2002-10-03

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However, an acceptance of external interrupt 0 cannot be disabled by the EF; therefore, if disablement is necessary, either the external interrupt function must be disabled with INTOEN in the external interrupt control register (INTOEN) or interrupt processing must be avoided by the program. (When INTOEN = 0, the interrupt latch IL3 isnotset, therefore, the falling edge of the INTO pin input cannot be detected.)

Example 1 : Disables an external interrupt 0 using INTOEN:

TMP87CM24A/P24A

LD (EINTCR), OOOOOOOOB ; INT0EN<-0

Example 2 : Disables the processing of external interrupt 0 under the software control (using bit 0

at address OOFOh as the interrupt processing disable switch):

PINTO: TEST (OOFOH). 0

Returns without interrupt processing if(OOFOH)o= 1 JRS T, SINTO RETI

SINTO: : Interrupt processing :

RETI

VINTO :

(2) General-Purpose register save/restore processing

During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but not the accumulator and other registers. These registers are saved by the program if necessary. Also, when nesting multiple interrupt services, it is necessary to avoid using the same data memory area for saving registers. The following method is used to save/restore the general-purpose registers:

General-purpose registers can be saved at high-speed by switching to a register bank that is not in use. Normally, bank 0 is used for the main task and banks 1 to 15 are assigned to interrupt service tasks. To increase the efficiency of data memory utilization, the same bank is assigned for interrupt sources which are not nested. The switched bank is automatically restored by executing an interrupt return instruction [RETI] or [RETN]. Therefore, it is not necessary for a program to save the RBS.

Example: Register Bank Changeover

PINTxx : LD RBS, n

PINTO

; Switches to bank n (1//S at 8M Hz)

interrupt processing

RETI

; Restores bank and Returns

Figure 1-25. Saving/Restoring General-purpose Registers

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TMP87CM24A/P24A

General-purpose register save/restore using push and pop instructions: To save only a specific register, and when the same interrupt source occurs more than once, the general-purpose registers can be saved/restored using push/pop instructions.

Example

PINTxx

PCl

PC.

PSW

At acceptance of an interrupt

General-purpose registers save/restore using data transfer instruction: Data transfer instructions can be used to save only a specific general-purpose register during processing of a single interrupt.

Example : Saving/restoring a register using data transfer instructions

PINTxx: LD (GSAVA), A ; Save A register

PUSH WA PUSH HL ; interrupt processing POP HL POP WA RETI

RETI Return

H A

PCl'

PSW

At execution of a push instruction

interrupt processing ;

A, (GSAVA) ; Restore A registerLD

At execution

of a pop instruction

Save WA register pair Save HL register pair

Restore HL register pair Restore WA register pair Return

PCl

PC.

PSW

Address (example)

0238h

0239 023A 023B 023C 023D 023E 023F

At execution of an

interrupt return instruction

The interrupt return instructions [RETI]/[RETN] perform the following operations.

[RETI] Maskable interrupt return

® The contents of the program counter and the

program status word are restored from the stack.

® The stack pointer is incremented 3 times.

® The interrupt master enable flag is set to "1

Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed.

Note: When the interrupt processing time is longer than the interrupt request generation

time, the interrupt service task is performed but not the main task.

3-24-36

[RETN] Non-maskable interrupt return

® The contents of the program counter and

program status word are restored from the stack.

® The stack pointer is incremented 3 times.

® The interrupt master enable flag is set to "1"

only when a non-maskable interrupt is accepted in interrupt enable status. However, the interrupt master enable flag remains at "0" when so clear by an interrupt service program.

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TMP87CM24A/P24A

1.9.2 Software Interrupt (INTSW)

Executing the [SWI] instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). However, if processing of a non-maskable interrupt is already underway, executing the SWI instruction will not generate a software interrupt but will result in the same operation as the [NOP] instruction. Thus, the [SWI] instruction behaves like the [NOP] instruction.

Note: Software interrupt generates during non-maskable interrupt processing to use SWI instruction

for software break in a development tool.

Use the [SWI] instruction only for detection of the address error or for debugging.

Address Error Detection

FFh is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address. Code FFh is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFh to unused areas of the program memory. Address trap reset is generated for instruction fetch from a part of RAM area (address 0040h to 083Fh) or SFR area (OOOOh to 003Fh).

Note: The fetch data from addresses 3F80h to 3FFFh (test ROM area) for

TMP87CM24A/P24A is not "FFh".

® Debugging

Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address.

1.9.3 External Interrupts

The TMP87CM24A/P24A have five external interrupts (INTO to INT5 : INTO, INTI, INT2, INT3, INT5). Three of these (INTI, INT2, INT3) have digital noise cancellation circuits (pulse inputs of less than a fixed time are cancelled as noise). Edge selection is possible with pins INTI, INT2,and INT3. The INT0/P10 pin can be selected either as an external interrupt input pin or as an I/O port. At reset, it is initialized as an input port. Edge selection, noise cancellation control, and INT0/P10 pin function selection are performed by the external interrupt control register 1 (EINTCR). The both-edge detect function of the INT3 pin is selected by the external interrupt control register 1 (EINTCR) and the external interrupt control register 2 (EINT3CR). Table 1-3 lists enable conditions, edge select, noise cancellation conditions. The following are notes on the usage of external interrupts:

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Notes on usage of external interrupts:

Note 1: When INTO to INT5 flNTO, INTI, INT2, INT3, INT5J are used in SLOW or SLEEP mode, the noise

cancellation function is disabled. Noise cancellation time for a pulse input during operating mode transition is indeterminate.

Note 2: Input pulse width for INTO and I NTS must be one machine cycle or more at both high and low

levels.

TMP87CM24A/P24A

INTO, INT5 input pulse

tiNTL tiNTH

tiNTL, tiNTH > tcyc

tcyc = 4/fc [s] (at NORMAL 1/2 and IDLE 1/2 modes)

4/fs [s] (at SLOW and SLEEP modes)

Note 3: If a signal without noise is input to the external interrupt pin in NORMAL 1/2 or IDLE 1/2 mode,

the maximum times from input signal edge to input latch set are as described below:

193/fc [s] (when INTINC = 0)

(2) INT2 pin 25/fc [s] 2 INT3 pin 25/fc [s] (when #00371-1: INT3W = 0, falling or rising edge)

25/fc [s] (when #0037H: INT3W= 1 and #001FH: NCS (0, 0, 0) ) (26/fc) x8.5 + 19/fc [s] (when #0037H: INT3W= 1 and #001 FH: NCS (0, 0, 1) ) (27/fc) x8.5 + 19/fc Is] (when #0037H: INT3W= 1 and #001 FH: NCS (0, 1, 0) ) (28/fc) x8.5 + 19/fc [s] (when #0037H: INT3W= 1 and #001 FH: NCS (0, 1, 1) ) (29/fc) x8.5 + 19/fc Is] (when #0037H: INT3W= 1 and #001 FH: NCS (1, 0, 0) )

(210/fc) x8.5 + 19/fc [s] (when #0037H: INT3W= 1 and #001 FH: NCS (1, 0, 1) )

(211/fc) x8.5 + 19/fc [s] (when #0037H: INT3W= 1 and #001 FH: NCS (1, 1, 0) ) (212/fc) x8.5 + 19/fc Is] (when #0037H: INT3W= 1 and #001 FH: NCS (1, 1, 1) )

Note 4: Noise cancellation/pulse receive conditions for timer/counter are as described below:

® TCI pin : Less than 7/fc [s] (noise cancellation) and 24/fc [s] or more (pulse receive) 2 TC3 pin : When INT3W=0, less than 7/fc [s] (noise cancellation) and 24/fc [s] or more

(pulse receive). For when INT3W = 1, see Table 1-3 (b).

Note 5: When INTOEN = 0, interrupt latch IL3 is not set even if a falling edge is detected for INTO pin

input.

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Note 6: Change EINTCR only when IMF = 0. After changing EINTCR, interrupt latches of external

interrupt inputs must be cleared to "0" using load instruction.

Example : Changes INT2 edge selection from rising edge to falling edge

Dl ; IMF <-0 (disables interrupt service) LD (EINTCR), 10000110B ; INT2ES ^ 1 (changes edge selection) LD (ILL),01111111B ; IL7 ^ 0 (dears interrupt latch) El ; IMF <-1 (enables interrupt service)

Note?: if changing the contents of INT1ES during NORMAL1/2 mode, interrupt latch of external

interrupt input INTI must be cleared after 14 machine cycles (when INT1NC =1) or 50 machine cycles (when INT1NC = 0) from the time of changing. During SLOW mode, 3 machine cycles are required.

Note 8: In order to change of external interrupt input by rewriting the contents of INT2ES and INT3ES

during NORMAL1/2 mode, clear interrupt latches of external interrupt inputs (INT2 and INT3) after 8 machine cycles from the time of rewriting. During SLOW mode, 3 machine cycles are required.

Note 9: In order to change an edge of timer counter input by rewriting the contents of INT2ES and

INT3ES during NORMAL 1/2 mode, rewrite the contents after timer counter is stopped (TC*s = 0),

that is, interrupt disable state. Then, clear interrupt laches of external interrupt inputs (INT2

and INT3) after 8 machine cycles from the time of rewriting to change to interrupt enable state. Finally, start timer counter. During SLOW mode, 3 machine cycles are required.

Example : When changing TCI pin inputs edge in external trigger timer mode from rising edge to

falling edge.

TMP87CM24A/P24A

LD(TC1CR),01001000B Dl LD (EINTCR),00000100B

8-machine

cycles

Note 10: When high-impedance is specified for port output in stop mode, port input is forcibly fixed

to low level internally. Thus, interrupt latches of external interrupt inputs except I NTS

(P20/STOP) which are also used as ports may be set to "1". To specify high-impedance for port output in stop mode, first disable interrupt service (IMF = 0), activate stop mode. After releasing stop mode, clear interrupt latches using load instruction, then, enable interrupt service.

Example : Activating stop mode

LD (SYSCR1),01000000B Dl SET

(SYSCRI).STOP

LDW

(IL), 1111011101010111B

NOP

to NOP LD (ILL),01111111B El LD(TC1CR),01111000B

OUTEN <- 0 (specifies high-impedance)

IMF <- 0 (disables interrupt service)

STOP <- 1 (activates stop mode)

IL11,7, 5, 3 <-0 (clears interrupt latches) IMF <- 1 (enables interrupt service)

TCI00 (stop TCI)

IMF 0 (disable interrupt service) INT2ES <- 1 (change edge selection)

IL7 <-0 (clear interrupt latch) IMF 1 (enable interrupt service)

TCIS^II (startTCI)

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TMP87CM24A/P24A

Table 1-3. (a) External Interrupts

SOURCE Pin

Secondary

function

INTO TÑÍÜ P10

INTI INTI P11 IMF- EF5= 1

INT2 INT2

P12/TC1

INT3 INT3 P40/TC3

INT5 TÑÍ5 P20/STOP

Note 1: Pulses less than 15/fc [s] or 63/fc [s] are cancelled as noise. Pulses equal to or more than 48/fc [s] or 192/fc [s] are

Note 2: Pulses less than 7/fc [s] are cancelled as noise. Pulses equal to or more than 24/fc [s] are regarded as signals. Note 3: For falling or rising edge, pulses less than 7/fc [s] are cancelled as noise. Pulses equal to or more than 24/fc [s] are

Note 4: Noise cancellation conditions are as listed in Table 1-3 (b). They are applied to the INT3 pin when it is used for

Note 5: To detect the edge at which an interrupt is generated, read bit 7 (INTEDT) in EINT3CR (#001 Fh), that is, at the

regarded as signals.

regarded as signals. Same applies to pin TC3 (at one edge).

both-edge interrupts. To detect remote control signals using timer 3 in capture mode, the INT3 pin is used for both-edge interrupts.

beginning of the interrupt processing routine. INTEDT is valid only for both-edge interrupts (INT3W =1). INTEDT is set to 1 by an interrupt as the non-selected edge; cleared to 0 after read automatically. For both-edge interrupts, rising or falling edge is selected by setting/modifying bit 3 (INT3ES) in EINTCR (#0037h).

When rising edge is selected (INT3ES = 0), bit 7 in INTEDT (^01 Fh ) is set to 1 when a falling edge is detected at the

INT3 pin. (That is, remains 0 if rising edge is detected.)

When falling edge is selected (INT3ES = 1), bit 7 in INTEDT: #001 Fh is set to 1 when a rising edge is detected at the

INT3 pin. (That is, remains 0 at falling edge.)

Enable

Condition

IMF= 1, INT0EN = 1

IMF- EFy= 1

IMF- EFii = 1, INT3W = 0

IMF- EFii = 1, INT3W= 1

IMF- EFi5= 1

Edge

rising falling both

INTIES

INT2ES

INT3ES

INTIES

INT2ES

INT3ES

INT3W

Notes)

Digital noise reject

— (hysteresis input)

—

Note 1)

—

Note 2)

Note 3)

Note 4)

— (hysteresis input)

Table 1-3. (b) Noise reject condition for INT3 (both-edge interrupt)

EINT3CR

NCS2

Note: In SLOW mode, set (NCS) = (0,0,0).

NCS1 NCSO

0 0 0 0 0 0 0 1 1 1 1 1 1 1

1 1 1 0 0 0

In SLOW mode, the digital noise filter in the above table is disabled.

(26/fc) x7-6/fc (26/fc) X 8 + 5/fc (27/fc) X 7 - 6/fc (27/fc) X 8 + 5/fc

(28/fc) x7-6/fc (28/fc) X 8 + 5/fc (29/fc) x7-6/fc (29/fc) X 8 + 5/fc

(2io/fc)x7-6/fc (210/fc) x8 + 5/fc

(211/fc) X 7 - 6/fc (211/fc) X 8 + 5/fc (2i2/fc)x7-6/fc (2i2/fc)x8 + 5/fc

max pulse width

for noise reject

3-24-40 2002-10-03

min pulse width

for immediate signal

- (histeresis input)

TOSHIBA

External interrupt Control Register 1

EINTCR

(0037h)

5 4

INT I

INT O IN T3

NC EN ES ES E S

INT 2 INT I IN T3W

(initial value 00**

00 0 0

TMP87CM24A/P24A

)

INT1NC

Noise reject time select 0 : Pulses of less than 63/fc [s] are eliminated as noise

INTOEN P10/INT0 pin configuration

INT3ES 0 : Rising edge INT2ES INT3tolNT1 edge select INTIES 1 : Falling edge

INT3W INT3 both edge selection

Note 1 : fc: High-frequency clock [Hz] *: Don't care

External interrupt Control Register 2 EINT3CR

(001Fh)

INT ' Mf- c ' IN T3 EO T 1 1 D ET

INTEDT

Flag indicating an interrupt at selected edge/non-selected edge, when INT3W = 1 (for

both-edge interrupts).

NCS

Noise cancellation time select for INT3 digital noise filter (valid only when INT3W = 1)

INT3DET

INT3 interrupt detection flag 0 : No interrupt

1 : Pulses of less than 15/fc [s] are eliminated as noise 0 : P10 input/output

1 : INTO pin (port PI 0 should be set to an input mode)

0 : Refer to INT3ES 1 : Both edge detection

Figure 1-26. (a) External Interrupt Control Register

(initial value :

0 : Interrupt at selected edge or no interrupt 1 : Interrupt at non-selected edge

No noise cancellation

00 0 00 1

Cancels (2®/fc x 7 - 6/fc) as noise.

01 0

Cancels (27fc x 7 - 6/fc) as noise. Cancels (2®/fc x 7 - 6/fc) as noise.

oil

Cancels (2®/fc x 7 - 6/fc) as noise.

10 0

Cancels (2’°/fc x 7 - 6/fc) as noise.

10 1

Cancels (2"/fc x 7 - 6/fc) as noise.

110 111

Cancels (2’Vfc x 7 - 6/fc) as noise.

1 : Interrupt

00 0 0 0

R/W

***)

R/W

Note 1: INTEDT and NCS are valid only when the INT3W bit in EINTCR (#0037h) is set to 1.

Therefore, when INT3W = 0, the digital noise filter set by the NCS bit is disabled.

Figure 1-26. (b) External Interrupt Control Register 2

3-24-41

2002-10-03

N> N>

H o

(/)

DD >

o o

INT3 control register

Figure1-26. (C) Bother One Edge Detictor of INT3/TC3 Pin

■O

vl n

N> > N>

TOSHIBA

Notes on the usage of INT3 pin (external interrupt)

1. In the case of using the INT3 pin for one edge (either rising or falling).

Note: In order to set/rewrite external interrupt control register(EINTCR), set/rewirte external

interrupt register in the interrupt disable state (IMF = 0). Then, enable interrupt

acceptance after interrupt latch cleared.

2. In the case of using the INT3 pin for both edge (rising and falling).

Note 1: When using the INT3 pin for both edges (rising and falling), set bit 0 (INT3W) in EINTCR

(#0037h) to 1.

Note 2: To detect the edge at which an interrupt is generated, read bit 7 (INTEDT) in EINT3CR

(#001 Eh), that is, at the beginning of the interrupt processing routine.

Note3: INTEDT is valid only for both-edge interrupts (INT3W = 1). INTEDT is set to 1 by an

interrupt as the non-selected edge; cleared to 0 after read automatically.

When rising edge is selected (INT3ES = 0), bit 7 in INTEDT (#001 Eh) is set to 1 when a falling

edge is detected at the INT3 pin. (That is, remains 0 if rising edge is detected.)

When falling edge is selected (INT3ES = 1), bit 7 in INTEDT: #001 Fh is set to 1 when a rising

edge is detected at the INT3 pin. (That is, remains 0 at falling edge.)

Note 4: In order to set/rewrite external interrupt control register(EINTCR), set/rewirte external

interrupt register in the interrupt disable state (IMF = 0). Then, enable interrupt acceptance after interrupt latch cleared.

TMP87CM24A/P24A

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TOSHIBA

Operation description for INT3 (both-edqe interrupt) in use:

1. Operation without setting/modifying external interrupt control register (EINTCR) after reset: For both-edge interrupts, rising edge is selected (INT3ES = 0) and fixed.

1)Case1: When the initial state of the INT3 pin is high after reset:

Reset

INT3ES ( = 0 : Keep rising edge)

INT3 terminal

TMP87CM24A/P24A

EI/DI instruction

I L11 (#003DH ; bitll)

Clear point of I L 11

INT3DET(#001FH ; bit3)

Read point of INT3DET

INTEDT(#001FH ; bit7)

Read point of INTEDT

(Dl)

(El)t

2)Case2: When the initial state of the INT3 pin is low after reset:

Reset

INT3ES ( = 0 : Keep rising edge)

INT3 terminal

EI/DI (Dl) instruction

I L11 (#003DH ; bitll)

Clear point of I L 11

INT3DET(#001FH ; bit3)

Read point of INT3DET

INTEDT (#001 FH ; bit7)

Read point of INTEDT

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2002-10-03

TOSHIBA

2. Operation with setting/modifying external interrupt control register (EINTCR) after reset:

1)Case3: When the initial state of the INT3 pin is low after reset/low at edge switchover from rising to falling:

Reset

INT3ES

INT3W

INT3 terminal

EI/DI (Dl) instruction

I L11 (#003DH ; bitll)

Clear point of I L 11

INT3DET(#001FH ; bit3)

Read point of INT3DET

INTEDT(#001FH ; bit7)

(rising edge)

(falling edge)

(El)t

* No interrupt generation at nonselected edge immediately after edge switchover.

TMP87CM24A/P24A

Read point of INTEDT

2)Case4: When the initial state of the INT3 pin is high after reset/high at edge switchover from rising to falling:

Reset

INT3ES (rising edge)

INT3W

INT3 terminal

EI/DI (Dl) instruction

I L11 (#003DH ; bitll)

Clear point of I L 11

INT3DET(#001FH ; bit3)

Read point of INT3DET

INTEDT (#001 FH ; bit7)

(falling edge)

(El)t

Read point of INTEDT

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TOSHIBA

3)Case5: When the initial state of the INT3 pin is high after reset/low at edge switchover from rising to falling:

Reset

INT3ES (rising edge)

TMP87CM24A/P24A

(falling edge)

INT3 terminal

EI/DI (Dl) instruction

I L11 (#003DH ; bitll)

INT3DET(#001FH ; bit3)

Read point of INT3DET

INTEDT(#001FH ; bit7)

Read point of INTEDT

(El)t

(Dl) t

(El)t

* No interrupt generation at non-selected edge immediately after edge switchover.

4)Case6: When the initial state of the INT3 pin is low after reset/high at edge switchover from rising to falling:

Reset

INT3ES (rising edge)

INT3W

INT3 terminal

(falling edge)

EI/DI (Dl) instruction

I L11 (#003DH ; bitll)

Clear point of I L 11

INT3DET(#001FH ; bit3)

Read point of INT3DET

INTEDT (#001 FH ; bit7)

Read point of INTEDT

(El)t

(Dl) t

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(El)t

2002-10-03

TOSHIBA

TMP87CM24A/P24A

1.10 Watchdog Timer (WDT)

The watchdog timer rapidly detects the CPU malfunction such as endless looping caused by noise or the like, and resumes the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a reset output or a non maskable interrupt request. However, selection is possible only once after reset. At first the reset output is selected. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals.

Note: Care must be given in system design so as to protect the Watchdog Timer from disturbing noise.

Otherwise the Watchdog Timer may not fully exhibit its functionality.

1.10.1 Watchdog Timer Configuration

MPX

Reset release signal from T.G.

I RESET

INTWDT

Figure 1-27. Watchdog Timer Configuration

1.10.2 Watchdog Timer Control

Figure 1-28 shows the watchdog timer control registers (WDTCR1, WDTCR2). The watchdog timer is automatically enabled after reset.

(1) Malfunction detection methods using the watchdog timer

The CPU malfunction is detected as follows.

If the CPU malfunction occurs for any cause, the watchdog timer output will become active at the rising of an overflow from the binary counters unless the binary counters are cleared. At this time,

when WDTOUT = 1 a reset is generated, which drives the RESET pin low to reset the internal

hardware and the external circuits. When WDTOUT = 0, a watchdog timer interrupt (INTWDT) is generated. The watchdog timertemporarily stops counting in the STOP mode including warm-up or IDLE mode, and automatically restarts (continues counting) when the STOP/IDLE mode is released.

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2002-10-03

TOSHIBA

Note: The watchdog timer consists of an internal divider and a two-stage binary counter. When

clear code 4Eh is written, only the binary counter is cleared, not the internal divider. Depending on the timing at which clear code 4Eh is written on the WDTCR2 register, the overflow time of the binary counter may be at minimum 314 of the time set in WDTCR1

<WDTT>. Thus, write the clear code using a shorter cycle than 314 of the time set in WDTCR1 <WDTT>.

Example : Sets the watchdog timer detection time to 22i/fc [s] and resets the CPU malfunction.

Within 3/4 of WDT

detection time

Within 3/4 of WDT

detection time

Watchdog Timer Control Register 1

WDTCR1

(0034h)

5 4 3

^ LD

L LD

r LD

WDT

(WDTCR1), 00001101B (WDTCR2), 4EH

(WDTCR2), 4EH

WCjJJ

WDT OUT

TMP87CM24A/P24A

WDTT<-10, WDTOUT<-1

Clears the binary counters (always clear immediately after changing WDTT)

Clears the binary counters

(Initial value

10 01

)

WDTEN

WDTT

WDTOUT

Note 1: WDTOUT cannot be set to "1" by program after clearing WDTOUT to "0 Note 2: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz] *: Don't care Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. Note 4: The watchdog timer must be disabled or the counter must be cleared immediately before entering

Watchdog Timer Control Register 2

WDTCR2

Watchdog timer enable/disable

Watchdog timer detection time

Watchdog timer output select

to the STOP mode. When the counter is cleared, the counter must be cleared again immediately after releasing the STOP mode.

5 4 3

(0035h)

WDTCR2

Note 1: The disable code is invalid unless written when WDTEN = 0. Note 2: *: Don't care Note 3: Since WDTCR2 is a write-only register, read-modify-write instructions (e.g., bit manipulating

Note 4: Write clear code 4Eh within 3/4 of the time set in W DTCR1<WDTT>.

Watchdog timer control code write register

instructions such as SET or CLR and arithmetic instructions such as AND or OR) cannot be used for read/write to this register.

Disable (it is necessary to write the disable code to WDTCR2)

Enable

00 2

^Vfc or 2'yfs [s]

01 2

^Vfc or 2’Vfs

10 2

^Vfc or 2’Vfs

2’7fc or 2"/fs

Interrupt request

Reset output

(Initial value : **** ****)

4Eh BIh

others

Watchdog timer binary counter clear (clear code) Watchdog timer disable (disable code)

Invalid

Write

only

Write

only

Figure 1-28. Watchdog Timer Control Registers

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TOSHIBA

TMP87CM24A/P24A

Table 1-4. Watchdog Timer Detection Time

Operating mode Detection time

NORMAL1 NORMAL2 SLOW Atfc = 8MHz At fs = 32.768 kHz

^Vfc [s]

^Vfc

'Vfc

2’7fc 2’7fc, 2"/fs

(2) Watchdog Timer Enable

The watchdog timer is enabled by setting WDTEN (bit 3 in WDTCR1) to "1WDTEN is initialized to

"1" during reset, so the watchdog timer operates immediately after reset is released.

Example: Enables watchdog timer

LD (WDTCR1), 00001OOOB ; WDTEN<-1

(3) Watchdog Timer Disable

The watchdog timer is disabled by writing the disable code (B1 h) to WDTCR2 after clearing WDTEN (bit 3 in WDTCR1) to "0". The watchdog timer is not disabled if this procedure is reversed and the disable code is written to WDTCR2 before WDTEN is cleared to "0".

During disabling the watchdog timer, the binary counters are cleared to "0".

Example: Disables watchdog timer

LDW (WDTCR1), 0B101H

^Vfc, 2’7fs rVh

^Vfc, 2’Vfs

’Vfs 1.048 ms

— —

; WDTEN<-0,WDTCR1<-disable code

4.194 s

262.1 ms

65.5 ms 62.5 ms

250 ms

1.10.3 Watchdog Timer Interrupt (INTWDT)

This is a pseudo non-maskable interrupt which can be accepted regardless of the contents of the EIR. If a watchdog timer interrupt or a software interrupt is already accepted, however, the new watchdog timer interrupt waits until the previous interrupt processing is completed (the end of the [RETN] instruction execution). The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source with WDTOUT.

Example : Watchdog timer interrupt setting up.

LD SP, 083FH ; LD (WDTCR1), 00001 OOOB ;

Sets the stack poi nter WDTOUT<-0

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2002-10-03

TOSHIBA

TMP87CM24A/P24A

1.10.4 Watchdog Timer Reset

If the watchdog timer output becomes active, a reset is generated, which drives the RESET pin low to reset the internal hardware. The reset output time is 220/fc [s] (131 ms at fc = 8 MHz). The RESET pin is sink open drain input/output with pull-up resistor.

Note: The high-frequency clock oscillator also turns on when a watchdog timer reset is generated in

SLOW mode. Thus, the reset output time is 220ifc. The reset output time include a certain amount of error if there is any fluctuation of the oscillation frequency when the high-frequency clock oscillator turns on. Thus, the reset output time must be considered approximate value.

2’7fc [s]

; ^ 2’7fc ^ :

Clock

”L

J~TwDTT = 11

Binary counter

Overflow

INTWDT interrupt

WDT reset output

_____

writes 4Eh to WDTCR2

Figure 1-29. Watchdog Timer Interrupt/Reset

____^____

(High-Z)

____i_____)^__________

;

~|("L" output)

1.11 Reset Circuit

The TMP87CM24A/P24A each have four types of reset generation procedures: an external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Table 1-5 shows on-chip hardware initialization by reset action. The internal source reset circuit (watchdog timer reset, address trap reset, and system clock reset) is not initialized when power is turned on. Thus, output from the RESET pin may go low (220/fc [s] (131 ms at 8 MHz) when power is turned on.

Table 1-5. Initializing Internal Status by Reset Action

On-chip Hardware Initial Value

Program counter Register bank selector Jump status flag Interrupt master enable flag Interrupt individual enable flags Interrupt latches

(PC)

(RBS)

(JF)

(IMF)

(EF)

(IL)

(FFFFh)-(FFFEh)

0 0 0

Divider of Timing generator

Watchdog timer Enable

Output latches of I/O ports

Control registers

On-chip Hardware Initial Value

Refer to I/O port

circuitry

Refer to each of

control register

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TOSHIBA

TMP87CM24A/P24A

1.11.1 External Reset Input

When the RESET pin is held at low for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEh to

FFFFh^

_ _

The RESET pin contains a Schmitt trigger (hysteresis) with an internal pull-up resistor. A simple power-on-

reset can be applied by connecting an external

capacitor and a diode.

Figure 1-30. Simple Power-on-

Reset Circuitry

1.11.2 Address-Trap-Reset

An address-trap-reset is one of fail-safe function that detects CPU malfunction such as endless looping

caused by noise or the like, and returns the CPU to the normal state. If the CPU attempts to fetch an instruction from a part of RAM or SFRs (address OOOOh to 083Fh forTMP87CM24A/P24A), an address-trapreset will be generated. Then, the RESET pin output will go low. The reset time is 220/fc [s] (131 ms at 8 MHz).

22“/fc [s]

Reset

|(High-Z)|

2Vfc

2^/fc

Reset release Xlristruction at address r

2^/fc

Execution

RESET output

Hotel: 0^a^083FH Note 2: During reset release, reset vector "r" is read out, and an instruction at address r is fetched and decoded.

Z)C

r Address-trap is occurred

________

("L" output) ((

Figure 1-31. Address-Trap-Reset

1.11.3 Watchdog Timer Reset

Refer to Section "1.10 Watchdog Timer".

1.11.4 System-Clock-Reset

Clearing both XEN and XTEN (bits 7 and 6 in SYSCR2) to "0" stops both high-frequency and low-

frequency oscillation, and causes the MCU to deadlock. This can be prevented by automatically

generating a reset signal whenever XEN = XTEN = 0 is detected to continue the oscillation. Then, the RESET pin output goes low from high-impedance. The reset time is 220/fc [s] (131 ms at 8 MHz).

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TOSHIBA

TMP87CM24A/P24A

2. Peripheral Hardware Functions

2.1 Special Function Registers (SFR) and Data Buffer Registers (DBR)

The TLCS-870 Series uses the memory mapped I/O system, and all peripherals control and data transfers

are performed through the special function registers (SFR) and data buffer registers (DBR).

The SFR are mapped to addresses OOOOh to OOBFh and the DBR to addresses OFBOh to OFFFh-

Figure 2-1 shows the TMP87CM24A/P24A SFRs and DBRs.

Address

OOOOh

03 04 05 06 07 08 09 OA OB OC OD OE OF

10 11

13 14 15 16 17 18 19 1A IB 1C ID IE IF

Address

0F80h

0F93 0F94

OFEF OFFO

0FF7 0FF8

OFFF

Read Write

PO Port PI Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Port P8 Port P9 Port

POCR (PO I/O control) P1CR(P1 I/O control) P4CR1 (P4 I/O control)

ADCDR (AD conv. result)

ADCCR (AD converter control)

TREG1B,

TREGIBh

TREG3A (Timer register 3A)

TREG3B (Timer register 3B)

EINT3CR (External interrupt control 2)

P5CR (P5 I/O control)

TREGIAl TREGIAh

■■ (Timer register 1B)

TCI CR (TCI control) TC2CR (TC2 control) TREG2, TREG2.

TC3CR (TC 3 control)

reserved reserved

TREG5 (Timer registers) TC5CR (TC 5 control)

Read Write

LCD

display data buffer

Reserved

5101

transmit and receive

data buffer

5102

transmit and receive

data buffer

(b) Data Buffer Registers

Address

(Timer register 1A)

(Timer register 2)

(a) Special Function Registers

0020h

SI01SR(SI01 status) SI01CR1

SI02SR(SI02 status)

23 24 25 26 27 28

Reserved Reserved Reserved Reserved

(SI01 control)

SI01CR2

SI02CR1

(SI02 control)

SI02CR2

LCDCR (LCD control)

Read Write

2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B

TBTCR (TBT^G/pyO control)

EINTCR (External Interrupt control l)

SYSCR1 SYSCR2

EIR, EIR

3C 3D 3E

PSW (program status word) I RBS (register bank selector)

Note 1: Do not access reserved areas by the program. Note 2: When defining address 003Fh with assembler

symbols, use GPSW and GRBS.

Note3: Do not access. Note 4: Operations specified to writing registers and

interrupt latches by read modifying write instructions (bit operation instructions such as

SET, CLR, etc. , or operation instructions such as AND, OR, etc.) are not effective.

•P 7.C P. i P./ .^9 9 P? .9 9.9 i 9 9^. 99 P.^. (9J}

P8CR (pSsegpieptgutput control) P9CR (pSsegpieptgutput control)

P4CR2 (P4 output control) Reserved Reserved Reserved Reserved Reserved Reserved

yVDJCRI

WDTCR2

■ (System control).......................

■ (Interrupt enable register)--

■■ (Interrupt latch)-

Reserved

control

•(

WDT

Figure 2-1. SFR & DBR

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2002-10-03

TOSHIBA

TMP87CM24A/P24A

2.2 I/O Ports

The TMP87CM24A/P24A have 10 parallel input/output ports (69 pins) each as follows:

Primary Function Secondary Functions

Port PO 8-bit I/O port Port PI 8-bit I/O port External interrupt input, timer/counter input/output, and divider

Port P2 3-bit I/O port Low-frequency resonator connections, external interrupt input, and

Port P3 6-bit I/O port Port P4 8-bit I/O port

Port P5 8-bit I/O port Analog input Port P6 8-bit I/O port Segment Output Port P7 8-bit I/O port Segment Output Port P8 8-bit I/O port Segment Output Port P9 4-bit I/O port Segment Output

Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should either be held externally until read or reading should be performed several times before processing. Figure 2-2 shows input/output timing examples.

External data is read from an I/O port in the SI state of the read cycle during execution of the read

instruction. This timing can not be recognized from outside, so that transient input such as chattering

must be processed by the program.

Output data output changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O port.

output

STOP mode release signal input

Serial interface, external interrupt input, timer/counter input/output

Fetch cycle Fetch cycle Read cycle

----------

Instruction SO S1 S2 S3 SO S1 S2 S3 SO S1 S2 S3

execution

cycle —

Input strobe—

Data input

When reading an I/O port except programmable I/O ports, whether the pin input data or the output latch

contents are read depends on the instructions, as shown below:

(1) Instructions that read the output latch contents

(2) Instructions that read the pin input data

® Instructions other than the above (1) © (HL) side of ADD/ADDC/SUB/SUBB/AND/OR/XOR (src),(HL)

H-i

------------

E)jc.: L,D jx)

(a) Input Timing (b) Output Timing

Note: The positions of the read and write cycles may vary, depending on the instruction.

^l-f

------------

____I___I___I___

Figure 2-2. Input/Output Timing (Example)

execution

cycle"

Output latch__.

pulse

Data output

Fetch cycle Fetch cycle Write cycle

so SI S2 S3 SO SI S2 S3 SO SI S2 S3

___

1 1 ...................................................

Old

X New

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TOSHIBA

2.2.1 Port PO (P07 to POO)

Port PO is an 8-bit general-purpose input/output port which can be configured as either an input or an

output in one-bit unit under software control. Input/output mode is specified by the corresponding bit

in the port PO input/output control register (POCR). Port PO is configured as an input if its corresponding

POCR bit is cleared to "0", and as an output if its corresponding POCR bit is set to "1

During reset, POCR is initialized to "0", which configures port PO as input. The PO output latches are also

initialized to "0".

Output latch

Notel: i = 7to0 Note2 : STOP: bit 7 ofSYSCR 1 Notes : OUTEN: bit 4 ofSYSCR2

TMP87CM24A/P24A

POi

(OOOOh)

R/W

POCR

P07

6 5

P06 P05

6 5

(OOOAh)

POCR

Example : Setting the upper 4 bits of port PO as an input port and the lower 4 bits as an output

I/O control for port PO 0 : Input mode Write (Set for each bit individually) 1 : Output mode

port (Initial output data are 1010b).

P04

2 1

P02

P03

Figure 2-3. Port PO and POCR

POI POO

2 1

(Initial value : 0000 0000)

LD (PO), 0000101 OB ; Sets initial data to PO output latches LD (POCR), 00001111B ; Sets the port PO input/output mode

Note 1

Note 2

Ports set to the input mode read the pin states. When input pin and output pin exist in port PO together, the contents of the output latch of ports set to the input mode may be rewritten by executing the bit manipulation instructions. Pins set to the output mode read a value of the output latch.

The POCR is a write-only register. It can not be operated by the read-mod ify-write instruction

(Bit manipulation instructions of SET, CLR, etc. and Arithmetic instructions of AND, OR, etc.)

only

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TOSHIBA

TMP87CM24A/P24A

2.2.2 PortPI (P17to P10)

Port PI is an 8-bit input/output port which can be configured as an input or an output in one-bit unit

under software control. Input/output mode is specified by the corresponding bit in the port PI

input/output control register (P1CR). Port PI is configured as an input if its corresponding P1CR bit is

cleared to "0", and as an output if its corresponding P1CR bit is set to "1". During reset, the P1CR is

initialized to "0", which configures port PI as an input. The PI output latches are also initialized to "0".

Port PI is also used as an external interrupt input, a timer/counter input/output, and a divider output. When used as secondary function pin, the input pins should be set to the input mode, and the output

pins should be set to the output mode and beforehand the output latch should be set to "1".

It is recommended that pins P11 and PI 2 should be used as external interrupt inputs, timer/counter input,

or input ports. The interrupt latch is set at the rising or falling edge of the output when used as output

ports.

Pin P10 (INTO) can be configured as either an I/O port or an external interrupt input with INTOEN (bit 6 in

EINTCR). During reset, pin P10 (INTO) is configured as an input port P10.

STOP

OUTEN

PICRi

Data input

Data output

Control output -

Control input

4 3 2

P17

(0001h)

R/W

P1CR

(OOOBh)

LD (EINTCR), 01000000B ; INT0EN<-1 LD (PI), 10111111B ; P17<-1, P14<-1, P16<-0 LD (P1CR), 11010000B

Note 1

Note 2

P16 P15

7 6 5 4 3 2

P1CR

Ports set to the input mode read the pin states. When input pin and output in exist in port PI together, the contents of the output latch of ports set to the input mode may be rewritten by executing the bit manipulation instructions. Pins set to the output mode read a value of the output latch.

The P1CR is a write-only register. It can not be operated by the read-mod ify-write instruction

(Bit manipulation instructions of SET, CLR, etc. and Arithmetic instructions of AND, OR, etc.)

I/O control for port PI 0 : Input mode Write (Set for each bit individually) 1 : Output mode

Example : Sets P17, P16 and P14 as output ports, P13 and P11 as input ports, and the others as function

P14

P13

TC2

PPG

DVÜ

pins. Internal output data is "1" forthe P17 and P14 pins, and "0" forthe P16 pin.

Output latch

P12

P11

INTI

P10

(Initial value : 0000 0000)

INT2

TCI

Figure 2-4. Port PI and P1CR

Q pii

Note: i = 7 to 0

only

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TOSHIBA

TMP87CM24A/P24A

2.2.3 Port P2 (P22 to P20)

Port P2 is a 3-bit input/output port. It is also used as an external interrupt input, a STOP mode release signal input, and low-frequency crystal connection pins. When used as an input port, or a secondary function pin, the output latch should be set to "1". During reset, the output latches are initialized to

## ^ n

A low-frequency crystal (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dual-clock

mode. In the single-clock mode, pins P21 and P22 can be used as normal input/output ports.

It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal

input, or an input port. If used as an output port, the interrupt latch is set on the falling edge of the

output pulse. When a read instruction is executed for port P2, bits 7 to 3 read in as indefinite.

(0002h)

R/W

P22

P21

XTOUT

XTIN

Figure 2-5. Port P2

3-24-56

P20

(Initial value: *****

INT5

STOP

11 1

)

2002-10-03

TOSHIBA

TMP87CM24A/P24A

2.2.4 Port P3 (P35 to P30)

Port P3 is an 6-bit input/output port. When used as an input port, the output latch should be set to "1 The output latches are initialized to "1" during reset. When a read instruction is executed for port P3, bit 7 and bit 6 read in as indefinite.

Example 1: Output the immediate data 2Ah to the P3 port.

LD (P3),2AH ; P3^2Ah

Example 2: Inverts the output of the upper 3bits (P35 to P34) of the P3 port.

XOR (P3), 110000B

; P35toP34^-^toP34

CM P/MCM P/TEST/others

(0003h)

R/W

; - -

6 5

P35

P34

2 1

P32

P33

Figure 2-6. Port P3

P31 P30

(Initial value: **11 1111)

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2002-10-03

TOSHIBA

TMP87CM24A/P24A

2.2.5 Port P4 (P47 to P40)

Port P4 is an 8-bit input/output port, and is also used as an external interrupt input, a timer/counter

input/output and a serial interface input/output. Input/output mode is specified by the corresponding

bit in the port P4 input/output control register (P4CR1). It can be selected whether output circuit of P4

port is Push-pull port or Sink open drain individually, by setting P4CR2. When used as a timer/counter output and serial interface output, respective P4CR1 should be set to "1"

after P4 output latch is set to "1". When used as an input port, external interrupt input, timer/counter input and serial interface input,

respective P4CR1 should be set to "0" after P4CR2 is set to "0".

During reset, the P4CR1 is initialized to "1", and configures port P4 as an output mode. Also, port P4

output latch is initialized to "1 ".

(0004h)

R/W

P4CR1

(OOOCh)

P47

S02

P4CR1

P45

SCK2

P44

SOI

P46

SI2

Port 4/1/0 select (Set for each bit individually)

P43

SI1

P42 ; P41

SCK1

P40

PWM

INT3

PDO

TC3

0: Input mode 1 : Output mode

(Initial value: 1111 1111)

Write-

only

7 6 5 4 3 2 1 0

P4CR2

(002Dh)

P4CR2

Note 1: Ports set to the input mode read the pin states. When input pin and output pin exist in port P4

together, the contents of the output latch of ports set to the input mode may be rewritten by executing the bit manipulation instructions. Pins set to the output mode read a value of the output latch.

Note 2: The P4CR1 and P4CR2 are a write-only register. It can not be operated by the read-modify-

write instruction (Bit manipulation instructions of SET, CLR, etc. and Arithmetic instructions of

AND, OR, etc.)

Port 4/Output circuit control (Set for each bit individually)

0: Sink open-drain output 1 : Push-pull output

Figure 2-7. Port P4

(Initial value: 0000 0000)

Write -

only

3-24-58 2002-10-03

TOSHIBA

TMP87CM24A/P24A

2.2.6 Port P5 (P57 to P50)

Port P5 is a general-purpose 8-bit I/O port that can be specified bitwise. It is also used for analog input.

Specify input or output using the P5 I/O control register (P5CR) and AINDS (bit 4 of ADCCR). During reset,

because P5CR and AINDS are initialized to "0", P50 port is specified for analog input and P51 to P57 ports

are specified for port input. At reset, the output latch of port P5 is initialized to "0". The P5CR is write-

only register. The pins of port P5 not specified for analog input can be used as an I/O port; to maintain

accuracy, do not use them for output instructions during AD conversion. While the AD converter is

operating, if a read instruction is executed for port P5, read data of port selected to analog input is "1".

(0005h)

R/W

P5CR

AIN7

P57

6 5

P56 P55

AIN6 AIN5

6 5

(OOODh)

P5CR

Note 1: P5CR is a write-only register and must not be used with any of the read-modify-write instruction. Note 2: Unused analog input pins cannot be configured as output mode when AINDS = 0.

Note 1: Ports set to the input mode read the pin states. When input pin and output pin exist in port P5

Note 2: The P5CR is a write-only register. It can not be operated by the read-modify-write instruction

(Bit manipulation instructions of SET, CLR, etc. and Arithmetic instructions of AND, OR, etc.)

I/O control for port P5 0: Input mode Write(Set for each bit individually) 1: Output mode

P54

AIN4

P53

AIN3

2 1

P52

P51 P50

AIN2 AIN1

2 1

Figure 2-8. Port P5

AINO

(Initial value: 0000 0000)

only

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TOSHIBA

TMP87CM24A/P24A

2.2.7 Ports P6 (P67 to P60) Port P7 (P77 to P70) Port P8 (P87 to P80) Port P9 (P93 to P90)

Port P6, P7, P8 and P9 are an 8-bit input/output ports and are also used as the segment output port.

Input/output mode or segement output mode is specified by the corresponding bit in the Px port control

output latches are also initialized to "1". PxCR can only be written. When a read instruction is executed for port P9, bits 7 to 4 read in as indefinite. Note: x = 6,7,8,9

Example: Setting the upper 2 bits of port P6 as a segment output port, and the others as

input/output port.

LD (P6CR), 11000000B

(0006h)

R/W

P6CR

(0029h)

(0007h)

R/W

P7CR

(002Ah)

(0008h)

R/W

P8CR

(002Bh)

(0009h)

R/W

P9CR

(002Ch)

P67

SEG16

P66

SEG17

P65

SEG18

P64

SEG19

P63

SEG20

P62

SEG21

P61

SEG22

P60

SEG23

(Initial value: 1111 1111)

(Initial value: 0000 0000)

P6CR Port P6/

segment output select

P77

P76

SEG24

SEG25

P75

SEG26

P74

SEG27

P73

SEG28

P72

SEG29

0: Port P6 mode

1: Segment output mode

P71

P70

SEG30

SEG31

(Initial value: 1111 1111)

(Initial value: 0000 0000)

P7CR Port P7/

segment output select

P87

P86

SEG32

SEG33

P85

SEG34

P84

SEG35

P83

SEG36

P82

SEG37

0: Port P7 mode

1: Segment output mode

P81

P80

SEG38

SEG39

(Initial value: 1111 1111)

(Initial value: 0000 0000)

P8CR Port P8/

segment output select

P93

SEG12

P92

SEG13

0: Port P8 mode

1: Segment output mode

P91

P90

SEG14

SEG15

(Initial value: 1111 1111)

(Initial value: 0000 0000)

P9CR Port P9/ 0: Port P9 mode Write-

segment output select 1: Segment output mode

Figure 2-9. Port P6, P7, P8, P9

Write-

only

Write-

only

Write-

only

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TOSHIBA

Note: The P6CR, P7CR, P8CR and P9CR are write-only register. It can not be operated by the read-

modify instruction (Bit manipulation instructions of SET, CLR, etc. and Arithmetic instructions of AND, OR, etc.)

TMP87CM24A/P24A

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2002-10-03

TOSHIBA

TMP87CM24A/P24A

2.3 Time Base Timer (TBT)

The time-base timer is used to generate the base time for key scan and dynamic display processing. For this purpose, it generates a time-base timer interrupt (INTTBT) at predetermined intervals. This interrupt is generated beginning with the first rising edge of the source clock (the timing

generator's divider output selected by TBTCK) after the time-base timer is enabled. Note that since the divider cannot be cleared by a program, the first interrupt only may occur earlier than the set interrupt

period. (See Figure 2-10. (b).) When selecting the interrupt frequency, make sure the time-base timer is disabled. (Do not change the selected interrupt frequency when disabling the active timer either.) However, you can select the

interrupt frequency simultaneously when enabling the timer.

Example : Sets the time base timer frequency to fc/2i6[Hz] and enables an INTTBT interrupt.

LD (TBTCR), 00001010B SET (EIRL). 6

TBTCR

(0036h)

Figure 2-10. Time Base Timer

(DVOEN)

TBTEN

TBTCK

6 5

(DVOCK)

Time base timer enable/disable

Time base timer interrupt frequency select

(DV7CK) TBTEN ,TBTCK ,

2 1

000

001

010

oil

100

101

110

0 Disable

Enable fc/223 or fs/2^^[Hz]

fc/22^ or fs/2^3 fc/2^^ or fs/2^ fc/2^^ or fs/2^ fc/2^3 or fs/2^ fc/2^2 or fs/2'^ fc/2" or fs/2^

(Initial value : 0**0 0***)

111 fc/2^ or fs/2

Note: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care

Figure 2-11. Time Base Timer Control Register

R/W

3-24-62

2002-10-03

TOSHIBA

TBTCK

000 001 fc/2^'' 010 oil 100 101

110

111

Table 2-1. Time Base Timer Interrupt Frequency

NORMAL1/2, DV7CK = 0

fc/223

fc/2^^ fs/2S

fc/2'^ fs/2^

fc/2^3 fc/2^2 fs/2^

fc/2"

fc/29

DLE1/2mode

DV7CK= 1 Atfc = 8MHz At fs = 32.768 kHz

fs/2^5 fs fs/2^3 fs/2^3

fs/25

fs/23 fs/2

SLOW, SLEEP mode

Interrupt Frequency

0.95 Hz

3.81

122.07

488.28

976.56

1953.12

3906.25 4096

15625

TMP87CM24A/P24A

1 Hz

4 128 512

1024 2048

16384

2.4 Divider Output (DVO)

A 50% duty pulse can be output using the divider output circuit, which is useful for piezo-electric buzzer drive. Divider output is from pin P13 (DVO). The P13 output latch should be set to "1" and then the P13 should be configured as an output mode. Divider output circuit is controlled by the control register (TBTCR) shown in Figure 2-12.

TBTCR

(0036h)

6 5

DVOEN DVpCK (DV7CK) (TBTEN) ,(TBTCK),

DVOEN

D\/nrK

Example : 1 kHz pulse output (at fc = 8 MHz)

Divider output enable/disable

Divider output (DVO) frequency selection

Note: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care

SET LD (PI CR), 00001OOOB LD

DVOCK

00 01 10 11 fc/2’° fs/2^

Figure 2-12. Divider Output Control Register

(P1).3

(TBTCR), 10000000B ; DVOEN<-1, DVOCK<-00

Frequency of

Divider Output

fc/2’^ or fs/2= 0.512 [kHz]

fc/2’2 fs/2^ 1.024

fc/2" fs/2^

2 1 0

01Disable

Enable

: fc/2^3 or fs/2^[Hz]

: fc/2^2 or fs/2'^

: fc/2" or fs/2^

11 : fc/2^° or fs/22

Table 2-2. Frequency of Divider Output

At fc = 4.194304 MHz Atfc = 8MHz At fs = 32.768 kHz

2.048 3.906 4.096

4.096

(Initial value : 0**0 0***)

; PI 3 output latch <-1 ; Configures PI 3 as an output mode

0.976 [kHz]

1.953 2.048

7.812 8.192

1.024 [kHz]

R/W

3-24-63 2002-10-03

TOSHIBA

TMP87CM24A/P24A

Figure 2-13. Divider Output

3-24-64

2002-10-03

N> Ò>

1Л

1л

(Ö'

3 Ф

r+ Ф

(/)

n >

О О N>

Fugure2-14. Timer/Counter 1

■O

vl n

N> > N>

TOSHIBA

TMP87CM24A/P24A

2.5.2 Control

The timer/counter 1 is controlled by a timer/counter 1 control register (TC1CR) and two 16-bit timer

registers (TREG1A and TREG1B). Reset does not affect TREG1A and TREG1B.

TREG1A

(0010, 001 1h)

TREG1B

(0012,0013h)

TC1CR

(0014h)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

_____1____1____1____

TREGIAu (0011h)

, , TREG1B^^(0013н)

xLj

___

iHi

___1____1____

, , TREG1Al(0010,h)

, , TREG 18^(0012^)

Read/Write (Write available in only PPG

TFF1

6 5 4 3 2 1 0

SCAPI

MCAP1

METTI

MPPG1

TC1S

_____1____

TC1CK

_____1____

TC1M

_____1____

(Initial value : 0000 0000)

output mode)

00 Timer/external trigger timer/event counter mode

Window mode

TC1M

TC1CK

TC1S

SCAPI

MCAP1

METTI

TCI mode select

TCI source clock select

TCI start control

Software capture control 0 Pulse width measurement control

External trigger timer control

10 Pulse width measurement mode 11

PPG output mode Internal clock fc/2" or fs/2^ [Hz]

00 01 Internal clock fc/2^

10 Internal clock fc/2^ 11

External clock (TCI pin nput) Stop and counter clear

00 01 Command start

10 Reserved 11

External trigger srart

: Software capture trigger (Note 3)

: Double edge capture 1 : Single edge capture

0 : Trigger srart 1 : Trigger start and stop

MPPG1 PPG output control 0 : Cotinuous pulse 1 : Single pulse

TFF1

Note 1: Note 2:

Note 3:

Note 4:

Note 5:

Note 6: Note 7:

Note 8: Note 9:

Timer F/F1 control for PPG output mode

fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz] Writing to the low-byte of the timer registers (TREGIAl , TREGIBi), the comparison is inhibited until the high-byte (TREGIAh , TREGIBh) is written. (Only the low-byte of the timer registers cannot be changed.) After writing to the high-byte, the comparison within 1 cycle (during instruction execution) is ignored. Set the mode, source clock, edge (INT2ES), PPG control and timer F/F1 control when TCI stops (TCI S = 00). Software capture can be used in only timer and event counter modes. SCAP1 is automatically cleared to "0" after software capture. Values to be loaded to timer registers must satisfy the following condition.

TREG1A>TREG1B>0 (PPG output mode) ; TREG1A>0 (others)

Always write "0" to TFF1 except the PPG output mode.

TC1CR is a write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. TREG1B cannot be written after setting to PPG output mode. In case of fc/23 is selected on the pulse width measurem ent mode. The LSB of counter (TREG1B) is always "0". In the other source clock is selected, the value of counter correspond with real count.

: Clear 1

: Set

Write only

Write

only

Figure 2-15. Timer Registers and TCI Control Register

3-24-66

2002-10-03

TOSHIBA

TMP87CM24A/P24A

2.5.3 Function

Timer/counter 1 has six operating modes: timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output mode.

(1) Timer Mode

In this mode, counting up is performed using the internal clock. The contents of TREG1A are compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared to"0". Counting up resumes after the counteriscleared. The current contents of up-counter can be transfered to TREG1B by setting SCAP1 (bit 6 in TC1CR) to "1" (software capture function). SCAP1 is automatically cleared to "0" after capaturing.

Table 2-3. Timer/Counter 1 Source Clock (Internal Clock)

Source clock

NORMAL1/2, IDLE1/2 modes

DV7CK = 0

fc/2" [Hz] fs/2^ [Hz] fs/2^ [Hz] fc/2' fc/2' fc/2^ fc/2^

Example 1 : Sets the timer mode with source clock fs/23[Hz] and generates an interrupt 1 s. later (at

Note : TC1CR is a write-only register, which cannot start by [SET(TC1CR).4] instruction.

Example 2 : Software capture

DV7CK= 1

fs = 32.768 kHz).

LD (TC1CR),00000000B ; Sets the TCI mode and source clock LDW (TREG1A), 1000H SET El LD

LD LD

SLOW, SLEEP modes

(EIRL).EF4

(TCI CR), 0001OOOOB

(TC1CR),01010000B WA, (TREG1B)

Atfc = 8MHz At fs = 32.768 kHz Atfc = 8MHz At fs = 32.768 kHz

256 JUS

Resolution Maximum time setting

244.14 juS

16 jtS

1 piS

; Sets the timer register (1 s^23/fs = iooOh) ; enable INTTC1

; Starts TCI

; SCAPI<-1 (Captures) ; Reads captured value

16.8 s 16.0 s

1.0 s

65.5 ms

3-24-67

2002-10-03

TOSHIBA

TMP87CM24A/P24A

Command start

Source clock

Up-counter

TREG1A

INTTC1 interrupt

Source clock

Up-counter

TREG1B

SCAPI

(2) External Trigger Timer mode

In this mode, counting up is started by an external trigger. This trigger is the edge of the TCI pin

input. Either the rising or falling edge can be selected. Edge selection is the same as for the external

interrupt input INT2 pin. Source clock is used an internal clock selected. The contents of TREG1A is compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared to"0" and halted. The counter is restarted by the selected edge of the TCI

pin input. When the edge input is opposite to the edge input way of the count start trigger at METTI (bit 6 in TC1CR) = 1, the counter is cleared, and count stops. In this mode, pulse input with a constant pulse width generates interrupt. When METTI is "0", the opposite edge input is ignored. The edge of TCI

pin input before match detection is also ignored. The TCI pin input has the same noise rejection as the INT2 pin; therefore, pulses of 7/fc [s] or less are

rejected as noise. A pulse width of 24/fc [s] or more is required for edge detection in NORMAL1/2 or

IDLE1/2 mode. The noise rejection circuit is turned off in SLOW and SLEEP modes. But, a pulse width of 4/fs [s] or more is required.

JlAllJlJlJinvrLnnnn^^

I)GZ)GZ)C2:XiZ)GZn^XHXZDGZ)(

Example 1 :Generates interrupt after 100 /¿sfrom TCI pin input rising edge (at fc = 8 MHz).

LD (EINTCR),00000000B LDW (TREG1A),0064H SET El LD

>2 :When

LD LDW (TREG1A), OOFAH 4 ms T 27/fc = FAh SET El LD

0 ;

Match

detect \rr

(a) Timer

Capture

Counter

11 n

(b) Software Capture

Figure 2-16. Timer Mode Timing Chart

INT2ES<-0 (rising edge) 100 //s ^ 23/fc = 64h

(EIRL).EF4

(TC1CR), 00111000B Starts TCI external trigger, METT = 0

"L" level pulses of 4ms or more is input to TCI pin, generates interrupt

(at fc =

8 MHz)

(EINTCR), 000001OOB INT2ES<-1 ("L" level)

(EIRL).EF4

(TC1CR), 011101 OOB

Enables INTTC1 interrupt

Starts TCI external trigger, METT = 1

Capture

3-24-68 2002-10-03

TOSHIBA

TMP87CM24A/P24A

TCI pin input

Internal clock

Up-counter

TREG1A

INTTC1

TCI pin input

Internal clock

Up-counter

TREG1A

INTTC1

Count start

Trigger

---------------------------------------------[ n <

(a) Trigger Start (METT = 0)

Count start

Trigger

Count

clear

Ijn^ Trigger

(b) Trigger Start and Stop (METTI = 1)

Match

Count start

' 1

i\~Y Clear

Count restart Rising edge select

^ Trigger

wRising edge select

*- (INT2ES = 0)

n-2Xn-lYnY 0

■'h

Match I Idear

Note : m <n

(INT2ES = 0)

Figure 2-17. External TriggerTimer Mode Timing Chart

(3) Event Counter Mode

In this mode, events are counted on the edge of the TCI pin input. Either the rising or falling edge can be selected with INT2ES in EINTCR. The contents of TREG1A are compared with the contents of

up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared. Counting up resumes after the counter is cleared. The maximum applied frequency is fc/24 [Hz] in

NORMAL1/2 or IDLE1/2 mode and fs/24 [Hz] in SLOW or SLEEP mode. Setting SCAP1 to "1" transferres the current contents of up-counter to TREG1B (software capture function). SCAP is automatically cleared after capturing.

3-24-69 2002-10-03

TOSHIBA

(4) Window mode

Counting up is performed on the rising edge of the pulse that is the logical AND-ed product of the TCI pin input (window pulse) and an internal clock. The contents of TREG1A are compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared. Positive or negative logic for the TCI pin input can be selected with INT2ES. Setting SCAP1 to "1" transférés the current contents of up-counter to TREG1B. It is necessary that the maximum applied frequency (TCI input) be such that the counter value can be analyzed by the program. That

is, the frequency must be considerably slower than the selected internal clock.

TCI pin input

TMP87CM24A/P24A

Command start

Internal clock

Up-counter

TREG1A

INTTC1 interrupt

TCI pin input

Internal clock

Up-counter

TREG1A

INTTC1 interrupt

jiJtLilnjiJiJTrlmj^^

______Xt_____________________________________________________<

Match

(a) Positive Logic (INT2ES = 0)

Command start

-----i------

0 )TTYTYTYTXT)r 6

(b) Negative Logic (INT2ES = 1)

Figure 2-19. Window Mode Timing Chart

Clear

Match Clear

(5) Pulse width measurement mode

Counting is started by the external trigger (set to external trigger start by TCI S). The trigger can be selected either the rising or falling edge of the TCI pin input. The source clock is used an internal clock. On the next falling (rising) edge, the counter contents are transferred to TREG1B and an

INTTC1 interrupt is generated. The counter is cleared when the single edge capture mode is set. When double edge capture is set, the counter continues and, at the next rising (falling) edge, the counter contents are again transferred toTREGIB. If a falling (rising) edge capture value is required,

it is necessary to read out TREG1B contents until a rising (falling) edge is detected. Falling or rising edge is selected with INT2ES, and single edge or double edge is selected with MCAP1 ( bit 6 in TC1CR).

3-24-70 2002-10-03

TOSHIBA

Example : Duty measurement (Resolution fc/2^ [Hz])

CLR LD (EINTCR),00000000B LD (TCI CR), 0000011 OB ; Sets the TCI mode and source clock

SET

El LD

CPL

JRS F,SINTTC1

LD (HPULSE),(TREG1BL) ; ReadsTREGIB LD (HPULSE + 1),(TREG1BH) RETI LD (WIDTH), (TREG1BL) LD (WIDTH+ 1),(TREG1BH)

RETI

(INTTC1SW). 0 ; INTTC1 service switch initial setting

; Sets the rise edge at the INT2 edge

(EIRL).4

(TC1CR),00110110B

(INTTC1SW). 0 ; Complements INTTC1 service switch

PINTTC1

WIDTH

^HPULSE

; Enables INTTC1

; Starts TCI with an external trigger

; Reads TREG IB (Period)

TMP87CM24A/P24A

TCI pin

INTTC1SW

Note : In case offcl2^ is selected on the pulse width measurement mode. The LSB of counter (TREG1B)

is always "0". In the other source clock is selected, the value of counter correspond with real count.

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2002-10-03

TOSHIBA

TCI pin input

TMP87CM24A/P24A

Count start Count start

Trigger

(INT2ES = 0)

Internal clock

Up-counter

TREG1B

INTTC1

TCI pin input

Internal clock

Up-counter

TREG1B

INTTC1

JinÜinJinJtJirlU^^

ZEIXIXIXDQC50«

(a) Single Edge Capture

Count start Count start

I 1

: \ Capture

______

[Applications] High or low pulse width measurement

JUlTLJinnAriJ^^

Capture

[Applications] ® Period/Frequency measurement

® Duty measurement

XDe

(INT2ES = 0)

Capture

(b) Double Edge Capture

Figure 2-20. Pulse Width Measurement Mode Timing Chart

(6) Programmable Pulse Generate (PPG) output mode

Counting is started by an edge of the TCI pin input (either the rising or falling edge can be selected) or by a command. The source clock is used an internal clock. First, the contents of TREG1B are compared with the contents of the up-counter. If a match is found, timer F/F1 output is toggled. Next, timer F/F1 is again toggled and the counter is cleared by matching with TREG1A. An INTTC1 interrupt is generated at this time. Timer F/F output is connected to the P14 (PPG) pin.

In the case of PPG output, set the P14 output latch to "1 " and configure as an output with PICR4. Timer F/F1 is cleared to "0" during reset. The timer F/F1 value can also be set by program and either a positive or negative logic pulse output is available. Also, writing to the TREG1B is not possible

unless the timer/counter 1 is set to the PPG output mode.

Example : "H" level 800 jus, "L"" level 200 jus pulse output at fc = 8 MHz

SET (P1).4 LD (P1CR),00010000B LD (TC1CR), 1000101 IB LDW (TREG1A), 03E8H LDW (TREG1B), 00C8H LD (TC1CR), 1001001 IB

PI 4 output latch<-1 Sets PI 4 to an output mode Sets PPG output mode Sets a period (1 ms ^ 1 //S = 03E8h) Sets "L" level pulse width (200 //S ^ 1 pis = OOCBh) Start

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TOSHIBA

TMP87CM24A/P24A

Internal clock

Up-counter

TREG1B

TREG1A

PPG output

INTTC1

TCI pin input

Internal clock

Up-counter

TREG1B

TREG1A

PPG output

___

(a) Pulse

Count start

Trigger

0 A2A A A'^ ^A A^A 0

Matcl\ \

_____

______

[I ;i

___

Command start

Note: m>n

Í1

External trigger start

INTTC1

TCI CR write strobe >-

Match with TREGIB >-

Match with TREG1A >■

INTTC1 interrupt

_____________________________n________________________________________

[Applications] One shot pulse output

(b) Single

Figure 2-21. PPG Output Mode Timing Chart

PI 4 output latch

Data output >■

TFF1 >■

Reset >■

MPPG1

>Set

> Clear Q

>Toggle

Timer F/F 1

►TC1S clear signal

Figure 2-22. PPG Output

Reset

3-24-73 2002-10-03

Output enable

P14(PPG) pin

Note: m>n

TOSHIBA

2.6 16-Bit Timer/Counter 2 (TC2)

2.6.1 Configuration

TMP87CM24A/P24A

INTTC2

interrupt

Timer/Counter 2 control register

16-bit timer register 2

Figure 2-23. Timer/Counter 2 (TC2)

TREG2H TREG2L

write strobe write strobe

2.6.2 Control

Thetimer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register

2 (TREG2). Reset does not affect TREG2.

TREG2

(0016, 001 7h)

TC2CR

(0015h)

_____^^________

6 5

TC2M

TC2CK

Timer/counter 2 operating

mode select

Timer/counter 2 source clock select

TC2S

Timer/counter 2 start control

Notel: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 2: When writing to the low-byte of timer register 2 (TREG2i), the comparison is inhibited until

Note 3: Set the mode and source clock when timer/counter stops (TC2S = 0). Note 4: Values to be loaded to the timer register must satisfy the following condition.

Note 5: "fc" can be selected as the source clock only in the timer mode during the SLOW mode. Note 6: TC2CR and TREG2 are write-only registers and must not be used with any of the read-

12 11 10

T,REG2h,(0017h)

4 3 2 1

TC2S

9 8

___^^_________

TC2CK, TC2M

7 6 5 4 3 2 1

_____^^________

T’^EG2l,(0016h)__^^

write only

(Initial value : **00 00*0)

_________

0 Timer/Event counter mode

1 Window mode

000 Internal clock

001 Internal clock

010 Internal clock

oil Internal clock

fc/2^^ or fs/2’=[Hz] fc/2’3 or fs/2= fc/2» fc/2^

100 Internal clock fc (Note 5)

101 Internal clock fs

110 Reserved

111

External clock (TC2 pin input)

Stop and counter clear

Start

the high-byte (TREG2h ) is written. After writing to the high-byte, any match during 1 m achine cycle (instruction execution cycle) is ignored.

TREG2 > 0(TREG2isfoii>0 when warm-up).

modify-write instructions.

Figure 2-24. Timer Register 2 and TC2 Control Register

Write

only

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TOSHIBA

TMP87CM24A/P24A

2.6.3 Function

The timer/counter 2 has three operating modes: timer, event counter and window modes. Also timer/counter 2 is used for warm-up when switching from SLOW mode to NORMAL2 mode.

(1) Timer Mode

In this mode, the internal clock is used for counting up. The contents of TREG2 are compared with the contents of up-counter. If a match is found, a timer/ counter 2 interrupt (INTTC2) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared. Also, when fc is selected as the source clock during SLOW mode, the lower 11 bits of TREG2 are

ignored and an INTTC2 interrupt is generated by matching the upper 5 bits. Thus, in this case, only the TREG2h setting is necessary.

Table 2-4. Source Clock (Internal Clock) for Timer/Counter 2

Source clock

NORMAL1/2,

DV7CK = 0

DLE1/2mode

DV7CK= 1 Atfc = 8MHz At fs = 32.768 kHz

SLOW mode SLEEP mode

fc/2^3[Hz] fs/2’=[Hz] fs/2’= [Hz] fs/2’= [Hz] fc/2’^ fs/2= fs/2= fs/2= 1.02 [ms] fc/2» fc/2» fc/2^ fc/2^

- -

fs fs

- -

fc (Note)

- - -

Resolution Maximum time setting

= 8MHz At fs = 32.768 kHz

Atfc

1.05 [s] 32 [/.s]

1 [a*s]

125 [ns]

1 [s] 1 [ms]

30.5 [jus]

19.1

[h]

1.1

[m]

2.1

[s]

65.5 [ms]

7.936 [ms]

18.2 [h] 1 [m]

2 [s]

Note : "fc" can be used only in the timer mode. This is used for warm up when switching from SLOW

mode to NORMAL2 mode.

Example : Sets the timer mode with source clock fc/23 [Hz] and generates an interrupt every 25ms

(at fc = 8 MHz).

LD (TC2CR), 000011008 LDW (TREG2),61A8H SET (EIRH).EF14

Sets the TC2 mode and source clock SetsTREG2(25ms^23/fc = 61A8h)

Enable INTTC2 El LD (TC2CR), 001011008

(2) Event Counter Mode

In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TREG2 are compared with the contents of the up-counter. If a match is found, an INTTC2 interrupt is generated, and the counter is cleared. The maximum frequency applied to the TC2 pin isfc/24 [Hz] in

; Starts TC2

NORMAL1/2 or IDLE1/2 mode, and fs/24 [Hz] in SLOW or SLEEP mode. But, a pulse width of 2 machine

cycles or more is required for both "H" and "L" level.

Example : Sets the event counter mode and generates an INTT2 interrupt 640 counts later.

LD (TC2CR), 000111008

; Sets the TC2 mode LDW (TREG2), 640 ; SetsTREG2 SET

(EIRH).EF14 ; Enable INTTC2 El LD

(TC2CR),001111008 ; Starts TC2

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TOSHIBA

(3) Window Mode

In this mode, counting up is performed on the rising edge of the pulse that is the logical AND-ed

product of the TC2 pin input (window pulse) and an internal clock. The internal clock is selected with TC2CK. The contents of TREG2 are compared with the contents of up-counter. If a match is found, an INTTC2 interrupt is generated, and the up-counter is cleared to "0". It is necessary that the maximum applied frequency (TC2 input) be such that the counter value can be analyzed by the

program. That is, the frequency must be considerably slower than the selected internal clock.

TC2 pin input

Internal clock

Example : Inputs "H" level pulse of 120 ms or more and generates interrupt. (atfc = 8 MHz).

LD (TC2CR), 00000101B ; Sets TC2 mode and source clock. LDW (TREG2), 0078H SET El LD

(EIRH).EF14

(TC2CR),00100101B ; Starts TC2

; SetsTREG2(120ms^2i3/fc = 0078H) ; Enables INTTC2 interrupt

TMP87CM24A/P24A

Up-counter

TREG2

INTTC2 interrupt

( n <

2.7 8-Bit Timer/Counter 3 (TC3)

2.7.1 Configuration

n-2

Figure 2-25. Window Mode Timing Chart

Match

Counter clear

Figure 2-26. Timer/Counter 3

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TOSHIBA

TMP87CM24A/P24A

2.7.2 Control

The timer/counter 3 is controlled by a timer/counter 3 control register (TC3CR) and two 8-bit timer

registers (TREG3A and TREG3B). Reset does not affect these timer registers.

TREG3A (0018h)

TREG3B

(0019h)

Read/Write Read only

TC3CR

(OOIAh)

TC3M

SCAP

TC3S

TC^CK TC3M

Timer/counter 3 0 : Timer/event counter operation mode set

1 : Capture

00 : Internal clock fc/2’^ or fs/2" [Hz]

TC3CK

Timer/counter 3 source clock select

01 : Internal clock fc/2’° or fs/2^

10 : Internal clock fc/2^ Write 11 : External clock (TC3 pin input)

TC3S

SCAP

Note 1 Note 2 Note 3

Note 4: Note 5:

Timer/counter 3 start select 1 : Start

Software capture control

fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz] *: Don't care Set the mode, the source clock and the edge selection (INT3ES) when the TC3 stops (TC3S = 0). Values to be loaded into timer register 3A must satisfy the following condition.

TREG3A > 0 (in the timer/event counter mode)

Software capture can be used in only timer and event counter mode. TC3CR is a write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc.

Figure 2-27. Timer Register 3A/3B and TC3 Control Register

0 : Stop and clear

0 :

1 : Software capture

2.7.3 Function

The timer/counter 3 has three operating modes : timer, event counter, and capture mode.

(1) Timer Mode

In this mode, the internal clock is used for counting up. The contents of TREG3A are compared with the contents of up-counter. If a match is found, a timer/counter 3 interrupt (INTTC3) is generated, and the up-counter is cleared. Counting up resumes after the up-counter is cleared. The current contents of up-counter are loaded into TREG3B by setting SCAP (bit 6 in TC3CR) to "1". SCAP is automatically cleared after capturing.

(Initial value : *0*0 00*0)

only

NORMAL1/2,

DV7CK = 0

fc/2’2 fc/2’° fs/2^ fc/2' fc/2'

Table 2-5. Source Clock (Internal Clock) for Timer Counter 3

Source clock

DLE1/2mode

DV7CK= 1

SLOW, SLEEP mode

fs/2^ [Hz] fs/2^ [Hz]

Resolution Maximum time setting

8MHz At fs = 32.768 kHz Atfc = 8MHz At fs = 32.768 kHz

Atfc =

512

pS 488.28 fxs 130.6 ms 124.5 ms

128 /xS

16 fxS

122.07 ixs

32.6 ms 31.1 ms

4.1 ms

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TOSHIBA

(2) Event Counter Mode

In this mode, the TC3 pin input pulses are used for counting up. Either the rising or falling edge can

be selected with INT3ES (bit 3 in EINTCR). The contents of TREG3A are compared with the contents of the up-counter. If a match is found, an INTTC3 interrupt is generated and the counter is cleared. The maximum applied frequency is fc/2^ [Hz] in the NORMAL1/2 or IDLE1/2 mode, and fs/2^ [Hz] in SLOW or SLEEP mode. Two or more machine cycles are required for both the "H" and "L" levels of the pulse width. The current contents of up-counter are loaded into TREG3B by setting SCAP (bit 6 in TC3CR) to "1". SCAP is automatically cleared after capturing.

(3) Capture Mode

The pulse width, period and duty of the TC3 pin input are measured in this mode, which can be used

in decoding the remote control signals, etc. The counter is free running by the internal clock. On the

rising (falling) edge of the TC3 pin input, the current contents of counter is loaded into TREG3A, then the up-counter is cleared and an INTTC3 interrupt is generated. On the falling (rising) edge of the TC3 pin input, the current contents of the counter is loaded into the TREG3B. In this case, counting continues. At the next rising (falling) edge of the TC3 pin input, the current contents of counter are

loaded into TREG3A, then the counter is cleared again and an interrupt is generated. If the counter overflows before the edge is detected, FFh issettotheTREG3Aand an overflow interrupt (INTTC3) is generated. During interrupt processing, it can be determined whether or not there is an overflow by checking whether or not the TREG3A value is overflow detection) is generated, capture and overflow detection are halted until TREG3A has been

read out; however, the counter continues. After TREG3A has been read out, capture and overflow detection are resumed, usually, TREG3B is

read out first.

Example : Generates an interrupt every 0.5 s, inputing 50Hz pulses to the TC3 pin.

LD (TC3CR), 00001100B LD (TREG3A), 19H LD (TC3CR), 00011100B

Sets TC3 mode and source clock

0.5 s^ 1/50 = 25= 19h Start TC3

FFh. Also, after an interrupt (capture to TREG3A, or

TMP87CM24A/P24A

Internal clock

Up-counter

TC3 pin input

TREG3A

TREG3B

INTTC3 interrupt Reading TREG3A

Ш1ЛЛДДЛЛДДЛЛЛЛДДЛЛЛЛГ

я я я

Figure 2-28. Timing Chart for Capture Mode (INT3ES = 0)

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TOSHIBA

2.8 8-Bit Timer/Counter 5 (TC5)

2.8.1 Configuration

2.8.2 Control

The TC5 is controlled by a timer/counter 5 control register (TC5CR) and an 8-bit timer register 5 (TREG5).

TMP87CM24A/P24A

Figure 2-29. Timer/Counter 5 (TC5)

TREG5 (001DH)

TC5CR (001 EH)

7 6

TC5S

TC5M

TC5CK

TC5S TC5 Start control

Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 2: The set value of timer register must satisfy the following conditions.

Note 3: Source clock fcl22, fcl2, and fc cannot be used except in PWM output mode. Note 4: Set the operating mode and the source clock selection when timer/counter stops (TC5S = 0).

TC5 Operating mode select

TC5 Source clock select

(a) When in PWM output mode, 5<TREG5<251 (b) When in any other mode than PW M output mode, 0< TREG5

4 3 2

TC5CK

_____1____1____

1 0

Write only

1 0

TC5M

_____1____

Timer mode

00 01 Reserved 10 Progrmmable divider output (PDO) mode 11 Pulse width modulation (PWM) output mode

000 Reserved

Internal clock fc/2ii or fs/23 [Hz]

001

Internal clock fc/27

010

Internal clock fc/23

oil

Internal clock fc/22

100

Internal clock fc/2

101

110 Internal clock fc

111

Reserved

0 Stop and clear

Start

(Initial **00 0000)

Write

only

Figure 2-30. Timer/Counter 5 Timer register. Control register

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TOSHIBA

2.8.3 Function

TC5 has 3 operating modes : timer, programmable divider output, and pulse width modulation output

mode.

(1) Timer mode

In this mode, the internal clock is used for counting up. The contents of the timer register 5 (TREG5)

is compared with the contents of the up-counter. Matching with TREG5 generates a timer/counter 5

interrupt (INTTC5) and clears the counter. Counting up resumes after the counter is cleared.

Table 2-6. Source Clock (Internal clock) for TC5

Source clock

NORMAL1/2,

DV7CK = 0

DLE1/2mode

DV7CK= 1 kHz kHz

SLOW, SLEEP mode

fc/2" [Hz] fs/2^ [Hz] fs/2^ [Hz] fc/2' fc/2' fc/2^ fc/2^

(2) Programmable divider output (PDO) mode

The internal clock is used for counting up. The contents of the TREG5 are compared with the contents of the up-counter. The timer F/F5 output is toggled and the counter is cleared each time a match is found. The timer F/F5 output is inverted and output to the PDO (P41) pin. In the case of

PDO output, set the P41 output latch to "1" and configure as an output with P4CR1. This mode can

be used for 50% duty pulse output. INTTC5 interrupt is generated each time the PDO output is toggled.

resolution maximum setting time

fc = 8MHz

256 [//s]

16 [/.S]

1 [//S]

fs = 32.768

244.14 [//s]

TMP87CM24A/P24A

fc = 8MHz

65.3 [ms] 62.3 [ms]

4.1 [ms]

255 [//s]

fs = 32.768

Example 1024 Hz pulse output (atfc = 4.194304 MHz)

Internal clock

PDOO pin

INTTC5 interrupt

SET (P4).1 P41 output latch<-1 LD (TC5CR), 0000101 OB LD

(TREG5), 10H

LD (TC5CR), 0010101 OB

Figure 2-31. PDO Mode Timing Chart

Sets to TC5 modes and source clock 1/1024^27fc^2 = IOh Starts TC5

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TOSHIBA

(3) Pulse width modulation (PWM) output mode

PWM output with a resolution of 8-bits is possible. The internal clock is used for counting up. The contents of the TREG5 is compared with the contents of the up-counter. If a match is found, the timer F/F5 output is toggled. The counter continues counting and, when an overflow occurs, the timer F/F5 is again toggled and the counter is cleared. The timer F/F5 output is inverted and output to the PWM (P41) pin. In the case of PWM output, set the P41 output latch to "1" and configure as an output with P4CR1. An INTTC5 interrupt is generated when an overflow occurs. TREG5 is configured a 2- stage shift register and, during output, will not switch until one output cycle

is completed even if TREG5 is overwritten; therefore, output can be altered continuously. Also, the first time, TREG5 is shifted by setting TC5S (bit 5 in TC5CR) to "1" after data are loaded toTREGS.

Note : PWM output mode can be used in only NORMAL 1/2 or IDLE 1/2 mode.

Internal clock

TMP87CM24A/P24A

PWM pin

INTTC5 interrupt

NORMAL1/2,

DV7CK = 0

Source clock

DLE1/2mode

DV7CK= 1

fc/2^ [Hz]

fc/2 fc 125 [ns]

At fc = 8MHz At fc = 4.194304 MHz At fc = 8MHz At fc = 4.194304 MHz

1 cycle

Figure 2-32. PWM Output Mode Timing Chart

Table 2-7. PWM Output Mode

Resolution

500 [ns] 250 [ns] 476.8 [ns] 64 [//s] 122 [^s]

953.7 [ns]

238.4 [ns]

128 [/.s] 244 [//s]

32 [^s]

Repeat cycle

61 i^s]

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TOSHIBA

TMP87CM24A/P24A

2.9 Serial Interface (SI01, SI02)

The TMP87CM24A/P24A each have two clocked-synchronous 8-bit serial interfaces (SI01 and SI02). Each serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. The serial interfaces are connected to external devices via pins P44 (SOI), P43 (SI1), P42 (SCK1) for SI01

and P47 (S02), P46 (SI2), P45 (SCK2) for SI02. The serial interface pins are also used as port P4. When used as serial interface pins, the output latches of these pins should be set to "1". In the transmit mode, pins P43 and P46 can be used as normal I/O ports, and in the receive mode, the pins P44 and P47 can be used as normal I/O ports.

2.9.1 Configuration

The SI01 and SI02 have the same configuration, except for the addresses/bit positions of the control/ status registers and buffer registers.

2.9.2 Control

The serial interfaces are controlled by SIO control registers (SI01CR1/SI01CR2 or SI02CR1/SI02CR2). The serial interface status can be determined by reading SIO status registers (SI01SR or SI02SR). The transmit and receive data buffer is controlled by the BUF (bits 2 to 0 in SI01CR2/SI02CR2). The data

buffer is assigned to addresses OFFOh to 0FF7h for SI01 or 0FF8h to OFFFh for SI02 in the DBR area, and

can continuously transfer up to 8 words (bytes or nibbles) at one time. When the specified number of words has been transferred, a buffer empty (in the transmit mode) or a buffer full (in the receive mode or transmit/receive mode) interrupt (INTSI01 or INTSI02) is generated. When the internal clock is used as the serial clock in the 8-bit receive mode and the 8-bit transmit/receive

mode, a fixed interval wait can be applied to the serial clock for each word transferred. Four different wait times can be selected with WAIT (bits 4 and 3 in SI01CR2/SI02CR2).

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TOSHIBA

SI01, SI02 Control Registers 1

7 6 5 4

SI01CR1

(0020h)

SI02CR1

(0022h)

SIOS

INH

SIOS Indicate transfer start/stop

SIOINH Conti nue/abort transfer

SIOM

SCK

Note 1 Note 2 Note3

TMP87CM24A/P24A

SIO

,SIOM ,

____

________

(Initial value : 0000 0000)

0 : Stop 1 : Start

0 : Continue transfer 1 : Abort transfer (automatically cleared after abort)

000 : 8-bit transmit mode 010 : 4-bit transmit mode

Transfer mode select

100 : 8-bit transmit/receive mode 101 : 8-bit receive mode 110: 4-bit receive mode

000 : Internal clock fc/2’^ or fs/2= [Hz] 001 : Internal clock fc/2® L /Output on\

Serial clock select

010 : Internal clock fc/2® j \SCKpin / 011 : Internal clock fc/2^ 111 : External clock (input from SCK pin)

fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz]

Set SIOS to "0" and SIOINH to "1" when setting the transfer mode or serial clock. SI01CR/SI02CR1 are write-only registers and must not be used with any of read-modify-write instructions such as bit operate, etc.

Write

only

SI01, SI02 Status Registers

SlOF

SEF

6 5

Serial transfer operating status monitor

Shift operating status monitor

SI01SR

(0020h)

SI02SR

(0022h)

SI01, SI02 Control Registers 2

SI01CR2 7 6 5 4

(0021h)

SI02CR2

SlOF SEF "1" "1" "1" "1" "1"

(0023h)

WAIT

BUF

Wait control

Number of transfer words

WAIT

____I____

2 1

"1" ;

0 : Transfer terminated ( After SIOS is cleared to "0",SIOFis\

. _ X ■ 1 cleared to "0" atthe termination 1

1 : Transfer in process \ of transfer orsettlnq of sioinh. / 0 : Shift operation terminated

Read

only

1 : Shift operation in process

BUF

________

(Initial value: ***0 0000)

Always sets "00" except 8-bit transmit/receive mode.

00 : Tf =Td (non-wait) 01 : Tf =2Td -I 10:Tf=4To (wait) 11 : Tf = 8Td -1

000 : 1 word transfer 001 : 2 words transfer 010 : 3 words transfer 011 : 4 words transfer 100 : 5 words transfer 101 : 6 words transfer 110:7 words transfer 111:8 words transfer

Buffer address used

SI01

SI02

OFFOh 0FF8h

OFFO toOFFlH 0FF8 toOFF9n OFFO toOFF2H 0FF8 toOFFAn OFFO toOFF3H OFFO to0FF4H OFFO toOFFSH OFFO toOFF6H

0FF8 toOFFBn 0FF8 toOFFCn 0FF8 toOFFDn 0FF8 toOFFEn

OFFO toOFF7H 0FF8 toOFFFn

Write

only

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TOSHIBA

TMP87CM24A/P24A

Motel: Tf frame time, Tq: data transfer time

^pin Un_Jn_Jn_Jn_n_nLnLr

Note 2:

Note 3:

Note 4: Note 5: Note 6:

Note 7:

The lower 4 bits of each buffer are used during 4-bit transfers. Zeros (0) are stored to the upper 4bits when receiving. Transmitting starts at the lowest address. Received data are also stored starting from the lowest address to the highest address. For example, in the case of SI01, the first buffer address transmitted is

OFFOh.

The value to be loaded to BUF is held after transfer is completed. SI01CR2/SI02CR2 must be set when the serial interface is stopped (SlOF = 0). SI01CR2/SI02CR2 are write-only registers, which cannot access any of read-modify-write instructions such as bit operate, etc. *: Don't care

Figure 2-34. SIO Control Registers and Status Registers

(1) Serial Clock

a. Clock Source

SCK (bits 2 to 0 in SI01CR1/SI02CR1) is able to select the following:

Any of four frequencies can be selected. The serial clock is output to the outside on the SCK1/SCK2 pin. The SCK pin goes high when transfer starts. When data writing (in the transmit mode) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wait function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed.

ULT

Table 2-8. Serial Clock Rate

Serial clock

NORMAL1/2,

DV7CK = 0

DLE1/2mode

DV7CK= 1

SLOW, SLEEP mode

fc/2’^ [Hz] fs/2= [Hz] fs/2= [Hz] fc/2» fc/2» fc/2® fc/2® fc/2= fc/2=

3-24-84

Maximum transfer rate

Atfc = 8MHz At fs = 32.768 kHz

0.954 kbit/s 1 kbit/s

30.5 122 244

Note: 1 Kbit = 1024 bit

2002-10-03

TOSHIBA

b.Shift edge

TMP87CM24A/P24A

External Clock An external clock connected to the SCK1/SCK2 pin is used as the serial clock. In this case, the P42 (SCK1)/P45 (SCK2)output latch must be set to "1To ensure shifting, a pulse width of at least 4 machine cycles is required. Thus, the maximum transfer speed is 244K-bit/s. (at fc = 8 MHz).

SCK pin input

tsCKL tsCKH

tscKL. tscKH > 4 tcyc

The leading edge is used to transmit, and the trailing edge is used to receive.

Note : tcyc = 4/fc (In NORAML1/2, IDLE1/2 modes)

___________

4/fs (In SLOW, SLEEP modes)

__________

Transmitted data are shifted on the leading edge of the serial clock (falling edge of the SCK pin input/output).

@ Trailing Edge

Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK pin input/output).

SCK pin

SO pin

Shift register

SCK pin

SI pin

Shift register

(2) Number of Bits to Transfer

Either 4-bit or 8-bit serial transfer can be selected. When 4-bit serial transfer is selected, only the

lower 4 bits of the transmit/receive data buffer register are used. The upper 4 bits are cleared to "0" when receiving. The data is transferred in sequence starting at the least significant bit (LSB).

I I

___

!\ BitO X Bit1 X Bit 2 X Bits

~X 3210 X *321 X **32 X

(a) Leading Edge

f I

___

Y BitO X Bit2 X Bits

I I

___

f I

___

I I

f I

___

Y 0*** X~ 10** ^ 210* DChÌ£

(b) Trailing Edge

Figure 2-36. Shift Edge

*: Don't care

3-24-85 2002-10-03

TOSHIBA

(3) Number of Words to Transfer

Up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be transferred continuously. The number of words to be transferred is loaded to BUF. An INTSIO interrupt is generated when the specified number of words has been transferred. If the number of words is to be changed during transfer, the serial interface must be stopped before making the change. The number of words can be changed during automatic-wait operation of an

internal clock. In this case, the serial interface is not required to be stopped.

TMP87CM24A/P24A

2.9.3 Transfer Mode

SIOM (bits 5 to 3 in SI01CR1/SI02CR1) is used to select the transmit, receive, ortransmit/receive mode.

(1) 4-Bit and 8-Bit Transmit Modes

In these modes, the SI01CR1/SI02CR1 is set to the transmit mode and then the data to be transmitted first are written to the data buffer registers (DBR). After the data are written, the transmission is started by setting SIOS to "1". The data are then output sequentially to the SO pin in synchronous with the serial clock, starting with the least significant bit (LSB). As soon as the LSB has

been output, the data are transferred from the data buffer register to the shift register. When the final data bit has been transferred and the data buffer register is empty, an INTSIO (buffer empty)

interrupt is generated to request the next transmitted data. When the internal clock is used, the serial clock will stop and an automatic-wait will be initiated if the next transmitted data are not loaded to the data buffer register by the time the number of data words specified with the BUF has been transmitted. Writing even one word of data cancels the automatic-wait; therefore, when transmitting two or more words, always write the next word

before transmission of the previous word is completed.

Note: Automatic-waits are also canceled by writing to a DBR not being used as a transmit data

buffer register; therefore, during SIO do not use such DBR for other applications. For example, when 3 words are transmitted, do not use the DBR of the remained 5 words.

3-24-86

2002-10-03

TOSHIBA

When an external clock is used, the data must be written to the data buffer register before shifting next data. Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service

program. When the transmit is started, after the SlOF goes "high" output from the SO pin holds final bit of the

last data until falling edge of the SCK.

If it is necessary to change the number of words, SIOS should be cleared to "0", then BUF must be

rewritten after confirming that SlOF has been cleared to "0". That the transmission has ended can

be determined from the status of SlOF (bit 7 in SI01SR/SI02SR) because SlOF is cleared to "0" when a transfer is completed. When SIOINH is set, the transmission is immediately ended and SlOF is cleared

0".

to " The transmission is ended by clearing SIOS to "0" or setting SIOINH to "1" in buffer empty interrupt service program. When an external clock is used, it is also necessary to clear SIOS to "0" before shifting the next data; otherwise, dummy data will be transmitted and the operation will end.

TMP87CM24A/P24A

■ Clear SIOS.

SIOS

SlOF

SEF

SCK pin (output)

SO pin

INTSIO interrupt

DBR

SIOS

SlOF

SEF

SCK pin (output)

SO pin

INTSIO interrupt

DBR

Ib.^

____

________________________

_____

t t

Write Write

(a) (b)

(a) Internal Clock

■Clear SIOS

i_r

\ aoXai X a2A asXanX asX asX ayX boXbiXb2X bsXbnX bsXbsXby/

_______________________________n_____________________________________

]di

t t

Write Write

(a) (b)

(b) External Clock

Figure 2-38. Transfer Mode (Example: 8-Bit, 1 Word Transfer)

3-24-87

2002-10-03

TOSHIBA

SCK pin

TMP87CM24A/P24A

SlOF

SO pin Bite

Figure 2-39. Transmitted Data Hold Time at End of Transmit

Bit?

tsoDH =min 3.5/fc [s] (In the NORMAL1/2, IDLE1/2 modes)

= min 3.5/fs [s] (In the SLOW, SLEEP modes)

(2) 4-Bit and 8-Bit Receive Modes

After setting the control registers to the receive mode, set SIOS to "1" to enable receiving. The data are then transferred to the shift register via the SI pin in synchronous with the serial clock. When one word of data has been received, it is transferred from the shift register to the data buffer register (DBR). When the number of words specified with the BUF has been received, an INTSIO (buffer full)

interrupt is generated to request that these data be read out. The data are then read from the data

buffer registers by the interrupt service program. When the internal clock is used, and the previous data are not read from the data buffer register

before the next data are received, the serial clock will stop and an automatic-wait will be initiated

until the data are read. A wait will not be initiated if even one data word has been read.

Note: Waits are also canceled by reading a DBR not being used as a received data buffer register

is read; therefore, during SIO do not use such DBR for other applications.

When an external clock is used, the shift operation is synchronized with the external clock; therefore, the previous data are read before the next data are transferred to the data buffer

buffer register and the receiving of any more data will be canceled. When an external clock is used, the maximum transfer speed is determined by the delay between the time when the interrupt

request is generated and when the data received have been read. The receiving is ended by clearing SIOS to "0" or setting SIOINH to "1" in buffer full interrupt service

program. When SIOINH is set, the receiving is immediately ended and SlOF is cleared to "0". When SIOS is cleared, the current data are transferred to the buffer in 4-bit or 8-bit blocks. The

receiving mode ends when the transfer is completed. SlOF is cleared to "0" when receiving is ended and thus can be sensed by program to confirm that receiving has ended.

If it is necessary to change the number of words in external clock operation, SIOS should be cleared to "0" then BUF must be rewritten after confirming that SlOF has been cleared to "0".

If it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of data receive, BUF must be rewritten before the received data is

read out.

Note: The buffer contents are lost when the transfer mode is switched. If it should become

necessary to switch the transfer mode, end receiving by clearing SIOS to "0", read the last data and then switch the transfer mode.

3-24-88 2002-10-03

TOSHIBA

(3) 8-bit Transmit/Receive Mode

After setting the control registers to the 8-bit transmit/receive mode, write the data to be transmitted first to the data buffer registers (DBR). After that, enable transceiving by setting SlOSto

"1When transmitting, the data are output from the SO pin at leading edges of the serial clock. When receiving, the data are input to the SI pin at the trailing edges of the serial clock. 8-bit data are transferred from the shift register to the data buffer register. An INTSIO interrupt is generated when the number of data words specified with the BUF has been transferred. The interrupt service

program reads the received data from the data buffer register and then writes the data to be transmitted. The data buffer register is used for both transmitting and receiving; therefore, always write the data to be transmitted after reading the received data. When the internal clock is used, a wait is initiated until the received data are read and the next data are written. A wait will not be initiated if even one data word has been written.

TMP87CM24A/P24A

Note: The wait is also canceld by writing to a DBR not being used as a transmit data buffer

When an external clock is used, the shift operation is synchronized with the external clock; therefore, it is necessary to read the received data and write the data to be transmitted next before starting the next shift operation. When an external clock is used, the transfer speed is determined by the maximum delay between generation of an interrupt request and the received data are read and the data to be transmitted next are written. When the receive is started, after the SlOF goes "high"output from the SO pin holds final bit of the

last data until falling edge of the SCK. The transmit/receive operation is ended by clearing SlOSto "0" or setting SIOINH to "1" in interrupt service program. When SIOS is cleared, the current data are transferred to the data buffer register in 8-bit blocks. The transmit mode ends when the transfer is completed SlOF is cleared to "0" when receiving is ended and thus can be sensed by program to confirm that receiving has ended. When SIOINH is set, the transmit/receive operation is immediately ended and SlOF is cleared to "0".

If it is necessary to change the number of words in external clock operation, SIOS should be cleared to "0", then BUF must be rewritten after confirming that Siof has been cleared to "0".

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TOSHIBA

If it is necessary to change the number of words in internal clock, during automatic-wait operation which occurs after completion of transmit/receive operation, BUF must be rewritten before reading and writing of the receive/transmitdata.

Note: The buffer contents are lost when the transfer mode is switched. If it should become

SIOS

SlOF

SEF

SCK pin output

50 pin

51 pin

TMP87CM24A/P24A

necessary to switch the transfer mode, end receiving by clearing SIOS to "0", read the last data and then switch the transfer mode.

Clear SIOS

INTSIO interrupt

DBR

Figure 2-41. Transmit/Receive Mode (Example : 8-bit, Iword, internal clock)

XIX

Write (a)

SCK pin

SlOF

SO pin

Figure 2-42. Transmitted Data Hold Time at End of Transmit/Receive

Bite

tsoDH = min 4/fc [s] (In the NORMAL1/2, IDLE1/2 modes)

Read out (c) Write (b)

Bit?

= min 4/fs [s] (In the SLOW, SLEEPmodes)

Read out (d)

tsODH

3-24-90 2002-10-03

TOSHIBA TMP87CM24A/P24A

2.10 LCD Driver

The TMP87CM24A/P24A each have a driver and control circuit to directly drive the liquid crystal device

(LCD). The pins to be connected to LCD are as follows:

(3) Common output port 4 pins (COMB to COMO)

In addition, CO, Cl, VI, V2, V3 pin are provided forthe LCD driver's booster circuit.

The devices that can be directly driven is selectable from LCD of the following drive methods:

® 1/4Duty (1/3 Bias) LCD........................................... Max 160 Segments (8-segment x 20 digits)

(2) 1/3 Duty (1/3 Bias) LCD........................................... Max 120 Segments(8-segmentx 15digits)

(3) 1/2 Duty (1/3 Bias) LCD........................................... Max 80 Segments (8-segmentx 10 digits)

@ Static LCD ........................................................................ Max40 Segments (8-segmentx 5 digits)

2.10.1 Configuration

LCDCR

3 2 10

CO Cl VI V2 V3 COMO to COM3

SEGO to SEG11SEG12to SEG39

Figure 2-43. LCD Driver

3-24-91

2002-10-03

TOSHIBA

TMP87CM24A/P24A

2.10.2 Control

The LCD driver is controlled using the LCD control register (LCDCR). The LCD driver's display is enabled

using the EDSP. Immediately after return from reset or standby, it takes maximum 1 s (Торг =-10 °C)

(fc = 8 MHz, SLFR :00h) for the LCD driver's booster circuit to boost up to the specified voltage. If the display is enabled before the specified voltage is reached, the voltage may not be boosted properly due to load on the SEG/COM.

LCDCR

(0028h )

6 5

EDSP

DUTY Selection of

Note 1: fc: High-frequency clock, fs: Low-frequency clock Note 2: The LCDCR is a write-only register. It can not be operated by the read-modify-write

SLfR

SLF Selection of LCD

frame frequency

driving methods

SLFR Selection of boost

frequency

EDP

LCD Display Control

instruction (Bit manipulation instructions of SET, CLR, etc. and Arithmetic instructions of AND, OR, etc.)

4 3 2

____

________

00 : fc/2^^ or fs/2^ [Hz] 01 : fc/2^^ or fs/2^

10 : fc/2^5 11 : fc/2^3

000:1/4 Duty (1/3 Bias) 001:1/3 Duty (1/3 Bias) 010: Reserved 011:1/2 Duty (1/3 Bias)

100: Static 101: Reserved 11*: Reserved

00 : fc/2^3 or fs/2^ [Hz] 01 : fc/2" or fs/2^

10 : fc/2^° or fs/2^ 11 : fc/29

0 : Blanking

1 : Enables LCD display (Blanking is released)

Figure 2-44. LCD Driver Control Register

___

1 0

_____

(Initial value : 0000 0000)

Write

only

3-24-92

2002-10-03

TOSHIBA

(1) LCD driving methods

As for LCD driving method, 4 types can be selected by DUTY (bit 4 to bit 2 of LCDCR). The driving method is initialized in the initial program according to the LCD used.

TMP87CM24A/P24A

VlCD3 —

- V| —

VlCD3 ~

- Vi —

0 -

h I—'

0 -■

L □

data"1" data "0"

1 1/fp n

r —11—1 n

u U 1

data "1" data "0"

(a) 1/4 Duty (1/3 Bias)

1/fp -

_______________________________

Note: fp: Frame frequency Vlcd3- ¿CD drive voltage

Figure 2-45. LCD Drive Waveform (COM - SEG pins)

_____________

Vlcd3 -

0 --

- V| —

1/fp

u J^JITL

data"1" data "0" —

(b) 1/3 Duty (1/3 Bias)

Vlcd3 ~

1/fp ^1

0 --

-VlCD3 ~

I"*

-----

data "1"

----------

— data "0"

--------------

*"l

(d) Static

3-24-93 2002-10-03

TOSHIBA

(2) Frame frequency

Frame frequency (fp) is set according to driving method and base frequency as shown in the following Table 2-9. The base frequency is selected by SLF (bit 1 and 0 of LCDCR) according to the frequency fc and fs of the basic clock to be used.

(a) At the single clock mode. At the dual clock mode (DV7CK = 0).

TMP87CM24A/P24A

Table 2-9. Setting of LCD Frame Frequency

SLF

Base frequency [Hz]

1/4 Duty 1/3 Duty 1/2 Duty Static

fc fc

217 217

(fc = 8MHz)

61 81

fc fc 4 fc 4 fc fc

2i6 216

(fc = 4MHz)

fc fc 4 fc 4 fc fc

215 215

(fc = 4MHz)

122

fc fc 4 fc 4 fc fc

Note: fc: High-frequency clock [Hz]

(b) At the dual clock mode (DV7CK = 1 or SYSCK = 1)

SLF

2i3 2i3

(fc= 1 MHz)

Base frequency [Hz]

122

1/4 Duty 1/3 Duty 1/2 Duty Static

Frame frequency [Hz]

4 . fc 4 . fc

122

2 2

122

2^7

2^9

3 2^7

3 2^^ 81

3 2^9

162 244

3 2^9

2^9

162 244

Frame frequency [Hz]

217

216

215

122

219

122

(fs = 32.768 kHz) 64

(fs = 32.768 kHz)

Note: fs: Low-frequency clock [Hz]

128

3-24-94

4 . _fs_ 3 29

85 128

4 ^ fs

3 2^

171

4 . _fs_

4 , _fs_

256 128

29 64

2002-10-03

TOSHIBA

(3) Booster circuit for LCD driver

The TMP87CM24A/P24A incorporate a booster circuit for the LCD driver (IV x 3 times) so that the

LCD display does not flicker due to fluctuations in the power supply voltage.

The booster circuit boosts the output voltage for the segment/common signal by double (VLCD2) and triple (VLCD3) in relation to the on-chip output voltage (1V typ).

Figure 2-46 shows an example of a booster circuit for the LCD driver. It takes to maximum 1 s

(Topr= -10°C) for the booster circuit to reach the specified voltage at return from reset or standby. If the LCD circuit is enabled before the specified voltage is reached boosting takes longer. The reference frequency of the booster circuit at initialization is 1 kHz. Selecting the frequency

using the SLFR in the command register (LCDCR) raises the drive capability of segment/common. Table 2-10 shows the reference frequency of the booster circuit.

TMP87CM24A/P24A

V3 V2 VI

TMP87CM24A/P24A

SLFR

Boosting frequency

fc/213 orfs/25

fc/211 or fs/23

fc/210 or fs/24

fc/29

Figure 2-46. Example of a Booster Circuit

Table 2-10. Reference Frequency of the Booster Circuit

Frequency

fc/213 orfs/25

fc/211 orfs/23 fc/210 orfs/22

fc/29

Table 2-11. Selection of V3 Boosting Frequency

fc = 8 MHz fs = 32.768 kHz

0.98 kHz 1.02 kHz

3.91 kHz 4.09 kHz

7.81 kHz

15.63 kHz —

fc = 8MHz fc = 4MHz fc = 32.768 MHz

40 ms 80 ms 40 ms 10 ms 20 ms 10 ms

5 ms 10 ms 5 ms

2.5 ms 5 ms

C = 0.1 to0.47//F

8.19 kHz

—

Л/oie 7; Торг = 25 X, 0.1 juF^ 0.47juF

Note 2: V3 booting time at VDD is stable.

3-24-95 2002-10-03

TOSHIBA

Figure 2-47. Temperature Characteristics of Voltage Booster Output

Notice of using LCD driver

(1) The falling time and fluctuation of power supply voltage.

When LCD driver is used with the following condition, LCD may not be displayed temporarily,

because the V1/V2/V3 pins output will be unstable by stopping of LCD booster circuit.

Therefore, please take an enough time by software, before enabling LCD.

TMP87CM24A/P24A

Та

a) When the falling time of power supply voltage is shorter than 1 ms, within an operating voltage,

(at 2.2V to 5.5V, Торг = -10 to 70c)

b) When the fluctuation of power supply within 1 ms is bigger than 0.7V.

(2) Powerdown of an instant.

When power supply voltage falls out of operating voltage and then rises within operating voltage, the maximum period that the V1/V2/V3 pins output will resume is 1 s. (Торг = - 10 °C). Therefore,

please take an enough time by software, before enabling LCD

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2002-10-03

TOSHIBA

2.10.3 LCD Display Operation

(1) Display data setting

Display data is stored to the display data area (assigned to address 0F80 to 0F93h) in the DBR. The display data which are stored in the display data area is automatically read out and sent to the LCD driver by the hardware. The LCD driver generates the segment signal and common signal according to the display data and driving method. Therefore, display patterns can be changed by only over writing the contents of display data area by the program. Figure 2-48 shows the correspondence

between the display data area and SEG/COM pins.

LCD light when display data is "1" and turn off when "0". According to the driving method of LCD, the number of pixels which can be driven becomes different, and the number of bits in the display data area which is used to store display data also becomes different. Therefore, the bits which are not used to store display data as well as the data buffer which corresponds to the addresses not connected to LCD can be used to store general user process data (see Table 2-12.)

TMP87CM24A/P24A

Address

0F80h

82 83

8A 88

8D 8E 8F

Bit 7 Bits Bits Bit 4

1 1 1

SEG1

SEG3 SEG5 SEG7 SEG9 SEG8

SEG11 SEG10

SEG13 SEG15 SEG17 SEG19 SEG18

SEG21

SEG23 SEG25 SEG27 SEG29 SEG28

SEG31 SEG30

Bits Bit 2 Biti Bito

90 SEG33 91 SEG35

92 SEG37

93 , SEG39 , , SEG38 ,

COM3 COM2 COMI COMO COM3 COM2 COMI COMO

Figure 2-48. LCD Display Data Area (DBR)

(2) Blanking

Blanking is enabled when EDSP is cleared to "0".

Blanking turns off LCD through outputting a non-selective level to COM pin. A signal level is continuously output to SEG pin according to display data and driving method. For static drive, lightsout by data (clearing display data to "0") does not apply any voltage between pins COM and SEG. On the other hand, lights-out by blanking makes the output to COM pin at a non-selective level, so that the part between pins COM and SEG becomes in the state driven by non-selective level.

1 1 1

SEGO

SEG2 SEG4 SEG6

SEG12 SEG14 SEG16

SEG20 SEG22 SEG24 SEG26

SEG32 SEG34 SEG36

Table 2-12. Driving Method and Bit for Display Data

Driving methods

1/4 Duty COM3 1/3 Duty 1/2 Duty

Static

Note: This bit is not used for display data

Bit 7/3 Bit 6/2 Bit 5/1 Bit 4/0

COM2 COMI

- - COMI

- - -

COMO COMO COMO COMO

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2002-10-03

TOSHIBA

2.10.4 Control Method of LCD Driver

(1) Initial setting

Figure 2-49 shows the flowchart of initialization.

Example : To operate a 1/4 duty LCD of 40 segments x 4 com-mons

at frame frequency fc/2i6 [Hz]

TMP87CM24A/P24A

LD (LCDCR),00000001B

(2) Store of display data

Generally, display data are prepared as fixed data in program memory and stored in display data area by load command.

Example 1 : To display using 1/4 duty LCD a numerical value which corresponds to the LCD data

TABLE

SNEXT:

(P6CR),0FFH

(LCDCR),10000001B

stored in data memory at address 80h (when pins COM and SEG are connected to

LCD as in Figure 2-50), display data become as shown in Table 2-12.

LD A, (BOH) ADD A,TABLE-$-5 LD HL,0F80H LD (HL),(PC + A) JRS T,SNEXT DB 11011111B, 00000110B,

11100011B, 10100111B,

00110110B, 10110101B,

11110101B, 00010111B, 11110111B, 10110111B

; Sets LCD driving method and

frame frequency.

Boost frequency

; Sets P6 port as segment

output.

; Sets the initial value of

display data.

; Display enable

Figure 2-50. Example of COM, SEG

Figure 2-49. Initial Setting

of LCD Driver

Pin Connection (1/4 Duty)

Note : DB is a byte data difinition instruction.

3-24-98 2002-10-03

TOSHIBA

TMP87CM24A/P24A

Table 2-13. Example of Display Data (1/4 Duty)

No.

3 10100111 8 11110111

Example 2 : Table 2-14 shows an example of display data which are displayed using 1/2 duty LCD

display display data

6 l

in the same way as Table 2-13. The connection between pins COM and SEG are the same as shown in Figure 2-51.

11011111 5 10110101

00000110 6 11110101

11100011

00110110 9 10110111

No.

display display data

00000111

Table 2-14. Example of Display Data (1/2 Duty)

Number

0 **01**11 1 2 3 **10**10 **01**11 8 4 **11**10

Note: *: Don't care

High order address Low order address High order address Low order address

**00**10 **00**10 6

**10**01

Display data

**01**11

**01**11 7

**00**10 9

3-24-99

Number

Display data

**11**10 **11**11

**01**10 **00**11 **11**11

**11**10

**01**01 **01**01

**01**11 **01**11

2002-10-03

O O

SEG2

Display data area

Address

*111*010

OF80h

0F81

**01

*: Don't care

SEG1 SEGO

COMO

COMI

COM2"

SEG1

SEG2

(/)

COMO COMI

COM2

l_r

Ú I

~ Vlcd3

— 0

~ VlcD3

— 0

~ Vlcd3

— 0

“ Vlcd3

— 0

~ VlcD3

— 0

“ VlcD3

L 0

■D_ fD o

1“

n Q

<’ fD

c r+

N> O O N>

O W

COMO-SEG1

(Selected) _r

COM1-SEG2

(Non—Selected)

Figure 2-53. 1/3 Duty (1/3 Bias) Drive

Ir^

1__r~L

■“ Vlcd3

— 0

— ~Vlcd3

— V|_cD3

“Vlcd3

■o

N> > N>

Toshiba TMP87CP24AF User Manual

Specifications and Main Features

Frequently Asked Questions

User Manual

Features

Block Diagram

Pin Functions

1.1 Memory Address Map

1.2 Program Memory (ROM)

1.3 Program Counter (PC)

ХЗЗЕОСЗЕПС

1.4 Data Memory (RAM)

1.5 General-purpose Register Banks

1.6 Program Status Word (PSW)

1.6.1 Register Bank Selector (RBS)

1.6.2 Flags

1.7 Stack and Stack Pointer

1.7.1 Stack

1.7.2 Stack Pointer (SP)

1.8 System Clock Controller

1.8.1 Clock Generator

1.8.2 Timing Generator

1.8.3 Stand-by Controller

1.8.4 Operating Mode Control

iJHJHJijnjijnjnjnjnjnjnjijnjnjnjx

1.9 Interrupt Controller

1.9.1 Interrupt Sequence

"Z)C

DOGXHOC

)OOC )OEK

1.9.2 Software Interrupt (INTSW)

1.9.3 External Interrupts

1.10 Watchdog Timer (WDT)

1.10.1 Watchdog Timer Configuration

1.10.2 Watchdog Timer Control

1.10.3 Watchdog Timer Interrupt (INTWDT)

1.10.4 Watchdog Timer Reset

1.11 Reset Circuit

1.11.1 External Reset Input

1.11.2 Address-Trap-Reset

1.11.3 Watchdog Timer Reset

1.11.4 System-Clock-Reset

2. Peripheral Hardware Functions

2.1 Special Function Registers (SFR) and Data Buffer Registers (DBR)

2.2 I/O Ports

2.2.1 Port PO (P07 to POO)

2.2.2 PortPI (P17to P10)

2.2.3 Port P2 (P22 to P20)

2.2.4 Port P3 (P35 to P30)

2.2.5 Port P4 (P47 to P40)

2.2.6 Port P5 (P57 to P50)

2.2.7 Ports P6 (P67 to P60) Port P7 (P77 to P70) Port P8 (P87 to P80) Port P9 (P93 to P90)

2.3 Time Base Timer (TBT)

2.4 Divider Output (DVO)

2.5.2 Control

2.5.3 Function

I)GZ)GZ)C2:XiZ)GZn^XHXZDGZ)(

JUlTLJinnAriJ^^

2.6 16-Bit Timer/Counter 2 (TC2)

2.6.1 Configuration

2.6.2 Control

2.6.3 Function

2.7 8-Bit Timer/Counter 3 (TC3)

2.7.1 Configuration

2.7.2 Control

2.7.3 Function

Ш1ЛЛДДЛЛДДЛЛЛЛДДЛЛЛЛГ

2.8 8-Bit Timer/Counter 5 (TC5)

2.8.1 Configuration

2.8.2 Control

2.8.3 Function

2.9 Serial Interface (SI01, SI02)

2.9.1 Configuration

2.9.2 Control

2.9.3 Transfer Mode

2.10 LCD Driver

2.10.1 Configuration

2.10.2 Control

2.10.3 LCD Display Operation

2.10.4 Control Method of LCD Driver