TC74AC166P/F/FN
TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic
TC74AC166P,TC74AC166F,TC74AC166FN
8-Bit Shift Register (P-IN, S-OUT)
The TC74AC166 is an advanced high speed CMOS 8-BIT
PARALLEL/SERIAL-IN, SERIAL-OUT SHIFT REGISTER
fabricated with silicon gate and double-layer metal wiring
2
C
MOS technology.
It achieves the high speed operation similar to equivalent
Bipolar Schottky TTL while maintaining the CMOS low power
dissipation.
It consists of parallel-in or serial-in, serial-out 8-bit shift
register with a gated clock input and an overriding clear input.
The parallel-in or serial-in modes are controlled by the
SHIFT/
high, the serial data input is enabled and the eight flip-flops
perform serial shifting on each clock pulse. When held low, the
parallel data inputs are enabled and synchronous loading occurs
on the next clock pulse. Clocking is accomplished on the
low-to-high transition of the clock pulse. The CLOCK-INHIBIT
input should be shifted high only while the CLOCK input is held
high. A direct clear input overrides all other inputs, including the
clock, and sets all the flip-flops to zero. Functional details are
shown in the truth table and the timing charts.
discharge or transient excess voltage.
LOAD
input. When the SHIFT/
All inputs are equipped with protection circuits against static
LOAD
input is held
Features
Note: xxxFN (JEDEC SOP) is not available in
Japan.
TC74AC166P
TC74AC166F
TC74AC166FN
• High speed: f
• Low power dissipation: I
• High noise immunity: V
• Symmetrical output impedance: |I
Capability of driving 50 Ω
transmission lines.
• Balanced propagation delays: t
• Wide operating voltage range: V
• Pin and function compatible with 74HC166
= 170 MHz (typ.) at VCC = 5 V
max
= 8 μA (max) at Ta = 25°C
CC
NIH
= V
= 28% VCC (min)
NIL
| = IOL = 24 mA (min)
OH
∼
t
−
pLH
pHL
(opr) = 2 to 5.5 V
CC
Pin Assignment
Weight
DIP16-P-300-2.54A : 1.00 g (typ.)
SOP16-P-300-1.27A : 0.18 g (typ.)
SOL16-P-150-1.27 : 0.13 g (typ.)
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IEC Logic Symbol
TC74AC166P/F/FN
Truth Table
Inputs
CLR
L X X X X X L L L
H X X X X No Change
H L L X a･･････h a b h
H H L H X H QAn QGn
H H L L X L QAn QGn
H X H X X X No Change
LOAD
SHIFT/
CK INH.
CK
SERIAL
IN
PARALLEL
･･････H
A
X: Don’t care
a･･････h: The level of steady state input voltage at inputs A through H respectively
Internal
Output
QA QB QH
Output
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Timing Chart
TC74AC166P/F/FN
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System Diagram
TC74AC166P/F/FN
Absolute Maximum Ratings (Note 1)
Characteristics Symbol Rating Unit
Supply voltage range VCC −0.5 to 7.0 V
DC input voltage VIN −0.5 to VCC + 0.5 V
DC output voltage V
Input diode current IIK ±20 mA
Output diode current IOK ±50 mA
DC output current I
DC VCC/ground current ICC ±100 mA
Power dissipation PD 500 (DIP) (Note 2)/180 (SOP) mW
Storage temperature T
Note 1: Exceeding any of the absolute maximum ratings, even briefly, lead to deterioration in IC performance or
even destruction.
Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the
significant change in temperature, etc.) may cause this product to decrease in the reliability significantly
even if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute
maximum ratings and the operating ranges.
Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook
(“Handling Precautions”/Derating Concept and Methods) and individual reliability data (i.e. reliability test
report and estimated failure rate, etc).
Note 2: 500 mW in the range of Ta = −40 to 65°C. From Ta = 65 to 85°C a derating factor of −10 mW/°C should be
applied up to 300 mW.
−0.5 to VCC + 0.5 V
OUT
±50 mA
OUT
−65 to 150 °C
stg
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TC74AC166P/F/FN
Operating Ranges (Note)
Characteristics Symbol Rating Unit
Supply voltage VCC 2.0 to 5.5 V
Input voltage VIN 0 to V
Output voltage V
Operating temperature T
Input rise and fall time dt/dV
0 to V
OUT
opr
0 to 100 (V
0 to 20 (V
CC
CC
−40 to 85 °C
= 3.3 ± 0.3 V)
CC
= 5 ± 0.5 V)
CC
Note: The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
Electrical Characteristics
DC Characteristics
Characteristics Symbol
High-level input
voltage
Low-level input
voltage
High-level output
voltage
Low-level output
voltage
Input leakage
current
Quiescent supply
current
V
V
V
V
I
I
CC
IH
IL
OH
OL
IN
V
IN
= V
IH
V
IL
V
IN
= V
IH
V
IL
VIN = VCC or GND 5.5 ⎯ ⎯ ±0.1 ⎯ ±1.0 μA
VIN = VCC or GND 5.5 ⎯ ⎯ 8.0 ⎯ 80.0 μA
Test Condition Ta = 25°C
V
(V)
2.0
3.0
5.5
2.0
3.0
5.5
2.0
3.0
4.5
3.0
4.5
5.5
2.0
3.0
4.5
3.0
4.5
5.5
CC
1.50
2.10
3.85
2.58
3.94
IOH = −50 μA
or
= −4 mA
I
OH
I
= −24 mA
OH
I
= −75 mA (Note)
OH
IOL = 50 μA
or
= 12 mA
I
OL
I
= 24 mA
OL
I
= 75 mA (Note)
OL
⎯
⎯
Min Typ. Max Min Max
⎯
⎯
⎯
⎯
⎯
⎯
1.9
2.9
4.4
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
⎯
2.0
3.0
4.5
⎯
⎯
⎯
0.0
0.0
0.0
⎯
⎯
⎯
V
V
ns/V
⎯
⎯
⎯
0.50
0.90
1.65
⎯
⎯
⎯
⎯
⎯
⎯
0.1
0.1
0.1
0.36
0.36
⎯
Ta
1.50
2.10
3.85
⎯
⎯
⎯
1.9
2.9
4.4
2.48
3.80
3.85
⎯
⎯
⎯
⎯
⎯
⎯
= −40 to
85°C
⎯
⎯
⎯
0.50
0.90
1.65
⎯
⎯
⎯
⎯
⎯
⎯
0.1
0.1
0.1
0.44
0.44
1.65
Unit
V
V
V
V
Note: This spec indicates the capability of driving 50 Ω transmission lines.
One output should be tested at a time for a 10 ms maximum duration.
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TC74AC166P/F/FN
Timing Requirements
Characteristics Symbol
Minimum pulse width
(CK)
Minimum pulse width
(
CLR )
Minimum set-up time
(SI, PI)
Minimum set-up time
(
LS/ )
Minimum hold time
(SI, PI)
Minimum hold time
(
LS/ )
Minimum removal time
(
)
CLR
(input: tr = tf = 3 ns)
t
W (H)
t
W (L)
t
W (L)
t
⎯
s
⎯
t
s
t
⎯
h
⎯
t
h
⎯
t
rem
=
7.0
5.0
8.0
5.0
8.0
4.0
7.0
4.0
0.5
0.5
1.0
1.0
4.0
1.5
Ta
−40 to
85°C
7.0
5.0
8.0
5.0
8.0
4.0
7.0
4.0
0.5
0.5
1.0
1.0
4.0
1.5
Test Condition
V
⎯
⎯
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
CC
± 0.3
± 0.5
± 0.3
± 0.5
± 0.3
± 0.5
± 0.3
± 0.5
± 0.3
± 0.5
± 0.3
± 0.5
± 0.3
± 0.5
Ta =
25°C
(V) Limit Limit
AC Characteristics
Characteristics Symbol
Propagation delay
time
(CK-QH)
Propagation delay
time
(
CLR -QH)
Maximum clock
frequency
Input capacitance CIN ⎯ ⎯ 5 10 ⎯ 10 pF
Power dissipation
capacitance
(CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns)
Test Condition Ta = 25°C
t
pLH
t
pHL
t
pHL
f
max
C
PD
(Note)
V
⎯
⎯
⎯
⎯ ⎯ 67 ⎯ ⎯ ⎯ pF
(V) Min Typ. Max Min Max
CC
3.3
5.0
3.3
5.0
3.3
5.0
± 0.3
± 0.5
± 0.3
± 0.5
± 0.3
± 0.5
⎯
⎯
⎯
⎯
55
90
9.4
6.6
9.2
6.4
105
150
16.1
10.0
15.2
9.6
⎯
⎯
Ta
1.0
1.0
1.0
1.0
55
90
= −40 to
85°C
18.3
11.4
17.4
10.9
⎯
⎯
Unit
ns
ns
ns
ns
ns
ns
ns
Unit
ns
ns
MHz
Note: CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
I
(opr) = CPD･VCC･fIN + ICC
CC
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Package Dimensions
TC74AC166P/F/FN
Weight: 1.00 g (typ.)
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Package Dimensions
TC74AC166P/F/FN
Weight: 0.18 g (typ.)
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Package Dimensions (Note)
TC74AC166P/F/FN
Note: This package is not available in Japan.
Weight: 0.13 g (typ.)
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TC74AC166P/F/FN
RESTRICTIONS ON PRODUCT USE
• Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information
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responsible for complying with safety standards and for providing adequate designs and safeguards for their hardware, software and
systems which minimize risk and avoid situations in which a malfunction or failure of Product could cause loss of human life, bodily
injury or damage to property, including data loss or corruption. Before creating and producing designs and using, customers must
also refer to and comply with (a) the latest versions of all relevant TOSHIBA information, including without limitation, this document,
the specifications, the data sheets and application notes for Product and the precautions and conditions set forth in the “TOSHIBA
Semiconductor Reliability Handbook” and (b) the instructions for the application that Product will be used with or for. Customers are
solely responsible for all aspects of their own product design or applications, including but not limited to (a) determining the
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information contained in this document, or in charts, diagrams, programs, algorithms, sample application circuits, or any other
referenced documents; and (c) validating all operating parameters for such designs and applications.
LIABILITY FOR CUSTOMERS’ PRODUCT DESIGN OR APPLICATIONS.
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