Toshiba TB 6560 HQ Service Manual

www.DataSheet4U.com

TOSHIBA BiCD Integrated Circuit Silicon Monolithic

y

Preliminar

TB6560HQ,TB6560FG

PWM Chopper-Type bipolar

Stepping Motor Driver IC

The TB6560HQ/FG is a PWM chopper-type sinusoidal micro-step
bipolar stepping motor driver IC.
It supports both 2-phase/1-2-phase/W1-2-phase/2W1-2-phase
excitation mode and forward/reverse mode and is capable of
low-vibration, high-performance drive of 2-phase bipolar type
stepping motors using only a clock signal.

Features

• Single-chip bipolar sinusoidal micro-step stepping motor
driver

• Uses high withstand voltage BiCD process:
Ron (upper  lower) = 0.6 Ω (typ.)

• Forward and reverse rotation control available

• Selectable phase drive (2, 1-2, W1-2, and 2W1-2)

• High output withstand voltage: V

• High output current: I

FG: 2.5 A (peak)

• Packages: HZIP25-P-1.27/HQFP64-P-1010-0.50

• Built-in input pull-down resistor: 100 kΩ (typ.)

• Output monitor pin equipped: MO current (I

• Equipped with reset and enable pins

• Built-in overheat protection circuit

= HQ: 3.5 A (peak)

OUT

CEO

= 40 V

(max) = 1 mA)

MO

TB6560HQ

TB6560FG

Weight:
HZIP25-P-1.27: 9.86 g (typ.)
HQFP64-P-1010-0.50: 0.26 g (typ.)

TB6560HQ/FG

The TB6560HQ/FG is a Pb-free product.
The following conditions apply to solderability:
*Solderability

1. Use of Sn-63Pb solder bath

*solder bath temperature = 230°C
*dipping time = 5 seconds
*number of times = once
*use of R-type flux

2. Use of Sn-3.0Ag-0.5Cu solder bath

*solder bath temperature = 245°C
*dipping time = 5 seconds
*the number of times = once
*use of R-type flux

*: Since this product has a MOS structure, it is sensitive to electrostatic discharge. These ICs are highly sensitive to

electrostatic discharge. When handling them, please be careful of electrostatic discharge, temperature and
humidity conditions.

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2006-05-31

Block Diagram

+

r

r

TB6560HQ/FG

M1

M2

CW/CCW

CLK



RESET

ENABLE

DCY1

DCY2

OSC

23/36

22/35

21/33

3/45

5/48

4/47

25/39

24/38

7/53

Input

circuit

OSC

VDD

Protect MO

Overheat protection

circuit

Current selector

circuit A

Decode

Decode

VMA

18/25, 26 17/2319/2820/30, 31

Bridge

driver A

Bridge

driver B B

OUT_AP

16/19, 20

13/10, 11

OUT_AM

14/13, 14, 15

8/55, 56

12/6, 7

9/61, 62

OUT_BM

NFA

V

MB

OUT_BP

NFB

Maximum current

setting circuit

TQ1 TQ2

Current selector

circuit B

+

15/166/50, 51

SGND PGNDA PGNDB

TB6560HQ/TB6560FG

11/2, 3, 4

10/1 1/42 2/43

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2006-05-31

Pin Functions

TB6560HQ/FG

Pin No.

HQ FG

1 42 Input TQ2 Torque setting input (current setting) (built-in pull-down resistor)

2 43 Input TQ1

3 45 Input CLK Step transition, clock input (built-in pull-down resistor)

4 47 Input ENABLE H: Enable; L: All output OFF (built-in pull-down resistor)

5 48 Input

6 50/51 ⎯ SGND Signal ground (control side) (Note 1)

7 53 ⎯ OSC Connects to and oscillates CR. Output chopping.

8 55/56 Input VMB Motor side power pin (B phase side) (Note 1)

9 61/62 Output OUT_BM OUT_B output (Note 1)

10 1 ⎯ PGNDB

11 2/3/4 ⎯ N

12 6/7 Output OUT_BP

13 10/11 Output OUT_AM

14 13/14/15 ⎯ N

15 16 ⎯ PGNDA

16 19/20 Output OUT_AP OUT_A output (Note 1)

17 23 Output MO Initial state detection output. ON when in initial state (open drain).

18 25/26 Input VMA Motor side power pin (A phase side) (Note 1)

19 28 Output Protect When TSD, ON (open drain). Normal Z.

20 30/31 Input VDD Control side power pin. (Note 1)

21 33 Input CW/CCW

22 35 Input M2 Excitation mode setting input (built-in pull-down resistor)

23 36 Input M1 Excitation mode setting input (built-in pull-down resistor)

24 38 Input DCY2 Current Decay mode setting input (built-in pull-down resistor)

25 39 Input DCY1 Current Decay mode setting input (built-in pull-down resistor)

I/O Symbol Functional Description

Torque setting input (current setting) (built-in pull-down resistor)

L: Reset (output is reset to its initial state) (built-in pull-down resistor)

Power ground

B channel output current detection pin (resistor connection).
Short the two pins for FG. (Note 1)

OUT_B output (Note 1)

OUT_A output (Note 1)

A channel output current detection pin (resistor connection).
Short the two pins for FG. (Note 1)

Power ground

Forward/Reverse toggle pin. L: Forward; H: Reverse
(built-in pull-down resistor)

RESET

FB

FA

HQ: No Non-connection (NC)

FG: Other than the above pins, all are NC

(Since NC pins are not connected to the internal circuit, a potential can be applied to those pins.)

All control input pins: Pull-down resistor 100 kΩ (typ.)

Note 1: If the FG pin number column indicates more than one pin, the indicated pins should be tied to each other at

a position as close to the pins as possible.
(The electrical characteristics of the relevant pins in this document refer to those when they are handled in
that way.)

<Terminal circuits>

Input pins
(M1, M2, CLK, CW/CCW,
ENABLE and RESET)

VDD

100 Ω

100 kΩ

Output ins
(MO, PROTECT)

100 Ω

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2006-05-31

TB6560HQ/FG

>

Absolute Maximum Ratings

(Ta = 25°C)

Characteristic Symbol Rating Unit

V

Power supply voltage

Output current Peak

HQ 3.5

FG

MO drain current I

Input voltage V

DD

V

MA/B

I

O (PEAK)

(MO)

IN

HQ

Power dissipation

P

D

FG

Operating temperature T

Storage temperature T

opr

stg

Note 1: Ta = 25°C, No heat sink.

Note 2: Ta = 25°C, with infinite heat sink (HZIP25).

Note 3: Ta = 25°C, with soldered leads.

6

V

40

A/phase

2.5

1 mA

5.5

V

5 (Note 1)

43 (Note 2)

W

1.7 (Note 3)

4.2 (Note 4)

−30 to 85 °C

−55 to 150 °C

Note 4: Ta = 25°C, when mounted on the board (4-layer board).

Susceptible to the board layout and the mounting conditions.

Operating Range

(Ta = −20 to 85°C)

Characteristic Symbol Test Condition Min Typ. Max Unit

Power supply voltage

Output current

HQ ⎯ ⎯ ⎯ 3

FG

Input voltage V

Clock frequency f

OSC frequency f

V

V

I

DD

MA/B

OUT

IN

CLK

OSC

V

MA/B

⎯ 4.5 5.0 5.5 V

VDD 4.5 ⎯ 26.4 V

A

⎯ ⎯ 1.5

⎯ 0 ⎯ 5.5

V

⎯ ⎯ ⎯ 15 kHz

⎯ ⎯ ⎯ 600 kHz

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TB6560HQ/FG

Electrical Characteristics

Characteristic Symbol

Input voltage

Input hysteresis voltage V

High V

Low V

(Ta = 25°C, VDD = 5 V, VM = 24 V)

IN (H)

IN (L)

1

H

Test

Circuit

1

M1, M2, CW/CCW, CLK,
ENABLE, DECAY, TQ1, TQ2, ISD

Test Condition Min Typ. Max Unit

RESET

2.0 ⎯ V

,

−0.2 ⎯ 0.8

⎯ 400 ⎯ mV

DD

M1, M2, CW/CCW, CLK, RESET ,

Input current

I

IN (H)

I

IN (L)

ENABLE, DECAY, TQ1, TQ2, ISD
V

= 5.0 V

IN

1

Built-in pull-down resistor

= 0 V ⎯ ⎯ 1

V

IN

30 55 80

Output open,

I

DD1

Consumption current VDD pin

Consumption current VM pin

I

DD2

I

DD3

I

DD4

IM1 RESET : H/L, ENABLE: L ⎯ 0.5 1

I

Output channel margin of error ∆V

V

NFHH

V

VNF level
Level differential

Minimum clock pulse width t

NFHL

V

NFLH

V

NFLL

W (CLK)

M2

O

 TQ1 = L, TQ2 = H 47 50 55
 TQ1 = H, TQ2 = L 70 75 80


RESET : H, ENABLE: H

⎯ 3 5

(2, 1-2 phase excitation)

Output open,

1

RESET : H, ENABLE: H

⎯ 3 5

(W1−2, 2W1-2 phase excitation)

RESET : L, ENABLE: L ⎯ 2 5

RESET : H, ENABLE: L ⎯ 2 5

1

RESET : H/L, ENABLE: H ⎯ 0.7 2

⎯ B/A, C

= 0.0033 µF −5 ⎯ 5 %

OSC

TQ1 = H, TQ2 = H 10 20 30

⎯

= L, TQ2 = L 100

TQ1

⎯ ⎯ ⎯ 100 ⎯ ns

MO output residual voltage VOL MO ⎯ IOL = 1 mA ⎯ ⎯ 0.5 V

TSD TSD ⎯ (Design target value) ⎯ 170 ⎯ °C

TSD hysteresis TSDhys ⎯ (Design target value) ⎯ 20 ⎯ °C

Oscillating frequency f

C = 330 pF 60 130 200 kHz

OSC

V

µA

mA

mA

%

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TB6560HQ/FG

Electrical Characteristics

Output Block

Characteristic Symbol

HQ

Output ON resistor

FG

2W1-2­phase
excitation

2W1-2­phase
excitation

2W1-2­phase
excitation

2W1-2­phase
excitation

2W1-2­phase
excitation

2W1-2­phase

A-B chopping current (Note)

excitation

2W1-2­phase
excitation

2W1-2­phase
excitation

2-phase excitation

Reference voltage V

Output transistor switching
characteristics

Delay time

Output leakage current

W1-2­phase
excitation

1-2­phase
excitation

⎯ ⎯ θ = 1/8 93 98 100

W1-2­phase

⎯ θ = 2/8 87 92 97

excitation

⎯ ⎯ θ = 3/8 78 83 88

W1-2­phase
excitation

1-2­phase
excitation

⎯ ⎯ θ = 5/8 51 56 61

W1-2­phase

⎯ θ = 6/8 33 38 43

excitation

⎯ ⎯ θ = 7/8 15 20 25

Upper side I

Lower side I

(Ta = 25°C, VDD = 5 V, VM = 24 V)

Circuit

Ron

Ron

Ron

Ron

U1H

L1H

U1F

L1F

Vector ⎯

NF

t

r

t

f

t

pLH

t

pLH

t

pHL

LH

LL

Test

4

⎯

7

6 VM = 40 V

Test Condition Min Typ. Max Unit

I

= 1.5 A

OUT

I

= 1.5 A

OUT

θ = 0 ⎯ 100 ⎯

= L, TQ2 = L

TQ1

θ = 4/8 66 71 76

⎯

TQ1, TQ2
OSC

= L (100%)

= 100 kHz

RL = 2 Ω, VNF = 0 V,
C

= 15 pF

L

RESET to output ⎯ 0.1 ⎯

ENABLE to output

⎯ 0.3 0.4

⎯ 0.3 0.4

⎯ 0.35 0.5

⎯ 0.35 0.5

⎯ 100 ⎯

450 500 550 mV

⎯ 0.1 ⎯

⎯ 0.1 ⎯

⎯ 0.3 ⎯

⎯ 0.2 ⎯
⎯ ― 1
⎯ ― 1

Ω

%

µs

µA

Note: Maximum current (θ = 0): 100%

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2006-05-31

Description of Functions

1. Excitation Settings

You can use the M1 and M2 pin settings to configure four different excitation settings. (The default is
2-phase excitation using the internal pull-down.)

Input

M2 M1

L L 2-phase

L H 1-2-phase

H L W1-2-phase

H H 2W1-2-phase

2. Function

When the ENABLE signal goes Low level, it sets an OFF on the output. The output changes to the Initial
mode shown in the table below when the
CLK and CW/CCW pins are irrelevant.

Input

CLK CW/CCW RESET ENABLE

L H H CW

H H H CCW

X X L H Initial mode

X X X L Z

TB6560HQ/FG

Mode

(Excitation)

RESET signal goes Low level. In this mode, the status of the

Output Mode

X: Don’t care

3. Initial Mode

When RESET is used, the phase currents are as follows. In this instance, the MO pin is L (connected to
open drain).

Excitation Mode A Phase Current B Phase Current

2-phase 100% −100%

1-2-phase 100% 0%

W1-2-phase 100% 0%

2W1-2-phase 100% 0%

4. Current Decay Settings

Output is generated by four PWM blasts; 25% decay is created by inducing decay during the last blast in
Fast mode; 50% decay is created by inducing decay during the last two blasts in Fast mode; and 100%
decay is created by inducing all four blasts in Fast mode.
If there is no input with the pull-down resistor connection then the setting is Normal.

Dcy2 Dcy1 Current Decay Setting

L L Normal 0%

L H 25% Decay

H L 50% Decay

H H 100% Decay

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2006-05-31

5. Torque Settings (Current Value)

The current ratio used in actual operations is determined in regard to the current setting due to resistance.
Configure this for extremely low torque scenarios such as when Weak Excitation mode is stopped.
If there is no input with the pull-down resistor connection then the setting is 100% tor qu e.

TQ2 TQ1 Current Ratio

L L 100%

L H 75%

H L 50%

H H

6. Protect and MO (Output Pins)

You can configure settings from the receiving side by using an open-drain connection for the output pins
and making the pull-up voltage variable.
When a given pin is in its designated state it will go ON and output at Low level.

Pin State Protect MO

TB6560HQ/FG

20%

(weak excitation)

Low Overheat protection operation Initial state

Z Normal operation Other than initial state

7. OSC

Output chopping waves are generated by connecting the condenser and having the CR oscillate.
The values are as shown below (roughly: ± 30% margin of error).

Condenser Oscillating Frequency

1000 pF 44 kHz

330 pF 130 kHz

100 pF 400 kHz

Open-drain connection

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2006-05-31

Relationship between Enable, RESET and Output (OUT and MO)

Ex-1: ENABLE 1-2-Phase Excitation (M1: H, M2: L)

CLK

ENABLE

RESET

MO

(%)
100

71

TB6560HQ/FG

CW

−71

−100

0

t

0

t1 t2 t

3

t

7

t

8t9t10

t11 t12 OFF

IA

The ENABLE signal at Low level disables only the output signals. Internal logic functions proceed in
accordance with input clock signals and without regard to the ENABLE signal. Therefore output current is
initiated by the timing of the internal logic circuit after release of disable mode.

Ex-2:

RESET

1-2-Phase Excitation (M1: H, M2: L)

CLK

ENABLE

RESET

MO

(%)

100

71

CW

−71

−100

0

t

0t1

t2 t

When the

IA

RESET signal goes Low level, output goes Initial state and the MO output goes Low level (Initial

state: A Channel output current is 100%).

Once the

RESET signal returns to High level, output continues from the next state after Initial from the

next raise in the Clock signal.

3

t

2t3

t

4

5

t7 t8 t

t

6

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2-Phase Excitation (M1: L, M2: L, CW Mode)

CW

CLK

MO

(%)
100

TB6560HQ/FG

IA

I

B

0

−100

(%)
100

0

−100

t1 t2 t3 t

t

0

t4 t5t

6

1-2-Phase Excitation (M1: H, M2: L, CW Mode)

CW

CLK

MO

(%)
100

71

7

−71

−100

(%)
100

71

−71

−100

0

0

t1 t2 t3 t

t

0

t4 t5t

7t8

6

IA

IB

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W1-2-Phase Excitation (M1: L, M2: H, CW Mode)

CLK

MO

(%)
100

92

71

38

0

I

A

−38

TB6560HQ/FG

CW

−71

−92

−100

(%)
100

92

71

38

0

I

B

−38

−71

−92

−100

t0 t1 t2t3 t

t4 t5t

6

t

7

8

10t11

t12 t13 t9t

t14 t15t

16

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2W1-2-Phase Excitation (M1: H, M2: H, CW Mode)

CLK

MO

(%)

100

98
92

83

71

56

38

20

I

−20

−38

−56

−71

−83

−92

−98

−100

0

A

TB6560HQ/FG

CW

(%)

100

98
92

83

71

56

38

IB

20

−20

−38

−56

−71

−83

−92

−98

−100

0

t

0 t1 t2 t3

t

t4t5 t

t6

7 t8

t9 t10t

11

12t13

t

14

t15t

t17t

16

23

t19t20t21t22t

18

t27 t28 t24 t25 t26 t29 t30t31t

32

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<Input Signal Example>

CK

MO

M1

M2

RESET

(%)

100

91

71.4

40

I

A

0

−40

TB6560HQ/FG

−71.4

−91

−100

1-2-phase excitation

W1-2-phase excitation

It is recommended that M1 and M2 signals be changed after setting the RESET signal Low during the Initial
state (MO is Low). Even when the MO is Low, changing the RESET signal without setting the RESET signal
Low may cause the discontinuity in the current waveform.

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1. Current Waveform and Settings of Mixed Decay Mode

You can configure the points of the current’s shaped width (current’s pulsating flow) using 1-bit input in

Decay mode for constant-current control.

“NF” refers to the point at which the output current reaches its setting current value and “RNF” refers to

the monitoring timing of the setting current.

The smaller the MDT value, the smaller the current ripple (current wave peak), and the current’s decay

capability will fall.

f

chop

OSC Pin
Internal
Waveform

Setting Current Value

TB6560HQ/FG

Normal
Mode

25%
Decay
Mode

50%
Decay
Mode

NF

Charge mode → NF: Setting current value reached → Slow mode

→ Current monitoring → (When setting current value > Output

current) Charge mode

Setting Current Value

NF

Charge mode → NF: Setting current value reached → Slow
mode

→ Mixed decay timing → Fast mode → Current monitoring

→ (When setting current value > Output current) Charge mode

Setting Current Value

NF

MDT

MDT

RNF

RNF

100%
Decay
Mode

Charge mode → NF: Setting current value reached → Slow

→ Mixed decay timing → Fast mode → Current monitoring

mode

→ (When setting current value > Output current) Charge mode

Setting Current Value

NF

Charge mode → NF: Setting current value reached → Fast mode

→ Current monitoring → (When setting current value > Output

current) Charge mode

14

RNF

RNF

2006-05-31

2. Current Control Modes (Decay Mode effect)

• Direction in which current value increases (sine wave)

TB6560HQ/FG

Setting
Current

Value

Slow Slow

Setting
Current
Value

Fast Charge

FastCharge

• Direction in which sine wave decreases
(when a high decay ratio (MDT%) is used in Mixed Decay mode)

Slow Slow

Setting
Current
Value

Charge

Fast

Charge

Fast

Setting
Current
Value

Slow

Fast

Charge

Since the current’s rate of decay is fast, its compliance
with the setting current value is also fast.

Slow

Charge

Slow

Slow

Fast

Fast

Charge

Fast

• Direction in which sine wave decreases
(when a low decay ratio (MDT%) is used in Mixed Decay mode)

Since the current’s rate of decay is slow, its
compliance with the setting current value takes a
long time (or may not follow at all).

Setting
Current
Value

Charge

Slow

Fast

Charge

Slow

Fast

Setting
Current
Value

Slow

Fast

Slow

Fast

During Mixed Decay mode and Fast Decay mode, if the setting current value < output current at RNF:
current monitoring point, the Charge mode at the next chopping cycle will disappear and the pattern will
change to Slow  Fast Mode (Slow → Fast occurs at MDT). (In reality, a charge is applied momentarily to
confirm the current.)

Note: These figures are intended for illustrative purposes only. If designed more realistically, they would show

transient response curves.

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2006-05-31

3. Mixed Decay Mode Waveform (Current Waveform)

TB6560HQ/FG

f

f

chop

OSC Pin
Internal
Waveform

I

OUT

Setting
Current
Value

25%
Mixed
Decay
Mode

NF

MDT (Mixed Decay Timing) Points

Setting Current

• When the NF points come after mixed decay timing

f

f

chop

I

OUT

MDT (Mixed Decay Timing) Points

Setting current value

chop

NF

Value

RNF

Switches to Fast mode after Charge mode

chop

NF

Setting
Current
Value

25%
Mixed
Decay
Mode

NF

RNF

CLK Signal Input

• When the output current value > Setting current value in mixed decay mode

f

Setting
Current
Value

I

OUT

25%
MIXED
DECAY
MODE

NF

f

chop

RNF

f

chop

Setting Current

Value

MDT (Mixed Decay Timing) Points

RNF

chop

RNF

NF

CLK Signal Input

*: Even if the output current rises above the setting current at the RNF point, a charge is applied momentarily to

confirm the current.

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2006-05-31

TB6560HQ/FG

4. Fast Decay Mode Waveform

After the current value set by RNF, torque or other means is attained, the output current to load will

make the transition to full regenerative mode.

f

chop

Setting
Current
Value

I

OUT

Transition to Charge mode for a brief moment

Fast
Decay
Mode
(100%
Decay
Mode)

RNF

Setting
Current
Value

NF

RNF

Since the setting current value > output
current, charge mode → NF → Fast Decay
mode transition will take place at even the
next cycle.

RNF

CLK Signal Input

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5. CLK Signal and Internal CR CK Output Current Waveform
(when the CLK signal is input in the middle of Slow mode)

25% Mixed Decay Mode

TB6560HQ/FG

OSC Pin
Internal
Waveform

Setting
Current
Value

I

OUT

f

chop

NF

f

chop

Setting

Current

Value

MDT

RNF

NF

f

chop

MDT

RNF

CLK Signal Input

The CR counter is reset here.

Transition to Charge mode for a brief moment

When the CLK signal is input, the Chopping Counter (OSC Counter) is forcibly reset at the timing of the

OSC.

As a result, the response to input data is fast in comparison to methods that don’t reset the counter.
The delay time is one OSC cycle: 10 µs @100 kHz Chopping using the Logic Block logic value.
After the OSC Counter is reset by CLK signal input, the transition is invariably made to Charge mode

for a brief moment to compare the current.

Note: Even in Fast Decay Mode, the transition is invariably made to Charge mode for a brief moment to

compare the current.

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2006-05-31

6. CLK Signal and Internal OSC Output Current Waveform
(when the CLK signal is input in the middle of Charge mode)

25% Mixed Decay Mode

TB6560HQ/FG

OSC Pin
Internal
Waveform

Setting
Current
Value

I

OUT

f

chop

f

chop

MDT

NF

Setting
Current
Value

RNF

f

chop

MDT

RNF

CLK Signal Input

The OSC Counter is reset here.

Transition to Charge mode for a brief moment

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2006-05-31

7. CLK Signal AND Internal OSC Output Current Waveform
(when the CLK signal is input in the middle of Fast mode)

25% Mixed Decay Mode

TB6560HQ/FG

OSC Pin
Internal
Waveform

Setting
Current
Value

I

OUT

NF

f

chop

Setting
Current
Value

f

chop

MDT

NF

RNF

f

chop

MDT

RNF

CLK Signal Input

The OSC Counter is reset here.

Transition to Charge mode for a brief moment

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2006-05-31

TB6560HQ/FG

8. Internal OSC Output Current Waveform when Setting Current is Reverse
(when the CLK signal is input using 2-phase excitation)

25% Mixed Decay Mode

Setting
Current
Value

I

OUT

f

chop

f

chop

0

f

chop

RNF

NF

RNF

MDT

NF

Setting
Current
Value

CLK Signal Input

The OSC Counter is reset here.

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2006-05-31

TB6560HQ/FG

Current Draw-out Path when ENABLE is Input in Mid Operation

When all the output transistors are forced OFF during Slow mode, the coil energy is drawn out in the

following modes:

Note: Parasitic diodes are indicated on the designed lines. However, these are not normally used in Mixed

Decay mode.

U1

ON

OFF

L1

V

M

Note

Load

RNF

PGND

Charge Mode

U2

OFF

ON

L2

U1

OFF

ON

L1

VM

U2

Note

Load

R

NF

PGND

Slow Mode Force OFF Mode

OFF

ENABLE is input

L2

ON

U1

OFF

L1

OFF

RNF

V

M

Note

Load

PGND

As shown in the figure above, an output transistor has parasitic diodes.

Normally, when the energy of the coil is drawn out, each transistor is turned ON and the power flows in the
opposite-to-normal direction; as a result, the parasitic diode is not used. However, when all the output
transistors are forced OFF, the coil energy is drawn out via the parasitic diode.

U2

OFF

L2

OFF

22

2006-05-31

Output Stage Transistor Operation Mode

TB6560HQ/FG

U1

ON

OFF

L1

V

M

U2

Note

Load

RNF

PGND

Charge Mode Slow Mode Fast Mode

OFF

ON

L2

U1

OFF

ON

L1

VM

Note

Load

R

NF

PGND

Output Stage Transistor Operation Functions

U2

OFF

L2

ON

U1

OFF

L1

ON

RNF

V

M

Note

Load

U2

ON

L2

OFF

PGND

CLK U1 U2 L1 L2

CHARGE ON OFF OFF ON

SLOW OFF OFF ON ON

FAST OFF ON ON OFF

Note: The above chart shows an example of when the current flows as indicated by the arrows in the above figures.

If the current flows in the opposite direction, refer to the following chart:

CLK U1 U2 L1 L2

CHARGE OFF ON ON OFF

SLOW OFF OFF ON ON

FAST ON OFF OFF ON

Upon transitions of above-mentioned functions, a dead time of about 300 ns is inserte d respectively.

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2006-05-31

Measurement Waveform

t

CLK

V

M

CLK

t

pLH

TB6560HQ/FG

t

50%

t

pHL

CLK

90% 90%

50%

GND

10%

tr t

10%

f

Figure 1 Timing Waveforms and Names

OSC-Charge DELAY:

The conversion from the OSC waveform to the internal OSC waveform is done by recognizing the level of
chopping wave. The voltages of 2 V or above are considered as a High level, and voltages of 0.5 V or below are
considered as a Low level as designed values. However, there is a response delay and that there occurs the
peak-to-peak voltage variation.

2 V

OSC

Waveform

0.5 V

OSC Pin
Internal
Waveform

Figure 2 Timing Waveforms and Names (CR and Output)

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2006-05-31

Power Dissipation

TB6560HQ

TB6560HQ/FG

25

2006-05-31

1. How to Turn on the Power

Turn on VDD. When the voltage has stabilized, turn on V
In addition, set the Control Input pins to Low when inputting the power.
(All the Control Input pins are pulled down internally.)
Once the power is on, the CLK signal is received and excitation advances when
excitation is output when ENABLE goes high. If only
only the internal counter will advance. Likewise, if only ENABLE goes high, excitation won't advance even
if the CLK signal is input and it will remain in the initial state.
The following is an example:

<Recommended Control Input Sequence>

CLK

TB6560HQ/FG

.

MA/B

RESET goes high and

RESET goes high, excitation won't be output and

OUT

H

L

H

L

H

L

ZOutput current setting

Internal current setting: Invariable

Output OFF

RESET

ENABLE

Internal current Setting

2. Calculating the Setting Current

To perform constant-current operations, it is necessary to configure the base current using an external
resistor. If the voltage on the N

(B) pin is 0.5 V (with a torque of 100%) or greater, it will not charge.

FA

Ex.: If the maximum current value is 1 A, the external resistance will be 0.5 W.

3. PWM Oscillator Frequency (External Condenser Setting)

An external condenser connected to the OSC pin is used to internally generate a saw tooth waveform. PWM
is controlled using this frequency. Toshiba recommends 100 to 3300 pF for the capacitance, taking
variations between ICs into consideration.
Approximation: f

osc

= 1/(C

× 1.5 × (10/C

osc

+ 1)/66) × 1000 kHz

osc

4. Power Dissipation

The IC power dissipation is determined by the following equation:

P = V

× IDD + I

DD

× Ron × 2 drivers

OUT

The higher the ambient temperature, the smaller the power dissipation.
Check the PD-Ta curve, and be sure to design the heat dissipation with a sufficient margin.

5. Heat Sink Fin Processing

The IC fin (rear) is electrically connected to the rear of the chip. If current flows to the fin, the IC will
malfunction. If there is any possibility of a voltage being generated between the IC GND and the fin, either
ground the fin or insulate it.

OutputZ

Internal current setting: Variable

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2006-05-31

6. Thermal Protection

When the temperature reaches 170°C (as standard value), the thermal protection c ircuit is activated
switching the output to off. There is a variation of plus or minus about 20°C in the temperature that
triggers the circuit operation.

TB6560HQ/FG

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2006-05-31

TB6560HQ/FG

∼

3.3 V
or

5.0 V

MCU

or

External

input

10 µF5 V 1 µF

CLK

RESET

ENABLE

M1

M2

CW/CCW

DCY1

DCY2

TQ1

TQ2

Protect

MO

R1 R2

VDD VMA V

Logic

Current

Control

100 pF

NFCompA

OSC

400 kHz

H-SW A

H-SW B

SGND PGND

MB

NFCompB

1 µF 47 µF 24 V

OUTAP

NFA

N

FB

0.5

OUTAM

OUTBP

OUTBM

Ω: IOUTmax = 1.0 A

M

RNFA

RNFB

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2006-05-31

Package Dimensions

TB6560HQ/FG

Weight: 9.86 g (typ.)

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2006-05-31

Package Dimensions

TB6560HQ/FG

Weight: 0.26 g (typ.)

Note: The rear heat sink block will be 5.5 mm × 5.5 mm. (PROVISIONAL)

30

2006-05-31

TB6560HQ/FG

RESTRICTIONS ON PRODUCT USE

• The information contained herein is subject to change without notice. 021023_D

• TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor

devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical
stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of
safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of
such TOSHIBA products could cause loss of human life, bodily injury or damage to property.
In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as
set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and
conditions set forth in the “Handling Guide for Semiconductor Devices,” or “TOSHIBA Semiconductor Reliability
Handbook” etc.

• The TOSHIBA products listed in this document are intended for usage in general electronics applications
(computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances,
etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires
extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or
bodily injury (“Unintended Usage”). Unintended Usage include atomic energy control instruments, airplane or
spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments,
medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this
document shall be made at the customer’s own risk.

• The products described in this document shall not be used or embedded to any downstream products of which
manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q

021023_A

021023_B

060116EBA

• The information contained herein is presented only as a guide for the applications of our products. No
responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of
TOSHIBA or others.

• The products described in this document are subject to the foreign exchange and foreign trade laws.

021023_C

31

021023_E

2006-05-31