Texas instruments TVP5154A DATASHEET

TVP5154A

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SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

4-Channel Low-Power PAL/NTSC/SECAM Video Decoder

With Independent Scalers and Fast Lock

Check for Samples: TVP5154A

1 Introduction

1.1 Features

• Four Separate Video Decoder Channels With • Internal Phase-Locked Loop (PLL) for Features for Each Channel: Line-Locked Clock (Separate for Each Channel)

– Accept NTSC (J, M, 4.43), PAL (B, D, G, H, I,

M, N, Nc), and SECAM (B, D, G, K, K1, L) • Sub-Carrier Genlock Output for Synchronizing

Video Color Sub-Carrier of External Encoder – Support ITU-R BT.601 Standard Sampling • Standard Programmable Video Output Format – High-Speed 9-Bit Analog-to-Digital Converter – ITU-R BT.656, 8-Bit 4:2:2 With Embedded

(ADC) Syncs – Two Composite Inputs or One S-Video Input – 8-Bit 4:2:2 With Discrete Syncs

(for Each Channel) – Fully Differential CMOS Analog Formats

Preprocessing Channels With Clamping and

Automatic Gain Control (AGC) for Best

Signal to Noise (SNR) Performance – Brightness, Contrast, Saturation, Hue, and

Sharpness Control Through Inter-Integrated

Circuit (I2C) – Complementary 4-Line (3-H Delay) Adaptive

Comb Filters for Both Cross-Luminance and

Cross-Chrominance Noise Reduction – Patented Architecture for Locking to Weak,

Noisy, or Unstable Signals

• Four Independent Polymorphic Scalers

• Single or Concurrent Scaled and Unscaled Outputs Via Dual Clocking Data, Interleaved 54-MHz Data or Single 27-MHz Clock

• Scaled/Unscaled Image Toggle Mode Gives Variable Field Rate for Both Scaled and Unscaled Video

• Low Power Consumption: 700 mW Typical

• 128-Pin Thin Quad Flat Pack (TQFP) Package

• Single 14.31818-MHz Crystal for All Standards and All Channels

and Sampling

• Advanced Programmable Video Output

– 2× Over-Sampled Raw Vertical Blanking

Interval (VBI) Data During Active Video

– Sliced VBI Data During Horizontal Blanking

or Active Video

• VBI Modes Supported: – Teletext (NABTS, WST) – Closed-Caption Decode With FIFO, and

Extended Data Services (EDS)

– Wide Screen Signaling (WSS), Video

Program System (VPS), Copy Generation Management System (CGMS), Vertical Interval Time Code (VITC)

– Gemstar 1×/2× Electronic Program Guide

Compatible Mode

– Custom Configuration Mode Allows User to

Program the Slice Engine for Unique VBI Data Signals

• Improved Fast Lock Mode Can Be Used When Input Video Standard Is Known and Signals on Switching Channels Are Clean

• Four Possible I2C Addresses Allowing 16 Decoder Channels on a Single I2C Bus

• Available in Commercial (0°C to 70°C) and Industrial (–40°C to 85°C) Temperature Ranges

1.2 Description

The TVP5154A device is a 4-channel, low-power, NTSC/PAL/SECAM video decoder. Available in a space-saving 128-pin thin quad flat pack (TQFP) package, each channel of the TVP5154A decoder converts NTSC, PAL, or SECAM video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

TVP5154A

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

available. All four channels of the TVP5154A are independently controllable. The decoders share one crystal for all channels and for all supported standards. The TVP5154A can be programmed using a single inter-integrated circuit (I2C) serial interface. The decoder uses a 1.8-V supply for its analog and digital supplies, and a 3.3-V supply for its I/O. The optimized architecture of the TVP5154A decoder allows for low power consumption. The decoder consumes less than 720 mW of power in typical operation.

Each channel of the TVP5154A is an independent video decoder with a programmable polymorphic scaler. Each channel converts baseband analog video into digital YCbCr 4:2:2 component video, which can then be scaled down to any resolution to 1/256 vertical and 15-bit horizontal in 2-pixel decrements. Composite and S-video inputs are supported. Each channel includes one 9-bit analog-to-digital converter (ADC) with 2× sampling. Sampling is ITU-R BT.601 (27.0) MHz, generated from a single 14.31818-MHz crystal or oscillator input) and is line locked. The output formats can be 8-bit 4:2:2 with discrete syncs or 8-bit ITU-R BT.656 with embedded synchronization.

The TVP5154A utilizes Texas Instruments patented technology for locking to weak, noisy, or unstable signals. A real-time control (RTC) output is generated for each channel for synchronizing downstream video encoders.

Complementary 4-line adaptive comb filtering is available per channel for both the luma and chroma data paths to reduce both cross-luma and cross-chroma artifacts. A chroma trap filter also is available.

An improved fast lock mode can be used when the input video standard is known and the signals on the switching channels are clean. Note, switching from snow and/or noisy channels to good channels takes longer. In fast lock mode, video lock is achieved in three fields or less.

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Video characteristics, including hue, contrast, brightness, saturation, and sharpness, may be independently programmed for each channel using the industry standard I2C serial interface. The TVP5154A generates synchronization, blanking, lock, and clock signals in addition to digital video outputs for each channel. The TVP5154A includes methods for advanced vertical blanking interval (VBI) data retrieval. The VBI data processor slices, parses, and performs error checking on teletext, closed caption, and other data in several formats.

I2C commands can be sent to one or more decoder cores simultaneously, reducing the amount of I2C activity necessary to configure each core. A register controls which decoder core receives I2C commands, and can be configured such that all four decoders receive commands at the same time.

The main blocks for each of the channels of the TVP5154A decoder include:

• Robust sync detector

• ADC with analog processor

• Y/C separation using 4-line adaptive comb filter

• Independent, concurrent scaler outputs

• Chrominance processor

• Luminance processor

• Video clock/timing processor and power-down control

• I2C interface

• VBI data processor

1.3 Applications

• Security/Surveillance Digital Video Recorders/Servers and PCI Products

• Automotive Infotainment Video Hub

• Large-Format Video Wall Displays

• Games Systems

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1.4 Related Products

• TVP5150AM1

• TVP5151

• TVP5146M2

• TVP5147M1

• TVP5158

1.5 Trademarks

PowerPAD is a trademark of Texas Instruments. Macrovision is a trademark of Macrovision Corporation. Gemstar is a trademark of Gemstar-TV Guide International. Other trademarks are the property of their respective owners.

1.6 Document Conventions

Throughout this data manual, several conventions are used to convey information. These conventions are:

• To identify a binary number or field, a lower case b follows the numbers. For example: 000b is a 3-bit binary field.

• To identify a hexadecimal number or field, a lower case h follows the numbers. For example: 8AFh is a 12-bit hexadecimal field.

• All other numbers that appear in this document that do not have either a b or h following the number are assumed to be decimal format.

• If the signal or terminal name has a bar above the name (for example, RESETB), then this indicates the logical NOT function. When asserted, this signal is a logic low, 0, or 0b.

• RSVD indicates that the referenced item is reserved.

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

1.7 Ordering Information

0°C to 70°C

–40°C to 85°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI web site at www.ti.com.

PACKAGED DEVICES

128-PIN TQFP PowerPAD™

TVP5154APNP Tray

TVP5154APNPR Tape and reel

TVP5154AIPNP Tray

TVP5154AIPNPR Tape and reel

(1)

PACKAGE OPTION

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TVP5154A

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

1 Introduction .............................................. 1

1.1 Features .............................................. 1 4 I

1.2 Description ........................................... 1 4.1 I2C Write Operation ................................. 20

1.3 Applications .......................................... 2

1.4 Related Products ..................................... 3

1.5 Trademarks .......................................... 3

1.6 Document Conventions .............................. 3

1.7 Ordering Information ................................. 3

2 Device Details ............................................ 5

2.1 Functional Block Diagram ............................ 5

2.2 Terminal Diagram .................................... 6

2.3 Terminal Functions ................................... 7

3 Functional Description ................................. 9

3.1 Analog Front End .................................... 9

3.2 Composite Processing Block Diagram ............... 9

3.3 Adaptive Comb Filtering ............................ 10

3.4 Color Low-Pass Filter ............................... 11

3.5 Luminance Processing ............................. 11

3.6 Chrominance Processing ........................... 11

3.7 Timing Processor ................................... 11

3.8 VBI Data Processor ................................ 12

3.9 VBI FIFO and Ancillary Data in Video Stream ..... 13

3.10 Raw Video Data Output ............................ 14

3.11 Output Formatter ................................... 14

3.12 Synchronization Signals ............................ 14

3.13 Active Video (AVID) Cropping ...................... 15

3.14 Embedded Syncs ................................... 17

3.15 Clock and Data Control ............................. 18

C Host Interface ...................................... 19

4.2 I

C Read Operation ................................. 20

5 Clock Circuits .......................................... 22

6 Genlock Control and RTC ........................... 23

6.1 TVP5154A Genlock Control Interface .............. 23

6.2 RTC Mode .......................................... 23

6.3 Reset and Power Down ............................ 24

6.4 Reset Sequence .................................... 25

7 Internal Control Registers ........................... 26

7.1 Overview ............................................ 26

7.2 Direct Register Definitions .......................... 29

7.3 Indirect Register Definitions ........................ 75

8 Scaler Configuration .................................. 79

8.1 Overview ............................................ 79

8.2 Horizontal Scaling .................................. 79

8.3 Vertical Scaling ..................................... 80

8.4 Field Interleaving ................................... 81

9 Electrical Specifications ............................. 82

9.1 Absolute Maximum Ratings ........................ 82

9.2 Recommended Operating Conditions .............. 82

9.3 Reference Clock Specifications .................... 82

9.4 Electrical Characteristics ........................... 83

9.5 Timing Requirements ............................... 84

9.6 I

C Host Port Timing ................................ 85

9.7 Thermal Specifications ............................. 85

10 Schematic ............................................... 86

11 Revision History ....................................... 87

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M U X

AIP1A

AIP1B

AIP2A

AIP2B

AIP3A

AIP3B

AIP4A

AIP4B

PGA

9−Bit A/D

Y/C

VBI Data

Processor (VDP)

Luminance Processing

Chrominance

Processing

Scaler

Output Formatter

CH1_OUT [7:0] YCBCR8−Bit 4:2:2

CH2_OUT [7:0] YCBCR8−Bit 4:2:2

CH3_OUT [7:0] YCBCR8−Bit 4:2:2

CH4_OUT [7:0] YCBCR8−Bit 4:2:2

SCL

SDA

XIN/OSC

XOUT

Horizontal and

Color PLLs

Host

Interface

Embedded

Processor

Timing Processor

FID/GLCO[1−4]

VSYNC/PAL[1−4]

INTERQ/GPCL/BLK[1−4]

HSYNC[1−4]

AVID[1−4]

CLK[1−4]

SCLK[1−4]

Y/CY/CY/C

Separation

Separation Separation Separation

Output Formatter Output Formatter Output Formatter

Luminance Processing

Chrominance

Processing

Luminance Processing

Chrominance

Processing

Luminance Processing

Chrominance

Processing

VBI Data

Processor (VDP)

VBI Data

Processor (VDP)

VBI Data

Processor (VDP)

TVP5154A

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2 Device Details

2.1 Functional Block Diagram

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

Figure 2-1. Functional Block Diagram

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CH2_OUT0 CH2_OUT1

IOVDD

INT 2/GPCL2/VBLK2REQ

AVID2 HSYNC2 VSYNC2/PALI2 FID2/GLCO2

DGND DVDD

120

119

118

117

116

115

114

113

112

111

110

109

124

123

122

121

128

127

126

125

INT 1/GPCL1/VBLK1REQ

AVID1

HSYNC1

IOGND

CH1_OUT0

XIN/OSC

SDA

I2CA0

DVDD

I2CA1

XOUT

PDN

CH1_OUT5

CH1_OUT6

CH1_OUT7

CH1_OUT4

CH1_OUT3

CH1_OUT2

CH1_OUT1

CH3_OUT1

100

104

103

102

101

108

107

106

105

92 91 90 89 88 87 86 85 84 83 82

81 80 79 78 77

96 95 94 93

AIP1A

5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

1 2 3 4

21 22 23 24 25 26 27 28 29 30

AGND

576258

CH4_OUT5

CH4_OUT4

CH4_OUT6

CH4_OUT7

CH4_OUT3

CH4_OUT1

CH4_OUT0

CH4_OUT2

TMS

SCLK3

CLK3

FID4/GLCO4

VSYNC4/PALI4

CLK4

SCLK4

HSYNC4

IOVDD

IOGND

68 67

70 69

76 75

72 71

CLK2

SCLK2

CH2_OUT7

CH2_OUT6

CH2_OUT2 CH2_OUT3

CH2_OUT5

CH2_OUT4

IOGND

31 32

66 65

CH3_OUT2

RESETB

SCL

REFM1

REFP1

CH3_OUT0

AIP2B

REFM2

REFP2

PLL_GND

PLL_VDD

AGND

AVDD

AIP3A

REFM3

REFP3

PLL_GND

PLL_VDD

AGND

AVDD

AI4GND

REFM4

REFP4

PLL_GND

PLL_VDD

AGND

AVDD

AVID4

DGND

IOVDD

AI3GND

AVDD

AGND

AI1GND

AI2GND

IOVDD

IOGND

DVDD

DGND

DGND DVDD

IOGND

DVDD

DGND

IOVDD

FID3/GLCO3

VSYNC3/PALI3

HSYNC3

AVID3

CH3_OUT6 CH3_OUT7

CH3_OUT5

CH3_OUT4

CH3_OUT3

CLK1

SCLK1

VSYNC1/PALI1 FID1/GLCO1

AGND

AVDD

AIP4A

PLL_GND

PLL_VDD

PNP Package

(TopView)

AIP1B

AIP2A

AIP3B

AIP4B

TVP5154A

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

2.2 Terminal Diagram

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2.3 Terminal Functions

TERMINAL

NAME NO.

Analog Section

AIP1A 2 maximum input range is 0–0.75 VPP, and may require an attenuator to reduce the input AIP1B 3 amplitude to the desired level. If not used, connect to AGND via a 0.1-µF capacitor. See the

AIP2A 11 maximum input range is 0-0.75 VPP, and may require an attenuator to reduce the input AIP2B 12 amplitude to the desired level. If not used, connect to AGND via a 0.1-µF capacitor. See the

AIP3A 22 maximum input range is 0-0.75 VPP, and may require an attenuator to reduce the input AIP3B 23 amplitude to the desired level. If not used, connect to AGND via a 0.1-µF capacitor. See the

AIP4A 31 maximum input range is 0-0.75 VPP, and may require an attenuator to reduce the input AIP4B 32 amplitude to the desired level. If not used, connect to AGND via a 0.1-µF capacitor. See the

AVDD P Analog power supply. Connect to 1.8-V analog supply.

AGND 29, 35, G Analog power supply return. Connect to analog ground.

AIxGND G Analog input signal return. Connect to analog ground.

PLL_GND G PLL power supply return. Connect to analog ground.

PLL_VDD P PLL power supply. Connect to 1.8-V analog supply.

REFMx I

REFPx I

Digital Section

DGND G Digital power supply return. Connect to digital ground

DVDD P Digital power supply. Connect to 1.8-V digital supply.

IOGND G I/O power supply return. Connect to digital ground.

IOVDD P I/O power supply. Connect to 3.3-V digital supply

FID1/GLCO1 94 FID2/GLCO2 75 FID3/GLCO3 56 FID4/GLCO4 37

AVID1 101 AVID2 78 Active video indicator. This signal is high during the horizontal active time of the video AVID3 59 output. AVID4 40

INTREQ1/GPCL1/VBLK1 102 INTREQ2/GPCL2/VBLK2 83 INTREQ3/GPCL3/VBLK3 60 INTREQ4/GPCL4/VBLK4 41

8, 15, 19,

28, 127

9, 16, 20,

128

1, 10, 21,

5, 14, 25,

4, 13, 24,

6, 17, 26, Reference supply decoupling . Connect to analog ground through a 1-µF capacitor. Connect

125 to REFPx through a 1-µF capacitor.

7, 18, 27, Reference supply decoupling . Connect to analog ground through a 1-µF capacitor. Connect

126 to REFMx through a 1-µF capacitor.

47, 66, 82,

99, 116

46, 65, 81,

98, 115

44, 63, 79,

96, 113

45, 64, 80,

97, 114

I/O DESCRIPTION

Analog inputs for Channel 1. Connect to the video analog input via a 0.1-µF capacitor. The

schematic in Section 10. Analog inputs for Channel 2. Connect to the video analog input via a 0.1-µF capacitor. The

schematic in Section 10. Analog inputs for Channel 3. Connect to the video analog input via a 0.1-µF capacitor. The

schematic in Section 10. Analog inputs for Channel 4. Connect to the video analog input via a 0.1-µF capacitor. The

schematic in Section 10.

1. FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1 indicates the odd field.

O 2. GLCO: This serial output carries color PLL information. A slave device can decode the

information to allow chroma frequency control from the TVP5154A decoder. Data is transmitted at the CLK rate in Genlock mode.

1. Interrupt request : Open drain when active low.

2. GPCL: General-purpose output. In this mode, the state of GPCL is directly programmed

I/O

via I2C.

3. VBLK: Vertical blank output. In this mode, the GPCL terminal is used to indicate the VBI of the output video. The beginning and end times of this signal are programmable via I2C.

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TERMINAL

NAME NO.

HSYNC1 100 HSYNC2 77 HSYNC3 58 HSYNC4 39

VSYNC1/PALI1 95 VSYNC2/PALI2 76 VSYNC3/PALI3 57 VSYNC4/PALI4 38

PDN 122 I

RESETB 121 I SCL 120 I/O I2C serial clock (open drain)

SDA 119 I/O I2C serial data (open drain)

I2CA0 118 I address the device is configured to. A 10-kΩ resistor should pull this either high (to IOVDD)

I2CA1 117 I address the device is configured to. A 10-kΩ resistor should pull this either high (to IOVDD)

CLK1 103 CLK2 84 CLK3 61 CLK4 42

SCLK1 104 SCLK2 85 Scaled system data clock at 27 MHz. This signal can be used to qualify scaled/unscaled SCLK3 62 data when the unscaled system data clock is set to 54 MHz. SCLK4 43

XIN/OSC 124 I crystal oscillator. The user may connect XOUT to the other terminal of the crystal oscillator XOUT 123 O or not connect XOUT at all. One single 14.31818-MHz crystal or oscillator is needed for

CH1_OUT[7:0] 105–112 O Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 1 CH2_OUT[7:0] 86–93 O Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 2 CH3_OUT[7:0] 67–74 O Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 3 CH4_OUT[7:0] 48–55 O Decoded ITU-R BT.656 output/YCbCr 4:2:2 output with discrete sync for channel 4

TMS 36 I

I/O DESCRIPTION

O Horizontal synchronization

1. VSYNC: Vertical synchronization

2. PALI: PAL line indicator or horizontal lock indicator. For the PAL line indicator, a 1 indicates a noninverted line, and a 0 indicates an inverted line.

Power down (active low). A 0 on this pin puts the decoder in standby mode. PDN preserves the value of the registers.

Active-low reset. RESETB can be used only when PDN = 1. When RESETB is pulled low, it resets all the registers and restarts the internal microprocessor.

During power-on reset, this pin is sampled along with pin 117 (I2CA1) to determine the I2C or low to select different I2C device addresses.

During power-on reset, this pin is sampled along with pin 118 (I2CA0) to determine the I2C or low to select different I2C device addresses.

O Unscaled system data clock at either 27 MHz or 54 MHz

External clock reference. The user may connect XIN to an oscillator or to one terminal of a

ITU-R BT.601 sampling, for all supported standards.

Test-mode select. This pin should be connected to digital ground for correct device operation.

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3 Functional Description

3.1 Analog Front End

Each channel of the TVP5154A decoder has an analog input channel that accepts two video inputs, which should be ac coupled through 0.1-µF capacitors. The decoder supports a maximum input voltage range of

0.75 V; therefore, an attenuation of one-half is needed for standard input signals with a peak-to-peak variation of 1.5 V. The maximum parallel termination before the input to the device is 75 Ω. See the schematic in Section 10 for recommended configuration. The two analog input ports can be connected as follows:

• Two selectable composite video inputs or

• One S-video input An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The programmable gain amplifier (PGA) and the automatic gain control (AGC) circuit work together to

ensure that the input signal is amplified or attenuated correctly, ensuring the proper input range for the ADC.

When switching CVBS inputs from one input to the other, the AGC settings are internally stored and the previous settings for the new input are restored. This eliminates flashes and dark frames associated with switching between inputs that have different signal amplitudes.

The ADC has nine bits of resolution and runs at a maximum speed of 27 MHz. The clock input for the ADC comes from the PLL.

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

3.2 Composite Processing Block Diagram

The composite processing block processes NTSC/PAL/SECAM signals into the YCbCr color space.

Figure 2-1 shows the basic architecture of this processing block. Figure 2-1 shows the luminance/chrominance (Y/C) separation process in the TVP5154A decoders. The

composite video is multiplied by sub-carrier signals in the quadrature modulator to generate the color difference signals Cb and Cr. Cb and Cr are then low pass (LP) filtered to achieve the desired bandwidth and to reduce crosstalk.

An adaptive 4-line comb filter separates CbCr from Y. Chroma is remodulated through another quadrature modulator and subtracted from the line-delayed composite video to generate luma. Contrast, brightness, hue, saturation, and sharpness (using the peaking filter) are programmable via I2C.

The Y/C separation is bypassed for S-video input. For S-video, the remodulation path is disabled.

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3.3 Adaptive Comb Filtering

The 4-line comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the luma path, then chroma trap filters are used which are shown in Figure 3-1 and

Figure 3-2. TI's patented adaptive 4-line comb filter algorithm reduces artifacts, such as hanging dots at

color boundaries, and detects and properly handles false colors in high-frequency luminance images, such as a multiburst pattern or circle pattern.

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Figure 3-1. Chroma Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling

Figure 3-2. Chroma Trap Filter Frequency Response, PAL ITU-R BT.601 Sampling

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3.4 Color Low-Pass Filter

In some applications, it is desirable to limit the Cb/Cr bandwidth to avoid crosstalk. This is especially true in the case of video signals that have asymmetrical Cb/Cr sidebands. The provided color LP filters limit the bandwidth of the Cb/Cr signals. Color LP filters are needed when the comb filtering turns off, due to extreme color transitions in the input image. See Chrominance Control #2 Register (Section 7.2.27), for the response of these filters. The filters have three options that allow three different frequency responses based on the color frequency characteristics of the input video as shown in Figure 3-3.

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

Figure 3-3. Color Low-Pass Filter with Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling

3.5 Luminance Processing

The luma component is derived from the composite signal by subtracting the remodulated chroma information. A line delay exists in this path to compensate for the line delay in the adaptive comb filter in the color processing chain. The luma information is then fed into the peaking circuit, which enhances the high-frequency components of the signal, thus, improving sharpness.

3.6 Chrominance Processing

For NTSC/PAL formats, the color processing begins with a quadrature demodulator. The Cb/Cr signals then pass through the gain control stage for chroma saturation adjustment. An adaptive comb filter is applied to the demodulated signals to separate chrominance and eliminate cross-chrominance artifacts. An automatic color-killer circuit is also included in this block. The color killer suppresses the chrominance processing when the burst amplitude falls below a programmable threshold (see I2C subaddress 06h,

Section 7.2.7). The SECAM standard is similar to PAL except for the modulation of color, which is FM

instead of QAM.

3.7 Timing Processor

The timing processor is a combination of hardware and software running in the internal microprocessor that serves to control horizontal lock to the input sync pulse edge, AGC and offset adjustment in the analog front end, and vertical sync detection.

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3.8 VBI Data Processor

The TVP5154A VBI data processor (VDP) slices various data services, such as teletext (WST, NABTS), closed caption (CC), wide screen signaling (WSS), etc. These services are acquired by programming the VDP to enable standards in the VBI. The results are stored in a FIFO and/or registers. The teletext results are stored in a FIFO only. Table 3-1 lists a summary of the types of VBI data supported according to the video standard. It supports ITU-R BT.601 sampling for each.

Table 3-1. Data Types Supported by the VDP

LINE MODE REGISTER

(D0h–FCh) BITS [3:0]

0000b WST SECAM Teletext, SECAM 0001b WST PAL B Teletext, PAL, System B 0010b WST PAL C Teletext, PAL, System C 0011b WST, NTSC B Teletext, NTSC, System B 0100b NABTS, NTSC C Teletext, NTSC, System C 0101b NABTS, NTSC D Teletext, NTSC, System D (Japan) 0110b CC, PAL Closed caption PAL 0111b CC, NTSC Closed caption NTSC 1000b WSS/CGMS-A, PAL Wide-screen signaling/Copy Generation Management System-Analog, PAL 1001b WSS/CGMS-A, NTSC Wide-screen signaling/Copy Generation Management System-Analog, NTSC 1010b VITC, PAL Vertical interval timecode, PAL 1011b VITC, NTSC Vertical interval timecode, NTSC 1100b VPS, PAL Video program system, PAL 1101b Gemstar 2x Custom 1 Electronic program guide 1110b Reserved Reserved 1111b Active Video Active video/full field

NAME DESCRIPTION

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At power up, the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents with the lookup table (see Section 7.2.69). This is done through port address C3h. Each read from or write to this address auto increments an internal counter to the next RAM location. To access the VDP-CRAM, the line mode registers (D0h–FCh) must be programmed with FFh to avoid a conflict with the internal microprocessor and the VDP in both writing and reading. Full field mode must also be disabled.

Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Each line can be any VBI mode. Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h–AFh,

both of which are available through the I2C port.

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3.9 VBI FIFO and Ancillary Data in Video Stream

Sliced VBI data can be output as ancillary data in the video stream in the ITU-R BT.656 mode. VBI data is output during the horizontal blanking period following the line from which the data was retrieved. Table 3-2 shows the header format and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into the FIFO. The size of FIFO is 512 bytes. Therefore, the FIFO can store up to 11 lines of teletext data with the NTSC NABTS standard.

Table 3-2. Ancillary Data Format and Sequence

BYTE NO. D6 D5 D4 D3 D2 D1 DESCRIPTION

0 0 0 0 0 0 0 0 0 Ancillary data preamble 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 3 NEP EP 0 1 0 DID2 DID1 DID0 Data ID (DID) 4 NEP EP F5 F4 F3 F2 F1 F0 Secondary data ID (SDID) 5 NEP EP N5 N4 N3 N2 N1 N0 Number of 32 bit data (NN) 6 Video line # [7:0] Internal data ID0 (IDID0) 7 0 0 0 Data error Match #1 Match #2 Video line # [9:8] Internal data ID1 (IDID1) 8 1. Data Data byte 1st word

9 2. Data Data byte 10 3. Data Data byte 11 4. Data Data byte

⋮ ⋮ ⋮

4(N+2)-1 0 0 0 0 0 0 0 0 Fill byte

D7 D0

(MSB) (LSB)

—1. Data Data byte Nth word

m. Data Data byte

NEP EP CS[5:0] Check sum

EP: Even parity for D0–D5 NEP: Negated even parity DID: 91h: Sliced data of VBI lines of first field

53h: Sliced data of line 24 to end of first field 55h: Sliced data of VBI lines of second field

97h: Sliced data of line 24 to end of second field SDID: This field holds the data format taken from the line mode register of the corresponding line. NN: Number of Dwords beginning with byte 8 through 4(N+2). This value is the number of Dwords where each Dword is 4

bytes. IDID0: Transaction video line number [7:0] IDID1: Bit 0/1 = Transaction video line number [9:8]

Bit 2 = Match 2 flag

Bit 3 = Match 1 flag

Bit 4 = 1 if an error was detected in the EDC block. 0 if not. CS: Sum of D0–D7 of DID through last data byte Fill byte: Fill bytes make a multiple of four bytes from byte 0 to last fill byte. For teletext modes, byte 8 is the sync pattern byte.

Byte 9 is 1. Data (the first data byte).

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3.10 Raw Video Data Output

The TVP5154A decoder can output raw A/D video data at 2× sampling rate for external VBI slicing. This is transmitted as an ancillary data block during the active horizontal portion of the line and during vertical blanking.

3.11 Output Formatter

The output formatter is responsible for generating the output digital video stream. The YCbCr digital output can be programmed as 8-bit 4:2:2 or 8-bit ITU-R BT.656 parallel interface standard. Depending on which output mode is selected, the output for each channel can be unscaled data, scaled data, or both scaled and unscaled data interleaved in various ways.

Table 3-3. Summary of Line Frequencies, Data Rates and Pixel Counts for Different Standards

STANDARDS PIXELS PER ACTIVE PIXELS LINES PER SUB-CARRIER

(ITU-R BT.601) LINE PER LINE FRAME FREQUENCY

NTSC-J, M 858 720 525 13.5 3.579545 15.73426 NTSC-4.43 858 720 525 13.5 4.43361875 15.73426

PAL-M 858 720 525 13.5 3.57561149 15.73426

PAL-B, D, G, H, I 864 720 625 13.5 4.43361875 15.625

PAL-N 864 720 625 13.5 4.43361875 15.625 PAL-Nc 864 720 625 13.5 3.58205625 15.625 SECAM 864 720 625 13.5 4.40625/4.25 15.625

PIXEL HORIZONTAL

FREQUENCY LINE RATE

(MHz) (kHz)

COLOR

(MHz)

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3.12 Synchronization Signals

External (discrete) syncs are provided via the following signals:

• VSYNC (vertical sync)

• FID/VLK (field indicator or vertical lock indicator)

• GPCL/VBLK (general-purpose I/O or vertical blanking indicator)

• PALI/HLK (PAL switch indicator or horizontal lock indicator)

• HSYNC (horizontal sync)

• AVID (active video indicator)

VSYNC, FID, PALI, and VBLK are software set and programmable to the CLK pixel count. This allows any

possible alignment to the internal pixel count and line count. The default settings for a 525-/625-line video

output are shown in Figure 3-4.

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Composite

Video

525

VSYNC

GPCL/VBLK

FID

1 2 3 4 5 6 7 8 9 10 11 20 21 22

525 LINE

262 263 264 265 266 267 268 269 270 271 272 273 282 283 284

310 311 312 313 314 315 316 317 318 319 320 333 334 335 336

622 623 624 625 1 2 3 4 5 6 7 20 21 22 23

625 LINE

Composite

Video

VSYNC

GPCL/VBLK

FID

Composite

Video

VSYNC

GPCL/VBLK

FID

Composite

Video

VSYNC

GPCL/VBLK

FID

↔

VBLK Start

↔

VBLK Stop

↔

VBLK Start

↔

VBLK Stop

↔

VBLK Start

↔

VBLK Stop

↔

VBLK Start

↔

VBLK Stop

Line numbering conforms to ITU-R BT.470.

HSYN AVID

AVID STOP

AVID START

HSYN START

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NOTE: AVID rising edge occurs four CLK cycles early when in ITU-R BT.656 output mode.

3.13 Active Video (AVID) Cropping

AVID cropping provides a means to decrease the amount of video data output. This is accomplished by

horizontally blanking a number of AVID pulses and by vertically blanking a number of lines per frame. The

horizontal AVID cropping is controlled using registers 11h and 12h for start pixels MSB and LSB,

respectively.

Figure 3-4. 8-Bit 4:2:2, Timing With 2× Pixel Clock (CLK) Reference

Figure 3-5. Horizontal Synchronization Signals

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VSYNC

HSYNC

Active Video Area

AVID Cropped Area

AVID

Stop

AVID Start

VBLK

Start

VBLK

Stop

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Registers 13h and 14h provide access to stop pixels MSB and LSB, respectively. The vertical AVID

cropping is controlled using the vertical blanking (VBLK) start and stop registers at addresses 18h and

19h. Figure 3-6 shows an AVID application.

AVID cropping can be independently controlled for scaled (registers 25h, 26h, 29h, and 2Ah) and

unscaled (registers 11h thru 14h) data streams. AVID start and stop must be changed in multiples of two

pixels to ensure correct UV alignment.

Additionally, AVID start and stop can be configured to include the SAV- and EAV-embedded sync signals

or to exclude them, and to either include or exclude ITU656 ancillary data.

The above settings alter AVID output timing, but the video output data is not forced to black level outside of the AVID interval.

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NOTE

Figure 3-6. AVID Application

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3.14 Embedded Syncs

Standards with embedded syncs insert SAV and EAV codes into the data stream at the beginning and end

of horizontal blanking. These codes contain the V and F bits that also define vertical timing. F and V

change on EAV. Table 3-4 gives the format of the SAV and EAV codes.

H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line

and field counter varies depending on the standard. See ITU-R BT.656 for more information on embedded

syncs.

The P bits are protection bits:

P3 = V x or H P2 = F x or H P1 = F x or V P0 = F x or V x or H

Table 3-4. EAV and SAV Sequence

8-BIT DATA

D7 (MSB) D6 D5 D4 D3 D2 D1 D0

Preamble 1 1 1 1 1 1 1 1 Preamble 0 0 0 0 0 0 0 0 Preamble 0 0 0 0 0 0 0 0 Status word 1 F V H P3 P2 P1 P0

The status word may be modified to pass information about whether the current data corresponds to

scaled or unscaled data. See register 1Fh for more information.

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Decoder

Scaler

Delay

54MHz

/2 =

SCLK

CLK

Data

Mode

CLK edge

SCLK edge

Mode

=2/3

!=3

CLK OE

SCLK OE

Blank

=01

=11

=00

Decoder

Scaler

Delay

54 MHz

/2 =

27 MHz

SCLK

CLK

Data

Mode

CLK edge

SCLK edge

Mode

=2/3

!=3

CLK OE

SCLK OE

Blank

=01

=11

=00

Field mode(0) Field mode(1) Field mode(2) Field mode(3) Field mode(4) Field mode(5) Field mode(6) Field mode(7) Field mode(8)

Field mode(9) Field mode(10) Field mode(11) Field mode(12) Field mode(13) Field mode(14) Field mode(15)

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3.15 Clock and Data Control

Figure 3-7 shows a logical schematic of the data and clock control signals.

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Figure 3-7. Clock and Data Control

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4 I2C Host Interface

The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which carry information between the devices connected to the bus. The input pins I2CA0 and I2CA1 are used to select the slave address to which the device responds. Although the I2C system can be multimastered, the TVP5154A decoder functions as a slave device only.

Both SDA and SCL must be connected to IOVDD via pullup resistors. When the bus is free, both lines are high. The slave address select terminals (I2CA0 and I2CA1) enable the use of four TVP5154A decoders on the same I2C bus. At the trailing edge of reset, the status of the I2CA0 and I2CA1 lines are sampled to determine the device address used. Table 4-1 summarizes the terminal functions of the I2C-mode host interface. Table 4-2 shows the device address selection options.

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

Table 4-1. I2C Terminal Description

SIGNAL TYPE DESCRIPTION

I2CA0 I Slave address selection I2CA1 I Slave address selection

SCL I/O (open drain) Input/output clock line SDA I/O (open drain) Input/output data line

Table 4-2. I2C Host Interface Device Addresses

A6 A5 A4 A3 A2 A1 (I2CA1) A0 (I2CA0) R/W HEX

1 0 1 1 1 0 0 1/0 B9/B8 1 0 1 1 1 0 1 1/0 BB/BA 1 0 1 1 1 1 0 1/0 BD/BC 1 0 1 1 1 1 1 1/0 BF/BE

Data transfer rate on the bus is up to 400 kbit/s. The number of interfaces connected to the bus is dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the SCL, except for start and stop conditions. The high or low state of the data line can only change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the SCL is high indicates an I2C start condition. A low-to-high transition on the SDA line while the SCL is high indicates an I2C stop condition.

Every byte placed on the SDA must be eight bits long. The number of bytes that can be transferred is unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the I2C master.

To simplify programming of each of the four decoder channels, a single I2C write transaction can be transmitted to any one or more of the four cores in parallel. This reduces the time required to download firmware or to configure the device when all channels are to be configured in the same manner. It also enables the addresses for all registers to be common across all decoders.

I2C sub-address 0xFE contains four bits, with each bit corresponding to one of the decoder cores. If this bit is set, I2C write transactions are sent to the corresponding decoder core. If the bit is 0, the corresponding decoder does not receive the I2C write transactions.

I2C sub-address 0xFF contains four bits, with each bit corresponding to one of the decoder cores. If this bit is set, I2C read transactions are sent to the corresponding decoder core. Note, only one of the bits in this register should be set at a given time, ensuring that only one decoder core is accessed at a time for read operations. If more than one bit is set, the lowest set bit number corresponds to the core that responds to the read transaction.

Note that, when register 0xFE is written to with any value, register 0xFF is set to 0x00. Likewise, when register 0xFF is written to with any value, register 0xFE is set to 0x00.

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4.1 I2C Write Operation

Data transfers occur utilizing the following illustrated formats. An I2C master initiates a write operation to the TVP5154A decoder by generating a start condition (S)

followed by the TVP5154A I2C address (as shown below), in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the TVP5154A decoder, the master presents the sub-address of the register, or the first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The TVP5154A decoder acknowledges each byte after completion of each transfer. The I2C master terminates the write operation by generating a stop condition (P).

Step 1 0

I2C start (master) S

Step 2 7 6 5 4 3 2 1 0

I2C general address (master) 1 0 1 1 1 0 X 0

Step 3 9

I2C acknowledge (slave) A

Step 4 7 6 5 4 3 2 1 0

I2C write register address (master) addr addr addr addr addr addr addr addr

Step 5 9

I2C acknowledge (slave) A

Step 6 7 6 5 4 3 2 1 0

I2C write data (master) Data Data Data Data Data Data Data Data

(1)

Step 7

I2C acknowledge (slave) A

Step 8 0

I2C stop (master) P

(1) Repeat steps 6 and 7 until all data have been written.

4.2 I2C Read Operation

The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates a write operation to the TVP5154A decoder by generating a start condition (S) followed by the TVP5154A I2C address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the TVP5154A decoder, the master presents the sub-address of the register or the first of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition (P).

The second phase is the data phase. In this phase, an I2C master initiates a read operation to the TVP5154A decoder by generating a start condition followed by the TVP5154A I2C address (as shown below for a read operation), in MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TVP5154A decoder, the I2C master receives one or more bytes of data from the TVP5154A decoder. The I2C master acknowledges the transfer at the end of each byte. After the last data byte desired has been transferred from the TVP5154A decoder to the master, the master generates a not acknowledge followed by a stop.

I2C Host Interface

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Read Phase 1

Step 1 0

I2C start (master) S

Step 2 7 6 5 4 3 2 1 0

I2C general address (master) 1 0 1 1 1 0 X 0

Step 3 9

I2C acknowledge (slave) A

Step 4 7 6 5 4 3 2 1 0

I2C read register address (master) addr addr addr addr addr addr addr addr

Step 5 9

I2C acknowledge (slave) A

Step 6 0

I2C stop (master) P

Read Phase 2

Step 7 0

I2C start (master) S

Step 8 7 6 5 4 3 2 1 0

I2C general address (master) 1 0 1 1 1 0 X 1

Step 9 9

I2C acknowledge (slave) A

Step 10 7 6 5 4 3 2 1 0

I2C read data (slave) Data Data Data Data Data Data Data Data

(1)

Step 11

I2C not acknowledge (master) A

Step 12 0

I2C stop (master) P

(1) Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.

4.2.1 I2C Timing Requirements

The TVP5154A decoder requires delays in the I2C accesses to accommodate its internal processor's timing. In accordance with I2C specifications, the TVP5154A decoder holds the I2C clock line (SCL) low to indicate the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition, the maximum delays must always be inserted where required. These delays are of variable length; maximum delays are indicated in the following diagram:

Table 4-3. I2C Timing

Start Ack Subaddress Ack Data (XXh) Ack Wait 128 µs

(1) If the SCL pin is not monitored by the master to enable pausing, a delay of 128 µs should be inserted between transactions for registers

00h through 8Fh.

Slave address

(B8h)

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(1)

Stop

124

XIN/OSC

14.31818-MHz Crystal

XOUT

123

TVP5154A

124

XIN/OSC

XOUT

123

TVP5154A

14.31818 -MHz

1.8-V Clock

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5 Clock Circuits

An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive the PLL. This may be input to the TVP5154A decoder on terminal 124 (XIN), or a crystal of

14.31818-MHz fundamental resonant frequency may be connected across terminals 123 and 124 (XIN and XOUT). Figure 5-1 shows the reference clock configurations. For the example crystal circuit shown (a parallel-resonant crystal with 14.31818-MHz fundamental frequency), the external capacitors must have the following relationship:

CL1= CL2= 2CL– C

where C

is the terminal capacitance with respect to ground and CLis the crystal load capacitance

STRAY

specified by the crystal manufacturer. Figure 5-1 shows the reference clock configurations.

NOTE: The resistor (R) in parallel with the crystal is recommended to support a wide range of crystal types. A 100-kΩ resistor

may be used for most crystal types.

STRAY

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Figure 5-1. Clock and Crystal Connectivity

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dto

ctrl

clk

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6 Genlock Control and RTC

A Genlock control (GLCO) function is provided to support a standard video encoder to synchronize its internal color oscillator for properly reproduced color with unstable timebase sources like VCRs.

The frequency control word of the internal color subcarrier digital control oscillator (DTO) and the subcarrier phase reset bit are transmitted via the GLCO terminal. The frequency control word is a 23-bit binary number. The frequency of the DTO can be calculated from the following equation:

where F of the CLK.

6.1 TVP5154A Genlock Control Interface

A write of 1 to bit 4 of the chrominance control register at I2C subaddress 1Ah causes the subcarrier DTO phase reset bit to be sent on the next scan line on GLCO. The active-low reset bit occurs seven CLKs after the transmission of the last bit of DCO frequency control. Upon the transmission of the reset bit, the phase of the TVP5154A internal subcarrier DCO is reset to zero.

A Genlock slave device can be connected to the GLCO terminal and uses the information on GLCO to synchronize its internal color phase DCO to achieve clean line and color lock.

6.2 RTC Mode

is the frequency of the DTO, F

dto

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

is the 23–bit DTO frequency control, and F

ctrl

is the frequency

clk

(1)

Figure 6-1 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is four times slower

than the GLCO clock rate. For PLL frequency control, the upper 22 bits are used. Each frequency control bit is two clock cycles long. The active-low reset bit occurs six CLKs after the transmission of the last bit of PLL frequency control.

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CLK

GLCO

23-Bit Frequency Control

Start Bit DCO Reset Bit

MSB

>128 CLK

1 CLK

7 CLK23 CLK

1 CLK

LSB

22 21

RTC

M S B

16 CLK

L S B

128 CLK

22-Bit Fsc Frequency Control

Start

Bit

Reset

Bit

2 CLK

1 CLK

2 CLK

3 CLK

1 CLK

PAL

Switch

44 CLK

GLCO Timing

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Figure 6-1. RTC Timing

6.3 Reset and Power Down

The RESETB and PDN terminals work together to put the TVP5154A decoder into one of the two modes.

Table 6-1 shows the configuration.

After power-up, the device is in an unknown state with its outputs undefined, until it receives a RESETB signal as depicted in Figure 6-2. After RESETB is released, the data (CHn_OUT[7:0]), sync (HSYNCn, VSYNCn/PALIn), and clock (CLKn, SCLKn) outputs are Hi-Z until the chip is initialized and the outputs are activated.

I2C SCL and SDA signals must not change state until the TVP5154A reset sequence has been completed.

NOTE

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RESETB

Normal Operation

Reset

PLL_AVDD

DVDD

IO_DVDD

SDA

PDN

SCL

Data

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Table 6-1. Reset and Power-Down Modes

PDN RESETB CONFIGURATION

0 0 Reserved (unknown state) 0 1 Powers down the decoder 1 0 Resets the decoder 1 1 Normal operation

Figure 6-2. Power-On Reset Timing

Table 6-2. Power-On Reset Timing

NO. PARAMETER MIN MAX UNIT

t1 Delay time between power supplies active and reset 20 ms t2 RESETB pulse duration 500 ns t3 Delay time between end of reset to I2C active 200 µs

6.4 Reset Sequence

Table 6-3 shows the reset sequence of the TVP5154A pins status during reset time and immediately after

reset time.

Table 6-3. Reset Sequence

PIN DESCRIPTION DURING RESETB

INTREQ1/GPCL1/VBLK1, INTREQ2/GPCL2/VBLK2, INTREQ3/GPCL3/VBLK3, INTREQ4/GPCL4/VBLK4, HSYNC1, HSYNC2, HSYNC3, HSYNC4, VSYNC1/PALI1, VSYNC2/PALI2, VSYNC3/PALI3, VSYNC4/PALI4, CH1_OUT[7:0], CH2_OUT[7:0], CH3_OUT[7:0], CH4_OUT[7:0],

AIP1A, AIP1B, AIP2A, AIP2B, AIP3A, AIP3B, AIP4A, AIP4B, RESETB, PDN, SDA, SCL, I2CA0, I2CA1, XIN/OSC, TMS

FID1/GLCO1, FID2/GLCO2, FID3/GLCO3, FID4/GLCO4, AVID1, AVID2, AVID3, AVID4, CLK1, CLK2, CLK3, CLK4, SCLK1, SCLK2, SCLK3, SCLK4, XOUT

3-state 3-state

Input Input

Output Output

IMMEDIATELY

AFTER RESETB

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7 Internal Control Registers

7.1 Overview

The TVP5154A decoder is initialized and controlled by sets of internal registers that set all device operating parameters. Communication between the external controller and the TVP5154A decoder is through the I2C. Two sets of registers exist, direct and indirect. Table 7-1 shows the summary of the direct registers. Reserved registers must not be written. Reserved bits in the defined registers must be written with zeros, unless otherwise noted. The detailed programming information of each register is described in the following sections.

I2C register FEh controls which of the four decoders receives I2C commands. I2C register FFh controls which decoder core responds to I2C reads. Note, for a read operation, it is necessary to perform a write first, to set the desired sub-address for reading.

After power up and the hardware reset, each decoder must be started by writing 00h to register 7Fh for all four decoders.

Table 7-1. Direct Register Summary

Video input source selection #1 00h 00h R/W Analog channel controls 01h 15h R/W Operation mode controls 02h 00h R/W Miscellaneous controls 03h 01h R/W Autoswitch mask 04h DCh R/W Clock control 05h 08h R/W Color killer threshold control 06h 10h R/W Luminance processing control #1 07h 60h R/W Luminance processing control #2 08h 00h R/W Brightness control 09h 80h R/W Color saturation control 0Ah 80h R/W Hue control 0Bh 00h R/W Contrast control 0Ch 80h R/W Outputs and data rates select 0Dh 47h R/W Luminance processing control #3 0Eh 00h R/W Configuration shared pins 0Fh 08h R/W Reserved 10h Active video cropping start MSB for unscaled data 11h 00h R/W Active video cropping start LSB for unscaled data 12h 00h R/W Active video cropping stop MSB for unscaled data 13h 00h R/W Active video cropping stop LSB for unscaled data 14h 00h R/W Genlock/RTC 15h 01h R/W Horizontal sync start 16h 80h R/W Ancillary SAV/EAV control 17h 52h R/W Vertical blanking start 18h 00h R/W Vertical blanking stop 19h 00h R/W Chrominance processing control #1 1Ah 0Ch R/W Chrominance processing control #2 1Bh 14h R/W Interrupt reset register B 1Ch 00h R/W Interrupt enable register B 1Dh 00h R/W

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(1)

(1) R = Read only, W = Write only, R/W = Read and write

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TVP5154A

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SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

Table 7-1. Direct Register Summary (continued)

Interrupt configuration register B 1Eh 00h R/W Output control 1Fh 00h R/W Reserved 20h Indirect Register Data 21h–22h 00h R/W Indirect Register Address 23h 00h R/W Indirect Register Read/Write Strobe 24h 00h R/W AVID start/control for scaled data 25h–26h 00h R/W Reserved 27h Video standard 28h 00h R/W AVID stop for scaled data 29h–2Ah 00h R/W Reserved 2Bh Cb gain factor 2Ch R Cr gain factor 2Dh R Reserved 2Eh–2Fh 656 Revision Select 30 00h R/W Reserved 31h–7Dh Patch Write Address 7Eh 00h R/W Patch Code Execute 7Fh 00h R/W MSB of device ID 80h 51h R LSB of device ID 81h 54h R ROM major version 82h 02h R ROM minor version 83h 00h R Vertical line count MSB 84h R Vertical line count LSB 85h R Interrupt status register B 86h R Interrupt active register B 87h R Status register #1 88h R Status register #2 89h R Status register #3 8Ah R Status register #4 8Bh R Status register #5 8Ch R Reserved 8Dh Patch Read Address 8Eh 00h R/W Reserved 8Fh Closed caption data registers 90h–93h R WSS/CGMS-A data registers 94h–99h R VPS/Gemstar 2x data registers 9Ah–A6h R VITC data registers A7h–AFh R VBI FIFO read data B0h R Teletext filter 1 B1h–B5h 00h R/W Teletext filter 2 B6h–BAh 00h R/W Teletext filter enable BBh 00h R/W Reserved BCh–BFh Interrupt status register A C0h 00h R/W Interrupt enable register A C1h 00h R/W Interrupt configuration C2h 04h R/W

(1)

(2)

(2) These registers are used for firmware patch code and should not be written to or read from during

normal operation.

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TVP5154A

SLES214C–DECEMBER 2007–REVISED SEPTEMBER 2010

Table 7-1. Direct Register Summary (continued)

VDP configuration RAM data C3h B8h R/W Configuration RAM address low byte C4h 1Fh R/W Configuration RAM address high byte C5h 00h R/W VDP status register C6h R FIFO word count C7h R FIFO interrupt threshold C8h 80h R/W FIFO reset C9h 00h W Line number interrupt CAh 00h R/W Pixel alignment register low byte CBh 4Eh R/W Pixel alignment register high byte CCh 00h R/W FIFO output control CDh 01h R/W Reserved CEh Full field enable CFh 00h R/W

Line mode registers R/W Full field mode register FCh 7Fh R/W

Reserved FDh Decoder core write enables FEh 0Fh R/W Decoder core read enables FFh 00h R/W

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(1)

D0h 00h

D1h–FBh FFh

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