Texas instruments TVP5150AM1 Data Manual

TVP5150AM1

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Ultralow-Power NTSC/PAL/SECAM Video Decoder

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1 Introduction

1.1 Features

• Accepts NTSC (J, M, 4.43), PAL (B, D, G, H, I, • Standard Programmable Video Output Formats M, N, Nc), and SECAM (B, D, G, K, K1, L) Video

• Supports ITU-R BT.601 Standard Sampling Syncs

• High-Speed 9-Bit Analog-to-Digital Converter – 8-Bit 4:2:2 With Discrete Syncs (ADC)

• Two Composite Inputs or One S-Video Input

• Fully Differential CMOS Analog Preprocessing Formats Channels With Clamping and Automatic Gain Control (AGC) for Best Signal-to-Noise (S/N) Performance

• Ultralow Power Consumption

• 48-Terminal PBGA Package (ZQC) or 32-Terminal TQFP Package (PBS)

• Power-Down Mode: <1 mW

• Brightness, Contrast, Saturation, Hue, and Sharpness Control Through I2C

• Complementary 4-Line (3-H Delay) Adaptive Comb Filters for Both Cross-Luminance and Cross-Chrominance Noise Reduction

• Patented Architecture for Locking to Weak, Noisy, or Unstable Signals

• Single 14.31818-MHz Crystal for All Standards

• Internal Phase-Locked Loop (PLL) for Data Signals Line-Locked Clock and Sampling

• Subcarrier Genlock Output for Synchronizing Color Subcarrier of External Encoder

• 3.3-V Digital I/O Supply Voltage Range

– ITU-R BT.656, 8-Bit 4:2:2 With Embedded

• Macrovision™ Copy Protection Detection

• Advanced Programmable Video Output

– 2× Oversampled Raw Vertical Blanking

Interval (VBI) Data During Active Video

– Sliced VBI Data During Horizontal Blanking

or Active Video

• VBI Modes Supported – Teletext (NABTS, WST) – Closed-Caption Decode With FIFO and

Extended Data Services (XDS)

– Wide Screen Signaling, Video Program

System, CGMS-A, Vertical Interval Time Code

– Gemstar 1x/2x Electronic Program Guide

Compatible Mode

– Custom Configuration Mode That Allows

User to Program Slice Engine for Unique VBI

• Power-On Reset

• Industrial Temperature Range (TVP5150AM1I): –40°C to 85°C

• Qualified for Automotive Applications (AEC-Q100 Rev G – TVP5150AM1IPBSQ1, TVP5150AM1IPBSRQ)

1.2 Description

The TVP5150AM1 device is an ultralow-power NTSC/PAL/SECAM video decoder. Available in a space-saving 48-terminal PBGA package or a 32-terminal TQFP package, the TVP5150AM1 decoder converts NTSC, PAL, and SECAM video signals to 8-bit ITU-R BT.656 format. Discrete syncs are also available. The optimized architecture of the TVP5150AM1 decoder allows for ultralow power consumption. The decoder consumes 115-mW power under typical operating conditions and consumes less than 1 mW in power-down mode, considerably increasing battery life in portable applications. The decoder uses just one crystal for all supported standards. The TVP5150AM1 decoder can be programmed using an I2C serial interface.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testingof all parameters.

TVP5150AM1

SLES209D–NOVEMBER 2007–REVISED SEPTEMBER 2010

The TVP5150AM1 decoder converts baseband analog video into digital YCbCr 4:2:2 component video. Composite and S-video inputs are supported. The TVP5150AM1 decoder includes one 9-bit analog-to-digital converter (ADC) with 2× sampling. Sampling is ITU-R BT.601 (27.0 MHz, generated from the 14.31818-MHz crystal or oscillator input) and is line locked. The output formats can be 8-bit 4:2:2 or 8-bit ITU-R BT.656 with embedded synchronization.

The TVP5150AM1 decoder utilizes Texas Instruments patented technology for locking to weak, noisy, or unstable signals. A Genlock/real-time control (RTC) output is generated for synchronizing downstream video encoders.

Complementary four-line adaptive comb filtering is available for both the luminance and chrominance data paths to reduce both cross-luminance and cross-chrominance artifacts; a chrominance trap filter is also available.

Video characteristics including hue, brightness, saturation, and sharpness may be programmed using the industry standard I2C serial interface. The TVP5150AM1 decoder generates synchronization, blanking, lock, and clock signals in addition to digital video outputs. The TVP5150AM1 decoder includes methods for advanced vertical blanking interval (VBI) data retrieval. The VBI data processor slices, parses, and performs error checking on teletext, closed caption, and other data in several formats.

The TVP5150AM1 decoder detects copy-protected input signals according to the Macrovision™ standard and detects Type 1, 2, 3, and colorstripe processes.

The main blocks of the TVP5150AM1 decoder include:

• Robust sync detector

• ADC with analog processor

• Y/C separation using four-line adaptive comb filter

• Chrominance processor

• Luminance processor

• Video clock/timing processor and power-down control

• Output formatter

• I2C interface

• VBI data processor

• Macrovision detection for composite and S-video

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1.3 Applications

The following is a partial list of suggested applications:

• Digital televisions

• PDAs

• Notebook PCs

• Cell phones

• Video recorder/players

• Internet appliances/web pads

• Handheld games

• Surveillance

• Portable navigation

• Portable video projectors

1.4 Related Products

• TVP5151

• TVP5154A

• TVP5146M2

• TVP5147M1

• TVP5158

SLES209D–NOVEMBER 2007–REVISED SEPTEMBER 2010

1.5 Trademarks

TI and MicroStar Junior are trademarks of Texas Instruments. Macrovision is a trademark of Macrovision Corporation. Gemstar is a trademark of Gemstar-TV Guide International. Other trademarks are the property of their respective owners.

1.6 Document Conventions

Throughout this data manual, several conventions are used to convey information. These conventions are:

• To identify a binary number or field, a lower case b follows the numbers. For example, 000b is a 3-bit binary field.

• To identify a hexadecimal number or field, a lower case h follows the numbers. For example, 8AFh is a 12-bit hexadecimal field.

• All other numbers that appear in this document that do not have either a b or h following the number are assumed to be decimal format.

• If the signal or terminal name has a bar above the name (for example, RESETB), this indicates the logical NOT function. When asserted, this signal is a logic low, 0, or 0b.

• RSVD indicates that the referenced item is reserved.

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1.7 Ordering Information

0°C to 70°C

-40°C to 85°C

(1) For the most current package and ordering information, see the Package Option Addendum at the end

of this document, or see the TI web site at www.ti.com. (2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. (3) AEC-Q100 Rev G Certified

PACKAGED DEVICES

(1) (2)

PACKAGE OPTION

TVP5150AM1PBS Tray

TVP5150AM1PBSR Tape and reel

TVP5150AM1ZQC Tray

TVP5150AM1ZQCR Tape and reel

TVP5150AM1IPBS Tray

TVP5150AM1IPBSR Tape and reel

TVP5150AM1IPBSQ1

TVP5150AM1IPBSRQ1

(3)

Tape and reel

TVP5150AM1IZQC Tray

TVP5150AM1IZQCR Tape and reel

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Tray

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1 Introduction .............................................. 1

1.1 Features .............................................. 1

1.2 Description ........................................... 1 3.15 I2C Host Interface ................................... 19

1.3 Applications .......................................... 3 3.16 Clock Circuits ....................................... 22

1.4 Related Products ..................................... 3

1.5 Trademarks .......................................... 3

1.6 Document Conventions .............................. 3

1.7 Ordering Information ................................. 4

2 Device Details ............................................ 6

2.1 Functional Block Diagram ............................ 6

2.2 Terminal Diagrams ................................... 7

2.3 Terminal Functions ................................... 8

4 Electrical Specifications ............................. 74

3 Functional Description ............................... 10

3.1 Analog Front End ................................... 10

3.2 Composite Processing Block Diagram ............. 10

3.3 Adaptive Comb Filtering ............................ 11

3.4 Color Low-Pass Filter ............................... 12

3.5 Luminance Processing ............................. 13

3.6 Chrominance Processing ........................... 13

3.7 Timing Processor ................................... 13

3.8 VBI Data Processor (VDP) ......................... 13

3.9 VBI FIFO and Ancillary Data in Video Stream ..... 14

3.10 Raw Video Data Output ............................ 15

3.11 Output Formatter ................................... 15

3.12 Synchronization Signals ............................ 15

5 Example Register Settings .......................... 78

6 Application Information .............................. 80

7 Revision History ....................................... 81

SLES209D–NOVEMBER 2007–REVISED SEPTEMBER 2010

3.13 Active Video (AVID) Cropping ...................... 17

3.14 Embedded Syncs ................................... 18

3.17 Genlock Control (GLCO) and RTC ................. 23

3.18 Reset and Power Down ............................ 24

3.19 Reset Sequence .................................... 26

3.20 Internal Control Registers .......................... 27

3.21 Register Definitions ................................. 30

4.1 Absolute Maximum Ratings ........................ 74

4.2 Recommended Operating Conditions .............. 74

4.3 Reference Clock Specifications .................... 74

4.4 Electrical Characteristics ........................... 75

4.5 DC Electrical Characteristics ....................... 75

4.6 Analog Electrical Characteristics ................... 75

4.7 Clocks, Video Data, Sync Timing ................... 76

4.8 I

C Host Port Timing ................................ 77

4.9 Thermal Specifications ............................. 77

5.1 Example 1 .......................................... 78

5.2 Example 2 .......................................... 79

6.1 Application Example ................................ 80

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M U X

AIP1A

AIP1B

PGA

A/D

Output

Formatter

YOUT[7:0] YCbCr 8-Bit 4:2:2

VBI Data

Processor (VDP)

Embedded Processor

XTAL1/OSC

XTAL2

PCLK/SCLK

Horizontal and

Color PLLs

FID/GLCO

VSYNC/PALI

INTREQ/GPCL/VBLK

HSYNC

Timing Processor

SCL

SDA

Y/C Separation

Chrominance

Processing

Luminance Processing

Macrovision

Detection

Host

Interface

AVID

PDN

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2 Device Details

2.1 Functional Block Diagram

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Figure 2-1. Functional Block Diagram

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2 3 4 5 6

PBGA (ZQC) PACKAGE

(BOTTOMVIEW)

TQFP (PBS) PACKAGE

(TOP VIEW)

31 30 29 28 27

PCLK/SCLK

IO_DVDD

YOUT7/I2CSEL

YOUT6

YOUT5

YOUT4

YOUT3

YOUT2

CH_A

VDD

CH_AGND

REFM

REFP

PDN

INTREQ/GPCL/VBLK

AVID

HSYNC

32 26 25

VSYNC/PALI FID/GLCO SDA SCL DVDD DGND YOUT0 YOUT1

AIP1A AIP1B

PLL_AGND

PLL_AVDD

XTAL1/OSC

XTAL2

AGND

RESETB

10 11 12 13 149 15 16

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2.2 Terminal Diagrams

The TVP5150AM1 video decoder is packaged in a 48-terminal PBGA package or a 32-terminal TQFP package. Figure 2-2 shows the terminal diagrams for both packages. Table 2-1 gives a description of the terminals.

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Figure 2-2. Terminal Diagrams

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2.3 Terminal Functions

Table 2-1. Terminal Functions

TERMINAL

NAME

Analog Section

AGND E1 7 G Substrate. Connect to analog ground.

AIP1A A1 1 I range is 0-0.75 VPP, and may require an attenuator to reduce the input amplitude to the

AIP1B B1 2 I range is 0-0.75 VPP, and may require an attenuator to reduce the input amplitude to the

CH_AGND A3 31 G Analog ground CH_AVDD A2 32 P Analog supply. Connect to 1.8-V analog supply.

NC – – No connect

PLL_AGND C2 3 G PLL ground. Connect to analog ground. PLL_AVDD C1 4 P PLL supply. Connect to 1.8-V analog supply.

REFM A4 30 O

REFP B4 29 O XTAL1/OSC D2 5 I External clock reference input. XTAL2 D1 6 O

Digital Section

AVID A6 26 O video AVID output. AVID toggling during vertical blanking intervals is controlled by bit 2 of

DGND E6 19 G Digital ground DVDD E7 20 P Digital supply. Connect to 1.8-V digital supply.

FID/GLCO C6 23 O GLCO: This serial output carries color PLL information. A slave device can decode the

HSYNC A7 25 O Horizontal synchronization signal

NO. I/O DESCRIPTION

ZQC PBS

Analog input. Connect to the video analog input via 0.1-µF capacitor. The maximum input desired level. If not used, connect to AGND via a 0.1-µF capacitor (see Figure 6-1).

B2, B3, B6, C4,

C5, D3–D6, E2–E5,

F2, F5, F6

A/D reference negative output. Connect to analog ground through a 1-µF capacitor. Also, it is recommended to connect directly to REFP through a 1-µF capacitor (see Figure 6-1).

A/D reference positive output. Connect to analog ground through a 1-µF capacitor (see

Figure 6-1).

External clock reference output. Not connected if XTAL1 is driven by an external single-ended oscillator.

Active video indicator output. This signal is high during the horizontal active time of the the active video cropping start pixel LSB register at address 12h (see Section 3.21.17).

FID: Odd/even field indicator or vertical lock indicator. For the odd/even indicator, a 1 indicates the odd field.

information to allow chrominance frequency control from the TVP5150AM1 decoder. Data is transmitted at the SCLK rate in Genlock mode. In RTC mode, SCLK/4 is used.

INTREQ: Interrupt request output

INTREQ/GPCL/ VBLK

IO_DVDD G2 10 P Digital output supply. Connect to 3.3-V digital supply. PCLK/SCLK G1 9 O System clock at either 1× or 2× the frequency of the pixel clock.

PDN A5 28 I

RESETB F1 8 I

B5 27 O

GPCL/VBLK: General-purpose control logic. This terminal has two functions:

• GPCL: General-purpose output. In this mode the state of GPCL is directly programmed via I2C.

• VBLK: Vertical blank output. In this mode the GPCL terminal indicates the vertical blanking interval of the output video. The beginning and end times of this signal are programmable via I2C.

Power-down terminal (active low). Puts the decoder in standby mode. Preserves the value of the registers.

Active-low reset. RESETB can be used only when PDN = 1. When RESETB is pulled low, it resets all the registers and restarts the internal microprocessor.

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Table 2-1. Terminal Functions (continued)

TERMINAL

NAME

SCL D7 21 I/O I2C serial clock (open drain) SDA C7 22 I/O I2C serial data (open drain)

VSYNC/PALI B7 24 O

YOUT[6:0] G5 15 O ITU-R BT.656 output/YCbCr 4:2:2 output with discrete syncs

YOUT7/I2CSEL F3 11 I/O

NO. I/O DESCRIPTION

ZQC PBS

VSYNC: Vertical synchronization signal PALI: PAL line indicator or horizontal lock indicator. For the PAL line indicator:

1 = Noninverted line 0 = Inverted line

G3 12 F4 13 G4 14

G6 16 G7 17 F7 18

I2CSEL: Determines address for I2C (sampled during reset). A pullup or pulldown resistor is needed (>1 kΩ) to program the terminal to the desired address. 1 = Address is BAh 0 = Address is B8h

YOUT7: Most significant bit (MSB) of ITU-R BT.656 output/YCbCr 4:2:2 output

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3 Functional Description

3.1 Analog Front End

The TVP5150AM1 decoder has an analog input channel that accepts two video inputs that are ac-coupled. The decoder supports a maximum input voltage range of 0.75 V; therefore, an attenuation of one-half is needed for most input signals with a peak-to-peak variation of 1.5 V. The nominal parallel termination before the input to the device is recommended to be 75 Ω. See the application diagram in

Figure 6-1 for the recommended configuration. The two analog input ports can be connected as either of

the following:

• Two selectable composite video inputs

• One S-video input An internal clamping circuit restores the sync-tip of the ac-coupled video signal to a fixed dc level. The programmable gain amplifier (PGA) and the automatic gain control (AGC) algorithm work together to

make sure that the input signal is amplified sufficiently to ensure the proper input range for the ADC. The ADC has nine bits of resolution and runs at a nominal speed of 27 MHz. The clock input for the ADC

comes from the horizontal PLL.

3.2 Composite Processing Block Diagram

The composite processing block processes NTSC/PAL/SECAM signals into the YCbCr color space.

Figure 3-1 shows the basic architecture of this processing block.

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Figure 3-1 shows the luminance/chrominance (Y/C) separation process in the TVP5150AM1 decoder. The

composite video is multiplied by subcarrier signals in the quadrature modulator to generate the color difference signals Cb and Cr. Cb and Cr are then low pass (LP) filtered to achieve the desired bandwidth and to reduce crosstalk.

An adaptive four-line comb filter separates CbCr from Y. Chrominance is remodulated through another quadrature modulator and subtracted from the line-delayed composite video to generate luminance. Brightness, hue, saturation, and sharpness (using the peaking filter) are programmable via I2C.

The Y/C separation is bypassed for S-video input. For S-video, the remodulation path is disabled.

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Line

Delay

Peaking

Quadrature Modulation

Notch

Filter

Color

LPF ↓ 2

4-Line

Adaptive

Comb

Filter

Burst

Accumulator

(Cr)

Notch

Filter

Delay

Brightness

Saturation

Adjust

Delay

Cb Cr

Burst

Accumulator

(Cb)

Delay

Color

LPF ↓ 2

Composite

+Delay

Gain Factor

Bandpass

Peak

Detector

Composite

SECAM Color Demodulation

Composite

SECAM Luminance

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Figure 3-1. Composite Processing Block Diagram (Comb/Trap Filter Bypassed for SECAM)

3.3 Adaptive Comb Filtering

The four-line comb filter can be selectively bypassed in the luminance or chrominance path. If the comb filter is bypassed in the luminance path, then chrominance trap filters are used which are shown in

Figure 3-2 and Figure 3-3. TI's patented adaptive four-line comb filter algorithm reduces artifacts such as

hanging dots at color boundaries and detects and properly handles false colors in high-frequency luminance images such as a multiburst pattern or circle pattern.

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Figure 3-2. Chrominance Trap Filter Frequency Figure 3-3. Chrominance Trap Filter Frequency

Response, NTSC ITU-R BT.601 Sampling Response, PAL ITU-R BT.601 Sampling

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3.4 Color Low-Pass Filter

In some applications, it is desirable to limit the Cb/Cr bandwidth to avoid crosstalk. This is especially true in case of video signals that have asymmetrical Cb/Cr sidebands. The color LP filters provided limit the bandwidth of the Cb/Cr signals. Color LP filters are needed when the comb filtering turns off, due to extreme color transitions in the input image. See Section 3.21.25, Chrominance Control #2 Register, for the response of these filters. The filters have three options that allow three different frequency responses based on the color frequency characteristics of the input video as shown in Figure 3-4.

Figure 3-4. Color Low-Pass Filter with Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling

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3.5 Luminance Processing

The luminance component is derived from the composite signal by subtracting the remodulated chrominance information. A line delay exists in this path to compensate for the line delay in the adaptive comb filter in the color processing chain. The luminance information is then fed into the peaking circuit, which enhances the high frequency components of the signal, thus improving sharpness.

3.6 Chrominance Processing

For NTSC/PAL formats, the color processing begins with a quadrature demodulator. The Cb/Cr signals then pass through the gain control stage for chrominance saturation adjustment. An adaptive comb filter is applied to the demodulated signals to separate chrominance and eliminate cross-chrominance artifacts. An automatic color killer circuit is also included in this block. The color killer suppresses the chrominance processing when the burst amplitude falls below a programmable threshold (see I2C subaddress 06h). The SECAM standard is similar to PAL except for the modulation of color which is FM instead of QAM.

3.7 Timing Processor

The timing processor is a combination of hardware and software running in the internal microprocessor that serves to control horizontal lock to the input sync pulse edge, AGC and offset adjustment in the analog front end, vertical sync detection, and Macrovision detection.

3.8 VBI Data Processor (VDP)

The TVP5150AM1 VDP slices various data services such as teletext (WST, NABTS), closed captioning (CC), wide screen signaling (WSS), etc. These services are acquired by programming the VDP to enable standards in the VBI. The results are stored in a FIFO and/or registers. The teletext results are stored only in a FIFO. Table 3-1 lists a summary of the types of VBI data supported according to the video standard. It supports ITU-R BT. 601 sampling for each.

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LINE MODE REGISTER

(D0h–FCh) BITS [3:0]

0000b WST SECAM Teletext, SECAM 0001b WST PAL B Teletext, PAL, System B 0010b WST PAL C Teletext, PAL, System C 0011b WST, NTSC B Teletext, NTSC, System B 0100b NABTS, NTSC C Teletext, NTSC, System C 0101b NABTS, NTSC D Teletext, NTSC, System D (Japan) 0110b CC, PAL Closed caption PAL 0111b CC, NTSC Closed caption NTSC 1000b WSS/CGMS-A Wide-screen signaling/Copy Generation Management System-Analog, PAL 1001b WSS/CGMS-A Wide-screen signaling/Copy Generation Management System-Analog, NTSC 1010b VITC, PAL Vertical interval timecode, PAL 1011b VITC, NTSC Vertical interval timecode, NTSC 1100b VPS, PAL Video program system, PAL 1101b Gemstar 2x Custom 1 Electronic program guide 1110b Reserved Reserved 1111b Active Video Active video/full field

Table 3-1. Data Types Supported by VDP

NAME DESCRIPTION

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At power-up the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents with the lookup table (see Section 3.21.64). This is done through port address C3h. Each read from or write to this address auto increments an internal counter to the next RAM location. To access the VDP-CRAM, the line mode registers (D0h to FCh) must be programmed with FFh to avoid a conflict with the internal microprocessor and the VDP in both writing and reading. Full field mode must also be disabled.

Available VBI lines are from line 6 to line 27 of both field 1 and field 2. Each line can be any VBI mode. Output data is available either through the VBI-FIFO (B0h) or through dedicated registers at 90h to AFh,

both of which are available through the I2C port.

3.9 VBI FIFO and Ancillary Data in Video Stream

Sliced VBI data can be output as ancillary data in the video stream in the ITU-R BT.656 mode. VBI data is output during the horizontal blanking period following the line from which the data was retrieved. Table 3-2 shows the header format and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into the FIFO. The size of FIFO is 512 bytes. Therefore, the FIFO can store up to 11 lines of teletext data with the NTSC NABTS standard.

Table 3-2. Ancillary Data Format and Sequence

BYTE NO. D6 D5 D4 D3 D2 D1 DESCRIPTION

0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 Ancillary data preamble 2 1 1 1 1 1 1 1 1 3 NEP EP 0 1 0 DID2 DID1 DID0 Data ID (DID) 4 NEP EP F5 F4 F3 F2 F1 F0 Secondary data ID (SDID) 5 NEP EP N5 N4 N3 N2 N1 N0 Number of 32-bit data (NN) 6 Video line [7:0] Internal data ID0 (IDID0)

7 0 0 0 Match 1 Match 2 Video line [9:8] Internal data ID1 (IDID1) 8 1. Data Data byte

9 2. Data Data byte 10 3. Data Data byte 11 4. Data Data byte

... ... ...

4(N+2)–1 1 0 0 0 0 0 0 0 Fill byte

EP: Even parity for D0–D5 NEP: Negated even parity DID: 91h: Sliced data of VBI lines of first field

SDID: This field holds the data format taken from the line mode register of the corresponding line. NN: Number of Dwords beginning with byte 8 through 4(N+2). This value is the number of

IDID0: Transaction video line number [7:0]

D7 D0

(MSB) (LSB)

Data error

m–1. Data Data byte

m. Data Data byte

RSVD CS[5:0] Check sum

53h: Sliced data of line 24 to end of first field 55h: Sliced data of VBI lines of second field 97h: Sliced data of line 24 to end of second field

Dwords where each Dword is 4 bytes.

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First word

Nthword

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IDID1: Bit 0/1 = Transaction video line number [9:8]

Bit 2 = Match 2 flag Bit 3 = Match 1 flag

Bit 4 = 1 if an error was detected in the EDC block; 0 if not CS: Sum of D0–D7 of DID through last data byte. Fill byte: Fill bytes make a multiple of 4 bytes from byte 0 to last fill byte.

3.10 Raw Video Data Output

The TVP5150AM1 decoder can output raw A/D video data at 2x sampling rate for external VBI slicing. This is transmitted as an ancillary data block during the active horizontal portion of the line and during vertical blanking.

3.11 Output Formatter

The YCbCr digital output can be programmed as 8-bit 4:2:2 or 8-bit ITU-R BT.656 parallel interface standard.

Table 3-3. Summary of Line Frequencies, Data Rates, and Pixel Counts

STANDARDS PIXELS PER LINES PER SUB-CARRIER

(ITU-R BT.601) LINE FRAME FREQUENCY

NTSC-J, M 858 720 525 13.5 3.579545 15.73426 NTSC-4.43 858 720 525 13.5 4.43361875 15.73426

PAL-M 858 720 525 13.5 3.57561149 15.73426

PAL-B, D, G, H, I 864 720 625 13.5 4.43361875 15.625

PAL-N 864 720 625 13.5 4.43361875 15.625

PAL-Nc 864 720 625 13.5 3.58205625 15.625

SECAM 864 720 625 13.5 4.40625/4.25 15.625

ACTIVE PIXEL HORIZONTAL

PIXELS PER FREQUENCY LINE RATE

LINE (MHz) (kHz)

COLOR

(MHz)

3.12 Synchronization Signals

External (discrete) syncs are provided via the following signals (see Figure 3-5 and Figure 3-6):

• VSYNC (vertical sync)

• FID/VLK (field indicator or vertical lock indicator)

• GPCL/VBLK (general-purpose output or vertical blanking indicator)

• PALI/HLK (PAL switch indicator or horizontal lock indicator)

• HSYNC (horizontal sync)

• AVID (active video indicator) (if set as output) The position and duration of the HSYNC, VSYNC, VBLK, and AVID outputs are I2C programmable,

providing control of synchronization timing relative to the video output.

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Composite

Video

525

VSYNC

GPCL/VBLK

FID

1 2 3 4 5 6 7 8 9 10 11 20 21 22

525 Line

262 263 264 265 266 267 268 269 270 271 272 273 282 283 284

310 311 312 313 314 315 316 317 318 319 320 333 334 335 336

622 623 624 625 1 2 3 4 5 6 7 20 21 22 23

625 Line

Composite

Video

VSYNC

GPCL/VBLK

FID

Composite

Video

VSYNC

GPCL/VBLK

FID

Composite

Video

VSYNC

GPCL/VBLK

FID

↔

VBLK Start

↔

VBLK Stop

↔

VBLK Start

↔

VBLK Stop

↔

VBLK Start

↔

VBLK Stop

↔

VBLK Start

↔

VBLK Stop

TVP5150AM1

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A. Line numbering conforms to ITU-R BT.470 and ITU-R BT.1700.

Figure 3-5. 8-Bit 4:2:2, Timing With 2× Pixel Clock (SCLK) Reference

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NTSC 601 1436

PAL 601 1436

ITU 656 Datastream

359

1437

718

1438

359

1439

719

1440

1441

1455

1459

1456

1460

HSYNC

AVID

ITU-R BT.656Timing

1583

1587

1584

1588

1711

1723

1712

1724

1713

1725

1714

1726

1715

1727

Y 0

Y 1

↔

AVID Stop

↔

AVID Start

↔

HSYNC Start

SECAM

1436 1437 1438 1439 1440

1441

1479 1480 1607 1608 1719 1720

1721 1722

1723

17241725172617

…

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A. AVID rising edge occurs four SCLK cycles early when in the ITU-R BT.656 output mode.

Figure 3-6. Horizontal Synchronization Signals

3.13 Active Video (AVID) Cropping

The AVID output signal provides a means to qualify and crop active video both horizontally and vertically. The horizontal start and stop position of the AVID signal is controlled using registers 11h-12h and 13h-14h, respectively. These registers also control the horizontal position of the embedded sync SAV/EAV codes.

SLES209D–NOVEMBER 2007–REVISED SEPTEMBER 2010

AVID vertical timing is controlled by the VBLK start and stop registers at addresses 18h and 19h. These VBLK registers have no effect on the embedded vertical sync code timing. Figure 3-7 shows an AVID application.

NOTE

The above settings alter AVID output timing, but the video output data is not forced to black level outside of the AVID interval.

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HSYNC

AVID Start AVID Stop

VBLK Stop

VBLK Start

VSYNC

AVID Cropped

Area

Active Video Area

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Figure 3-7. AVID Application

3.14 Embedded Syncs

Standards with embedded syncs insert SAV and EAV codes into the datastream at the beginning and end of horizontal blanking. These codes contain the V and F bits that also define vertical timing. F and V change on EAV. Table 3-4 gives the format of the SAV and EAV codes.

H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line and field counter varies depending on the standard. See ITU-R BT.656 for more information on embedded syncs.

The P bits are protection bits:

P3 = V xor H P2 = F xor H P1 = F xor V P0 = F xor V xor H

D7 (MSB) D6 D5 D4 D3 D2 D1 D0

Preamble 1 1 1 1 1 1 1 1 Preamble 0 0 0 0 0 0 0 0 Preamble 0 0 0 0 0 0 0 0 Status word 1 F V H P3 P2 P1 P0

Table 3-4. EAV and SAV Sequence

8-BIT DATA

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3.15 I2C Host Interface

The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which carry information between the devices connected to the bus. A third signal (I2CSEL) is used for slave address selection. Although the I2C system can be multimastered, the TVP5150AM1 decoder functions only as a slave device.

Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. When the bus is free, both lines are high. The slave address select terminal (I2CSEL) enables the use of two TVP5150AM1 decoders tied to the same I2C bus. At power up, the status of the I2CSEL is polled. Depending on the write and read addresses to be used for the TVP5150AM1 decoder, it can either be pulled low or high through a resistor. This terminal is multiplexed with YOUT7 and hence must not be tied directly to ground or IO_DVDD. Table 3-6 summarizes the terminal functions of the I2C-mode host interface.

SLES209D–NOVEMBER 2007–REVISED SEPTEMBER 2010

Table 3-5. Write Address

Selection

I2CSEL WRITE ADDRESS

0 B8h 1 BAh

Table 3-6. I2C Terminal Description

SIGNAL TYPE DESCRIPTION

I2CSEL (YOUT7) I Slave address selection

SCL I/O (open drain) Input/output clock line

SDA I/O (open drain) Input/output data line

Data transfer rate on the bus is up to 400 kbit/s. The number of interfaces connected to the bus is dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the high period of the SCL except for start and stop conditions. The high or low state of the data line can only change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the SCL is high indicates an I2C start condition. A low-to-high transition on the SDA line while the SCL is high indicates an I2C stop condition.

Every byte placed on the SDA must be eight bits long. The number of bytes which can be transferred is unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is generated by the I2C master.

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3.15.1 I2C Write Operation

Data transfers occur utilizing the following illustrated formats. An I2C master initiates a write operation to the TVP5150AM1 decoder by generating a start condition (S)

followed by the TVP5150AM1 I2C slave address (see the following illustration), in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the TVP5150AM1 decoder, the master presents the subaddress of the register, or the first of a block of registers it wants to write, followed by one or more bytes of data, MSB first. The TVP5150AM1 decoder acknowledges each byte after completion of each transfer. The I2C master terminates the write operation by generating a stop condition (P).

Step 1 0

I2C Start (master) S

Step 2 7 6 5 4 3 2 1 0

I2C slave address (master) 1 0 1 1 1 0 X 0

Step 3 9

I2C Acknowledge (slave) A

Step 4 7 6 5 4 3 2 1 0

I2C Write register address (master) Addr Addr Addr Addr Addr Addr Addr Addr

Step 5 9

I2C Acknowledge (slave) A

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Step 6 7 6 5 4 3 2 1 0

I2C Write data (master) Data Data Data Data Data Data Data Data

(1)

Step 7

I2C Acknowledge (slave) A

Step 8 0

I2C Stop (master) P

(1) Repeat steps 6 and 7 until all data have been written.

3.15.2 I2C Read Operation

The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master initiates a write operation to the TVP5150AM1 decoder by generating a start condition (S) followed by the TVP5150AM1 I2C slave address, in MSB first bit order, followed by a 0 to indicate a write cycle. After receiving an acknowledge from the TVP5150AM1 decoder, the master presents the subaddress of the register or the first of a block of registers it wants to read. After the cycle is acknowledged, the master terminates the cycle immediately by generating a stop condition (P).

Table 3-7. Read Address

I2CSEL READ ADDRESS

Selection

0 B9h 1 BBh

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The second phase is the data phase. In this phase, an I2C master initiates a read operation to the TVP5150AM1 decoder by generating a start condition followed by the TVP5150AM1 I2C slave address (see the following illustration of a read operation), in MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TVP5150AM1 decoder, the I2C master receives one or more bytes of data from the TVP5150AM1 decoder. The I2C master acknowledges the transfer at the end of each byte. After the last data byte desired has been transferred from the TVP5150AM1 decoder to the master, the master generates a not acknowledge followed by a stop.

3.15.2.1 Read Phase 1

Step 1 0

I2C Start (master) S

Step 2 7 6 5 4 3 2 1 0

I2C slave address (master) 1 0 1 1 1 0 X 0

Step 3 9

I2C Acknowledge (slave) A

Step 4 7 6 5 4 3 2 1 0

I2C Write register address (master) Addr Addr Addr Addr Addr Addr Addr Addr

Step 5 9

I2C Acknowledge (slave) A

SLES209D–NOVEMBER 2007–REVISED SEPTEMBER 2010

Step 6 0

I2C Stop (master) P

3.15.2.2 Read Phase 2

Step 7 0

I2C Start (master) S

Step 8 7 6 5 4 3 2 1 0

I2C slave address (master) 1 0 1 1 1 0 X 1

Step 9 9

I2C Acknowledge (slave) A

Step 10 7 6 5 4 3 2 1 0

I2C Read data (slave) Data Data Data Data Data Data Data Data

(1)

Step 11

I2C Not Acknowledge (master) A

Step 12 0

I2C Stop (master) P

(1) Repeat steps 10 and 11 for all bytes read. Master does not acknowledge the last read data received.

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TVP5150AM1

XTAL1

14.31818-MHz Crystal

XTAL2

TVP5150AM1

XTAL1

XTAL2

14.31818-MHz TTL Clock

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SLES209D–NOVEMBER 2007–REVISED SEPTEMBER 2010

3.15.2.3 I2C Timing Requirements

The TVP5150AM1 decoder requires delays in the I2C accesses to accommodate its internal processor's timing. In accordance with I2C specifications, the TVP5150AM1 decoder holds the I2C clock line (SCL) low to indicate the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the maximum delays must always be inserted where required. These delays are of variable length; maximum delays are indicated in the following diagram:

Normal register writing addresses 00h to 8Fh (addresses 90h to FFh do not require delays).

Start address Ack Subaddress Ack Data (XXh) Ack Wait 64 µs Stop

Slave (B8h)

The 64-µs delay is for all registers that do not require a reinitialization. Delays may be more for some registers.

3.16 Clock Circuits

An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive the PLL. This may be input to the TVP5150AM1 decoder on terminal 5 (XTAL1), or a crystal of

14.31818-MHz fundamental resonant frequency may be connected across terminals 5 and 6 (XTAL2).

Figure 3-8 shows the reference clock configurations. For the example crystal circuit shown (a

parallel-resonant crystal with 14.31818-MHz fundamental frequency), the external capacitors must have the following relationship:

CL1= CL2= 2CL– C

where C

is the terminal capacitance with respect to ground, and CLis the crystal load capacitance

STRAY

specified by the crystal manufacturer.

STRAY

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Figure 3-8 shows the reference clock configurations.

NOTE: The resistor (R) in parallel with the crystal is recommended to support a wide range of crystal types. A 100-kΩ resistor

may be used for most crystal types.

Figure 3-8. Reference Clock Configurations

Clock source frequency should have an accuracy of ±50 ppm (max).

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SCLK

GLCO

23-Bit Frequency Control

Start Bit DCO Reset Bit

MSB

>128 SCLK

1 SCLK

7 SCLK23 SCLK

1 SCLK

LSB

22 21

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3.17 Genlock Control (GLCO) and RTC

A Genlock control function is provided to support a standard video encoder to synchronize its internal color oscillator for properly reproduced color with unstable timebase sources such as VCRs.

The frequency control word of the internal color subcarrier digitally tuned oscillator (DTO) and the subcarrier phase reset bit are transmitted via terminal 23 (GLCO). The frequency control word is a 23-bit binary number. The frequency of the DTO can be calculated from the following equation:

= (f

dto

where f

/223) × f

ctrl

dto

sclk

is the frequency of the DTO, f

the SCLK.

3.17.1 GLCO Interface

A write of 1 to bit 4 of the chrominance control register at I2C subaddress 1Ah causes the subcarrier DTO phase reset bit to be sent on the next scan line on GLCO. The active-low reset bit occurs seven SCLKs after the transmission of the last bit of DTO frequency control. Upon the transmission of the reset bit, the phase of the TVP5150AM1 internal subcarrier DTO is reset to zero.

A Genlock slave device can be connected to the GLCO terminal and uses the information on GLCO to synchronize its internal color phase DTO to achieve clean line and color lock.

Figure 3-9 shows the timing diagram of the GLCO mode.

SLES209D–NOVEMBER 2007–REVISED SEPTEMBER 2010

is the 23-bit DTO frequency control, and f

ctrl

is the frequency of

sclk

Figure 3-9. GLCO Timing

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RTC

M S B

16 CLK

L S

21 0

128 CLK

22-Bit Fsc Frequency Control

Start

Bit

Reset

Bit

2 CLK

1 CLK

2 CLK

3 CLK

1 CLK

PAL

Switch

44 CLK

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SLES209D–NOVEMBER 2007–REVISED SEPTEMBER 2010

3.17.2 RTC Mode

Figure 3-10 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is four times slower

than the GLCO clock rate. For Color PLL frequency control, the upper 22 bits are used. Each frequency control bit is two clock cycles long. The active-low reset bit occurs six CLKs after the transmission of the last bit of PLL frequency control.

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Figure 3-10. RTC Timing

3.18 Reset and Power Down

The RESETB and PDN terminals work together to put the TVP5150AM1 decoder into one of the two modes. Table 3-8 shows the configuration.

After power-up, the device is in an unknown state with its outputs undefined, until it receives a RESETB signal as depicted in Figure 3-11. After RESETB is released, the data (YOUT0 to YOUT7) and sync (HSYNC, VSYNC/PALI) outputs are in high-impedance state until the TVP5150AM1 is initialized and the outputs are activated.

I2C SCL and SDA signals must not change state until the TVP5150AM1 reset sequence has been completed.

PDN RESETB CONFIGURATION

NOTE

Table 3-8. Reset and Power-Down Modes

0 0 Reserved (unknown state) 0 1 Powers down the decoder 1 0 Resets the decoder 1 1 Normal operation

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RESETB

Normal Operation

Reset

PLL_AVDD

DVDD

IO_DVDD

SDA

PDN

SCL

Data

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After RESETB is released, outputs SCLK and YOUT0 to YOUT7 are high-impedance until the chip is initialized and the outputs are activated.

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Figure 3-11. Power-On Reset Timing

Table 3-9. Power-On Reset Timing

NO. PARAMETER MIN MAX UNIT

t1 Delay time between power supplies active and reset 20 ms t2 RESETB pulse duration 500 ns t3 Delay time between end of reset to I2C active 200 µs

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