Texas instruments TVP5147M1 Data Manual
TVP5147M1
NTSC/PAL/SECAM 2 11-Bit Digital Video Decoder
With Macrovision™ Detection, YPbPr Inputs, and 5-Line
Comb Filter
Data Manual
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Literature Number: SLES140F
July 2005–Revised December 2010
TVP5147M1
SLES140F–JULY 2005–REVISED DECEMBER 2010
www.ti.com
Contents
1 Introduction ........................................................................................................................ 9
1.1 Features ...................................................................................................................... 9
1.2 Description ................................................................................................................. 10
1.3 Applications ................................................................................................................ 11
1.4 Related Products .......................................................................................................... 11
1.5 Ordering Information ...................................................................................................... 11
1.6 Functional Block Diagram ................................................................................................ 12
1.7 Terminal Assignments .................................................................................................... 13
1.8 Terminal Functions ........................................................................................................ 14
2 Functional Description ....................................................................................................... 16
2.1 Analog Processing and A/D Converters ................................................................................ 16
2.1.1 Video Input Switch Control .................................................................................... 17
2.1.2 Analog Input Clamping ......................................................................................... 17
2.1.3 Automatic Gain Control ........................................................................................ 17
2.1.4 Analog Video Output ........................................................................................... 17
2.1.5 A/D Converters .................................................................................................. 18
2.2 Digital Video Processing .................................................................................................. 18
2.2.1 2x Decimation Filter ............................................................................................ 18
2.2.2 Composite Processor .......................................................................................... 18
2.2.2.1 Color Low-Pass Filter .............................................................................. 20
2.2.2.2 Y/C Separation ..................................................................................... 21
2.2.3 Luminance Processing ......................................................................................... 22
2.2.4 Color Transient Improvement ................................................................................. 22
2.3 Clock Circuits .............................................................................................................. 23
2.4 Real-Time Control (RTC) ................................................................................................. 23
2.5 Output Formatter .......................................................................................................... 24
2.5.1 Separate Syncs ................................................................................................. 25
2.5.2 Embedded Syncs ............................................................................................... 30
2.6 I
2.7 VBI Data Processor ....................................................................................................... 33
2.8 Reset and Initialization .................................................................................................... 35
2.9 Adjusting External Syncs ................................................................................................. 36
2.10 Internal Control Registers ................................................................................................ 37
2.11 Register Definitions ........................................................................................................ 41
2.12 VBUS Register Definitions ............................................................................................... 86
3 Electrical Specifications ..................................................................................................... 93
3.1 Absolute Maximum Ratings .............................................................................................. 93
3.2 Recommended Operating Conditions .................................................................................. 94
3.3 Crystal Specifications ..................................................................................................... 94
3.4 Electrical Characteristics ................................................................................................. 95
2
C Host Interface .......................................................................................................... 30
2.6.1 Reset and I
2.6.2 I
2
C Operation .................................................................................................... 31
2
C Bus Address Selection ....................................................................... 31
2.6.3 VBUS Access ................................................................................................... 32
2.7.1 VBI FIFO and Ancillary Data in Video Stream .............................................................. 34
2.7.2 VBI Raw Data Output .......................................................................................... 35
2 Contents Copyright © 2005–2010, Texas Instruments Incorporated
TVP5147M1
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SLES140F–JULY 2005–REVISED DECEMBER 2010
3.5 DC Electrical Characteristics ............................................................................................. 95
3.6 Analog Processing and A/D Converters ................................................................................ 95
3.7 Clocks, Video Data, Sync Timing ....................................................................................... 96
3.8 I
2
C Host Port Timing ...................................................................................................... 96
3.9 Thermal Specifications .................................................................................................... 97
4 Example Register Settings .................................................................................................. 98
4.1 Example 1 .................................................................................................................. 98
4.1.1 Assumptions ..................................................................................................... 98
4.1.2 Recommended Settings ....................................................................................... 98
4.2 Example 2 .................................................................................................................. 99
4.2.1 Assumptions ..................................................................................................... 99
4.2.2 Recommended Settings ....................................................................................... 99
4.3 Example 3 ................................................................................................................. 100
4.3.1 Assumptions ................................................................................................... 100
4.3.2 Recommended Settings ...................................................................................... 100
5 Application Information .................................................................................................... 101
5.1 Application Example ..................................................................................................... 101
5.2 Designing With PowerPAD™ Devices ................................................................................ 102
Revision History ....................................................................................................................... 103
Copyright © 2005–2010, Texas Instruments Incorporated Contents 3
TVP5147M1
SLES140F–JULY 2005–REVISED DECEMBER 2010
www.ti.com
List of Figures
1-1 Functional Block Diagram....................................................................................................... 13
1-2 Terminal Assignments Diagram ................................................................................................ 13
2-1 Analog Processors and A/D Converters ...................................................................................... 16
2-2 Digital Video Processing Block Diagram...................................................................................... 18
2-3 Composite and S-Video Processing Block Diagram......................................................................... 19
2-8 Luminance Edge-Enhancer Peaking Block Diagram........................................................................ 22
2-9 Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling............................................................ 22
2-10 Reference Clock Configurations................................................................................................ 23
2-11 RTC Timing ....................................................................................................................... 24
2-12 Vertical Synchronization Signals for 525-Line System ...................................................................... 27
2-13 Vertical Synchronization Signals for 625-Line System ...................................................................... 28
2-14 Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode.................................................................. 29
2-15 Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode.................................................................. 30
2-16 VSYNC Position With Respect to HSYNC.................................................................................... 30
2-17 VBUS Access..................................................................................................................... 33
2-18 Reset Timing...................................................................................................................... 35
2-19 Teletext Filter Function .......................................................................................................... 75
3-1 Clocks, Video Data, and Sync Timing......................................................................................... 96
3-2 I
5-1 Example Application Circuit ................................................................................................... 101
2
C Host Port Timing ............................................................................................................. 96
4 List of Figures Copyright © 2005–2010, Texas Instruments Incorporated
TVP5147M1
www.ti.com
SLES140F–JULY 2005–REVISED DECEMBER 2010
List of Tables
1-1 Terminal Functions............................................................................................................... 14
2-1 Output Format .................................................................................................................... 24
2-2 Summary of Line Frequencies, Data Rates, and Pixel/Line Counts....................................................... 25
2-3 EAV and SAV Sequence........................................................................................................ 30
2-4 I
2-5 I
2-6 Supported VBI System .......................................................................................................... 33
2-7 Ancillary Data Format and Sequence ......................................................................................... 34
2-8 VBI Raw Data Output Format .................................................................................................. 35
2-9 Reset Sequence.................................................................................................................. 35
2-10 I
2-11 VBUS Register Summary ....................................................................................................... 40
2-12 Input Select Register ............................................................................................................ 41
2-13 Analog Channel and Video Mode Selection .................................................................................. 41
2-14 AFE Gain Control Register ..................................................................................................... 42
2-15 Video Standard Select Register ............................................................................................... 42
2-16 Operation Mode Control Register ............................................................................................. 43
2-17 Autoswitch Mask Register ...................................................................................................... 43
2-18 Color Killer Register ............................................................................................................. 44
2-19 Luminance Processing Control 1 Register ................................................................................... 44
2-20 Luminance Processing Control 2 Register ................................................................................... 45
2-21 Luminance Processing Control 3 Register ................................................................................... 45
2-22 Luminance Brightness Register ............................................................................................... 45
2-23 Luminance Contrast Register .................................................................................................. 46
2-24 Chrominance Saturation Register ............................................................................................. 46
2-25 Chroma Hue Register ........................................................................................................... 46
2-26 Chrominance Processing Control 1 Register ................................................................................ 47
2-27 Chrominance Processing Control 2 Register ................................................................................ 47
2-28 R/Pr Gain (Color Saturation) Register ........................................................................................ 47
2-29 G/Y Gain (Contrast) Register .................................................................................................. 48
2-30 B/Pb Gain (Color Saturation) Register ........................................................................................ 48
2-31 G/Y Offset Register ............................................................................................................. 48
2-32 AVID Start Pixel Register ....................................................................................................... 49
2-33 AVID Stop Pixel Register ....................................................................................................... 49
2-34 HSYNC Start Pixel Register .................................................................................................... 49
2-35 HSYNC Stop Pixel Register .................................................................................................... 50
2-36 VSYNC Start Line Register .................................................................................................... 50
2-37 VSYNC Stop Line Register ..................................................................................................... 50
2-38 VBLK Start Line Register ....................................................................................................... 50
2-39 VBLK Stop Line Register ....................................................................................................... 51
2-40 Embedded Sync Offset Control 1 Register .................................................................................. 51
2-41 Embedded Sync Offset Control 2 Register .................................................................................. 51
2-42 CTI Delay Register .............................................................................................................. 52
2-43 CTI Control Register ............................................................................................................ 52
2-44 Brightness and Contrast Range Extender Register ......................................................................... 52
2-45 Sync Control Register ........................................................................................................... 53
2-46 Output Formatter Control 1 Register .......................................................................................... 53
Copyright © 2005–2010, Texas Instruments Incorporated List of Tables 5
2
C Host Interface Terminal Description....................................................................................... 31
2
C Address Selection ........................................................................................................... 31
2
C Register Summary........................................................................................................... 37
TVP5147M1
SLES140F–JULY 2005–REVISED DECEMBER 2010
2-47 Output Formatter Control 2 Register .......................................................................................... 54
2-48 Output Formatter Control 3 Register .......................................................................................... 54
2-49 Output Formatter Control 4 Register .......................................................................................... 55
2-50 Output Formatter Control 5 Register .......................................................................................... 56
2-51 Output Formatter Control 6 Register .......................................................................................... 57
2-52 Clear Lost Lock Detect Register ............................................................................................... 57
2-53 Status 1 Register ................................................................................................................ 58
2-54 Status 2 Register ................................................................................................................ 59
2-55 AGC Gain Status Register ..................................................................................................... 59
2-56 Video Standard Status Register ............................................................................................... 60
2-57 GPIO Input 1 Register .......................................................................................................... 60
2-58 GPIO Input 2 Register .......................................................................................................... 61
2-59 AFE Coarse Gain for CH 1 Register .......................................................................................... 61
2-60 AFE Coarse Gain for CH 2 Register .......................................................................................... 62
2-61 AFE Coarse Gain for CH 3 Register .......................................................................................... 62
2-62 AFE Coarse Gain for CH 4 Register .......................................................................................... 63
2-63 AFE Fine Gain for Pb Register ................................................................................................ 63
2-64 AFE Fine Gain for Y_Chroma Register ....................................................................................... 64
2-65 AFE Fine Gain for Pr Register ................................................................................................. 64
2-66 AFE Fine Gain for CVBS_Luma Register .................................................................................... 64
2-67 Field ID Control Register ....................................................................................................... 65
2-68 F-Bit and V-Bit Decode Control 1 Register ................................................................................... 66
2-69 Back-End AGC Control Register .............................................................................................. 67
2-70 AGC Decrement Speed Register .............................................................................................. 67
2-71 ROM Version Register .......................................................................................................... 67
2-72 RAM Version MSB Register .................................................................................................... 67
2-73 AGC White Peak Processing Register ....................................................................................... 68
2-74 F-Bit and V-Bit Control 2 Register ............................................................................................. 69
2-75 VCR Trick Mode Control Register ............................................................................................. 69
2-76 Horizontal Shake Increment Register ......................................................................................... 70
2-77 AGC Increment Speed Register ............................................................................................... 70
2-78 AGC Increment Delay Register ................................................................................................ 70
2-79 Analog Output Control 1 Register ............................................................................................. 70
2-80 Chip ID MSB Register .......................................................................................................... 71
2-81 Chip ID LSB Register ........................................................................................................... 71
2-82 RAM Version LSB Register .................................................................................................... 71
2-83 Color PLL Speed Control Register ............................................................................................ 71
2-84 Status Request Register ........................................................................................................ 71
2-85 Vertical Line Count Register ................................................................................................... 72
2-86 AGC Decrement Delay Register ............................................................................................... 72
2-87 VDP TTX Filter and Mask Register ........................................................................................... 73
2-88 VDP TTX Filter Control Register .............................................................................................. 74
2-89 VDP FIFO Word Count Register .............................................................................................. 75
2-90 VDP FIFO Interrupt Threshold Register ...................................................................................... 76
2-91 VDP FIFO Reset Register ...................................................................................................... 76
2-92 VDP FIFO Output Control Register ........................................................................................... 76
2-93 VDP Line Number Interrupt Register ......................................................................................... 76
2-94 VDP Pixel Alignment Register ................................................................................................. 77
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6 List of Tables Copyright © 2005–2010, Texas Instruments Incorporated
TVP5147M1
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SLES140F–JULY 2005–REVISED DECEMBER 2010
2-95 VDP Line Start Register ........................................................................................................ 77
2-96 VDP Line Stop Register ........................................................................................................ 77
2-97 VDP Global Line Mode Register ............................................................................................... 77
2-98 VDP Full Field Enable Register ................................................................................................ 78
2-99 VDP Full Field Mode Register ................................................................................................. 78
2-100 VBUS Data Access With No VBUS Address Increment Register ......................................................... 78
2-101 VBUS Data Access With VBUS Address Increment Register ............................................................. 78
2-102 FIFO Read Data Register ...................................................................................................... 78
2-103 VBUS Address Register ........................................................................................................ 79
2-104 Interrupt Raw Status 0 Register ............................................................................................... 79
2-105 Interrupt Raw Status 1 Register ............................................................................................... 80
2-106 Interrupt Status 0 Register ..................................................................................................... 81
2-107 Interrupt Status 1 Register ..................................................................................................... 82
2-108 Interrupt Mask 0 Register ....................................................................................................... 83
2-109 Interrupt Mask 1 Register ....................................................................................................... 84
2-110 Interrupt Clear 0 Register ....................................................................................................... 85
2-111 Interrupt Clear 1 Register ....................................................................................................... 86
2-112 VDP Closed Caption Data Register ........................................................................................... 86
2-113 VDP WSS Data Register ....................................................................................................... 87
2-114 VDP VITC Data Register ....................................................................................................... 87
2-115 VDP V-Chip TV Rating Block 1 Register ..................................................................................... 88
2-116 VDP V-Chip TV Rating Block 2 Register ..................................................................................... 88
2-117 VDP V-Chip TV Rating Block 3 Register ..................................................................................... 88
2-118 VDP V-Chip MPAA Rating Data Register .................................................................................... 89
2-119 VDP General Line Mode and Line Address Register ....................................................................... 90
2-120 VDP VPS/Gemstar Data Register ............................................................................................. 91
2-121 Analog Output Control 2 Register ............................................................................................. 92
2-122 Interrupt Configuration Register ............................................................................................... 92
Copyright © 2005–2010, Texas Instruments Incorporated List of Tables 7
TVP5147M1
SLES140F–JULY 2005–REVISED DECEMBER 2010
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8 List of Tables Copyright © 2005–2010, Texas Instruments Incorporated
TVP5147M1
www.ti.com
SLES140F–JULY 2005–REVISED DECEMBER 2010
NTSC/PAL/SECAM 2 11-Bit Digital Video Decoder
With Macrovision™ Detection, YPbPr Inputs, and 5-Line Comb Filter
Check for Samples: TVP5147M1
1 Introduction
1.1 Features
12345
• Two 30-MSPS 11-bit A/D channels with • Certified Macrovision™ copy protection
programmable gain control detection
• Supports NTSC (J, M, 4.43), PAL (B, D, G, H, I, • Available in commercial (0°C to 70°C) and
M, N, Nc, 60), and SECAM (B, D, G, K, K1, L) industrial (−40°C to 85°C) temperature ranges
CVBS, and S-video
• Supports analog component YPbPr video (AEC-Q100 Rev G − TVP5147M1IPFPQ1 or
format with embedded sync TVP5147M1IPFPRQ1)
• Ten analog video input terminals for • VBI data processor
multisource connection
• Supports analog video output
• User-programmable video output formats
– 10-bit ITU-R BT.656 4:2:2 YCbCr with
embedded syncs
– 10-bit 4:2:2 YCbCr with separate syncs
– 20-bit 4:2:2 YCbCr with separate syncs
– 2x sampled raw VBI data in active video
during a vertical blanking period
– Sliced VBI data during a vertical blanking
period or active video period (full field mode)
• HSYNC/VSYNC outputs with programmable
position, polarity, width, and field ID (FID)
output
• Composite and S-video processing
– Adaptive 2-D 5-line adaptive comb filter for
composite video inputs; chroma-trap
available
– Automatic video standard detection
(NTSC/PAL/SECAM) and switching
– Luma-peaking with programmable gain
– Patented chroma transient improvement
(CTI)
– Patented architecture for locking to weak,
noisy, or unstable signals
– Single 14.31818-MHz reference crystal for all
standards
– Line-locked internal pixel sampling clock
generation with horizontal and vertical lock
signal outputs
– Genlock output RTC format for downstream
video encoder synchronization
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2PowerPAD, DLP are trademarks of Texas Instruments.
3Gemstar is a trademark of Gemstar-TV Guide Intermational.
4Macrovision is a trademark of Macrovision Corporation.
5All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
• Qualified for Automotive Applications
– Teletext (NABTS, WST)
– CC and extended data service (EDS)
– Wide screen signaling (WSS)
– Copy generation management system
(CGMS)
– Video program system (VPS/PDC)
– Vertical interval time code (VITC)
– Gemstar™ 1×/2× mode
– V-Chip decoding
– Register readback of CC, WSS (CGMS),
VPS/PDC, VITC and Gemstar 1×/2× sliced
data
• I2C host port interface
• Reduced power consumption: 1.8-V digital
core, 3.3-V for digital I/O, and 1.8-V/3.3 V analog
core with power-save and power-down modes
• 80-terminal TQFP PowerPAD™ package
Copyright © 2005–2010, Texas Instruments Incorporated
TVP5147M1
SLES140F–JULY 2005–REVISED DECEMBER 2010
1.2 Description
The TVP5147M1 device is a high-quality, single-chip digital video decoder that digitizes and decodes all
popular baseband analog video formats into digital component video. The TVP5147M1 decoder supports
the analog-to-digital (A/D) conversion of component YPbPr signals, as well as the A/D conversion and
decoding of NTSC, PAL, and SECAM composite and S-video into component YCbCr. This decoder
includes two 11-bit 30-MSPS A/D converters (ADCs). Preceding each ADC in the device, the
corresponding analog channel contains an analog circuit that clamps the input to a reference voltage and
applies a programmable gain and offset. A total of ten video input terminals can be configured to a
combination of YPbPr, CVBS, or S-video video inputs.
Composite or S-video signals are sampled at 2× the ITU-R BT.601 clock frequency, line-locked alignment,
and are then decimated to the 1× pixel rate. CVBS decoding uses five-line adaptive comb filtering for both
the luma and chroma data paths to reduce both cross-luma and cross-chroma artifacts. A chroma trap
filter is also available. On CVBS and S-video inputs, the user can control video characteristics such as
contrast, brightness, saturation, and hue via an I2C host port interface. Furthermore, luma peaking
(sharpness) with programmable gain is included, as well as a patented chroma transient improvement
(CTI) circuit.
The following output formats can be selected: 20-bit 4:2:2 YCbCr or 10-bit 4:2:2 YCbCr.
The TVP5147M1 decoder generates synchronization, blanking, field, active video window, horizontal and
vertical syncs, clock, genlock (for downstream video encoder synchronization), host CPU interrupt and
programmable logic I/O signals, in addition to digital video outputs.
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The TVP5147M1 decoder includes methods for advanced vertical blanking interval (VBI) data retrieval.
The VBI data processor (VDP) slices, parses, and performs error checking on teletext, closed caption
(CC), and other VBI data. A built-in FIFO stores up to 11 lines of teletext data, and with proper host port
synchronization, full-screen teletext retrieval is possible. The TVP5147M1 decoder can pass through the
output formatter 2× sampled raw luma data for host-based VBI processing.
The main blocks of the TVP5147M1 decoder include:
• Robust sync detection for weak and noisy signals as well as VCR trick modes
• Y/C separation by 2-D 5-line adaptive comb or chroma trap filter
• Two 11-bit, 30-MSPS A/D converters with analog preprocessors [clamp and automatic gain control
(AGC)]
• Analog video output
• Luminance processor
• Chrominance processor
• Clock/timing processor and power-down control
• Software-controlled power-saving standby mode
• Output formatter
• I2C host port interface
• VBI data processor
• Macrovision™ copy protection detection circuit (Type 1, 2, 3, and separate color stripe detection)
• 3.3-V tolerant digital I/O ports
10 Introduction Copyright © 2005–2010, Texas Instruments Incorporated
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1.3 Applications
• DLP™ projectors
• Digital TV
• LCD TV/monitors
• DVD recorders
• PVR
• PC video cards
• Video capture/video editing
• Video conferencing
• Automotive
• Industrial
1.4 Related Products
TVP5146M2 NTSC/PAL/SECAM 2 11-Bit Digital Video Decoder With Macrovision™ Detection,
YPbPr/RGB Inputs, and 5-Line Comb Filter
TVP5150AM1 Ultralow Power NTSC/PAL/SECAM Video Decoder With Robust Sync Detector
1.5 Ordering Information
T
A
0°C to 70°C
-40°C to 85°C
(1) For the most current package and ordering information, see the Package Option Addendum at the end
of this document, or see the TI web site at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design
guidelines are available at www.ti.com/package.
(3) AEC-Q100 Rev G Certified
SLES140F–JULY 2005–REVISED DECEMBER 2010
PACKAGED DEVICES
80-TERMINAL PLASTIC PACKAGE OPTION
FLAT-PACK PowerPAD™ PACKAGE
TVP5147M1PFP Tray
TVP5147M1PFPR Tape and reel
TVP5147M1IPFP Tray
TVP5147M1IPFPR Tape and reel
TVP5147M1IPFPQ1
TVP5147M1IPFPRQ1
(1) (2)
(3)
(3)
Tape and reel
Tray
Copyright © 2005–2010, Texas Instruments Incorporated Introduction 11
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Composite and S-V ideo Processor
Y/C
Separation
5-line
Adaptive
Comb
Luma
Processing
Chroma
Processing
M
U
X
CVBS/Y
C/CbCr
C
Y
Output
Formatter
Y[9:0]
VBI
Data
Processor
Copy
Protection
Detector
C[9:0]
Host
Interface
Timing Processor
With Sync Detector
VI_1_A
VI_1_B
VI_1_C
VI_2_A
VI_2_B
VI_2_C
VI_3_A
VI_3_B
VI_3_C
VI_4_A
CVBS/
Y
CVBS/
C/Pb
CVBS/
C/Pr
CVBS/Y
CVBS/Y
Analog
Front End
Sampling
Clock
GPIO
HS/CS
VS/VBLK
FID
AVID
XTAL1
XTAL2
DATACLK
RESETB
GLCO
PWDN
SCL
SDA
YCbCr
Clamping
AGC
2 × 11-Bit
ADC
TVP5147M1
SLES140F–JULY 2005–REVISED DECEMBER 2010
1.6 Functional Block Diagram
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Figure 1-1. Functional Block Diagram
12 Introduction Copyright © 2005–2010, Texas Instruments Incorporated
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22 23
C_6/GPIO
C_7/GPIO
C_8/GPIO
C_9/GPIO
DGND
DVDD
Y_0
Y_1
Y_2
Y_3
Y_4
IOGND
IOVDD
Y_5
Y_6
Y_7
Y_8
Y_9
DGND
DVDD
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
24
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
VI_1_B
VI_1_C
CH1_A33GND
CH1_A33VDD
CH2_A33VDD
CH2_A33GND
VI_2_A
VI_2_B
VI_2_C
CH2_A18GND
CH2_A18VDD
A18VDD_REF
A18GND_REF
NC
NC
VI_3_A
VI_3_B
VI_3_C
NC
NC
25 26 27 28
PFP PACKAGE
(TOP VIEW)
79 78 77 76 7580 74 72 71 7073
29
30 31 32 33
69 682167 66 65 64
34 35 36 37 38 39 40
63 62 61
VI_1_A
CH1_A18GND
CH1_A18VDD
PLL_A18GND
PLL_A18VDD
XTAL2
XTAL1
VS/VBLK/GPIO
HS/CS/GPIO
FID
C_0/GPIO
C_1
DGND
DVDD
C_2/GPIO
C_3/GPIO
C_4/GPIO
C_5/GPIO
IOGND
IOVDD
NC
NC
VI_4_A
NC
NC
AGND
DGND
SCL
SDA
INTREQ
DVDD
DGND
PWDN
RESETB
GPIO
AVID/GPIO
GLCO/I2CA
IOVDD
IOGND
DATACLK
TVP5147M1
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1.7 Terminal Assignments
SLES140F–JULY 2005–REVISED DECEMBER 2010
Copyright © 2005–2010, Texas Instruments Incorporated Introduction 13
Figure 1-2. Terminal Assignments Diagram
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SLES140F–JULY 2005–REVISED DECEMBER 2010
1.8 Terminal Functions
Table 1-1. Terminal Functions
TERMINAL
NAME NO.
Analog Video
VI_1_A 80 I/O
VI_1_B 1 I
VI_1_C 2 I
VI_2_A 7 I
VI_2_B 8 I
VI_2_C 9 I
VI_3_A 16 I
VI_3_B 17 I
VI_3_C 18 I
VI_4_A 23 I
Clock Signals
DATACLK 40 O Line-locked data output clock
XTAL1 74 I
XTAL2 75 O
Digital Video
57, 58, 59, Digital video output of CbCr, C[9] is MSB and C[0] is LSB. C_0 and C_[9-2] can be used as
C_[9:0] I/O
Y[9:0] O
Miscellaneous Signals
GPIO 35 I/O Programmable general-purpose I/O
GLCO/I2CA 37 I/O
INTREQ 30 O Interrupt request
NC 20, 21, 22,
PWDN 33 I 1 = Power down
RESETB 34 I Reset input, active low (see Section 2.8)
Host Interface
SCL 28 I I2C clock input
SDA 29 I/O I2C data bus
Power Supplies
AGND 26 Analog ground. Connect to analog ground.
A18GND_REF 13 Analog 1.8-V return
A18VDD_REF 12 Analog power for reference 1.8 V
CH1_A18GND 79 Analog 1.8-V return
CH2_A18GND 10
CH1_A18VDD 78 Analog power. Connect to 1.8 V.
60, 63, 64, programmable general purpose I/O. C_1 (pin 69) requires an external pulldown resistor and
65, 66, 69, should not be used for general purpose I/0.
70 For the 8-bit mode, the two LSBs are ignored. Unused outputs can be left unconnected.
43, 44, 45,
46, 47, 50, Digital video output of Y/YCbCr, Y[9] is MSB and Y[0] is LSB.
51, 52, 53, For the 8-bit mode, the two LSBs are ignored. Unused outputs can be left unconnected.
54
14, 15, 19,
24, 25
I/O DESCRIPTION
VI_1_A: Analog video input for CVBS/Pb/C or analog video output (see Table 2-79)
VI_1_x: Analog video input for CVBS/Pb/C
VI_2_x: Analog video input for CVBS/Y
VI_3_x: Analog video input for CVBS/Pr/C
VI_4_A: Analog video input for CVBS/Y
Up to ten composite, four S-video, and two composite or three component video inputs (or a
combination thereof) can be supported.
The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 µF.
The possible input configurations are listed in the input select register at I2C subaddress 00h
(see Table 2-12).
External clock reference input. It can be connected to an external oscillator with a 1.8-V
compatible clock signal or a 14.31818-MHz crystal oscillator.
External clock reference output. Not connected if XTAL1 is driven by an external single-ended
oscillator.
Genlock control output (GLCO) uses real time control (RTC) format.
During reset, this terminal is an input used to program the I2C address LSB.
Not connected. These terminals can be connected to power or ground (compatible with
TVP5146 terminals), internally floating.
Power down input:
0 = Normal mode
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14 Introduction Copyright © 2005–2010, Texas Instruments Incorporated
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SLES140F–JULY 2005–REVISED DECEMBER 2010
Table 1-1. Terminal Functions (continued)
TERMINAL
NAME NO.
CH2_A18VDD 11
CH1_A33GND 3 Analog 3.3-V return
CH2_A33GND 6
CH1_A33VDD 4 Analog power. Connect to 3.3 V.
CH2_A33VDD 5
DGND Digital return
DVDD Digital power. Connect to 1.8 V.
IOGND 39, 49, 62 Digital power return
IOVDD 38, 48, 61 Digital power. Connect to 3.3 V or less for reduced noise.
PLL_A18GND 77 Analog power return
PLL_A18VDD 76 Analog power. Connect to 1.8 V.
Sync Signals
HS/CS/GPIO 72 I/O
VS/VBLK/GPIO 73 I/O
FID 71 I/O Odd/even field indicator output. This terminal needs a pulldown resistor (see Figure 5-1).
AVID/GPIO 36 I/O
27, 32, 42,
56, 68
31, 41, 55,
67
I/O DESCRIPTION
Horizontal sync output or digital composite sync output
Programmable general-purpose I/O
Vertical sync output (for modes with dedicated VSYNC) or VBLK output
Programmable general-purpose I/O
Active video indicator output
Programmable general-purpose I/O
Copyright © 2005–2010, Texas Instruments Incorporated Introduction 15
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Clamp
CH1 A/D
Line-Locked
Sampling Clock
VI_4_A
M
U
X
VI_1_B
VI_1_C
M
U
X
VI_2_A
VI_2_B
VI_2_C
M
U
X
VI_3_A
VI_3_B
VI_3_C
11-Bit
ADC
Clamp
Clamp
Clamp
VI_1_A
I/O
PGA
CVBS/
Pb/C
CVBS/
Y
CVBS/
Pr/C
CVBS/
Y
M
U
X
PGA
CH2 A/D
11-Bit
ADC
PGA
Analog Front End
TVP5147M1
SLES140F–JULY 2005–REVISED DECEMBER 2010
2 Functional Description
2.1 Analog Processing and A/D Converters
Figure 2-1 shows a functional diagram of the analog processors and A/D converters, which provide the
analog interface to all video inputs. It accepts up to ten inputs and performs source selection, video
clamping, video amplification, A/D conversion, and gain and offset adjustments to center the digitized
video signal. The TVP5147M1 supports one analog video output for the selected analog input video.
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Figure 2-1. Analog Processors and A/D Converters
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2.1.1 Video Input Switch Control
The TVP5147M1 decoder has two analog channels that accept up to ten video inputs. The user can
configure the internal analog video switches via the I2C interface. The ten analog video inputs can be used
for different input configurations, some of which are:
• Up to ten selectable individual composite video inputs
• Up to four selectable S-video inputs
• Up to three selectable analog YPbPr video inputs and one CVBS input
• Up to two selectable analog YPbPr video inputs, one S-video input, and two CVBS inputs
The input selection is performed by the input select register at I2C subaddress 00h (see Table 2-12).
2.1.2 Analog Input Clamping
An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The clamping circuit
provides line-by-line restoration of the video sync level to a fixed dc reference voltage. The selection
between bottom and mid clamp is performed automatically by the TVP5147M1 decoder.
2.1.3 Automatic Gain Control
The TVP5147M1 decoder uses two programmable gain amplifiers (PGAs), one per channel. The PGA can
scale a signal with a voltage-input compliance of 0.5-VPP to 2.0-VPP to a full-scale 10-bit A/D output code
range. A 4-bit code sets the coarse gain with individual adjustment per channel. Minimum gain
corresponds to a code 0x0 (2.0-VPP full-scale input, -6-dB gain) while maximum gain corresponds to code
0xF (0.5 VPP full scale, +6-dB gain). The TVP5147M1 decoder also has 12-bit fine gain controls for each
channel and applies independently to coarse gain controls. For composite video, the input video signal
amplitude can vary significantly from the nominal level of 1 VPP. The TVP5147M1 decoder can adjust its
PGA setting automatically: an automatic gain control (AGC) can be enabled and can adjust the signal
amplitude such that the maximum range of the ADC is reached without clipping. Some nonstandard video
signals contain peak white levels that saturate the ADC. In these cases, the AGC automatically cuts back
gain to avoid clipping. If the AGC is on, then the TVP5147M1 decoder can read the gain currently being
used.
SLES140F–JULY 2005–REVISED DECEMBER 2010
The TVP5147M1 AGC comprises the front-end AGC before Y/C separation and the back-end AGC after
Y/C separation. The back-end AGC restores the optimum system gain whenever an amplitude reference
such as the composite peak (which is only relevant before Y/C separation) forces the front-end AGC to set
the gain too low. The front-end and back-end AGC algorithms can use up to four amplitude references:
sync height, color burst amplitude, composite peak, and luma peak.
The specific amplitude references being used by the front-end and back-end AGC algorithms can be
independently controlled using the AGC white peak processing register located at subaddress 74h. The
TVP5147M1 gain increment speed and gain increment delay can be controlled using the AGC increment
speed register located at subaddress 78h and the AGC increment delay register located at subaddress
79h.
2.1.4 Analog Video Output
One of the analog input signals is available at the analog video output terminal, which is shared with input
selected by I2C registers. The signal at this terminal must be buffered by a source follower. The nominal
output voltage is 2 V p-p, thus the signal can be used to drive a 75-Ω line. The magnitude is maintained
with an AGC in 16 steps controlled by the TVP5147M1 decoder. To use this function, terminal VI_1_A
must be set as an output terminal. The input mode selection register also selects an active analog output
signal.
Copyright © 2005–2010, Texas Instruments Incorporated Functional Description 17
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Copy
Protection
Detector
VBI Data
Processor
Output
Formatter
Composite
Processor
CVBS/Y
C/CbCr
YCbCr
Y[9:0]
Timing
Processor
AVID
FID
GLCO
XTAL1
XTAL2
RESETB
CH1 A/D
CH2 A/D
HS/CS
VS/VBLK
DATACLK
C[9:0]
Host
Interface
SCL
SDA
Slice VBI Data
2×
Decimation
PWDN
2×
Decimation
TVP5147M1
SLES140F–JULY 2005–REVISED DECEMBER 2010
2.1.5 A/D Converters
All ADCs have a resolution of 11 bits and can operate up to 30 MSPS. All A/D channels receive an
identical clock from the on-chip phase-locked loop (PLL) at a frequency between 24 MHz and 30 MHz. All
ADC reference voltages are generated internally.
2.2 Digital Video Processing
Figure 2-2 is a block diagram of the TVP5147M1 digital video decoder processing. This block receives
digitized video signals from the ADCs and performs composite processing for CVBS and S-video inputs
and YCbCr signal enhancements for CVBS and S-video inputs. It also generates horizontal and vertical
syncs and other output control signals such as genlock for CVBS and S-video inputs. Additionally, it can
provide field identification, horizontal and vertical lock, vertical blanking, and active video window
indication signals. The digital data output can be programmed to two formats: 20-bit 4:2:2 with external
syncs or 10-bit 4:2:2 with embedded/separate syncs. The circuit detects pseudosync pulses, AGC pulses,
and color striping in Macrovision-encoded copy-protected material. Information present in the VBI interval
can be retrieved and either inserted in the ITU-R BT.656 output as ancillary data or stored in internal FIFO
and/or registers for retrieval via the host port interface.
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Figure 2-2. Digital Video Processing Block Diagram
2.2.1 2x Decimation Filter
All input signals are typically oversampled by a factor of 2 (27 MHz). The A/D outputs initially pass through
decimation filters that reduce the data rate to 1× the pixel rate. The decimation filter is a half-band filter.
Oversampling and decimation filtering can effectively increase the overall signal-to-noise ratio by 3 dB.
2.2.2 Composite Processor
Figure 2-3 is a block diagram of the TVP5147M1 digital composite video processing circuit. This
processing circuit receives a digitized composite or S-video signal from the ADCs and performs Y/C
separation (bypassed for S-video input), chroma demodulation for PAL/NTSC and SECAM, and YUV
signal enhancements.
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Line
Delay
–
Peaking
NTSC/PAL
Remodulation
NTSC/PAL
Demodulation
Notch
Filter
Color LPF
↓ 2
5-Line
Adaptive
Comb
Filter
Notch
Filter
Notch
Filter
Notch
Filter
Contrast
Brightness
Saturation
Adjust
Cr
Y
Cb
Y
Burst
Accumulator
(U)
U
SECAM
Color
Demodulation
V
Delay
CVBS/Y
SECAM Luma
CVBS
CVBS/C
Color LPF
↓ 2
Burst
Accumulator
(V)
U
V
Delay
Delay
TVP5147M1
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The 10-bit composite video is multiplied by the subcarrier signals in the quadrature demodulator to
generate color difference signals U and V. The U and V signals are then sent to low-pass filters to achieve
the desired bandwidth. An adaptive 5-line comb filter separates UV from Y based on the unique property
of color phase shifts from line to line. The chroma is remodulated through a quadrature modulator and
subtracted from line-delayed composite video to generate luma. This form of Y/C separation is completely
complementary, thus there is no loss of information. However, in some applications, it is desirable to limit
the U/V bandwidth to avoid crosstalk. In that case, notch filters can be turned on. To accommodate some
viewing preferences, a peaking filter is also available in the luma path. Contrast, brightness, sharpness,
hue, and saturation controls are programmable through the host port.
SLES140F–JULY 2005–REVISED DECEMBER 2010
Figure 2-3. Composite and S-Video Processing Block Diagram
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f − Frequency − MHz
−70
−60
−50
−40
−30
−20
−10
0
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
ITU-R BT.601 −3 dB
at 1.42 MHz
Amplitude − dB
f − Frequency − MHz
−70
−60
−50
−40
−30
−20
−10
0
10
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0
Amplitude − dB
Filter 3
−3 dB at 554 kHz
Filter 2
−3 dB at 844 kHz
Filter 1
−3 dB
at 1.03 MHz
Filter 0
−3 dB at 1.41 MHz
TVP5147M1
SLES140F–JULY 2005–REVISED DECEMBER 2010
2.2.2.1 Color Low-Pass Filter
High filter bandwidth preserves sharp color transitions and produces crisp color boundaries. However, for
nonstandard video sources that have asymmetrical U and V side bands, it is desirable to limit the filter
bandwidth to avoid UV crosstalk. The color low-pass filter bandwidth is programmable to enable one of the
three notch filters. Figure 2-4 and Figure 2-5 represent the frequency responses of the wideband color
low-pass filters.
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Figure 2-4. Color Low-Pass Filter Frequency Figure 2-5. Color Low-Pass Filter With Filter
Response Characteristics, NTSC/PAL ITU-R BT.601 Sampling
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f − Frequency − MHz
−40
−35
−30
−25
−20
−15
−10
−5
0
5
10
0 1 2 3 4 5 6 7
No Notch Filter
Notch 3 Filter
Notch 1 Filter
Amplitude − dB
Notch 2 Filter
−40
−35
−30
−25
−20
−15
−10
−5
0
5
10
0 1 2 3 4 5 6 7
f − Frequency − MHz
Amplitude − dB
No Notch Filter
Notch 2 Filter
Notch 1 Filter
Notch 3 Filter
TVP5147M1
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2.2.2.2 Y/C Separation
Y/C separation can be done using adaptive 5-line (5-H delay) comb filters or a chroma trap filter. The
comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the
luma path, then chroma trap filters are used which are shown in Figure 2-6 and Figure 2-7. The TI
patented adaptive comb filter algorithm reduces artifacts such as hanging dots at color boundaries. It
detects and properly handles false colors in high-frequency luminance images such as a multiburst pattern
or circle pattern.
SLES140F–JULY 2005–REVISED DECEMBER 2010
Figure 2-6. Chroma Trap Filter Frequency Response, Figure 2-7. Chroma Trap Filter Frequency Response,
NTSC ITU-R BT.601 Sampling PAL ITU-R BT.601 Sampling
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Bandpass
Filter
×
Gain
Peaking
Filter
IN
+
OUT
Delay
Peak
Detector
f − Frequency − MHz
−1
0
1
2
3
4
5
6
7
0 1 2 3 4 5 6 7
Gain = 0
Gain = 2
Gain = 1
Gain = 0.5
Peak at
f = 2.64 MHz
Amplitude − dB
TVP5147M1
SLES140F–JULY 2005–REVISED DECEMBER 2010
2.2.3 Luminance Processing
The digitized composite video signal passes through either a luminance comb filter or a chroma trap filter,
either of which removes chrominance information from the composite signal to generate a luminance
signal. The luminance signal is then fed into the input of a peaking circuit. Figure 2-8 illustrates the basic
functions of the luminance data path. In the case of S-video, the luminance signal bypasses the comb filter
or chroma trap filter and is fed directly to the circuit. A peaking filter (edge enhancer) amplifies
high-frequency components of the luminance signal. Figure 2-9 shows the characteristics of the peaking
filter at four different gain settings that are user-programmable via the I2C interface.
Figure 2-8. Luminance Edge-Enhancer Peaking Block Diagram
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2.2.4 Color Transient Improvement
Color transient improvement (CTI) enhances horizontal color transients. The color difference signal
transition points are maintained, but the edges are enhanced for signals that have bandwidth-limited color
components.
22 Functional Description Copyright © 2005–2010, Texas Instruments Incorporated
Figure 2-9. Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling
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TVP5147M1
74
XTAL1
14.318-MHz
Crystal
75
XTAL2
TVP5147M1
74
XTAL1
75
XTAL2
C
L1
C
L2
14.318-MHz
Clock
TVP5147M1
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2.3 Clock Circuits
An internal line-locked PLL generates the system and pixel clocks. A 14.318-MHz clock is required to
drive the PLL. This can be input to the TVP5147M1 decoder at the 1.8-V level on terminal 74 (XTAL1), or
a crystal of 14.318-MHz fundamental resonant frequency can be connected across terminals 74 and 75
(XTAL2). If a parallel resonant circuit is used as shown in Figure 2-10, then the external capacitors must
have the following relationship:
CL1= CL2= 2CL − C
Where,
C
CLis the crystal load capacitance specified by the crystal manufacturer
Figure 2-10 shows the reference clock configurations. The TVP5147M1 decoder generates the DATACLK
signal used for clocking data.
is the terminal capacitance with respect to ground
STRAY
STRAY
SLES140F–JULY 2005–REVISED DECEMBER 2010
(1)
Figure 2-10. Reference Clock Configurations
2.4 Real-Time Control (RTC)
Although the TVP5147M1 decoder is a line-locked system, the color burst information is used to
determine accurately the color subcarrier frequency and phase. This ensures proper operation with
nonstandard video signals that do not follow exactly the required frequency multiple between color
subcarrier frequency and video line frequency. The frequency control word of the internal color subcarrier
PLL and the subcarrier reset bit are transmitted via terminal 37 (GLCO) for optional use in an end system
(for example, by a video encoder). The frequency control word is a 23-bit binary number. The
instantaneous frequency of the color subcarrier can be calculated using the following equation:
F
= (F
PLL
Where,
F
F
F
This information can be generated on the GLCO terminal. Figure 2-11 shows the detailed timing diagram.
/ 223) × F
ctrl
is the frequency of the subcarrier PLL
PLL
is the 23-bit PLL frequency control word
ctrl
is two times the pixel frequency
sclk
sclk
(2)
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RTC
45 CLK18 CLK
L
S
B
0
3 CLK128 CLK
23-Bit Fsc PLL Increment
Start
Bit
1 CLK
RS
Invalid
Sample
Valid
Sample
M
S
B
22
Reserved
TVP5147M1
SLES140F–JULY 2005–REVISED DECEMBER 2010
NOTE: RTC reset bit (R) is active-low, Sequence bit (S) PAL: 1 = (R-Y) line normal, 0 = (R-Y) line inverted, NTSC: 1 = no
change
Figure 2-11. RTC Timing
2.5 Output Formatter
The output formatter sets how the data is formatted for output on the TVP5147M1 output buses. Table 2-1
shows the available output modes.
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Table 2-1. Output Format
TERMINAL NAME TERMINAL NUMBER 10-Bit 4:2:2 YCbCr 20-Bit 4:2:2 YCbCr
Y_9 43 Cb9, Y9, Cr9 Y9
Y_8 44 Cb8, Y8, Cr8 Y8
Y_7 45 Cb7, Y7, Cr7 Y7
Y_6 46 Cb6, Y6, Cr6 Y6
Y_5 47 Cb5, Y5, Cr5 Y5
Y_4 50 Cb4, Y4, Cr4 Y4
Y_3 51 Cb3, Y3, Cr3 Y3
Y_2 52 Cb2, Y2, Cr2 Y2
Y_1 53 Cb1, Y1, Cr1 Y1
Y_0 54 Cb0, Y0, Cr0 Y0
C_9 57 Cb9, Cr9
C_8 58 Cb8, Cr8
C_7 59 Cb7, Cr7
C_6 60 Cb6, Cr6
C_5 63 Cb5, Cr5
C_4 64 Cb4, Cr4
C_3 65 Cb3, Cr3
C_2 66 Cb2, Cr2
C_1 69 Cb1, Cr1
C_0 70 Cb0, Cr0
24 Functional Description Copyright © 2005–2010, Texas Instruments Incorporated
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SLES140F–JULY 2005–REVISED DECEMBER 2010
Table 2-2. Summary of Line Frequencies, Data Rates, and Pixel/Line Counts
STANDARDS FREQUENCY LINE RATE
601 Sampling
NTSC-J, M 858 720 525 13.5 3.579545 15.73426
NTSC-4.43 858 720 525 13.5 4.43361875 15.73426
PAL-M 858 720 525 13.5 3.57561149 15.73426
PAL-60 858 720 525 13.5 4.43361875 15.73426
PAL-B, D, G, H, I 864 720 625 13.5 4.43361875 15.625
PAL-N 864 720 625 13.5 4.43361875 15.625
PAL-Nc 864 720 625 13.5 3.58205625 15.625
SECAM 864 720 625 13.5 15.625
PIXELS PER ACTIVE PIXELS LINES PER SUBCARRIER
LINE PER LINE FRAME FREQUENCY
PIXEL HORIZONTAL
(MHz) (kHz)
COLOR
(MHz)
Dr = 4.406250
Db = 4.250000
2.5.1 Separate Syncs
VS, HS, and VBLK are independently software programmable to a 1× pixel count. This allows any
possible alignment to the internal pixel count and line count. The default settings for 525-line and 625-line
video outputs are given as examples below. FID changes at the same transient time when the trailing
edge of vertical sync occurs. The polarity of FID is programmable by an I2C interface.
Copyright © 2005–2010, Texas Instruments Incorporated Functional Description 25
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First Field V ideo
525
VS
VBLK
FID
1 2 3 4 5 6 7 8 9 10 20 21
525-Line System
HS
VS Start VS Stop
CS
VBLK Start VBLK Stop
Second Field V ideo
262
VS
VBLK
FID
263 264 265 266 267 268 269 270 271 272 273 283 284
HS
VS Start VS Stop
CS
VBLK Start VBLK Stop
TVP5147M1
SLES140F–JULY 2005–REVISED DECEMBER 2010
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NOTE: Line numbering conforms to ITU-R BT.470.
Figure 2-12. Vertical Synchronization Signals for 525-Line System
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First Field V ideo
VS
VBLK
FID
625-Line System
HS
VS Start VS Stop
CS
VBLK Start VBLK Stop
Second Field V ideo
310
VS
VBLK
FID
311 312 313 314 315 316 317 318 319 320 336 337
HS
VS Start VS Stop
CS
VBLK Start VBLK Stop
622 623 624 625 1 2 3 4 5 6 7 23 24 25
338
TVP5147M1
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SLES140F–JULY 2005–REVISED DECEMBER 2010
NOTE: Line numbering conforms to ITU-R BT.470.
Figure 2-13. Vertical Synchronization Signals for 625-Line System
Copyright © 2005–2010, Texas Instruments Incorporated Functional Description 27
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Y[9:0]
NTSC 601 106
PAL 601
DATACLK = 2× Pixel Clock
112
128
1284248
Mode A B C
276
288
D
Cb
DATACLK
EAV
1
Y Cr Y
EAV
2
EAV3EAV
4
SAV1SAV2SAV3SAV
4
Cb0 Y0 Cr0 Y1
0
HS Start
Horizontal Blanking
HS
HS Stop
A C
B
AVID
D
AVID Stop AVID Start
TVP5147M1
SLES140F–JULY 2005–REVISED DECEMBER 2010
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NOTE: ITU-R BT.656 10-bit 4:2:2 timing with 2× pixel clock reference
Figure 2-14. Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode
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CbCr[9:0]
NTSC 601 53
PAL 601
DATACLK = 1× Pixel Clock
5664641922
Mode A B C
136
142
D
Cb
DATACLK
Cr Cb Cr Cb0 Cr0 Cb1 Cr1
0
HS Start
Horizontal Blanking
HS
HS Stop
A C
B
AVID
D
NOTE: AVID rising edge occurs four clock cycles early.
Y[9:0]
Y Y Y Y Y0 Y1 Y2 Y3Horizontal Blanking
2
AVID Stop AVID Start
TVP5147M1
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SLES140F–JULY 2005–REVISED DECEMBER 2010
NOTE: 20-bit 4:2:2 timing with 1× pixel clock reference
Figure 2-15. Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode
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NTSC 601 64
PAL 601
10-Bit (PCLK = 2 × Pixel Clock)
64
Mode B/2
First Field B/2
858
864
H/2
32
20-Bit (PCLK = 1 × Pixel Clock)
32
B/2
429
432
H/2
HS
VS
Second Field
HS
VS
B/2
H/2 + B/2 H/2 + B/2
TVP5147M1
SLES140F–JULY 2005–REVISED DECEMBER 2010
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Figure 2-16. VSYNC Position With Respect to HSYNC
2.5.2 Embedded Syncs
Standards with embedded syncs insert the SAV and EAV codes into the data stream on the rising and
falling edges of AVID. These codes contain the V and F bits, which also define vertical timing. Table 2-3
gives the format of the SAV and EAV codes.
H equals 1 always indicates EAV. H equals 0 always indicates SAV. The alignment of V and F to the line
and field counter varies depending on the standard.
The P bits are protection bits:
Preamble 1 1 1 1 1 1 1 1 1 1
Preamble 0 0 0 0 0 0 0 0 0 0
Preamble 0 0 0 0 0 0 0 0 0 0
Status word 1 F V H P3 P2 P1 P0 0 0
2.6 I2C Host Interface
P3 = V xor H; P2 = F xor H; P1 = F xor V; P0 = F xor V xor H
D9 (MSB) D8 D7 D6 D5 D4 D3 D2 D1 D0
Communication with the TVP5147M1 decoder is via an I2C host interface. The I2C standard consists of
two signals, the serial input/output data (SDA) line and the serial input clock line (SCL), which carry
information between the devices connected to the bus. A third signal (I2CA) is used for slave address
selection. Although an I2C system can be multimastered, the TVP5147M1 decoder functions as a slave
device only.
Table 2-3. EAV and SAV Sequence
30 Functional Description Copyright © 2005–2010, Texas Instruments Incorporated
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