Texas Instruments TSB14C01PM, TSB14C01MHVB, TSB14C01MHV, TSB14C01IPM Datasheet
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TSB14C01
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B – MARCH 1996 – REVISED MA Y 1997
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Supports Provisions of IEEE 1394-1995
(1394) Standard for High-Performance
Serial Bus
†
D
Fully Interoperable With FireWire
Implementation of 1394
D
Provides A Backplane Environment That
Supports 50 or 100 Megabits per Second
(Mbits/s)
D
Logic Performs System Initialization and
Arbitration Functions
D
Encode and Decode Functions Included for
Data-Strobe Bit-Level Encoding
D
Incoming Data Resynchronized to Local
Clock
D
Separate Transmitter and Receiver for
Greater Flexibility
D
Data Interface to Link-Layer Controller
(Link) Provided Through Two Parallel
Signal Lines at 25/50 MHz
D
100-MHz or 50-MHz Oscillator Provides
Transmit, Receive-Data, and Link Clocks at
25/50 MHz
D
Single 5-V Supply Operation
D
Packaged in a High-Performance 64-Pin
TQFP (PM) Package for 0°C to 70°C
Operation
D
Packaged in a 68-Pin CFP (HV) Package for
–55°C to 125°C Operation
description
The TSB14C01 provides the transceiver functions needed to implement a single port node in a backplanebased 1394 network. The TSB14C01 provides two terminals for transmitting, two terminals for receiving, and
a single terminal to externally control the drivers for data and strobe. The TSB14C01 is not designed to drive
the backplane directly , this function must be provided externally. The TSB14C01 is designed to interface with
a link-layer controller (link), such as the TSB12C01A.
The TSB14C01 requires an external 98.304-MHz or 49.152-MHz reference oscillator input for S100/50
operation. The reference signal is internally divided to provide the 49.152-MHz ±100-ppm system clock signals
used to control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock
signal is supplied to the associated link for synchronization of the two chips, when this device is in the S100 mode
of operation, OSC_SEL is asserted high. When the TSB14C01 is in the S50 mode of operation, the clock rate
supplied to the link is 24.576 MHz.
Data bits to be transmitted are received from the link on two parallel paths and are latched internally in the
TSB14C01 in synchronization with the 49.152-MHz system clock. These bits are combined serially , encoded,
and then transmitted at 98.304-Mbits/s (in S100 mode) as the outbound data-strobe information stream. During
transmission, the encoded data information is transmitted on TDATA, and the encoded strobe information is
transmitted on TSTRB.
During packet reception the encoded information is received on RDA TA and strobe information on RSTRB. The
received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The
serial data bits are split into two parallel streams, resynchronized to the local system clock, and sent to the
associated link.
The TSB14C01 is a 5-V device and provides CMOS-level outputs.
AVAILABLE OPTIONS
PACKAGES
T
A
CERAMIC FLAT PACK
(HV)
THIN QUAD FLAT PACK
(PM)
0°C to 70°C — TSB14C01PM
–55°C to 125°C TSB14C01MHV —
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright 1997, Texas Instruments Incorporated
†
This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.
FireWire is a trademark of Apple Computer, Incorporated.
TSB14C01
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B – MARCH 1996 – REVISED MA Y 1997
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
1718 19
NC
NC
NC
NC
NC
RDATA
RSTRB
V
CC
TDATA
TSTRB
GND
N_OEB_D
GND
PTEST_INDRV
V
CC
NC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
20
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ARB_CLK
PHYENA
V
CC
ENA_PRI
V
CC
N_POR
GND
LREQ
V
CC
SCLK
TSCLK
GND
CTL0
CTL1
D0
D1
21 22 23 24
OSC_SEL
63 62 61 60 5964 58
TI1
NC
XI_50
GND
EX_PRI3
EX_PRI2
EX_PRI1
EN_EXPRI
EX_ID5
EX_ID4
EX_ID3
EX_ID2
EX_ID1
EX_ID0
56 55 5457
25 26 27 28 29
53 52
NC
XI_100
51 50 49
30 31 32
EX_PRI0
NC
NC
GND
GND
GND
GND
RPREFIX
EN_EXID
NC – No connection
PM PACKAGE
(TOP VIEW)
V
CC
V
CC
V
CC
GND
VCCV
CC
TSB14C01
TSB14C01
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B – MARCH 1996 – REVISED MA Y 1997
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NC – No connection
HV PACKAGE
(TOP VIEW)
TSB14C01M
28 29
NC
NC
NC
NC
NC
RDATA
RSTRB
V
CC
TDATA
TSTRB
GND
N_OEB_D
GND
PTEST_INDRV
V
CC
NC
NC
30
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
NC
ARB_CLK
PHYENA
V
CC
ENA_PRI
V
CC
N_POR
GND
LREQ
V
CC
SCLK
TSCLK
GND
CTL0
CTL1
D0
D1
31 32 33 34
87 65493168672
35 36 37 38 39
66 65
27
64 63 62 61
40 41 42 43
VCCTI1
VCCGND
VCCVCCRPREFIX
GND
NC
GND
GND
GND
NC
NC
OSC_SEL
XI_100
XI_50
GND
EX_PRI3
EX_PRI2
EX_PRI1
EN_EXPRI
EX_ID5
EX_ID4
EX_ID3
EX_ID2
EX_ID1
EX_ID0
EX_PRI0
NC
NC
EN_EXID
V
CC
NC
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
TSB14C01
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B – MARCH 1996 – REVISED MA Y 1997
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
system block diagram
1394 Link-
Layer
Controller
Host
Interface
D0 – D1
CTL0 – CTL1
LREQ
SCLK
1394
Backplane
Physical-
Layer
Controller
TSB14C01
BPdata
BPstrb
NOTE A: The backplane transceiver is customer supplied and is different for each type of backplane.
2
/
2
/
Tdata
Rdata
Rstrb
Tstrb
N_OEB_D
functional block diagram
TSTRB
Sub Act Gap
Cycle Req
Iso Req
LINK/PHY
Interface
SCLK
D0 – D1
CTL0 – CTL1
LREQ
CLK
(see Note A)
Physical ID
Pr0 – Pr3
Fair/Urg Req
Ack Req
Arb Won
Arb Lost
Arb Res Gap
Ack Gap
Bus Reset
CLK
RxData
RxCLK
ARB
Control
Data
Encode
SCLK
D0, D1
Data
Resync/
Decode
CLK
TxArbStrb
TxArbData
RxStb
RxData
CLK
RxCLK
RSTRB
RDATA
ARB/DATA
MUX
TxPktStrb
TxPktData
TDATA
2
/
2
/
NOTE A: CLK is either terminal XI_50 or XI_100 depending on the mode selection.
TSB14C01
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B – MARCH 1996 – REVISED MA Y 1997
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME PM
NO.
HV
NO.
TYPE
I/O DESCRIPTION
ÁÁÁÁ
Á
ÁÁÁÁ
Á
ARB_CLK
ÁÁÁ
Á
Á
Á
Á
Á
Á
1
ÁÁ
Á
ÁÁ
Á
11
ÁÁ
Á
ÁÁ
Á
TTL
Á
Á
Á
Á
O
ББББББББББББББББ
Á
ББББББББББББББББ
Á
Arbitration clock. ARB_CLK is the clock used for arbitration. ARB_CLK is
for test and debug. It can be put into a high-impedance state by
PTEST_INDRV. This terminal is not used in normal operation and is
always at 49.152 MHz.
ÁÁÁÁ
Á
CTL0, CTL1
ÁÁÁ
Á
Á
Á
13, 14
ÁÁ
Á
23, 24
ÁÁ
Á
TTL
Á
Á
I/O
ББББББББББББББББ
Á
Control I/O. These are bidirectional signals that communicate between the
TSB14C01 and the link that control passage of information between the
two devices.
ÁÁÁÁ
Á
D0, D1
ÁÁÁ
Á
Á
Á
15, 16
ÁÁ
Á
25, 26
ÁÁ
Á
TTL
Á
Á
I/O
ББББББББББББББББ
Á
Data I/O. These are bidirectional information signals that communicate
between the TSB14C01 and the link.
ENA_PRI
ÁÁÁ
4
14
TTL
I
Enable priority . ENA_PRI is tied low to enable the 7-bit bus request. See
Table 1 for more information.
ÁÁÁÁ
Á
EN_EXID
ÁÁÁ
Á
Á
Á
18
ÁÁ
Á
30
ÁÁ
Á
TTL
Á
Á
I
ББББББББББББББББ
Á
Enable external ID. When EN_EXID is asserted high, the ID for this node
is set externally by EX_ID. When this terminal is tied/driven low, the
source of the ID comes from the internal ID register.
ÁÁÁÁ
Á
ÁÁÁÁ
Á
EN_EXPRI
ÁÁÁ
Á
Á
Á
Á
Á
Á
19
ÁÁ
Á
ÁÁ
Á
31
ÁÁ
Á
ÁÁ
Á
TTL
Á
Á
Á
Á
I
ББББББББББББББББ
Á
ББББББББББББББББ
Á
Enable external priority . When EN_EXPRI is asserted high (external
priority enabled) the priority level for this node is set externally (see
Table 1). This terminal should be tied low when not used.
EX_ID5 – EX_ID0
ÁÁÁ
20,21,22,
23,24,25
32,33,34,
35,36,37
TTL
I
External ID. The ID for this node is determined by the value on the EX_ID
terminals. Bit 0 is the MSB.
ÁÁÁÁ
Á
EX_PRI3 –
EX_PRI0
ÁÁÁ
Á
Á
Á
27,28,
29,30
ÁÁ
Á
39,40,
41,42
ÁÁ
Á
TTL
Á
Á
I
ББББББББББББББББ
Á
External priority. The priority for this node is determined by the values on
the EX_PRI terminals. See Table 1 for more information.
ÁÁÁÁ
Á
ÁÁÁÁ
Á
GND
ÁÁÁ
Á
Á
Á
Á
Á
Á
7,12,26,
36,38,49,
51,54,60,
64
ÁÁ
Á
ÁÁ
Á
4,8,17,
22,38,48,
50,61,63,
66
ÁÁ
Á
ÁÁ
Á
Supply
Á
Á
Á
Á
—
ББББББББББББББББ
Á
ББББББББББББББББ
Á
Circuit ground
LREQ
ÁÁÁ
8
18
TTL
I
Link request input. LREQ is an input from the link used by the link to
signal the TSB14C01 of a request to perform some service.
ÁÁÁÁ
Á
V
CC
ÁÁÁ
Á
Á
Á
3,5,9,17,
34,41,57,
59,61,62
ÁÁ
Á
1,3,5,6,
13,15,19,
29,46,53
ÁÁ
Á
Supply
Á
Á
—
ББББББББББББББББ
Á
Circuit power
ÁÁÁÁ
Á
ÁÁÁÁ
Á
NC
ÁÁÁ
Á
Á
Á
Á
Á
Á
31,32,33,
44,45,46,
47,48,53,
56
ÁÁ
Á
ÁÁ
Á
9,10,27,
28,43–45,
56–60,
65,68
ÁÁ
Á
ÁÁ
Á
—
Á
Á
Á
Á
—
ББББББББББББББББ
Á
ББББББББББББББББ
Á
Not connected. These terminals must be left floating.
ÁÁÁÁ
Á
N_OEB_D
ÁÁÁ
Á
Á
Á
37
ÁÁ
Á
49
ÁÁ
Á
TTL
Á
Á
O
ББББББББББББББББ
Á
External driver enable. N_OEB_D is a negative active signal that enables
the external driver for TDATA and TSTRB.
N_POR
ÁÁÁ
6
16
TTL
I
Logic reset input . Forcing N_POR low causes a reset condition and
resets the internal logic to the reset start state.
ÁÁÁÁ
Á
OSC_SEL
ÁÁÁ
Á
Á
Á
50
ÁÁ
Á
62
ÁÁ
Á
VCC /
GND
Á
Á
I
ББББББББББББББББ
Á
Select clock frequency. OSC_SEL should be pulled up to VCC when the
operating frequency is 50 MHz. When the operating frequency is 100 MHz
then it should be pulled to ground. It should not be left floating
.
ÁÁÁÁ
Á
ÁÁÁÁ
Á
PHYENA
ÁÁÁ
Á
Á
Á
Á
Á
Á
2
ÁÁ
Á
ÁÁ
Á
12
ÁÁ
Á
ÁÁ
Á
TTL
Á
Á
Á
Á
O
ББББББББББББББББ
Á
ББББББББББББББББ
Á
Phy enable. When the phy is driving it is low, PHYENA is the control to the
CTL0, CTL1, D0, and D1 drivers. PHYENA is for test and debug. It can
be put into a high-impedance state by PTEST_INDRV. This terminal is not
used in normal operation.
ÁÁÁÁ
Á
PTEST_INDRV
ÁÁÁ
Á
Á
Á
35
ÁÁ
Á
47
ÁÁ
Á
TTL
Á
Á
I
ББББББББББББББББ
Á
Test output enable. PTEST_INDRV enables/disables the drivers to the
test terminals ARB_CLK, PHYENA, and RPREFIX. During normal
operation, PTEST_INDRV should be tied to VCC to disable the drivers.
RDATA
ÁÁÁ
43
55
TTL
I
Receive data. Incoming data is received at the data rate.
TSB14C01
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B – MARCH 1996 – REVISED MA Y 1997
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (continued)
TERMINAL
NAME PM
NO.
HV
NO.
TYPE
I/O DESCRIPTION
ÁÁÁÁ
Á
RPREFIX
ÁÁ
Á
63
ÁÁ
Á
7
ÁÁ
Á
TTL
O
БББББББББББББББББ
Á
Receiver prefix. When asserted high (enabled), RPREFIX alerts the
receiver of an incoming packet. RPREFIX is for test and debug and is not
used in normal operation.
RSTRB
42
54
TTL
I
Receive strobe. RSTRB decodes the received data.
ÁÁÁÁ
Á
SCLK
ÁÁ
Á
10
ÁÁ
Á
20
ÁÁ
Á
TTL
O
БББББББББББББББББ
Á
System clock output. A 49.152-MHz or 24.576-MHz clock signal
synchronized with the data transfers, and provided to the link.
TDATA
40
52
CMOS
O
Transmit data. Data to be transmitted is serialized on TDAT A.
TI1
58
2
TTL
I
Test input 1. TI1 is used for test purposes only and should be tied to
ground for normal operation.
ÁÁÁÁ
Á
TSCLK
ÁÁ
Á
11
ÁÁ
Á
21
ÁÁ
Á
TTL
O
БББББББББББББББББ
Á
System clock output. A 49.152-MHz or 24.576-MHz clock signal that is 180
degrees out of phase with SCLK; it is available if needed.
TSTRB
39
51
CMOS
O
Transmit strobe. TSTRB encodes transmit data.
XI_50
55
67
CMOS
I
External oscillator input. An external 49.152-MHz oscillator can drive the
TSB14C01.
ÁÁÁÁ
Á
XI_100
ÁÁ
Á
52
ÁÁ
Á
64
ÁÁ
Á
CMOS
I
БББББББББББББББББ
Á
External oscillator input. An external 98.304-MHz oscillator can drive the
TSB14C01.
Table 1. External Priority Coding
EXTERNAL PRIORITY TERMINALS
ENA_PRI EN_EXPRI EX_PRI0 – EX_PRI3
DESCRIPTION
X H
L L L L
L L L H
.
.
.
H H H H
The priority for this node is determined by the values on EX_PRI0 – EX_PRI3.
The state of ENA_PRI can be either tied to VCC or GND.
L L X This sets a 7-bit bus request and is the cable environment format. Priority must be
set by executing a write request (see Table 10).
H L X This sets an 11-bit bus request and is the backplane environment format. Priority
is dynamically set as part of the bus request (see Table 8)
TSB14C01
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B – MARCH 1996 – REVISED MA Y 1997
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 6.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, V
I
–0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range at any output, V
O
–0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free air temperature, T
A
:TSB14C01 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSB14C01M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
TA ≤ 25°C
POWER RATING
DERATING FACTOR
‡
ABOVE TA = 25°C
TA = 70°C
POWER RATING
TA = 125°C
POWER RATING
HV 1689 mW 13.5 mW/°C 1081 mW 337 mW
PM 1350 mW 10.8 mW/°C 864 mW —
‡
This is the inverse of the traditional junction-to-ambient thermal resistance (R
θJA
) and uses a board-mounted R
θJA
of
92.5°C/W for the PM package and 74°C/W for the HV package.
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
4.5 5 5.25 V
p
CMOS inputs
0.7 V
CC
V
High-level input voltage, V
IH
TTL input
2
V
CC
V
p
CMOS inputs
0
0.2 V
CC
V
Low-level input voltage, V
IL
TTL input
0
0.8
V
Input voltage, V
I
CMOS/TTL
0
V
CC
V
p
CMOS Drivers
12
High-level output current, I
OH
TTL Drivers
8
mA
p
CMOS Drivers
24
Low-level output current, I
OL
TTL Drivers
8
mA
TSB14C01
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B – MARCH 1996 – REVISED MA Y 1997
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended ranges of operating conditions (unless otherwise
noted)
device
PARAMETER TEST CONDITIONS
MIN TYP MAX UNIT
V
OH
High-level output voltage
IOH = max,
VCC = min
VCC–0.8
V
V
OL
Low-level output voltage
IOL = min,
VCC = max
0.5
V
Input current
VI = VCC or 0
±1
µA
I
OZ
Off-state output current
VI = VCC or 0
±10
µA
thermal characteristics
PARAMETER
TEST CONDITION
MIN
TYP
MAX
UNIT
TSB14C01
83
°C/W
R
θJA
Junction-to-free-air thermal resistance
TSB14C01M
Board mounted, No air flo
w
74
°C/W
TSB14C01
16
°C/W
R
θJC
Junction-to-case thermal resistance
TSB14C01M
3
°C/W
switching characteristics, VCC = 5 V, TA = 25°C (See Note 1)
PARAMETER
БББББ
MEASURED
TEST CONDITION
MIN
TYP
MAX
UNIT
t
su
D, CTL, LREQ low or high before SCLK high
БББББ
50% to 50%
See Figure 1
7
ns
t
h
D, CTL, LREQ low or high after SCLK high
БББББ
50% to 50%
See Figure 1
1
ns
t
d
Delay time, SCLK high to D, CTL high or low
БББББ
50% to 50%
See Figure 2
10
ns
NOTE 1: These parameters are ensured by design and are not production tested.
PARAMETER MEASUREMENT INFORMATION
t
su
t
h
SCLK
D, CTL, LREQ
50%
Figure 1. D, CTL, LREQ Input Setup and Hold Timing Waveforms
t
d
SCLK
D, CTL
50%
Figure 2. D, CTL Output Delay Relative to SCLK Timing Waveforms
TSB14C01
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B – MARCH 1996 – REVISED MA Y 1997
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
internal register configuration
The accessible internal registers of this device are listed in Table 2. Bit field descriptions for the registers are
given in Table 3.
Table 2. Format for Registers
ADDRESS 0 1 2 3 4 5 6 7
0000 Physical
ID[0]
Physical
ID[1]
Physical
ID[2]
Physical
ID[3]
Physical
ID[4]
Physical
ID[5]
Reserved Reserved
0001 INHB IBR RESERVED
0011 RESERVED
0100 Priority
level[0]
Priority
level[1]
Priority
level[2]
Priority
level[3]
RESERVED
Table 3. Register Bit Field Key
ÁÁÁ
Á
FIELD
Á
Á
SIZE
(Bits)
ÁÁ
Á
TYPE
ББББББББББББББББББББББ
Á
DESCRIPTION
Physical ID
6
Read/Write
Physical identification. Physical ID is the address of the local node and is set to zero on power up.
INHB
1
Read/Write
Inhibit Drivers. INHB is used to turn off the drivers to TDA TA and TSTRB.
IBR
1
Read/Write
Initiate Bus Reset. IBR is turned on by the link and turned off by the phy when reset is complete.
ÁÁÁ
Á
Priority
Á
Á
4
ÁÁ
Á
Read/Write
ББББББББББББББББББББББ
Á
Priority setting. The four bits contain the priority of the local node. A higher value in this field
indicates a higher priority.
transceiver selection
The system designer must select transceivers appropriate to the system requirements to be used with the
TSB14C01 and the link layer selected. The following lists requirements for the transceivers needed.
D
The transceivers used must be appropriate to the backplane technology used.
The various backplane technologies require different electrical characteristics in their backplanes. For
example BTL uses an operating voltage on the backplane of 2.1 V and a characteristic impedance of 33 Ω
while GTL uses an operating voltage of 1.2 V and a characteristic impedance of 50 Ω (see
GTL/BTL a Low
Swing Solution for High-Speed Digital Logic
, TI literature number SCEA003). When a backplane is
designed to use BTL technology , then it would be appropriate to also use that technology for the two lines
dedicated to the 1394 serial bus. The drivers selected also must be able to supply the current required for the
expected backplane loading. For example, BTL operates correctly for a FutureBus configuration backplane
at 50 Mbits/s or for a limited number of nodes in a custom configuration at 100 Mbits/s. See the
GTL/BTL a
Low Swing Solution for High-Speed Digital Logic
, TI literature number SCEA003 or the documentation for
the transceiver being considered.
D
The transceivers used must assert logic states on the backplane in an appropriate manner for the 1394
backplane arbitration.
Arbitration under 1394 backplane rules requires the drivers to assert the bus to indicate a logical 1 state, that
is a logic 1 being driven by the TSB14C01. Conversely , the drivers should release the bus to indicate a logic
0 state, a logic 0 being driven by the TSB14C01. In other words, all drivers must operate in a Wired-OR mode
during arbitration.
D
The transceivers used must be able to monitor the bus and drive the bus at the same time.
TSB14C01
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SLLS231B – MARCH 1996 – REVISED MA Y 1997
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
During arbitration, each node that is arbitrating for the bus drives its code then its node number out onto the
bus. During each bit period, each node reads back what has been placed on the bus. If it reads back the
same data it was sending, the arbitrating node stays in contention for winning the bus. If it reads something
different then what it was driving, the arbitrating node loses the bus and drops out of contention. This is the
reason for requiring Wired-OR operation during arbitration. As long as each node is still sending 0s onto the
bus during arbitration, all nodes are still contending to win the bus. The node with the highest priority (or if all
priorities were zero then the highest node number) is the first to drive a 1 onto the bus during arbitration. The
node that sends the first 1 (asserting the bus) and reads it back wins the bus. All other nodes read back a 1,
which does not match the 0 (releasing the bus) they are sending, and drop out of contention. This arbitration
process requires the transceiver selected to be able to read from the bus at the same time it is driving the
bus.
For example, if three nodes, each with priority 0 and a node identifiers of 8, 7, and 2, were to arbitrate for the
bus the following would occur:
000 000
Driven by Node #2
(TSB14C01)
00 00
000 000
Driven by Node #7
(TSB14C01)
00 00
000 010
Driven by Node #8
(TSB14C01)
00 00
Bus Data Line
(voltage level on the bus)
Bus Read
NOTE A: This bus is reverse logic, a 1 being driven by the TSB14C01 is asserted by driving a 0 onto the bus by the transceiver.
Figure 3. Three Nodes Arbitrating for the Bus
Since the highest node number is 8 (1000b), node 8 outputs the first 1 (assert the bus) and wins the
arbitration. The other nodes drop out and do not try to drive their node number onto the bus.
D
The transceivers used must be appropriate for the transfer speed required.
The 1394 bus has two data lines that use Data-Strobe Encoding on the bus. This requires that the
transceivers be able to operate at a maximum frequency of one half of the maximum data transfer rate.
When operating at 50 Mbits/s, the maximum frequency the drivers are required to operate at is 25 MHz.
When operating at 100 Mbits/s, the maximum frequency the drivers are required to operate at is 50 MHz.
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