Texas Instruments TSB14C01APM, TSB14C01AIPM Datasheet
TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
D
Supports Provisions of IEEE 1394-1995
(1394) Standard for High-Performance
Serial Bus
D
Fully Interoperable With FireWire
†
Implementation of 1394
D
Provides A Backplane Environment That
Supports 50 or 100 Megabits per Second
(Mbits/s)
D
Logic Performs System Initialization and
Arbitration Functions
D
Encode and Decode Functions Included for
Data-Strobe Bit-Level Encoding
D
Incoming Data Resynchronized to Local
Clock
description
The TSB14C01A provides the transceiver functions needed to implement a single port node in a backplanebased 1394 network. The TSB14C01A provides two terminals for transmitting, two terminals for receiving, and
a single terminal to externally control the drivers for data and strobe. The TSB14C01A is not designed to drive
the backplane directly , this function must be provided externally . The TSB14C01A is designed to interface with
a link-layer controller (link), such as the TSB12C01A.
D
Separate Transmitter and Receiver for
Greater Flexibility
D
Data Interface to Link-Layer Controller
(Link) Provided Through Two Parallel
Signal Lines at 25/50 MHz
D
100-MHz or 50-MHz Oscillator Provides
Transmit, Receive-Data, and Link Clocks at
25/50 MHz
D
Single 5-V Supply Operation
D
Packaged in a High-Performance 64-Pin
TQFP (PM) Package for 0°C to 70°C
Operation and –40°C to 85°C Operation
D
Packaged in a 68-Pin CFP (HV) Package for
–55°C to 125°C Operation
The TSB14C01A requires an external 98.304-MHz or 49.152-MHz reference oscillator input for S100/50
operation. The reference signal is internally divided to provide the 49.152-MHz ±100-ppm system clock signals
used to control transmission of the outbound encoded strobe and data information. The 49.152-MHz clock
signal is supplied to the associated link for synchronization of the two chips. When this device is in the S100
mode of operation, OSC_SEL is asserted high. When the TSB14C01A is in the S50 mode of operation, the clock
rate supplied to the link is 24.576 MHz.
Data bits to be transmitted are received from the link on two parallel paths and are latched internally in the
TSB14C01A in synchronization with the 49.152-MHz system clock. These bits are combined serially , encoded,
and then transmitted at 98.304-Mbits/s (in S100 mode) as the outbound data-strobe information stream. During
transmission, the encoded data information is transmitted on TDATA, and the encoded strobe information is
transmitted on TSTRB.
During packet reception the encoded information is received on RDA TA and strobe information on RSTRB. The
received data-strobe information is decoded to recover the receive clock signal and the serial data bits. The
serial data bits are split into two parallel streams, resynchronized to the local system clock, and sent to the
associated link.
The TSB14C01A is a 5-V device and provides CMOS-level outputs.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
†
This serial bus implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.
FireWire is a trademark of Apple Computer, Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1
TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
AVAILABLE OPTIONS
PACKAGES
T
A
0°C to 70°C — TSB14C01APM
–40°C to 85°C — TSB14C01AIPM
–55°C to 125°C TSB14C01AMHV —
CERAMIC FLAT PACK
GND
RPREFIX
CC
(HV)
VCCV
GND
PM PACKAGE
(TOP VIEW)
CC
CC
V
V
TI1
NC
THIN QUAD FLAT PACK
GND
XI_50
NC
(PM)
GND
XI_100
GND
OSC_SEL
ARB_CLK
PHYENA
ENA_PRI
N_POR
GND
LREQ
SCLK
TSCLK
GND
CTL0
CTL1
NC – No connection
1
2
V
3
CC
4
V
5
CC
6
7
8
V
9
CC
10
11
12
13
14
15
D0
16
D1
63 62 61 60 5964 58
1718 19
CC
V
21 22 23 24
20
EX_ID5
EN_EXID
EN_EXPRI
TSB14C01A
EX_ID4
EX_ID3
EX_ID2
56 55 5457
25 26 27 28 29
53 52
GND
EX_ID1
EX_ID0
EX_PRI3
51 50 49
30 31 32
EX_PRI0
EX_PRI2
EX_PRI1
NC
NC
48
NC
47
NC
46
NC
45
NC
44
RDATA
43
RSTRB
42
V
41
CC
TDATA
40
TSTRB
39
GND
38
37
N_OEB_D
36
GND
35
PTEST_INDRV
34
V
CC
33
NC
NC
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
NC
TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
HV PACKAGE
(TOP VIEW)
VCCTI1
VCCGND
GND
VCCVCCRPREFIX
NC
GND
XI_50
NC
GND
XI_100
GND
OSC_SEL
NC
10
ARB_CLK
PHYENA
ENA_PRI
N_POR
GND
LREQ
SCLK
TSCLK
GND
CTL0
CTL1
NC – No connection
11
12
V
13
CC
14
V
15
CC
16
17
18
19
V
CC
20
21
22
23
24
25
D0
26
D1
27
87 65493168672
TSB14C01AM
28 29
30
31 32 33 34
NC
NC
CC
V
EX_ID5
EN_EXID
EN_EXPRI
35 36 37 38 39
EX_ID4
EX_ID3
EX_ID2
66 65
EX_ID1
EX_ID0
GND
EX_PRI3
64 63 62 61
40 41 42 43
EX_PRI2
EX_PRI1
EX_PRI0
NC
60
59
NC
58
NC
57
NC
56
NC
55
RDATA
54
RSTRB
53
V
CC
52
TDATA
51
TSTRB
50
GND
49
N_OEB_D
48
GND
47
PTEST_INDRV
46
V
CC
45
NC
44
NC
NC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
system block diagram
N_OEB_D
Iso Req
Ack Req
Arb Won
Arb Lost
Ack Gap
CLK
2
/
2
/
TSB14C01A
1394
Backplane
Physical-
Layer
Controller
ARB
Control
SCLK
D0, D1
CLK
RxData
TxArbStrb
TxArbData
RxStb
CLK
Tdata
Rdata
Tstrb
Rstrb
Data
Encode
Resync/
Decode
D0 – D1
Host
Interface
NOTE A: The backplane transceiver is customer supplied and is different for each type of backplane.
1394 Link-
Layer
Controller
CTL0 – CTL1
LREQ
SCLK
functional block diagram
SCLK
Physical ID
Pr0 – Pr3
Fair/Urg Req
Cycle Req
Arb Res Gap
Sub Act Gap
Bus Reset
D0 – D1
CTL0 – CTL1
LREQ
(see Note A)
2
/
2
/
LINK/PHY
Interface
CLK
Data
TxPktStrb
TxPktData
ARB/DATA
MUX
BPdata
BPstrb
TSTRB
TDATA
RSTRB
RDATA
RxData
RxCLK
NOTE A: CLK is either terminal XI_50 or XI_100 depending on the mode selection.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
RxCLK
TERMINAL
Á
Á
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
Á
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
Á
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
Á
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
Á
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
NAME PM
ARB_CLK
ÁÁÁÁ
ÁÁÁÁ
CTL0, CTL1
ÁÁÁÁ
D0, D1
ÁÁÁÁ
ENA_PRI
EN_EXID
ÁÁÁÁ
EN_EXPRI
ÁÁÁÁ
ÁÁÁÁ
EX_ID5 – EX_ID0
EX_PRI3 –
EX_PRI0
ÁÁÁÁ
GND
ÁÁÁÁ
ÁÁÁÁ
LREQ
V
CC
ÁÁÁÁ
NC
ÁÁÁÁ
ÁÁÁÁ
N_OEB_D
ÁÁÁÁ
N_POR
OSC_SEL
ÁÁÁÁ
PHYENA
ÁÁÁÁ
ÁÁÁÁ
PTEST_INDRV
ÁÁÁÁ
RDATA
NO.
1
Á
Á
13, 14
Á
15, 16
Á
4
18
Á
19
Á
Á
20,21,22,
23,24,25
27,28,
29,30
Á
7,12,26,
36,38,49,
Á
51,54,60,
64
Á
8
3,5,9,17,
34,41,57,
Á
59,61,62
31,32,33,
Á
44,45,46,
47,48,53,
Á
56
37
Á
6
50
Á
2
Á
Á
35
Á
43
HV
NO.
11
ÁÁ
ÁÁ
23, 24
ÁÁ
25, 26
ÁÁ
14
30
ÁÁ
31
ÁÁ
ÁÁ
32,33,34,
35,36,37
39,40,
41,42
ÁÁ
4,8,17,
22,38,48,
ÁÁ
50,61,63,
66
ÁÁ
18
1,3,5,6,
13,15,19,
ÁÁ
29,46,53
9,10,27,
ÁÁ
28,43–45,
56–60,
ÁÁ
65,68
49
ÁÁ
16
62
ÁÁ
12
ÁÁ
ÁÁ
47
ÁÁ
55
TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
Terminal Functions
TYPE
TTL
ÁÁ
ÁÁ
TTL
ÁÁ
TTL
ÁÁ
TTL
TTL
ÁÁ
TTL
ÁÁ
ÁÁ
TTL
TTL
ÁÁ
Supply
ÁÁ
ÁÁ
TTL
Supply
ÁÁ
—
ÁÁ
ÁÁ
TTL
ÁÁ
TTL
VCC /
ÁÁ
GND
TTL
ÁÁ
ÁÁ
TTL
ÁÁ
TTL
I/O DESCRIPTION
O
Arbitration clock. ARB_CLK is the clock used for arbitration. ARB_CLK is
for test and debug. It can be put into a high-impedance state by
Á
Á
Á
Á
ББББББББББББББББ
PTEST_INDRV. This terminal is not used in normal operation and is
ББББББББББББББББ
always at 49.152 MHz.
I/O
Control I/O. These are bidirectional signals that communicate between the
TSB14C01A and the link that controls passage of information between the
ББББББББББББББББ
two devices.
I/O
Data I/O. These are bidirectional information signals that communicate
between the TSB14C01A and the link layer.
ББББББББББББББББ
I
Enable priority . ENA_PRI is tied low to enable the 7-bit bus request. See
Table 1 for more information.
I
Enable external ID. When EN_EXID is asserted high, the ID for this node
is set externally by EX_ID. When this terminal is tied/driven low, the
Á
ББББББББББББББББ
source of the ID comes from the internal ID register.
I
Enable external priority . When EN_EXPRI is asserted high (external
Á
Á
ББББББББББББББББ
priority enabled) the priority level for this node is set externally (see
Table 1). This terminal should be tied low when not used.
ББББББББББББББББ
I
External ID. The ID for this node is determined by the value on the EX_ID
terminals. Bit 0 is the MSB.
I
External priority . The priority for this node is determined by the values on
the EX_PRI terminals. See Table 1 for more information.
Á
Á
Á
ББББББББББББББББ
—
Circuit ground
ББББББББББББББББ
ББББББББББББББББ
I
Link request input. LREQ is an input from the link used by the link to
signal the TSB14C01A of a request to perform some service.
—
Circuit power
Á
Á
Á
Á
ББББББББББББББББ
—
Not connected. These terminals must be left floating.
ББББББББББББББББ
ББББББББББББББББ
O
External driver enable. N_OEB_D is a negative active signal that enables
the external driver for TDATA and TSTRB.
ББББББББББББББББ
I
Logic reset input . Forcing N_POR low causes a reset condition and
resets the internal logic to the reset start state.
I
Select clock frequency. OSC_SEL should be pulled up to VCC when the
Á
ББББББББББББББББ
operating frequency is 50 MHz. When the operating frequency is 100 MHz
then it should be pulled to ground. It should not be left floating
O
Phy enable. When the phy is driving it is low, PHYENA is the control to the
Á
Á
ББББББББББББББББ
CTL0, CTL1, D0, and D1 drivers. PHYENA is for test and debug. It can
be put into a high-impedance state by PTEST_INDRV. This terminal is not
ББББББББББББББББ
used in normal operation.
I
Test output enable. PTEST_INDRV enables/disables the drivers to the
Á
ББББББББББББББББ
test terminals ARB_CLK, PHYENA, and RPREFIX. During normal
operation, PTEST_INDRV should be tied to VCC to disable the drivers.
I
Receive data. Incoming data is received at the data rate.
.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
TSB14C01A, TSB14C01AI, TSB14C01AM
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
DESCRIPTION
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
Terminal Functions (continued)
TERMINAL
NAME PM
RPREFIX
ÁÁÁÁ
RSTRB
SCLK
ÁÁÁÁ
TDATA
TI1
TSCLK
ÁÁÁÁ
TSTRB
XI_50
XI_100
ÁÁÁÁ
NO.
63
ÁÁ
42
10
ÁÁ
40
58
11
ÁÁ
39
55
52
ÁÁ
HV
NO.
7
ÁÁ
54
20
ÁÁ
52
2
21
ÁÁ
51
67
64
ÁÁ
TYPE
TTL
ÁÁ
TTL
TTL
ÁÁ
CMOS
TTL
TTL
ÁÁ
CMOS
CMOS
CMOS
ÁÁ
I/O DESCRIPTION
O
Receiver prefix. When asserted high (enabled), RPREFIX alerts the
receiver of an incoming packet. RPREFIX is for test and debug and is not
БББББББББББББББББ
used in normal operation.
I
Receive strobe. RSTRB decodes the received data.
O
System clock output. A 49.152-MHz or 24.576-MHz clock signal
synchronized with the data transfers, and provided to the link.
БББББББББББББББББ
O
Transmit data. Data to be transmitted is serialized on TDAT A.
I
Test input 1. TI1 is used for test purposes only and should be tied to
ground for normal operation.
O
System clock output. A 49.152-MHz or 24.576-MHz clock signal that is 180
degrees out of phase with SCLK; it is available if needed.
БББББББББББББББББ
O
Transmit strobe. TSTRB encodes transmit data.
I
External oscillator input. An external 49.152-MHz oscillator can drive the
TSB14C01A.
I
External oscillator input. An external 98.304-MHz oscillator can drive the
TSB14C01A.
БББББББББББББББББ
Table 1. External Priority Coding
EXTERNAL PRIORITY TERMINALS
ENA_PRI EN_EXPRI EX_PRI0 – EX_PRI3
L L L L
L L L H
X H
.
.
The priority for this node is determined by the values on EX_PRI0 – EX_PRI3.
The state of ENA_PRI can be either tied to VCC or GND.
.
H H H H
L L X This sets a 7-bit bus request and is the cable environment format. Priority must be
H L X This sets an 11-bit bus request and is the backplane environment format. Priority
set by executing a write request (see Table 10).
is dynamically set as part of the bus request (see Table 8)
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB14C01A, TSB14C01AI, TSB14C01AM
High-level input voltage, V
Low-level input voltage, V
High-level output current, I
mA
Low-level output current, I
mA
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
Input voltage range, V
Output voltage range at any output, V
CC
I
O
–0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous total power dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free air temperature, TA:TSB14C01A 0°C to 70°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSB14C01AI –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TSB14C01AM –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds 300°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATING TABLE
PACKAGE
HV 1689 mW 13.5 mW/°C 1081 mW 879 mW 337 mW
PM 1602 mW 12.8 mW/°C 1025 mW 833 mW —
‡
This is the inverse of the traditional junction-to-ambient thermal resistance (R
and 74°C/W for the HV package.
TA ≤ 25°C
POWER RATING
DERATING FACTOR
ABOVE TA = 25°C
‡
POWER RATING
θJA
TA = 70°C
) and uses a board-mounted R
TA = 85°C
POWER RATING
of 78°C/W for the PM package
θJA
–0.5 V to 6.0 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TA = 125°C
POWER RATING
recommended operating conditions
†
MIN NOM MAX UNIT
Supply voltage, V
Input voltage, V
Virtual Junction Temperature, TJ §
Operating Free-Air Temperature, T
§
Actual junction temperature is a function of ambient temperature, package selection, power dissipation, and air flow. Customer is responsible
for maintaining the junction temperature within the recommended operating conditions. Operating device at junction temperatures higher than
what is recommended will cause device to operate outside the characterization models established during device simulation and may affect the
reliability performance.
CC
p
p
I
p
p
IH
IL
OH
OL
A
CMOS inputs
TTL input
CMOS inputs
TTL input
CMOS/TTL
CMOS Drivers
TTL Drivers
CMOS Drivers
TTL Drivers
TSB14C01A
TSB14C01AI
TSB14C01AM
TSB14C01A
TSB14C01AI
TSB14C01AM
4.5 5 5.25 V
0.7 V
CC
2
0
0
0
0
–40
–55
0.2 V
V
V
CC
CC
0.8
CC
12
24
115
125
150
70
85
125
V
V
V
V
V
8
8
°C
°C
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
TSB14C01A, TSB14C01AI, TSB14C01AM
θJA
,
Á
Á
Á
Á
Á
θJC
БББББ
БББББ
БББББ
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
electrical characteristics over recommended ranges of operating conditions (unless otherwise
noted)
device
V
V
I
OH
OL
OZ
PARAMETER TEST CONDITIONS
High-level output voltage
Low-level output voltage
Input current
Off-state output current
IOH = max,
IOL = min,
VI = VCC or 0
VI = VCC or 0
VCC = min
VCC = max
MIN TYP MAX UNIT
VCC–0.8
0.5
±1
±10
V
V
µA
µA
thermal characteristics
R
ÁÁ
R
†
Junction-to-free-air thermal resistance
ББББББББ
Junction-to-case thermal resistance
Thermal characteristics vary depending on die, leadframe, pad size, and mold compound. These values represent typical die and pad sizes for
the respective package. The R
of metal.
†
PARAMETER
TSB14C01APM,
TSB14C01AIPM
TSB14C01AMHV
TSB14C01APM,
ÁÁÁÁ
TSB14C01AIPM
TSB14C01AMHV
value decreases as the die pad size increases. Thermal values represent PWB bands with minimal amount
θJA
TEST CONDITION
MIN
TYP
Board mounted, No air flow
БББББББÁÁÁÁ
MAX
78
74
16
3
UNIT
°C/W
°C/W
°C/W
ÁÁÁ
°C/W
switching characteristics, VCC = 5 V, TA = 25°C (See Note 1)
PARAMETER
t
D, CTL, LREQ low or high before SCLK high
su
t
D, CTL, LREQ low or high after SCLK high
h
t
Delay time, SCLK high to D, CTL high or low
d
NOTE 1: These parameters are ensured by design and are not production tested.
MEASURED
50% to 50%
50% to 50%
50% to 50%
TEST CONDITION
See Figure 1
See Figure 1
See Figure 2
MIN
TYP
MAX
UNIT
7
1
10
ns
ns
ns
PARAMETER MEASUREMENT INFORMATION
8
SCLK
t
su
50%
t
h
D, CTL, LREQ
Figure 1. D, CTL, LREQ Input Setup and Hold Timing Waveforms
SCLK
D, CTL
50%
t
d
Figure 2. D, CTL Output Delay Relative to SCLK Timing Waveforms
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TSB14C01A, TSB14C01AI, TSB14C01AM
Á
Á
Á
Á
Á
Á
Á
Á
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
APPLICATION INFORMATION
internal register configuration
The accessible internal registers of this device are listed in Table 2. Bit field descriptions for the registers are
given in Table 3.
Table 2. Format for Registers
ADDRESS 0 1 2 3 4 5 6 7
0000 Physical
ID[0]
0001 INHB IBR RESERVED
0011 RESERVED
0100 Priority
level[0]
Physical
ID[1]
Priority
level[1]
Physical
ID[2]
Priority
level[2]
Physical
ID[3]
Priority
level[3]
Physical
ID[4]
Table 3. Register Bit Field Key
Physical
ID[5]
RESERVED
Reserved Reserved
FIELD
ÁÁÁ
Physical ID
INHB
IBR
Priority
ÁÁÁ
SIZE
(Bits)
Á
6
1
1
4
Á
TYPE
ÁÁ
Read/Write
Read/Write
Read/Write
Read/Write
ÁÁ
DESCRIPTION
ББББББББББББББББББББББ
Physical identification. Physical ID is the address of the local node and is set to zero on power up.
Inhibit Drivers. INHB is used to turn off the drivers to TDATA and TSTRB.
Initiate Bus Reset. IBR is turned on by the link and turned off by the phy when reset is complete.
Priority setting. The four bits contain the priority of the local node. A higher value in this field
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indicates a higher priority.
transceiver selection
The system designer must select transceivers appropriate to the system requirements to be used with the
TSB14C01A and the link layer selected. The following lists requirements for the transceivers needed.
D
The transceivers used must be appropriate to the backplane technology used.
The various backplane technologies require different electrical characteristics in their backplanes. For
example BTL uses an operating voltage on the backplane of 2.1 V and a characteristic impedance of 33 Ω
while GTL uses an operating voltage of 1.2 V and a characteristic impedance of 50 Ω (see
Swing Solution for High-Speed Digital Logic
, TI literature number SCEA003). When a backplane is
designed to use BTL technology , then it would be appropriate to also use that technology for the two lines
dedicated to the 1394 serial bus. The drivers selected also must be able to supply the current required for the
expected backplane loading. For example, BTL operates correctly for a FutureBus configuration backplane
at 50 Mbits/s or for a limited number of nodes in a custom configuration at 100 Mbits/s. See the
Low Swing Solution for High-Speed Digital Logic
Bus-Interface Products
, TI literature number SCAA029, or the documentation for the transceiver being
, TI literature number SCEA003,
Understanding Advanced
considered.
GTL/BTL a Low
GTL/BTL a
D
The transceivers used must assert logic states on the backplane in an appropriate manner for the 1394
backplane arbitration.
Arbitration under 1394 backplane rules requires the drivers to assert the bus to indicate a logical 1 state, that
is a logic 1 being driven by the TSB14C01A. Conversely, the drivers should release the bus to indicate a
logic 0 state, a logic 0 being driven by the TSB14C01A. In other words, all drivers must operate in a wired-OR
mode during arbitration.
D
The transceivers used must be able to monitor the bus and drive the bus at the same time.
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9
TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
During arbitration, each node that is arbitrating for the bus drives its priority code then its node number out
onto the bus. During each bit period, each node reads back what has been placed on the bus. If it reads back
the same data it was sending, the arbitrating node stays in contention for winning the bus. If it reads
something different than what it was driving, the arbitrating node loses the bus and drops out of contention.
This is the reason for requiring wired-OR operation during arbitration. As long as each node is still sending
0s onto the bus during arbitration, all nodes are still contending to win the bus. The node with the highest
priority (or if all priorities were zero then the highest node number) is the first to drive a 1 onto the bus during
arbitration. The node that sends the first 1 (asserting the bus) and reads it back wins the bus. All other nodes
read back a 1, which does not match the 0 (releasing the bus) they are sending, and drop out of contention.
This arbitration process requires the transceiver selected to be able to read from the bus at the same time it
is driving the bus.
For example, if three nodes, each with priority 0 and a node identifiers of 8, 7, and 2, were to arbitrate for the
bus, the following would occur (see Figure 3):
Driven by Node #2
(TSB14C01A)
Driven by Node #7
(TSB14C01A)
Driven by Node #8
(TSB14C01A)
Bus Data Line
(voltage level on the bus)
Bus Read
NOTE A: This bus is reverse logic, a 1 being driven by the TSB14C01A is asserted by driving a 0 onto the bus by the transceiver.
000 000
000 000
000 010
00 00
00 00
00 00
Figure 3. Three Nodes Arbitrating for the Bus
Since the highest node number is 8 (1000b), node 8 outputs the first 1 (assert the bus) and wins the
arbitration. The other nodes drop out and do not try to drive their node number onto the bus.
D
The transceivers used must be appropriate for the transfer speed required.
The 1394 bus has two data lines that use data-strobe encoding on the bus. This requires that the
transceivers be able to operate at a maximum frequency of one half of the maximum data transfer rate.
When operating at 50 Mbits/s, the maximum frequency the drivers are required to operate at is 25 MHz.
When operating at 100 Mbits/s, the maximum frequency the drivers are required to operate at is 50 MHz.
10
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