Texas Instruments TSB12LV32PZ, TSB12LV32IPZ Datasheet

TSB12LV32, TSB12LV32I

IEEE 1394Ć1995 and P1394a Compliant
GeneralĆPurpose LinkĆLayer Controller

Data Manual

April 2000 Mixed-Signal Products

SLLS336A

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify , before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgment, including those pertaining to warranty , patent infringement,
and limitation of liability .

TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI’s standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.

Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and

operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.

TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be
or are used. TI’s publication of information regarding any third party’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.

Copyright  2000, Texas Instruments Incorporated

Contents

Section Title Page

1 Overview 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 TSB12LV32 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 TSB12LV32 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Terminal Assignments 1–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.5.1 STAT0, STAT1, and STAT2 Programming 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Internal Registers 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 TSB12LV32 Configuration Registers 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2 Configuration Register Definitions 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.1 Version Register at 00h 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.2 Data Mover Control Register at 04h 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.3 Control Register at 08h 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.4 Interrupt/Interrupt Mask Register at 0Ch and 10h 2–9. . . . . . . . . . . . . . . . . . . . .

2.2.5 Cycle Timer Register at 14h 2–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.6 Isochronous Port Register at 18h 2–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.7 Maint_Control Register at 1Ch 2–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.8 Diagnostic Register at 20h 2–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.9 Phy Access Register at 24h 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.10 Reserved Registers at 28h – 2Ch 2–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.11 FIFO Status Register at 30h 2–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.12 Bus Reset Register at 34h 2–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.13 Header0 Register at 38h 2–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.14 Header1 Register at 3Ch 2–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.15 Header2 Register at 40h 2–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.16 Header3 Register at 44h 2–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.17 Trailer Register at 48h 2–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.18 Asynchronous Retry Register at 4Ch 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.2.19 Asynchronous Retry Register at 4Ch 2–21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Microcontroller Interface 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 Microcontroller Byte Stack (Write) Operation 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Microcontroller Byte Unstack (Read) 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Microcontroller Interface Read/Write Timing 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1 Microcontroller Handshake Mode 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.2 Microcontroller Fixed-Timing Mode 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.3 Microcontroller ColdFire Mode 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.4 Microcontroller Critical TIming 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.5 Endian Swapping 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 Link Core 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Physical Interface 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

Section Title Page

4.2 Transmitter 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Receiver 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Cycle Timer 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 Cycle Monitor 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Cyclic Redundancy Check (CRC) 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7 Packet Routing Control Logic 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Data Mover Port Interface 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Data Mover Data Flow Diagram 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.1 Isochronous Receive 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.2 Isochronous Transmit 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.3 Asynchronous Receive 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1.4 Asynchronous Transmit 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2 Data Mover Modes of Operation 5–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.2.1 Isochronous Transmit With Automatic Header Insertion 5–11. . . . . . . . . . . . . .

5.2.2 Isochronous Transmit Without Automatic Header Insertion 5–12. . . . . . . . . . .

5.2.3 Isochronous Packet Receive Without Header and Trailer 5–13. . . . . . . . . . . . .

5.2.4 Isochronous Packet Receive With Header and Trailer 5–13. . . . . . . . . . . . . . .

5.2.5 Asynchronous Packet Transmit With Automatic Header Insertion 5–14. . . . . .

5.2.6 Asynchronous Packet Transmit Without Automatic Header Insertion 5–15. . .

5.2.7 Asynchronous Packet Receive With Headers and Trailer 5–16. . . . . . . . . . . . .

5.2.8 Asynchronous Packet Receive Without Headers and Trailer 5–16. . . . . . . . . .

5.3 Data Mover Byte Mode 5–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Data Mover Endian Swapping 5–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Data Mover Handshake Mode 5–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Data Mover Critical Timing 5–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 FIFO Memory Access 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.1 General 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.2 ATF Access 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.3 ATF Burst Access 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.4 General-Receive-FIFO (GRF) 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6.5 GRF Stored Data Format 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 TSB12LV32 Data Formats 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Asynchronous Transmit (Host Bus to TSB12LV32) 7–1. . . . . . . . . . . . . . . . . . . . . . . . .

7.1.1 Quadlet Transmit 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.2 Block Transmit 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.3 Quadlet Receive 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1.4 Block Receive 7–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 Isochronous Transmit (Host Bus to TSB12LV32) 7–7. . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2.1 Isochronous Receive (TSB12LV32 to Host Bus) 7–7. . . . . . . . . . . . . . . . . . . . .

7.3 Phy Configuration 7–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3.1 Extended Phy Packets 7–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Receive Self-ID Packet 7–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

Section Title Page

8 TSB12LV32/Phy Interface 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.1 Principles of Operation 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.2 TSB12LV32 Service Request 8–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.3 Status Transfer 8–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.4 Receive Operation 8–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.5 Transmit Operation 8–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8.6 TSB12LV32/Phy Interface Critical Timing 8–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9 Electrical Characteristics 9–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range 9–1. . . . .

9.2 Recommended Operating Conditions 9–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

9.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage and

Operating Free-Air Temperature 9–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

10 Mechanical Information 10–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

List of Illustrations

Figure Title Page

1–1 TSB12LV32 Functional Block Diagram 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Microcontroller Byte Stack Operation (Write) 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Microcontroller Byte Unstack Operation (Read) 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 Byte Handshake Read 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 Word Handshake Read 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 Byte Handshake Write 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 Word Handshake Write 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–7 Byte Fixed-Timing Read 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–8 Word Fixed-Timing Read 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–9 Byte Fixed-Timing Write 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–10 Word Fixed-Timing Write 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–11 GRF Read Access (Byte Fixed-Timing Mode) 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–12 GRF Read Access (Word Fixed-Timing Mode) 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–13 ColdFire Read 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–14 ColdFire Write 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–15 Big Endian Format 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–16 Little Endian Format 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–17 Little-Endian Data Invariance Illustration Chart 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–18 Little-Endian Address Invariance Illustration Chart 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Link Core Components 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 A Typical System Diagram 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 Isochronous DM Flow Control (TSB12LV32 Transmit) 5–2. . . . . . . . . . . . . . . . . . . . . . . . . .

5–3 Transmit Data Path 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–4 Asychronous DM Flow Control (TSB12LV32 Transmit) 5–3. . . . . . . . . . . . . . . . . . . . . . . . . .

5–5 Isochronous Receive Without Header and Trailer 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–6 Isochronous Receive With Header and Trailer 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–7 Isochronous Transmit With Auto Header Insertion 5–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–8 Isochronous Transmit Without Auto Header Insertion 5–6. . . . . . . . . . . . . . . . . . . . . . . . . . .

5–9 Asynchronous Receive Without Headers and Trailer 5–7. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–10 Asynchronous Receive With Headers and Trailer 5–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–11 Asynchronous Transmit With Auto Header Insertion 5–9. . . . . . . . . . . . . . . . . . . . . . . . . . .

5–12 Asynchronous Transmit Without Auto Header Insertion 5–10. . . . . . . . . . . . . . . . . . . . . . .

5–13 Isochronous Transmit With Auto Header Insertion at 400 Mbps 5–11. . . . . . . . . . . . . . . .

5–14 Isochronous Transmit With Auto Header Insertion at 200 Mbps 5–11. . . . . . . . . . . . . . . .

5–15 Isochronous Transmit With Auto Header Insertion at 100 Mbps 5–12. . . . . . . . . . . . . . . .

5–16 Isochronous Transmit Without Auto Header Insertion 5–12. . . . . . . . . . . . . . . . . . . . . . . . .

5–17 Isochronous Receive Without Header and Trailer 5–13. . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–18 Isochronous Receive With Header and Trailer 5–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–19 Isochronous Receive With Header and Trailer at 200 Mbps 5–14. . . . . . . . . . . . . . . . . . . .

5–20 Asynchronous Quadlet Transmit With Automatic Header Insertion 5–14. . . . . . . . . . . . . .

5–21 Asynchronous Block Transmit With Automatic Header Insertion at 200 Mbps 5–14. . . .

vi

5–22 Asynchronous Block Transmit With Automatic Header Insertion at 400 Mbps 5–15. . . .

5–23 Asynchronous Quadlet Transmit Without Automatic Header Insertion

at 400 Mbps 5–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–24 Asynchronous Block Transmit Without Automatic Header Insertion

at 400 Mbps 5–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–25 Asynchronous Quadlet Receive With Headers and Trailer at 400 Mbps 5–16. . . . . . . . .

5–26 Asynchronous Block Receive With Headers and Trailer at 400 Mbps 5–16. . . . . . . . . . .

5–27 Asynchronous Quadlet Receive Without Headers and Trailer at 400 Mbps 5–17. . . . . .

5–28 Asynchronous Block Receive Without Headers and Trailer at 400 Mbps 5–17. . . . . . . . .

5–29 Endian Swapping in Byte Mode 5–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–30 Endian Swapping in Word Mode 5–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–31 Data Mover Handshake Mode (GPLynx mode) 5–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–32 Clock to Output Timing With Respect to DMCLK 5–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 TSB12LV32 Controller-FIFO-Access Address Map 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 Asynchronous Packet With N Quadlets (ATV Loading Operation) 6–1. . . . . . . . . . . . . . . .

7–1 Quadlet-Transmit Format (Write Request) 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2 Quadlet-Transmit Format (Read Response) 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3 Block-Transmit Format 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4 FIFO Quadlet-Receive Format 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5 Data Mover Quadlet-Receive Format 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–6 FIFO Block-Receive Format 7–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–7 Data Mover Block-Receive Format 7–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–8 Isochronous-Transmit Format 7–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–9 Data Mover Isochronous-Receive Format 7–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–10 GRF Isochronous-Receive Format 7–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–11 Phy Configuration Packet Format 7–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–12 Received Phy Configuration Packet Format 7–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–13 Ping Packet Format 7–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–14 Remote Access Packet Format 7–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–15 Remote Command Packet Format 7–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–16 Resume Packet Format 7–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–17 Receive Self-ID Packet Format (RXSID=1, FULLSID=1) 7–13. . . . . . . . . . . . . . . . . . . . . .

7–18 Receive Self-ID Packet Format (RXSID=1, FULLSID=0) 7–13. . . . . . . . . . . . . . . . . . . . . .

7–19 Phy Self-ID Packet #0 Format 7–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–20 Phy Self-ID Packet #1 Format 7–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–21 Phy Self-ID Packet #2 Format 7–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–1 Phy-LLC Interface 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–2 LREQ Request Stream 8–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–3 Status Transfer Timing 8–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–4 Normal Packet Reception Timing 8–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–5 Null Packet Reception Timing 8–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–6 Normal Packet Transmission Timing 8–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–7 Critical Timing for the TSB12LV32/Phy Interface 8–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

List of Tables

Table Title Page

1–1 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–2 STAT Terminals Programming 1–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 Configuration Register (CFR) Map 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Header Usage for CFRs 38h–44h 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Microcontroller Interface Modes of Operation 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 TSB12LV32 MP/MC Interface Terminal Function Matrix 3–1. . . . . . . . . . . . . . . . . . . . . . . . .

3–3 Endian Swapping Operation 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Receiver Routing 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 Modes of Operation 5–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–2 CLK to Output Timing With Respect to DMCLK 5–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 Packet Token Definition 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1 Quadlet-Transmit Format Functions 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2 Block-Transmit Format Functions 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3 Quadlet–Receive Format Functions 7–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4 Block-Receive Format Functions 7–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5 Isochronous-Transmit Functions 7–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–6 Isochronous-Receive Functions 7–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–7 Phy Configuration Packet Functions 7–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–8 Receive Phy-Configuration Packet 7–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–9 Ping Packet Fields 7–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–10 Remote Access Packet Fields 7–1 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–11 Remote Command Packet Fields 7–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–12 Resume Packet Fields 7–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–13 GRF Receive Self-ID Setup Using Control Register Bits (RXSID and FULLSID) 7–13. .

7–14 Receive Self-ID Function 7–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–15 Phy Self-ID Packet Fields 7–15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–1 CTL Encoding When the Phy Has Control of the Bus 8–2. . . . . . . . . . . . . . . . . . . . . . . . . . .

8–2 CTL Encoding When the TSB12LV32 Has Control of the Bus 8–2. . . . . . . . . . . . . . . . . . . .

8–3 Request Stream Bit Length 8–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–4 Request Type Encoding 8–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–5 Bus Request 8–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–6 Bus Request Speed Encoding 8–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–7 Read Register Request 8–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–8 Write Register Request 8–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–9 Acceleration Control Request 8–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–10 Status Bits 8–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8–11 Receive Speed Codes 8–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

viii

1 Overview

1.1 TSB12LV32 Description

The TSB12LV32 (GP2Lynx) is a high-performance general-purpose IEEE P1394a link-layer controller
(LLC) with the capability of transferring data between a host controller, the 1394 Phy-link interface, and
external devices connected to the data mover port (local bus interface). The 1394 Phy-link interface
provides the connection to the 1394 physical layer device and is supported by the LLC. The LLC provides
the control for transmitting and receiving 1394 packet data between the microcontroller interface and the
Phy-link interface via internal 2K byte FIFOs at rates up to 400 Mbit/s. The TSB12LV32 transmits and
receives correctly formatted 1394 packets, generates and detects the 1394 cycle start packets,
communicates transaction layer transmit requests to the Phy , and generates and inspects the 32-bit cyclic
redundancy check (CRC). The TSB12L V32 is capable of being cycle master (CM), isochronous resource
manager (IRM), bus manager, and supports reception of isochronous data on two channels.

The TSB12LV32 supports a direct interface to many microprocessors/microcontrollers including
programmable endian swapping. TSB12LV32 has a generic 16/8-bit host bus interface which includes
support for the ColdFire microcontroller mode at rates up to 60 MHz. The microinterface may operate in
byte or word (16 bit) accesses. The data mover block in GP2Lynx is meant to handle an external memory
interface of large data blocks. The port can be configured to either transmit or receive data packets. The
packets can be either asynchronous, isochronous, or streaming data packets. Asynchronous or
isochronous receive packets will be routed to the DM port or the GRF via the receiver routing control logic.

The internal FIFO is separated into a transmit FIFO and a receive FIFO each of 517 quadlets (2 Kbytes).
Asynchronous packets may be transmitted from the DM port or the internal FIFO. If there is contention the
FIFO has priority and will be transmitted first.

The LLC also provides the capability to receive status information from the physical layer device and to
access the physical layer control and status registers by the application software.

1.2 TSB12LV32 Features

• Compliant With IEEE 1394-1995 Standards and P1394a Supplement for High Performance
Serial Bus

• Supports Transfer Rates of 400, 200, or 100 Mbit/s

• Compatible With Texas Instruments Physical Layer Controllers (Phys)

• Supports the Texas Instruments Bus Holder Galvanic Isolation Barrier

• Glueless Interface to 68000 and ColdFire Microcontrollers/Microprocessors

• Supports ColdFire Burst Transfers

• 2K-Byte General Receive FIFO (GRF) Accessed Through Microcontroller Interface Supports

Asynchronous and Isochronous Receive

• 2K-Byte Asynchronous Transmit FIFO (ATF) Accessed Through Microcontroller Interface
Supports Asynchronous Transmissions

• Programmable Microcontroller Interface With 8-Bit or 16-Bit Data Bus, Multiple Modes of
Operation Including Burst Mode, and Clock Frequency to 60 MHz.

• 8-Bit or 16-Bit Data Mover Port (DM Port) Supports Isochronous, Asynchronous, and Streaming
Transmit/Receive From an Unbuffered Port at a Clock Frequency of 25 MHz.

• Backward Compatible With All TSB12LV31(GPLynx) Microcontroller and Data Mover
Functionality in Hardware.

• Four-Channel Support for Isochronous Transmit From Unbufferred 8/16 Bit Data Mover Port.

• Single 3.3-V Supply Operation With 5-V Tolerance Using 5-V Bias Terminals.

• High Performance 100-Pin PZ Package

†

Implements technology covered by one or more patents of Apple Computer, Incorporated and SGS Thomson, Limited.

ColdFire is a trademark of Motorola, Inc.

†

1–1

1.3 Functional Block Diagram

Microcontroller Interface

MCA
MCS

MRW

BCLK

Data

Port

7

Byte Stacker

16

DM D0–D15
DM Control

DMCLK

8-/16-to-32

bits

32

16

Figure 1–1. TSB12L V32 Functional Block Diagram

MA0 – MA6

MD0 – MD15

Mover

7

Data

Mover

DM

Address

7

Data
32

Host Interface

FIFO

2K ATF

2K GRF

32
32

CFR

ATF

GRF

DM IR/IR
DM IT/AT

÷ 2

Control

Status

ATF
32

Link Core

ARF

32

IRF
32

Packet Router Control

CTL[0:1]

D[0:7]

LREQ

LPS

LinkOn

Physical Layer Chip (PHY)

SCLK

1–2

1.4 Terminal Assignments

PZ PACKAGE

(TOP VIEW)

INT

CYSTART

TEA
MCA
GND

BCLK

MCS

MWR
RESET
VDD5V

MDINV

COLDFIRE

M8BIT/SIZ0

MCMODE/SIZ1

V

DD

TESTMODE

MA6
MA5
MA4

V

DD

MA3
MA2

MA1
MA0

GND

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

MD0

GND

99

100

27

26

MD1

MD2

97

98

28

29

MD3

V

95

96

31

30

DD

MD4

MD5

93

94

33

32

MD6

MD7

91

92

TSB12LV32

35

34

MD8

GND

89

90

37

36

MD9

88

38

MD10

MD11

86

87

40

39

DD

MD12

V5V

84

85

42

41

MD14

MD13

82

83

44

43

DD

MD15

V

80

81

46

45

DIRECT

GND

DMREADY

77

78

79

49

48

47

CYCLEIN

76

LENDIAN

75

LREQ

74

GND

73

SCLK

72
71

V

70

CTL0

69

CTL1

68

V

67

D0

66

D1

65

CONTNDR

64

LINKON

63

D2

62

D3

61

D4
D5

60
59

D6

58

D7
GND

57
56

STAT2

55

STAT1

54

STAT0

53

LPS

52

DMERROR

51

PKTFLAG

50

DD

DD

DMD0

DMD1

DMD2

DMD3

GND

DMD4

DMD6

DMD5

DD

DMD7

V5V

DMD9

DMD8

DD

V

DMD11

DMD10

DMD12

DMD14

DMD13

GND

DMD15

DMCLK

DD

V

DMPRE

DMRW

DMDONE

1–3

1.5 Terminal Functions

I/O

DESCRIPTION

The terminal functions are described in Table 1–1.

T able 1–1. Terminal Functions

TERMINAL

NAME NO.

Microcontroller/Microprocessor Interface

BCLK 6 I Microinterface clock. Maximum frequency is 60 MHz. In the ColdFire mode,

COLDFIRE 12 I ColdFire mode. To operate in this mode, COLDFIRE must be asserted high.
LENDIAN 75 I Little-endian mode for the microinterface. When this terminal is pulled up, the

MA0 – MA6 24 – 21

19 – 17

M8BIT/SIZ0 13 I Configuration bit for microinterface. If the microinterface is 8 bits wide, this

MCMODE/SIZ1 14 I Mode bit for microinterface. If the microinterface wants to communicate in a

MCA 4 O Microinterface cycle acknowledge. When asserted low, MCA signals an

MCS 7 I Microinterface cycle start. When asserted low, MCS signals the beginning of a

MDINV 11 I Microinterface data invariant mode. This terminal is meaningful only when

MD0 – MD15 99 – 96

94 – 91
89 – 86
84 – 81

MWR 8 I Microcontroller read/write indicator. When asserted high, MWR indicates a read

TEA 3 O Transfer error acknowledge. This active-low signal is asserted low for one BCLK

BCLK is the same as CLK, which is the clock-input signal to the ColdFire.

data on MD0–MD15 will be byte-swapped to little endian byte format before it is
written to the CFR or FIFO and after it is read from the CFR or FIFO.

I Microcontroller address bus. MA0 is the most significant bit (MSB) of these 7 bits.

terminal must be pulled up to the supply voltage. In ColdFire mode, this terminal
represents burst SIZ0.

handshake manner this terminal must be pulled up to the supply voltage. When
the ColdFire mode terminal (12) is high, this terminal represents burst SIZ1.

acknowledge of the microcontroller cycle from the TSB12L V32.

microcontroller operation to the TSB12L V32.

LENDIAN (75) is high. When asserted high, the microinterface operates in the
data invariant mode. When low, the microinterface operates in address invariant
mode.

I/O Microinterface bidirectional data bus. MD0 is the most significant bit. However,

byte significance is dependent on the state of the LENDIAN and MDINV
terminals.

access from the TSB12LV32. When asserted low , MWR
to the TSB12LV32.

cycle whenever there is an illegal transfer request by the microcontroller (i.e.,
requested data transfer size is unsupported or MCS
one BCLK cycle in ColdFire mode).

indicates a write access

is asserted low for more than

1–4

T able 1–1. Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NO.

Data-Mover Port Interface

DMD0–DMD15 26 – 29

31 – 34
36 – 39

41 – 44
DMCLK 46 O Data mover clock at (SCLK/2) MHz
DMDONE 50 O Data mover done. For transmit, this will be activated when the packet per block

DMERROR 52 O Data mover error. DMERROR is asserted high when there is an error in the

DMPRE 48 O Data mover predata indicator. In transmit mode, DMPRE pulses for one DMCLK

DMREADY 77 I Data mover ready. Must be asserted high by the external logic controlling the DM

DMRW 49 O Data mover read/write indicator. When data is being moved from 1394 to the DM

PKTFLAG 51 O Packet flag. When set, PKTFLAG is asserted high to indicate the first (header) or

CTL0, CTL1 70, 69 I/O Phy-link interface control lines.
D0–D7 67, 66,

63–58

LINKON 64 I Link-on from the Phy is a 4 MHz – 8 MHz clock. This signal will be activated when

LPS 53 O Link power status. LPS is used to drive the LPS input to the Phy. It indicates to the

LREQ 74 O Link request to Phy. LREQ makes bus requests and register access requests to

SCLK 72 I System clock. SCLK is a 49.152 MHz clock supplied by the Phy. DMCLK is

I/O Data mover (DM) bidirectional data port. DMD0 is the MSB of these 16 bits.

counter in the CFR counts down to zero. For receive, this terminal will pulse for
one DMCLK prior to the first byte/word available to the DM interface.

received packet or an illegal transmit speed was attempted.

prior to sending the first quadlet. In isochronous receive mode, DMPRE will pulse
for one DMCLK when the sync bit in the header matches a bit set in the
isochronous register. DMPRE is not used in asynchronous receive mode.

interface when it is ready to supply data for transmit. DMREADY must be set low
when the data mover is in receive mode.

port (receive) this signal will go active high to indicate data is available on
DMD[0:15]. When data is being moved from DM to 1394 bus (transmit) this signal
will go active high to indicate that data must be supplied to the DMD[0:15] port for
transmission.

last (trailer) quadlet of a received packet on the DM interface. PKTFLAG is not
valid in transmit mode.

Phy/Link Interface

I/O Phy-link interface data lines. Data is only expected on D0 and D1 at 100 Mbit/s,

D0–D3 at 200 Mbit/s, and D0–D7 at 400 Mbit/s. D0 is the MSB bit.

the link is inactive and the Phy has detected a link-on packet or a Phy interrupt.
This clock will persist for no more than 500 ns. When the link detects this terminal
as active, it will turn on and drive LPS.

Phy that the link is powered up and active. LPS toggles at a rate = 1/16 of BCLK.

the Phy.

generated from SCLK.

1–5

T able 1–1. Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NO.

Miscellaneous Functions

CONTNDR 65 I/O Contender. When asserted high, this terminal tells the link that this node is a

CYCLEIN 76 I Cycle in. This input is an optional external 8-kHz clock used as the isochronous

CYSTART 2 O Isochronous cycle start indicator. CYSTAR T signals the beginning an isochronous

DIRECT 79 I Isolation terminal. When this terminal is asserted high, no isolation is present

GND 5, 25, 30,

INT 1 O Interrupt. NOR of all internal interrupts.

RESET

STAT0–STAT2 54 – 56 O General status outputs. STATn is the output signal selected with the CFR at

TESTMODE 16 I This terminal is used to place the TSB12LV32 in the test mode. In normal

VDD5V 10, 35, 85 5 V (± 0.5V) supply voltage for 5-V tolerant inputs. Only the Phy/link interface side

V

DD

45, 57, 73,

78, 90,

100

9 I

15, 20, 40,
47, 68, 71,

80, 95

contender for isochronous resource manager (IRM) or bus manager functions.
The state of the CONTNDR must match the state of the Phy contender terminal for
1394-1995 compliant Phys, and the Phy register bit for 1394.A compliant Phys.
This terminal defaults to being an input on power up. After power up, the value of
this terminal may be driven internally by the CTNDRSTAT bit (bit#12 at 08h)

cycle clock. It should only be used if attached to the cycle-master node. It is
enabled by the cycle source bit and should be tied high when not used.

cycle by pulsing for one DMCLK period.

between the TSB12LV32 and the Phy. When low, bus holder isolation becomes
active.

Ground reference

System reset. This activeĆlow signal is asynchronous to the TSB12LV32.

address 20h.

operation, this terminal must be tied to ground.

of the TSB12LV32 is not 5-V tolerant. T ie this terminal to the 3.3-V supply voltage if
the TSB12LV32 is not connected to any devices driving 5-V signals. Tie this
terminal to the 5-V supply voltage if the TSB12L V32 is connected to any devices
driving 5-V signals. This terminal is only used to make inputs 5-V tolerant, it is not
used for any outputs.

3.3 V (± 0.3 V) supply voltage

1–6

1.5.1 STAT0, STAT1, and STAT2 Programming

ST AT0, ST AT1 and ST AT2 terminals can be independently programmed to show one of fourteen possible
internal hardware status. The controls for the ST AT terminals are in the
of the CFR register. STAT0 is controlled by STATSEL0(bits 16–19), STAT1 is controlled by bits
STATSEL1(bits 20–23), and STAT2 is controlled by STATSEL2 (bits 24–27). Refer to Table 1–2 for
programming the STAT terminals.

T able 1–2. STAT Terminals Programming

STATSEL0,

STATSEL1, or

STATSEL2

0 0 0 0 Reserved Reserved
0 0 0 1 ATFFULL ATF is full. Bit 12 in CFR at 30h.
0 0 1 0 Bus Reset 1394 Bus reset. Bit 3 in CFR at 0Ch
0 0 1 1 Arbitration reset gap Bit 26 in CFR at 0Ch

0 1 0 0 CYCLEOUT

0 1 0 1 RXDMPKT

0 1 1 0 RXGRFPKT
0 1 1 1 BX_BUSY Byte busy. This represents the OR of bits 0 – 3 of CFR at 20h
1 0 0 0 SUBGP

1 0 0 1 CYCLE_DONE

1 0 1 0
1 0 1 1 DMACKERR DM acknowledge was not Complete. Bit 17 in CFR at 0Ch

1 1 0 0 DMEN DM enable. Bit 26 in CFR at 04h
1 1 0 1
1 1 1 0 Reserved Reserved

1 1 1 1 Reserved Reserved

STAT0/STAT1/STAT2 DESCRIPTION

Cycle out. This is the link’s cycle clock. It is based on the timer
controls and the received cycle-start messages.

Packet received to DM interrupt. Activated at the end of a received
packet. Bit 9 in CFR at 0Ch

Packet received to GRF interrupt. Activated at the end of a received
packet. . Bit 6 of CFR at 0Ch

Subaction gap. Activated upon detection of a subaction gap. Bit 27
in CFR at 0Ch

Cycle done. Indicates the end of the isochronous period. This
happens when a subaction gap has been detected.

ATSTARTED
(default setting for STAT1)

GRFEMPTY
(default setting for STAT2)

Activated when an asynchronous packet transfer has started from
the ATF. Bit 5 in CFR at 0Ch

GRF is empty. Bit 15 in CFR at 30h.

Diagnostic

register at address 20h

1–7

1–8

2 Internal Registers

2.1 TSB12LV32 Configuration Registers

2–1

Table 2–1. Configuration Register (CFR) Map

MSB LSB

0123456789101112131415161718192021222324252627 293031
01110001000101010011100010100000

00h

AUTOUP

HANDSHK

BDIV0

BUSNRST

SNTRJ

TCERR

HDRERR

SNTRJ

TCERR

HDRERR

DMACK

BDIV1

DMACKCOMP

FIFOACK

DMACKERR

FIFOACK

DMACKERR

CYTEN

CYSRC

CYMAS

FIFOACKCOMP

CYST

CYSEC

CYST

CYSEC

CYDNE

CYDNE

MCERROR

MCERROR

SPEED

CHNLCNT

SID

ERROR

CODE

CLSIDER

CYLST

CARBFL

CYLST

CARBFL

CYCLE OFFSET

ISYNCRCVN

DMEN

DMHDR

SUBGP

ARBGP

SUBGP

ARBGP

PING VALUE

04h

PACKET PER BLOCK

08h

TXEN

RXSLD

FULLSID

0Ch

10h

14h

18h

1Ch

FLSHERR

INT

INT

E_HCRC

PHY_PKT_ENA

PHINT

PHRST

PHRRX

PHINT

PHRST

PHRRX

SECONDS COUNT CYCLE COUNT

IRPORT1

TAG1

F_ACK

NO_PKT

E_DCRC

RXEN

BSYCTL

RXGRFPKT

SELFIDEND

ATSTARTED

RXGRFPKT

SELFIDEND

ATSTARTED

NO_ACK

ENA_ACCEL

ENA_CONCAT

ENA_INSERT_IDLE

CMDRST

DMERROR

RXDMPKT

CMDRST

DMERROR

RXDMPKT

TAG2

ENDSWAP

RSTTX

RSTRX

CTNDRSTAT

LINKONLINKON

ATSTK

SELFIDER

ATSTK

SELFIDER

IRPORT2

ACK

BYTEMODE

CTNDRISIN

ATFEMPTY

ATFEMPTY

28

AR0

CMAUTO

IRCVALL

AR1

DMASYNC

IRP1EN

IRP2EN

VERSION
(711538A0h)

DM Control

DMRX

Control

Interrupt

IARBFL

Interrupt
Mask

IARBFL

Cycle Timer
Isochronous

Port

MONTAG

Maint_Control

20h

B3_PND

RAM_TEST

REGRW

24h

B0_BUSY

B1_BUSY

RDPHY

WRPHY

B1_PND

B2_PND

B0_PND

B2_BUSY

B3_BUSY

PHYRGAD PHYRGDATA

28h–2Ch

30h

34h

ATFCLR

ATFWBMTY

NRIDVAL

NODECNT

ATFAVAIL

GRFCLR

ATFFULL

IRMNODEID BUS NUMBER NODE NUMBER

ROOT

CONTENDER

38h

3Ch

40h
44h

48h

ASYNC RETRY COUNT RETRY INTERVAL

4Ch

NUMBER OF QUADLETS

NOTES: A. All dark gray areas (bits) are reserved bits.

B. All light gray areas are read-only bits. All remaining are read/write bits.

2–2

STATSEL0 STATSEL1 STATSEL2

PHYRXAD PHYRXDATA

CD

ATACK GRFUSED

GRFEMPTY

ACKCODE SPD

Diagnostic

Phy Access

Reserved

FIFO Status

Bus Reset

Header0
Header1

Header2
Header3

Trailer

LPS_OFF

LPS_RESET

Asynchronous
Retry

DIRECTION

y

Asynchronous

OF DM DATA

TRANSFER

TRANSMIT

(to 1394 Bus)

RECEIVE

(from 1394

Bus)

PACKET TYPE

Isochronous

Asynchronous/

asynchronous

streaming

Isochronous/

asynchronous

streaming

T able 2–2. Header Usage for CFRs 38h–44h

AUTO HEADER

INSERT/

EXTRACT

YES

NO

YES

NO

YES

NO

YES

NO

Header 0 CFR formatted for isochronous transmission.
Header1 – Header3 are used for additional channels.

Isochronous header supplied by DM interface. Header0 CFR
is automatically written with extracted (from transmitted
packet) isochronous header.

Header0–Header3 CFRs formatted for asynchronous trans­mission.

Asynchronous header supplied by DM interface. Header0 –
Header3 CFRs are automatically written with extracted (from
transmitted packet) header.

Header0 – Header3 are always automatically updated. The
isochronous header is streamed through the DM port. The
trailer quadlet is always appended to the data stream.

Header0 – Header3 are always automatically updated. The
isochronous header is streamed through the DM port along
with the payload data. The trailer quadlet is always appended
to the data stream.

Header0 – Header3 are always automatically updated.
Asynchronous headers are not streamed through the DM
port. The trailer quadlet is always appended to the data
stream.

Header0 – Header3 are always automatically updated.
Asynchronous headers are streamed through the DM port
along with data. The trailer quadlet is always appended to the
data stream.

HEADER REGISTER

2–3

2.2 Configuration Register Definitions

2.2.1 Version Register at 00h

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128
01110001000101 0 10 011100010100000

This register uniquely identifies this device to the software. The value is fixed at 7115_38A0’h. This register
is read only .

2.2.2 Data Mover Control Register at 04h

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128

PACKET PER BLOCK

ENDSWAP

AUTOUP

HANDSHK

BYTEMODE

DMACK

SPEED

DMEN

CHNLCNT

AR0

DMHDR

AR1

DMASYNC

This register controls the Data Mover port and must be set up before using the port. The power-up reset
value of this register = 0000_0000’h

BIT

NUMBER

0–11 PACKET PER-

12 ENDSWAP Endian Swap R/W Swap endian. When this bit is set, the quadlet formed by

13 BYTEMODE Byte Mode R/W Byte mode. When this bit is set the DM port will only look

14 HANDSHK Handshake

15 AUTOUP Automatic

16–20 DMACK DM

21 RESERVED RESERVED

22–23 SPEED DM Speed

BIT NAME FUNCTION DIR DESCRIPTION

BLOCK

Packets per

Block

R/W Number of packets per block. A packet is the size of the

data payload and is specified as part of the header. The
data mover logic uses this value to deactivate DMDONE.
This field is only used in transmit mode.

stacking the DM data will be byte reversed, (i.e. the
quadlet formed by fetching doublet AB01 then ‘CD02’ will
be 02CD–01AB instead of AB01CD02). In byte mode the
quadlet formed by fetching AB, 01, CD, 0 will be
02CD01AB instead of AB01CD02.

at DM0–DM7. DM8–DM15 will be ignored for transmit
and will not be driven on receive. In this mode, the
maximum speed allowed is 200 Mbps.

R/W Handshake. When this bit is 1 DMREADY and DMDONE

Mode

(CPLynx

Mode)

are in strict handshake mode (i.e., TSB12LV31
compatible mode). DMREADY must not be deactivated
until DMDONE activates. When this bit is set to 0,
DMREADY may be deactivated before DMDONE
activates.

R/W Automatic update offset address. Valid only for

Address Up-

date

asynchronous transmit using header insert mode (bit 27
DMHDR set to 1). For write request asynchronous
packets, header quadlet 2 contains the destination offset
low address for the write. When this bit is set, header
quadlet 2 will be updated by the value of the payload size
(rounded up to the nearest quadlet boundary).

R DM acknowledge. This is the ack received from the

Acknowledge

receiving node. This is updated only when the transfer is
from the DM port.

R/W Speed code. This is valid for isochronous transmit and

Code

asynchronous transmit through the DM port. The DM
logic uses this field to specify to the Phy the speed of the
isochronous transfer.

DMRX

2–4

BIT

NUMBER

24–25 CHNLCNT Channel

Count

26 DMEN DM Enable R/W DMEN controls the transmission of packets from the DM

27 DMHDR DM Header

Insert Control

28–29 AR0, AR1 Receive

Control

Routing

30 DMASYNC DM

Asynchronous

31 DMRX DM Receive R/W If this bit is set to 1 the DM port is configured to receive.

R/W Channel count. This field is valid only in isochronous

transmit. This field allows the node to transmit multiple
packets during a single isochronous period. Each packet
must have a different channel number, however,
hardware does not check this. When the isochronous
transmit header is supplied by the DM interface or
automatically inserted by the hardware, a maximum of
four different channels may be accessed in one
isochronous period. In isochronous transmit with
automatic header insert, Header0–Header3 CFRs are
used as the isochronous header registers.

port. If this bit is 0, transmission through from the DM port
is inhibited. This is used for asynchronous flow control. In
normal operation, if an asynchronous packet trans­mitted from the DM port receives an acknowledge from
the receiving node other than
be set to 0 and DMERROR is asserted high. Software will
need to set this bit to allow further transmission of
asynchronous packets from the DM port. The default and
power-up value is 0.

R/W DM header insert bit. When set to 0, the hardware will

automatically insert the header(s) into the DM transmit
data. In receive, setting this bit to 0 will strip off the
header(s) before routing packet to the DM. Header(s) are
always written to the CFR header registers regardless of
the value of DMHDR.

R/W Receive packet routing control encoded bits. These bits

in conjunction with DMASYNC and DMRX bits in the DM
control register controls the routing of the received
packet to either the data mover port or to the GRF . Refer
to Table 4–1.

R/W If this bit is set to 1 the DM port is configured for

asynchronous traffic only. The DM port can not accept
both asynchronous and isochronous traffic. It must be
configured for asynchronous (DMASYNC = 1) or
isochronous (DMASYNC = 0).

The DM port cannot both transmit and receive data at the
same time, it must be configured for either transmit or
receive.

DESCRIPTIONDIRFUNCTIONBIT NAME

ack complete

, this bit will

2–5

2.2.3 Control Register at 08h

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128

RXSID

FLSHERR

FULLSID

BSYCTRL

PHY_PKT_ENA

TXEN

RXEN

ENA_ACCEL

RSTTX

ENA_CONCAT

ENA_INSERT_IDLE

RSTRX

CTNDRSTAT

CTNDRISIN

BDIV0

BUSNRST

BDIV1

DMACKCOMP

CYSRC

CYMAS

FIFOACKCOMP

CYTEN

SIDERCODE

CLSIDER

IRP1EN

CMAUTO

IRP2EN

The control register dictates the basic operation of the TSB12L V32. The power-up reset value of this register
equals E004_0200’h

BIT

NUMBER

0 FLSHERR Flush GRF

1 RXSID Received

2 FULLSID Save full

3 PHY_PKT_ENA Phy Packets

4 BSYCTRL Busy Control R/W BSYCTRL controls which busy status the chip returns to

5 TXEN Transmit

6 RXEN Receive

7 ENA_ACCEL Acceleration

8 ENA_CONCAT Concatenation

BIT NAME FUNCTION DIR DESCRIPTION

R/W This bit controls the flushing of the GRF when a packet with

on error

a data CRC error is detected. The power–up value is 1,
which means flush the GRF when a data CRC error is
detected.

R/W If set, the self-identification (SID) packets generated by Phy

Self-ID

packets

devices during the bus initialization are received and placed
into the GRF as a single packet. The default setting of this
bit is 1. When set to 0, the SIDs are not placed into the GRF .

R/W Save the full self-ID packets.When this bit is 1 the self-ID

Self-ID Packet

in GRF

data quadlet and its inverse quadlet are saved in the GRF.
When this bit is 0 only the self-ID data quadlet is saved in the
GRF .

R/W Phy packet enable allows reception of all Phy packets. If this

Receive

Enable

bit is reset to 0, all Phy packets, except for self-IDs, will be
rejected and interrupt HDERR (if not masked) will be
generated. One HDERR interrupt will be generated for
every Phy packet received.

incoming packets. When this bit is 0 the chip follows normal
busy/retry protocol, only send busy when necessary. When
this bit is 1 the chip sends a busy acknowledge to all
incoming packets following the normal busy/retry protocol.

R/W When TXEN is cleared, the transmitter does not arbitrate or

Enable

send packets. TXEN bit is cleared following a bus reset, and
all traffic through the DM port will be interrupted. TXEN must
be set before packet transmit can resume. Power-on reset
value of TXEN is 0

R/W When RXEN is cleared, the receiver does not receive any

Enable

packets. This bit is not affected by a bus reset and is set to 0
after a power-on reset.

R/W Enable acceleration. When this bit is set, fly-by acceleration

Enable

and accelerated arbitration are enabled. This bit cannot be
set while TXEN and RXEN are set. This bit must only be
used with a 1394a capable Phy.

R/W Enable concatenation. When this bit is set it allows the link

Enable

to concatenate multiple isochronous or asynchronous
packets. This bit must only be used with a 1394a capable
Phy.

2–6

BIT

NUMBER

9 ENA_

INSERT_IDLE

Insert Idle

Enable

DESCRIPTIONDIRFUNCTIONBIT NAME

R/W Per P1394a, the link is required to insert an idle state on the

control lines after the Phy grants the link control of the
Phy/link interface. If using a P1394a Phy, this bit should be
set to 1 in order for the link to drive an idle state following the
grant state from the Phy. For 1394-1995 Phys this bit must
remain low.

10 RSTTX Transmitter

Reset

11 RSTRX Receiver

Reset

12 CTNDRSTAT Contenter

status

13 CTNDRISIN Contender

Driver Enable

14 RESERVED Reserved
15 BUSNRST Bus number

reset enable

16–17 BDIV0, BDIV1 BCLK divisor

encode bits

R/W When RSTTX is set, the entire transmitter resets

synchronously. This bit clears itself.

R/W When RSTRX is set, the entire receiver resets

synchronously. This bit clears itself.

R/W Contender status. On power up, this bit reflects the status of

the CONTNDR pin. When bit 13, CTNDRISIN, is 0 this bit
will be driven out to the CONTNDR pin. If CTNDRISIN is 1
this bit is not used. (Only use on 1394–1995 Phys, or
P1394a Phys when using hardware reset, otherwise, use
the 1394a Phy registers to set the nodes contender status).

R/W Driver enable for the CONTNDR pin. On power up this bit is

set to 1 which disables the driver and allows reading of the
state of the CONTNDR pin. Writing a 0 to this bit will enable
the driver and will drive bit 12, CTNDRSTAT, to the
CONTNDR pin.

R/W When this enable is set to high, the bus number field clears

to 3FFh when a local bus reset is received.

R/W

BCLK divisors encode bits. Used to divide down the BCLK
to generate the link power status (LPS) clock to the Phy.

BDIV0 BDIV1 DESCRIPTION

0 0 Divide by 16. Default power on value.

0 1 Divide by 2. Recommended for BCLK

1 0 Divide by 4. Recommended for BCLK

1 1 Divide by 32. Recommended for BCLK

Recommended for BCLK frequencies in
the range of 8 – 88 MHz.

frequencies in the range of 1 – 1 1 MHz.

frequencies in the range of 2 – 22 MHz.

frequencies in the range of 16 – 176
MHz

18 DMACKCOMP Data Mover

Acknowledge

Complete

19 FIFOACKCOMP FIFO

Acknowledge

Complete

R/W Data mover acknowledge complete. This bit controls the

acknowledge response to an asynchronous packet
received and routed to the DM port. The default and power
on value is 0 which means to respond with ack pending. A 1
means to respond with an ack complete for write request
packets.

R/W FIFO acknowledge complete. This bit controls the

acknowledge response to an asynchronous packet
received and routed to the GRF. The default and power on
value is 0 which means to respond with ack pending. A 1
means to respond with ack complete.

2–7

BIT

NUMBER

20 CYMAS Cycle Master R/W When CYMAS is set and the TSB12LV32 is attached to the

21 CYSRC Cycle Source R/W When CYSRC is set, the cycle_count field increments and

22 CYTEN Cycle timer

enable

23 CLRSIDER Self-ID

error-code

clear

24–27 SIDERCODE Self-ID error

code

28 CMAUTO Auto set cycle

master

29 IRP1EN IR port 1

enable

30 IRP2EN IR port 2

enable

31 RESERVED Reserved

root Phy, the cyclemaster function is enabled. When the
cycle_count field of the cycle timer register increments, the
transmitter sends a cycle-start packet.

the cycle_offset field resets for each positive transition of
CYCLEIN. When CYSRC is cleared, the cycle_count field
increments when the cycle_offset field rolls over .

R/W When CYTEN is set, the cycle_offset field increments.

W When CLRSIDER is set, the SIDERCODE field (bits 24–27)

is cleared.This bit clears itself.

R

SIDERCODE contains the error code of the first Self-ID
Error. The error code is as follows:

0000 No error
0001 Last self-ID received was not all child ports
0010 Received Phy ID in self-ID not as expected

0011 Quadlet not inverted (phase error)
0100 Phy ID sequence error (two or more gaps in IDs)
0101 Phy ID sequence error (large gap in IDs)

0110 Phy ID error within packet

0111 Quadlet not the inversion of the prior quadlet
1000 Reserved

R/W When CMAUTO is high, the TSB12LV32 automatically

enables CYMAS when the this node becomes the root
following a bus reset.

R/W When IRP1EN is set, the receiver accepts isochronous

packets when the channel number matches the value in the
IR port1 field at18h

R/W When IRP2EN is set, the receiver accepts isochronous

packets when the channel number matches the value in the
IR Port2 field at18h

DESCRIPTIONDIRFUNCTIONBIT NAME

2–8

2.2.4 Interrupt/Interrupt Mask Register at 0Ch and 10h

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128

INT

PHINT

PHRST

PHRRX

RXGRFPKT

SELFIDEND

ATSTARTED

CMDRST

DMERROR

RXDMPKT

SELFIDER

ATSTK

LINKON

SNTRJ

ATFEMPTY

TCERR

HDRERR

FIFOACK

DMACKERR

CYSEC

MCERROR

CYST

CYDNE

CYLST

ARBGP

CARBFL

SUBGP

The interrupt and interrupt mask register work in tandem to inform the host bus interface when the state of
the TSB12L V32 changes. The interrupt register is at 0Ch, the interrupt mask register is at 10h. The interrupt
register powers up all 0s, however, the interrupt mask register powers up with the INT and the MCERROR
bit set, i.e. 8000_1000h. The mask bits allows individual control for each interrupt. A 1 in the mask bit field
allows the corresponding interrupt in the interrupt register to be generated. Once an interrupt is generated
it must be cleared by writing a 1 to the bit in the interrupt register. For testing, each interrupt bit can be set
manually . This is done by first setting the REGRW bit at20h and then setting the individual interrupt bit. This
is also true for bit 0 at0Ch. In this test mode, the interrupt mask register is not used and has no effect.

BIT

NUMBER

0 INT Interrupt R/W INT contains the value of all interrupt and interrupt mask bits

1 PHINT Phy chip

2 PHRRX Phy register

3 PHRST Phy reset

4 SELFIDEND Self-ID

5 ATSTARTED Asynchronous

6 RXGRFPKT GRF packet

7 CMDRST CSR register

8 DMERROR Data Mover

9 RXDMPKT Data Mover

10 SELFIDER Self-ID packet

BIT NAME FUNCTION DIR DESCRIPTION

ORed together

R/W When PHINT is set, the Phy has signalled an interrupt

interrupt

through the Phy interface

R/W When PHRRX is set, a register value has been transferred to

information

the Phy access register (offset 24h) from the Phy interface

received

R/W When PHRST is set, a Phy-LLC reconfiguration has started

started

(1394 bus reset)

R/W Self-ID end. This bit is set at the end of the self-ID reporting

validated

process. When this bit is set, the contentF of the bus reset
CFR at34h is valid.

R/W Asynchronous transfer started. Activated when the bus has

transfer started

been granted and the first quadlet from the FIFO is about to
be popped from the ATF.

R/W Receive packet to GRF . This bit is set whenever a complete

received

packet has been confirmed into the GRF (asynchronous or
isochronous).

R/W If CMDRST is set, the receiver has been sent a quadlet write

reset request

request to the Reset_Start CSR register(target address is
FFFF_F000_000Ch)

R/W DM error. This bit will be set whenever there is an error in the

error

DM stream. For transmit, if the DM port is configured for byte
access and the speed code in the DM control register or the
asynchronous header register is set for 400 Mbps then this
bit will be set. Under this condition DMEN will be reset to 0
preventing further transmit. For receive this bit will be set if
there is a header or data CRC error or if the DM port is config­ured for byte access and the data is received at 400 Mbps.

R/W Receive packet to DM. This bit is set whenever a packet is

packet receive

received to the DM port.

R/W Set if an error in the self-ID quadlet/packet has been de-

error

tected.

IARBFL

2–9

BIT

NUMBER

11 LINKON Link-ON detect R/W Set if a link-on pulse is detected on the LINKON input termi-

12 ATSTK Transmitter is

stuck (AT)

13 ATFEMPTY ATF empty

interrupt

14 SNTRJ Busy

acknowledge

sent by receiver

15 HDRERR Header error R/W When HDRERR is set, the receiver detected a header CRC

16 TCERR Transaction

code error

17 DMACKERR Data Mover

acknowledge

error

18 FIFOACK FIFO

acknowledge

interrupt

19 MCERROR Micro-interface

error

20 CYSEC Cycle second

incremented

21 CYST Cycle started R/W When CYST is set, the transmitter has sent or the receiver

22 CYDNE Cycle done R/W When CYDNE is set, an arbitration gap has been detected

23 RESERVED RESERVED
24 CYLST Cycle lost R/W When CYLST is set, the cycle timer has rolled over twice

25 CARBFL Cycle

arbitration failed

26 ARBGP Arbitration gap R/W When ARBGP is set, the serial bus has been idle for an ar-

nal. This bit should be used by software to reactivate the LPS
output to the Phy .

R/W When ATSTK is set, the transmitter has detected invalid data

at the asynchronous transmit-FIFO interface. If the first
quadlet of a packet is not written to the ATF_First or
ATF_First&Update, the underflow of the ATF also causes an
ATStuck interrupt. When this state is entered, no asynchro­nous packets can be sent until the ATF is cleared by way of
the CLR ATF control bit. Isochronous packets can be sent
while in this state.

R/W ATFEMPTY. This bit is set to 1 when the ATF is empty.

R/W When SNTRJ is set, the receiver is forced to send a busy ac-

knowledge to a packet addressed to this node because the
GRF overflowed.

error on an incoming packet that may have been addressed
to this node.

R/W When TCERR is set, the transmitter detected an invalid

transaction code in the data at the transmit-FIFO interface.

R/W DM acknowledge error. Set to 1 when the acknowledge re-

ceived is not
of the DM Control CFR at04h will be reset to 0 and no more
asynchronous transmit from the DM port will be allowed to
take place until DMEN is set to 1.

R/W FIFO ack interrupt. This bit will be set when an acknowledge

from a previous ATF transmit has been received.

R/W Micro-interface error. Set whenever the microcontroller write

protocol is violated.

R/W When CYSEC is set, the cycle-second field in the cycle timer

register has incremented. This occurs about every second
when the cycle timer is enabled.

has received a cycle-start packet.

on the bus after the transmission or reception of a cycle-start
packet. This indicates that the isochronous cycle is over.

without the reception of a cycle-start packet. This occurs
only when this node is not the cycle master. All isochronous
traffic stop once CYLST is set. However , asynchronous and
asynchronous streaming traffic will not be affected.

R/W When CARBFL is set, the arbitration to send a cycle-start

packet has failed.

bitration reset gap.

ack complete

DESCRIPTIONDIRFUNCTIONBIT NAME

. When this occurs, DMEN(bit 26)

2–10

BIT

NUMBER

27 SUBGP Subaction gap R/W When SUBGP is set, the serial bus has been idle for a subac-

28–30 RESERVED RESERVED

31 IARBFL Isochronous

arbitration failed

tion gap time (fair-gap). This bit can be set only when the
REGRW bit has been set in the diagnostics register at 20h.

R/W When IARFL is set, the arbitration to send an isochronous

packet has failed.

DESCRIPTIONDIRFUNCTIONBIT NAME

2.2.5 Cycle Timer Register at 14h

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128

SECOND COUNT CYCLE OFFSETCYCLE COUNT

This register must be written to as a quadlet. The power-up reset value of this register = 0000_0000’h

BIT NUMBER BIT NAME FUNCTION NAME DIR DESCRIPTION

0–6 Seconds_count Seconds count R/W 1-Hz cycle timer counter

7–19 Cycle_count Cycle count R/W 8,000-Hz cycle timer counter

20–31 Cycle_offset Cycle offset R/W 24.576-MHz cycle timer counter

2–11

2.2.6 Isochronous Port Register at 18h

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128

TAG1

IRPORT1 IRPORT2 ISYNCRCVN

TAG2

The power-up reset value of this register = 0000_0000h

BIT

NUMBER

0–1 TAG1 Tag Field 1 R/W The TAG1 field can further qualify the isochronous reception

2–7 IRPORT1 Isochronous

8–9 TAG2 Tag Field 2 R/W The TAG2 field can further qualify the isochronous reception

10–15 IRPORT2 Isochronous

16–23 RESERVED Reserved
24–27 ISYNCRCVN Synchronous

28 IRCVALL Receive all

29–30 RESERVED Reserved

31 MONTAG Match on tag R/W MONTAG is set when the user wants to only accept

BIT NAME FUNCTION DIR DESCRIPTION

for isochronous Receive PORT1 when the MONT AG bit is set.

R/W IR port1 contains the channel number of the isochronous

receive port

1 channel

number

packets that the receiver accepts. The receiver accepts
isochronous packets with this channel number when the
IRP1EN is set.

for isochronous Receive PORT2 when the MONT AG bit is set.

R/W IR port2 contains the channel number of the isochronous

receive port

2 channel

number

packets that the receiver accepts. The receiver accepts
isochronous packets with this channel number when the
IRP2EN is set.

R/W In isochronous receive mode to the DM port, when the

Enable

ISYNCRCVN enable bits are high, the DMPRE terminal pulses
when an isochronous packet is received whose SYNC bit field
in its header matches the bit pattern in this field. The default is
0000b.

R/W When the IRCVALL bit is set high, the TSB12L V32 receives all

isochronous

packets

isochronous packets regardless of the channel number or tag
number. The default is off.

isochronous packets that match both the tag field and the
channel number field. When set, MONTAG indicates that
isochronous receive data is accepted. The default is off.

IRCVALL

MONTAG

2–12

2.2.7 Maint_Control Register at 1Ch

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128

PING VALUEACK

E_HCRC

E_DCRC

F_ACK

NO_PKT

NO_ACK

This register is used to generate test conditions. The control bits in this register allow errors to be inserted
into various places in the packets generated by this node. After the completion of error insertion, enabled
error-insertion controls are disabled. The power-up reset value of this register = 0000_0000’h

BIT

NUMBER

0 E_HCRC Header CRC

1 E_DCRC Data CRC

2 NO_PKT No Packet R/W If NO_PKT is set, the next primary packet to be generated by

3 F_ACK Ack Field R/W If F_ACK is set, the ack field shall be used within the next ac-

4 NO_ACK R/W If NO_ACK is set, the next acknowledge packet (that would

5–7 RESERVED Reserved

8–15 ACK R/W The 8-bit ACK field contains the 8-bit acknowledge packet

16–23 RESERVED Reserved
24–31 PINGVALUE Ping timer

BIT NAME FUNCTION DIR DESCRIPTION

R/W If E_HCRC is set, the packet header CRC component of the

Error

next primary packet generated by this node shall be in error or
shall be invalid; otherwise, this bit has no effect. After the next
packet for this node is generated, this bit will be cleared.

R/W If E_DCRC is set, the packet data CRC component of the next

Error

primary packet generated by this node shall be in error or shall
be invalid; otherwise, this bit has no effect. After the next packet
for this node is generated, this bit will be cleared to zero im­mediately upon transmission of the erroneous CRC.

this node shall be discarded. This bit will be cleared to zero im­mediately after the next packet for this node is discarded.

knowledge packet generated by this node. This bit will be
cleared to zero immediately after the next acknowledge packet
for this node is generated.

normally have been generated by this node) is not sent. This bit
will be immediately cleared to zero when the next acknowledge
packet for this node is discarded.

(ack_code and ack_parity) to be supplied when the F_ACK bit
indicates a modified acknowledge packet is to be generated.

R/W Ping timer value. This value reflects the time it takes a node

value

to respond to a ping packet. The granularity of this timer is
40 ns.

2–13

2.2.8 Diagnostic Register at 20h

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 3128

STATESEL0 STATESEL1 STATESEL2

B0_BUSY

B1_BUSY

B2_BUSY

B3_BUSY

B1_PND

B0_PND

B2_PND

B3_PND

REGRW

RAMTEST

The power-up reset value of this register = 0000_4AD0’h

BIT

NUMBER

0 B0_BUSY Byte 0 busy R Byte 0 busy. When this bit is set, no microinterface write to byte 0 of

1 B1_BUSY Byte 1 busy R Byte 1 busy. When this bit is set, no microinterface write to byte 1 of

2 B2_BUSY Byte 2 busy R Byte 2 busy. When this bit is set, no microinterface write to byte 2 of

3 B3_BUSY Byte 3 busy R Byte 3 busy. When this bit is set, no microinterface write to byte 3 of

4 B0_PND Byte 0

5 B1_PND Byte 1

6 B2_PND Byte 2

7 B3_PND Byte 3

8 RAM_TEST R/W This bit can be set only when TESTMODE is high. When this bit is

9 REGRW Register

10–15 RESERVED Reserved
16–19 STATSEL0 State0

20–23 STATSEL1 State1

24–27 STATSEL2 State2

28–31 RESERVED Reserved

BIT NAME FUNCTION DIR DESCRIPTION

any CFRs is allowed. The microinterface must first poll this bit
before writing to byte 0.

any CFRs is allowed. The microinterface must first poll this bit
before writing to byte 1.

any CFRs is allowed. The microinterface must first poll this bit
before writing to byte 2.

any CFRs is allowed. The microinterface must first poll this bit
before writing to byte 3.

R Byte 0 pending. When this bit is set, it indicates that byte 0 of a word

pending

or quadlet write has been accepted and the hardware is waiting for
the remaining bytes to be written. When the full write is complete,
this bit will be cleared.

R Byte 1 pending. When this bit is set, it indicates that byte 1 of a word

pending

or quadlet write has been accepted and the hardware is waiting for
the remaining bytes to be written. When the full write is complete,
this bit will be cleared.

R Byte 2 pending. When this bit is set, it indicates that byte 2 of a word

pending

or quadlet write has been accepted and the hardware is waiting for
the remaining bytes to be written. When the full write is complete,
this bit will be cleared.

R Byte 3 pending. When this bit is set, it indicates that byte 3 of a word

pending

or quadlet write has been accepted and the hardware is waiting for
the remaining bytes to be written. When the full write is complete
this bit will be cleared.

set, the built in self test(BIST) for the FIFOs (transmit and receive)
will be run. On completion of the test hardware will reset this bit to 0
and simultaneously set bit 30 and 31.

R/W When REGRW is set, write-protected bits in various registers can

read/write

be written to.

access

R/W Status output select bits. Used to program the output of STAT0

select

terminal. See table in

Operation

section.

R/W Status output select bits. Used to program the output of STAT1

select

terminal. See table in

Operation

section.

R/W Status output select bits. Used to program the output of STAT2

select

terminal. See table in Operation section.

2–14