Texas Instruments TSB12LV26PZT Datasheet

TSB12LV26

OHCIĆL ynx PCIĆBased IEEE 1394 Host Controller

2000 Bus Solutions

Data Manual

Printed in U.S.A., 03/00 SLLS366A

TSB12LV26

OHCI-Lynx PCI-Based IEEE 1394

Host Controller

Data Manual

Literature Number: SLLS366A

March 2000

Printed on Recycled Paper

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating

safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent

that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  2000, Texas Instruments Incorporated

iii

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Related Documents 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Terminal Descriptions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 TSB12LV26 Controller Programming Model 3–1. . . . . . . . . . . . . . . . . . . . . . . . .

3.1 PCI Configuration Registers 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Vendor ID Register 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Device ID Register 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 Command Register 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 Status Register 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Class Code and Revision ID Register 3–6. . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Latency Timer and Class Cache Line Size Register 3–6. . . . . . . . . . . . . .

3.8 Header Type and BIST Register 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9 OHCI Base Address Register 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10 TI Extension Base Address Register 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.11 Subsystem Identification Register 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12 Power Management Capabilities Pointer Register 3–9. . . . . . . . . . . . . . .

3.13 Interrupt Line and Pin Register 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.14 MIN_GNT and MAX_LAT Register 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.15 OHCI Control Register 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.16 Capability ID and Next Item Pointer Register 3–11. . . . . . . . . . . . . . . . . . . .

3.17 Power Management Capabilities Register 3–12. . . . . . . . . . . . . . . . . . . . . .

3.18 Power Management Control and Status Register 3–13. . . . . . . . . . . . . . . .

3.19 Power Management Extension Register 3–13. . . . . . . . . . . . . . . . . . . . . . . .

3.20 Miscellaneous Configuration Register 3–14. . . . . . . . . . . . . . . . . . . . . . . . . .

3.21 Link Enhancement Control Register 3–15. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.22 Subsystem Access Register 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.23 GPIO Control Register 3–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 OHCI Registers 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 OHCI Version Register 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 GUID ROM Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Asynchronous Transmit Retries Register 4–6. . . . . . . . . . . . . . . . . . . . . . .

4.4 CSR Data Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 CSR Compare Register 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 CSR Control Register 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

4.7 Configuration ROM Header Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 Bus Identification Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9 Bus Options Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.10 GUID High Register 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11 GUID Low Register 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12 Configuration ROM Mapping Register 4–11. . . . . . . . . . . . . . . . . . . . . . . . . .

4.13 Posted Write Address Low Register 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.14 Posted Write Address High Register 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . .

4.15 Vendor ID Register 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.16 Host Controller Control Register 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.17 Self-ID Buffer Pointer Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.18 Self-ID Count Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.19 Isochronous Receive Channel Mask High Register 4–15. . . . . . . . . . . . . .

4.20 Isochronous Receive Channel Mask Low Register 4–16. . . . . . . . . . . . . . .

4.21 Interrupt Event Register 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.22 Interrupt Mask Register 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.23 Isochronous Transmit Interrupt Event Register 4–20. . . . . . . . . . . . . . . . . .

4.24 Isochronous Transmit Interrupt Mask Register 4–21. . . . . . . . . . . . . . . . . . .

4.25 Isochronous Receive Interrupt Event Register 4–22. . . . . . . . . . . . . . . . . . .

4.26 Isochronous Receive Interrupt Mask Register 4–22. . . . . . . . . . . . . . . . . . .

4.27 Fairness Control Register 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.28 Link Control Register 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.29 Node Identification Register 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.30 PHY Layer Control Register 4–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.31 Isochronous Cycle Timer Register 4–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.32 Asynchronous Request Filter High Register 4–28. . . . . . . . . . . . . . . . . . . . .

4.33 Asynchronous Request Filter Low Register 4–30. . . . . . . . . . . . . . . . . . . . .

4.34 Physical Request Filter High Register 4–31. . . . . . . . . . . . . . . . . . . . . . . . . .

4.35 Physical Request Filter Low Register 4–33. . . . . . . . . . . . . . . . . . . . . . . . . .

4.36 Physical Upper Bound Register (Optional Register) 4–34. . . . . . . . . . . . . .

4.37 Asynchronous Context Control Register 4–35. . . . . . . . . . . . . . . . . . . . . . . .

4.38 Asynchronous Context Command Pointer Register 4–36. . . . . . . . . . . . . .

4.39 Isochronous Transmit Context Control Register 4–37. . . . . . . . . . . . . . . . . .

4.40 Isochronous Transmit Context Command Pointer Register 4–38. . . . . . . .

4.41 Isochronous Receive Context Control Register 4–38. . . . . . . . . . . . . . . . . .

4.42 Isochronous Receive Context Command Pointer Register 4–40. . . . . . . .

4.43 Isochronous Receive Context Match Register 4–41. . . . . . . . . . . . . . . . . . .

5 GPIO Interface 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Serial ROM Interface 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Electrical Characteristics 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Absolute Maximum Ratings Over Operating Temperature Ranges 7–1.

7.2 Recommended Operating Conditions 7–2. . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 Electrical Characteristics Over Recommended Operating Conditions 7–3

7.4 Switching Characteristics for PCI Interface 7–3. . . . . . . . . . . . . . . . . . . . . .

v

7.5 Switching Characteristics for PHY-Link Interface 7–3. . . . . . . . . . . . . . . . .

8 Mechanical Information 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

List of Illustrations

Figure Title Page

2–1 Terminal Assignments 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 TSB12LV26 Block Diagram 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 GPIO2 and GPIO3 Logic Diagram 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vii

List of Tables

Table Title Page

2–1 Signals Sorted by Terminal Number 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Signal Names Sorted Alphanumerically to Terminal Number 2–3. . . . . . . . . .

2–3 Power Supply Terminals 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 PCI System Terminals 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 PCI Address and Data Terminals 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 PCI Interface Control Terminals 2–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 IEEE 1394 PHY/Link Terminals 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–8 Miscellaneous Terminals 2–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Bit Field Access Tag Descriptions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 PCI Configuration Register Map 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 Command Register Description 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 Status Register Description 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 Class Code and Revision ID Register Description 3–6. . . . . . . . . . . . . . . . . . .

3–6 Latency Timer and Class Cache Line Size Register Description 3–6. . . . . . .

3–7 Header Type and BIST Register Description 3–7. . . . . . . . . . . . . . . . . . . . . . . .

3–8 OHCI Base Address Register Description 3–7. . . . . . . . . . . . . . . . . . . . . . . . . .

3–9 Subsystem Identification Register Description 3–8. . . . . . . . . . . . . . . . . . . . . .

3–10 Interrupt Line and Pin Register Description 3–9. . . . . . . . . . . . . . . . . . . . . . . . .

3–11 MIN_GNT and MAX_LAT Register Description 3–10. . . . . . . . . . . . . . . . . . . . .

3–12 OHCI Control Register Description 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–13 Capability ID and Next Item Pointer Register Description 3–11. . . . . . . . . . . . .

3–14 Power Management Capabilities Register Description 3–12. . . . . . . . . . . . . . .

3–15 Power Management Control and Status Register Description 3–13. . . . . . . . .

3–16 Power Management Extension Register Description 3–13. . . . . . . . . . . . . . . . .

3–17 Miscellaneous Configuration Register 3–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–18 Link Enhancement Control Register Description 3–15. . . . . . . . . . . . . . . . . . . .

3–19 Subsystem Access Register Description 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . .

3–20 GPIO Control Register Description 3–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 OHCI Register Map 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 OHCI Version Register Description 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 GUID ROM Register Description 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Asynchronous Transmit Retries Register Description 4–6. . . . . . . . . . . . . . . .

4–5 CSR Control Register Description 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Configuration ROM Header Register Description 4–8. . . . . . . . . . . . . . . . . . . .

4–7 Bus Options Register Description 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–8 Configuration ROM Mapping Register Description 4–11. . . . . . . . . . . . . . . . . . .

4–9 Posted Write Address High Register Description 4–12. . . . . . . . . . . . . . . . . . . .

viii

4–10 Host Controller Control Register Description 4–13. . . . . . . . . . . . . . . . . . . . . . . .

4–11 Self-ID Count Register Description 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–12 Isochronous Receive Channel Mask High Register Description 4–15. . . . . . .

4–13 Isochronous Receive Channel Mask Low Register Description 4–16. . . . . . . .

4–14 Interrupt Event Register Description 4–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–15 Interrupt Mask Register Description 4–19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–16 Isochronous Transmit Interrupt Event Register Description 4–20. . . . . . . . . . .

4–17 Isochronous Receive Interrupt Event Register Description 4–22. . . . . . . . . . .

4–18 Fairness Control Register Description 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–19 Link Control Register Description 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–20 Node Identification Register Description 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . .

4–21 PHY Control Register Description 4–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–22 Isochronous Cycle Timer Register Description 4–27. . . . . . . . . . . . . . . . . . . . . .

4–23 Asynchronous Request Filter High Register Description 4–28. . . . . . . . . . . . .

4–24 Asynchronous Request Filter Low Register Description 4–30. . . . . . . . . . . . . .

4–25 Physical Request Filter High Register Description 4–31. . . . . . . . . . . . . . . . . . .

4–26 Physical Request Filter Low Register Description 4–33. . . . . . . . . . . . . . . . . . .

4–27 Asynchronous Context Control Register Description 4–35. . . . . . . . . . . . . . . . .

4–28 Asynchronous Context Command Pointer Register Description 4–36. . . . . . .

4–29 Isochronous Transmit Context Control Register Description 4–37. . . . . . . . . .

4–30 Isochronous Receive Context Control Register Description 4–38. . . . . . . . . . .

4–31 Isochronous Receive Context Match Register Description 4–41. . . . . . . . . . . .

6–1 Registers and Bits Loadable through Serial ROM 6–1. . . . . . . . . . . . . . . . . . .

6–2 Serial ROM Map 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1–1

1 Introduction

1.1 Description

The Texas Instruments TSB12LV26 is a PCI-to-1394 host controller compatible with the latest

PCI Local Bus, PCI

Bus Power Management Interface

, IEEE 1394-1995, and

1394 Open Host Controller Interface Specification

. The
chip provides the IEEE 1394 link function, and is compatible with serial bus data rates of 100 Mbits/s, 200 Mbits/s,
and 400 Mbits/s.

As required by the

1394 Open Host Controller Interface Specification

(OHCI) and IEEE proposal 1394a specification,
internal control registers are memory-mapped and nonprefetchable. The PCI configuration header is accessed
through configuration cycles specified by PCI, and provides Plug-and-Play (PnP) compatibility. Furthermore, the
TSB12L V26 is compliant with the

PCI Bus Power Management Interface Specification

, per the

PC 99 Design Guide

requirements. TSB12LV26 supports the D0, D2, and D3 power states.
The TSB12LV26 design provides PCI bus master bursting, and is capable of transferring a cacheline of data at

132 Mbytes/s after connection to the memory controller. Since PCI latency can be large, deep FIFOs are provided
to buffer 1394 data.

The TSB12L V26 provides physical write posting buffers and a highly tuned physical data path for SBP-2 performance.
The TSB12L V26 also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal
arbitration, and bus holding buffers on the PHY/link interface.

An advanced CMOS process is used to achieve low power consumption while operating at PCI clock rates up to
33 MHz.

1.2 Features

The TSB12LV26 supports the following features:

• 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments

• Serial bus data rates of 100, 200, and 400 Mbits/s

• Provides bus-hold buffers on physical interface for low-cost single capacitor isolation

• Physical write posting of up to three outstanding transactions

• Serial ROM interface supports 2-wire devices

• External cycle timer control for customized synchronization

• Implements PCI burst transfers and deep FIFOs to tolerate large host latency

• Provides two general-purpose I/Os

• Fabricated in advanced low-power CMOS process

• Packaged in 100-terminal LQFP (PZ)

• Supports PCI_CLKRUN

protocol

1–2

1.3 Related Documents

•

1394 Open Host Controller Interface Specification 1.0

•

P1394 Standard for a High Performance Serial Bus

(IEEE 1394-1995)

•

P1394a Draft Standard for a High Performance Serial Bus (Supplement)

•

PC 99 Design Guide

•

PCI Bus Power Management Interface Specification (Revision 1.0)

•

PCI Local Bus Specification (Revision 2.2)

•

Serial Bus Protocol 2

(SBP–2)

1.4 Ordering Information

ORDERING NUMBER NAME VOLTAGE PACKAGE

TSB12LV26 OHCI-Lynx PCI-Based IEEE 1394 Host Controller 3.3V-, 5V-Tolerant I/Os 100-Terminal LQFP

2–1

2 Terminal Descriptions

This section provides the terminal descriptions for the TSB12LV26. Figure 2–1 shows the signal assigned to each
terminal in the package. Table 2–1 is a listing of signal names arranged in terminal number order, and Table 2–2 lists
terminals in alphanumeric order by signal names.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

REG18

PHY_SCLK

GND

PHY_DATA1

PHY_DATA2

PHY_DATA5

GND

PHY_DATA6

PHY_DATA7

PCI_AD25

PCI_AD24

PCI_C/BE3

PCI_IDSEL

GND

PCI_AD18

PCI_AD17

PCI_AD16

GND

REG18

PZ PACKAGE

(TOP VIEW)

PHY_DATA0

PCI_AD21

PHY_LREQ

PHY_DATA3

PHY_DATA4

PCI_AD19

GPIO2
GPIO3

SCL

SDA

V

CCP

PCI_CLKRUN

PCI_INTA

3.3 V

CC

G_RST

GND

PCI_CLK

PCI_GNT

V

CCP

PCI_AD30

3.3 V

CC

PCI_AD29
PCI_AD28
PCI_AD27

GND

PCI_AD26

3.3 V

CC

PCI_REQ

PCI_PME

PCI_AD31

GND

GND

PCI_AD1
PCI_AD2

3.3 V

CC

PCI_AD5
PCI_AD7
PCI_AD8

PCI_AD9

GND

PCI_AD12
PCI_AD14

PCI_AD15
PCI_C/BE1

PCI_AD0

PCI_AD3

PCI_AD4
PCI_AD6

PCI_C/BE0
V

CCP

PCI_AD10

PCI_AD11

PCI_AD13

3.3 V

CC

PCI_PAR
PCI_SERR

PCI_RST

CYCLEOUT

CYCLEIN

REG_EN

CCP

V

CC

3.3 V

PHY_CTL1

PHY_CTL0

CC

3.3 V

PHY_LINKON

PHY_LPS

PCI_AD22

PCI_AD23

PCI_AD20

CCP

V

PCI_C/BE2

PCI_FRAME

PCI_IRDY

PCI_TRDY

PCI_DEVSEL

PCI_STOP

PCI_PERR

CC

3.3 V

CC

3.3 V

CC

3.3 V

Figure 2–1. Terminal Assignments

2–2

Table 2–1. Signals Sorted by T erminal Number

NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME

1 GND 26 PCI_AD25 51 PCI_SERR 76 PCI_RST
2 GPIO2 27 PCI_AD24 52 PCI_PAR 77 CYCLEOUT
3 GPIO3 28 PCI_C/BE3 53 PCI_C/BE1 78 CYCLEIN
4 SCL 29 PCI_IDSEL 54 PCI_AD15 79 REG_EN
5 SDA 30 GND 55 3.3 V

CC

80 3.3 V

CC

6 V

CCP

31 PCI_AD23 56 PCI_AD14 81 PHY_DATA7
7 PCI_CLKRUN 32 PCI_AD22 57 PCI_AD13 82 PHY_DATA6
8 PCI_INTA 33 PCI_AD21 58 PCI_AD12 83 GND
9 3.3 V

CC

34 PCI_AD20 59 PCI_AD1 1 84 PHY_DATA5

10 G_RST 35 3.3 V

CC

60 GND 85 PHY_DATA4
11 GND 36 PCI_AD19 61 PCI_AD10 86 PHY_DATA3
12 PCI_CLK 37 PCI_AD18 62 PCI_AD9 87 V

CCP

13 3.3 V

CC

38 PCI_AD17 63 V

CCP

88 PHY_DATA2

14 PCI_GNT 39 V

CCP

64 PCI_AD8 89 PHY_DATA1
15 PCI_REQ 40 PCI_AD16 65 PCI_C/BE0 90 PHY_DATA0
16 V

CCP

41 PCI_C/BE2 66 PCI_AD7 91 3.3 V

CC

17 PCI_PME 42 REG18 67 PCI_AD6 92 PHY_CTL1
18 PCI_AD31 43 PCI_FRAME 68 PCI_AD5 93 PHY_CTL0
19 PCI_AD30 44 PCI_IRDY 69 PCI_AD4 94 GND
20 3.3 V

CC

45 PCI_TRDY 70 3.3 V

CC

95 PHY_SCLK

21 PCI_AD29 46 3.3 V

CC

71 PCI_AD3 96 3.3 V

CC

22 PCI_AD28 47 PCI_DEVSEL 72 PCI_AD2 97 PHY_LREQ
23 PCI_AD27 48 PCI_STOP 73 PCI_AD1 98 PHY_LINKON
24 GND 49 PCI_PERR 74 PCI_AD0 99 PHY_LPS
25 PCI_AD26 50 GND 75 GND 100 REG18

2–3

Table 2–2. Signal Names Sorted Alphanumerically to T erminal Number

TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO.

CYCLEIN 78 PCI_AD11 59 PCI_CLK 12 PHY_DATA7 81

CYCLEOUT 77 PCI_AD12 58 PCI_CLKRUN 7 PHY_LINKON 98

GND 1 PCI_AD13 57 PCI_DEVSEL 47 PHY_LPS 99
GND 11 PCI_AD14 56 PCI_FRAME 43 PHY_LREQ 97
GND 24 PCI_AD15 54 PCI_GNT 14 PHY_SCLK 95
GND 30 PCI_AD16 40 PCI_IDSEL 29 REG_EN 79
GND 50 PCI_AD17 38 PCI_INTA 8 REG18 42
GND 60 PCI_AD18 37 PCI_IRDY 44 REG18 100
GND 75 PCI_AD19 36 PCI_PAR 52 SCL 4
GND 83 PCI_AD20 34 PCI_PERR 49 SDA 5
GND 94 PCI_AD21 33 PCI_PME 17 V

CCP

6

GPIO2 2 PCI_AD22 32 PCI_REQ 15 V

CCP

16

GPIO3 3 PCI_AD23 31 PCI_RST 76 V

CCP

39

G_RST 10 PCI_AD24 27 PCI_SERR 51 V

CCP

63

PCI_AD0 74 PCI_AD25 26 PCI_STOP 48 V

CCP

87

PCI_AD1 73 PCI_AD26 25 PCI_TRDY 45 3.3 V

CC

9

PCI_AD2 72 PCI_AD27 23 PHY_CTL0 93 3.3 V

CC

13

PCI_AD3 71 PCI_AD28 22 PHY_CTL1 92 3.3 V

CC

20

PCI_AD4 69 PCI_AD29 21 PHY_DAT A0 90 3.3 V

CC

35

PCI_AD5 68 PCI_AD30 19 PHY_DAT A1 89 3.3 V

CC

46

PCI_AD6 67 PCI_AD31 18 PHY_DAT A2 88 3.3 V

CC

55

PCI_AD7 66 PCI_C/BE0 65 PHY_DAT A3 86 3.3 V

CC

70

PCI_AD8 64 PCI_C/BE1 53 PHY_DAT A4 85 3.3 V

CC

80

PCI_AD9 62 PCI_C/BE2 41 PHY_DAT A5 84 3.3 V

CC

91

PCI_AD10 61 PCI_C/BE3 28 PHY_DATA6 82 3.3 V

CC

96

The terminals in Table 2–3 through Table 2–8 are grouped in tables by functionality, such as PCI system function
and power supply function. The terminal numbers are also listed for convenient reference.

Table 2–3. Power Supply T erminals

TERMINAL

NAME NO.

I/O

DESCRIPTION

GND

1, 11, 24, 30,

50, 60, 75, 83,

94

I Device ground terminals

V

CCP

6, 16, 39, 63,

87

I PCI signaling clamp voltage power input. PCI signals are clamped per the

PCI Local Bus Specification

.

3.3 V

CC

9, 13, 20, 35,

46, 55, 70, 80,

91, 96

I 3.3-V power supply terminals

2–4

Table 2–4. PCI System Terminals

TERMINAL

NAME NO.

I/O

DESCRIPTION

G_RST 10 I

Global power reset. This reset brings all of the TSB12LV26 internal registers to their default states, including
those registers not reset by PCI_RST

. When G_RST is asserted, the device is completely nonfunctional.
When implementing wake capabilities from the 1394 host controller, it is necessary to implement two resets
to the TSB12LV26. G_RST

should be a one-time power-on reset, and PCI_RST should be connected to the

PCI bus RST

. If wake capabilities are not required, G_RST may be connected to the PCI bus RST (see

PCI_RST

, terminal 76).

PCI_CLK 12 I

PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at rising edge
of PCI_CLK.

PCI_INTA 8 O

Interrupt signal. This output indicates interrupts from the TSB12L V26 to the host. This terminal is implemented
as open-drain.

PCI_RST 76 I

PCI reset. When this bus reset is asserted, the TSB12L V26 places all output buffers in a high impedance state
and resets all internal registers except device power management context- and vendor-specific bits initialized
by host power-on software. When PCI_RST

is asserted, the device is completely nonfunctional.

If this terminal is implemented, then it should be connected to the PCI bus RST

signal. Otherwise, it should

be pulled high to link VCC through a 4.7-kΩ resistor, or strapped to the G_RST

terminal (see G_RST , terminal

10).

2–5

Table 2–5. PCI Address and Data Terminals

TERMINAL

NAME NO.

I/O

DESCRIPTION

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD1
PCI_AD0

18
19
21
22
23
25
26
27
31
32
33
34
36
37
38
40
54
56
57
58
59
61
62
64
66
67
68
69
71
72
73
74

I/O

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the PCI interface.
During the address phase of a PCI cycle, AD31–AD0 contain a 32-bit address or other destination information.
During the data phase, AD31–AD0 contain data.

2–6

Table 2–6. PCI Interface Control Terminals

TERMINAL

NAME NO.

I/O

DESCRIPTION

PCI_C/BE0
PCI_C/BE1
PCI_C/BE2
PCI_C/BE3

65
53
41
28

I/O

PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the same PCI
terminals. During the address phase of a bus cycle PCI_C/BE3

–PCI_C/BE0 defines the bus command. During

the data phase, this 4-bit bus is used as byte enables.

PCI_CLKRUN 7 I/O

Clock run. This terminal provides clock control through the PCI_CLKRUN protocol. An internal pulldown
resistor is implemented on this terminal.
This terminal is implemented as open-drain.

PCI_DEVSEL 47 I/O

PCI device select. The TSB12LV26 asserts this signal to claim a PCI cycle as the target device. As a PCI
initiator, the TSB12LV26 monitors this signal until a target responds. If no target responds before time-out
occurs, then the TSB12LV26 terminates the cycle with an initiator abort.

PCI_FRAME 43 I/O

PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle. PCI_FRAME is asserted to indicate
that a bus transaction is beginning, and data transfers continue while this signal is asserted. When PCI_FRAME
is deasserted, the PCI bus transaction is in the final data phase.

PCI_GNT 14 I

PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB12LV26 access to the PCI bus after
the current data transaction has completed. This signal may or may not follow a PCI bus request, depending
upon the PCI bus parking algorithm.

PCI_IDSEL 29 I

Initialization device select. IDSEL selects the TSB12L V26 during configuration space accesses. IDSEL can be
connected to one of the upper 24 PCI address lines on the PCI bus.

PCI_IRDY 44 I/O

PCI initiator ready. IRDY indicates the ability of the PCI bus initiator to complete the current data phase of the
transaction. A data phase is completed upon a rising edge of PCLK where both PCI_IRDY

and PCI_TRDY are

asserted.

PCI_PAR 52 I/O

PCI parity. In all PCI bus read and write cycles, the TSB12L V26 calculates even parity across the AD and C/BE
buses. As an initiator during PCI cycles, the TSB12LV26 outputs this parity indicator with a one PCI_CLK delay .
As a target during PCI cycles, the calculated parity is compared to the initiator parity indicator; a miscompare
can result in a parity error assertion (PCI_PERR

).

PCI_PERR 49 I/O

PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match
PCI_PAR when PERR_ENB (bit 6) is set in the PCI command register (offset 04h, see Section 3.4).

PCI_PME 17 O Power management event. This terminal indicates wake events to the host.
PCI_REQ 15 O

PCI bus request. Asserted by the TSB12LV26 to request access to the bus as an initiator. The host arbiter
asserts the PCI_GNT

signal when the TSB12LV26 has been granted access to the bus.

PCI_SERR 51 O

PCI system error. When SERR_ENB (bit 8) in the PCI command register (offset 04h, see Section 3.4) is set
the output is pulsed, indicating an address parity error has occurred. The TSB12LV26 needs not be the target
of the PCI cycle to assert this signal.
This terminal is implemented as open-drain.

PCI_STOP 48 I/O

PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus
transaction. This signal is used for target disconnects, and is commonly asserted by target devices which do
not support burst data transfers.

PCI_TRDY 45 I/O

PCI target ready. PCI_TRDY indicates the ability of the PCI bus targer to complete the current data phase of
the transaction. A data phase is completed upon a rising edge of PCI_CLK where both PCI_IRDY

and

PCI_TRDY

are asserted.

2–7

Table 2–7. IEEE 1394 PHY/Link Terminals

TERMINAL

NAME NO.

I/O

DESCRIPTION

PHY_CTL1
PHY_CTL0

92
93

I/O

PHY -link interface control. These bidirectional signals control passage of information between the two devices.
The TSB12LV26 can only drive these terminals after the PHY has granted permission following a link request
(PHY_LREQ).

PHY_DATA7
PHY_DATA6
PHY_DATA5
PHY_DATA4
PHY_DATA3
PHY_DATA2
PHY_DATA1
PHY_DATA0

81
82
84
85
86
88
89
90

I/O

PHY -link interface data. These bidirectional signals pass data between the TSB12LV26 and the PHY device.
These terminals are driven by the TSB12LV26 on transmissions and are driven by the PHY on reception. Only
PHY_DATA1–PHY_DATA0 are valid for 100-Mbit speeds, PHY_DATA3–PHY_DATA0 are valid for 200-Mbit
speeds, and PHY_DATA7–PHY_DATA0 are valid for 400-Mbit speeds.

PHY_LINKON 98 I/O

LinkOn wake indication. The PHY_LINKON signal is pulsed by the PHY to activate the link, and 3.3-V signaling
is required.
When connected to the TSB41LV0X C/LKON terminal, a 1-kΩ series resistor is required between the link and
PHY .

PHY_LPS 99 I/O

Link power status. The PHY_LPS signal is asserted when the link is powered on, and 3.3-V signaling is

required.
PHY_LREQ 97 O Link request. This signal is driven by the TSB12L V26 to initiate a request for the PHY to perform some service.
PHY_SCLK 95 I System clock. This input from the PHY provides a 49.152-MHz clock signal for data synchronization.

Table 2–8. Miscellaneous Terminals

TERMINAL

NAME NO.

I/O

DESCRIPTION

CYCLEOUT 77 I/O This terminal provides an 8-kHz cycle timer synchronization signal.

CYCLEIN 78 I/O

The CYCLEIN terminal allows an external 8-kHz clock to be used as a cycle timer for synchronization with other

system devices.

If this terminal is not implemented, then it should be pulled high to the link VCC through a 4.7-kΩ resistor.
GPIO2 2 I/O

General-purpose I/O [2]. This terminal defaults as an input and if it is not implemented, then it is recommended

that it be pulled low to ground with a 220-Ω resistor.
GPIO3 3 I/O

General-purpose I/O [3]. This terminal defaults as an input and if it is not implemented, then it is recommended

that it be pulled low to ground with a 220-Ω resistor.
REG_EN 79 I Regulator enable. This terminal is pulled low to ground through a 220-Ω resistor.

REG18

42

100

I

The REG18 terminals are connected to a 0.01 µF capacitor which, in turn, is connected to ground. The

capacitor provides a local bypass for the internal core voltage.

SCL 4 I/O

Serial clock. The TSB12LV26 determines whether a two-wire serial ROM is implemented at reset. If a two-wire

serial ROM is implemented, then this terminal provides the SCL serial clock signaling.

This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the design),

this terminal should be pulled high to the ROM VCC with a 2.7-kΩ resistor. Otherwise, it should be pulled low

to ground with a 220-Ω resistor.

SDA 5 I/O

Serial data. The TSB12LV26 determines whether a two-wire serial ROM is implemented at reset. If a two-wire

serial ROM is detected, then this terminal provides the SDA serial data signaling. This terminal must be wired

low to indicate no serial ROM is present.

This terminal is implemented as open-drain, and for normal operation (a ROM is implemented in the design),

this terminal should be pulled high to the ROM VCC with a 2.7-kΩ resistor. Otherwise, it should be pulled low

to ground with a 220-Ω resistor.

2–8

3–1

3 TSB12LV26 Controller Programming Model

This section describes the internal registers used to program the TSB12L V26. All registers are detailed in the same
format: a brief description for each register, followed by the register of fset and a bit table describing the reset state
for each register.

A bit description table, typically included when the register contains bits of more than one type or purpose, indicates
bit field names, field access tags which appear in the

type

column,and a detailed field description. Table 3–1

describes the field access tags.

Table 3–1. Bit Field Access Tag Descriptions

ACCESS TAG NAME MEANING

R Read Field may be read by software.

W Write Field may be written by software to any value.

S Set Field may be set by a write of 1. Writes of 0 have no effect.
C Clear Field may be cleared by a write of 1. Writes of 0 have no effect.
U Update Field may be autonomously updated by the TSB12LV26.

A simplified block diagram of the TSB12LV26 is provided in Figure 3–1.

3–2

Internal

Registers

ISO Transmit

Contexts

Async Transmit

Contexts

Physical DMA

& Response

PCI

Target

SM

PHY

Register

Access

& Status

Monitor

Central
Arbiter

&

PCI

Initiator

SM

Cycle Start

Generator &

Cycle Monitor

Synthesized

Bus Reset

Receive

FIFO

Link

Transmit

Link

Receive

PCI

Host

Bus

Interface

Resp

Timeout

Request

Filters

General

Request Receive

Async Response

Receive

ISO Receive

Contexts

OHCI PCI Power

Mgmt & CLKRUN

Transmit

FIFO

Receive

Acknowledge

Serial

ROM

GPIOs

CRC

PHY /

Link

Interface

MISC

Interface

Figure 3–1. TSB12LV26 Block Diagram

3–3

3.1 PCI Configuration Registers

The TSB12LV26 is a single-function PCI device. The configuration header is compliant with the

PCI Local Bus

Specification

as a standard header. Table 3–2 illustrates the PCI configuration header that includes both the

predefined portion of the configuration space and the user definable registers.

Table 3–2. PCI Configuration Register Map

REGISTER NAME OFFSET

Device ID Vendor ID 00h

Status Command 04h

Class code Revision ID 08h

BIST Header type Latency timer Cache line size 0Ch

OHCI registers base address 10h

TI extension registers base address 14h

Reserved 18h
Reserved 1Ch
Reserved 20h
Reserved 24h
Reserved 28h

Subsystem ID Subsystem vendor ID 2Ch

Reserved 30h

Reserved

PCI power

management

capabilities pointer

34h

Reserved 38h

Maximum latency Minimum grant Interrupt pin Interrupt line 3Ch

PCI OHCI control register 40h

Power management capabilities Next item pointer Capability ID 44h

PM data PMCSR_BSE Power management CSR 48h

Reserved 4Ch–ECh

PCI miscellaneous configuration register F0h

Link_Enhancements register F4h

Subsystem ID alias Subsystem vendor ID alias F8h

GPIO3 GPIO2 Reserved FCh

3.2 Vendor ID Register

The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.
The vendor ID assigned to Texas Instruments is 104Ch.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Vendor ID
Type R R R R R R R R R R R R R R R R
Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0

Register: Vendor ID
Type: Read-only
Offset: 00h
Default: 104Ch

3–4

3.3 Device ID Register

The device ID register contains a value assigned to the TSB12L V26 by Texas Instruments. The device identification
for the TSB12LV26 is 8020h.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Device ID
Type R R R R R R R R R R R R R R R R
Default 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0

Register: Device ID
Type: Read-only
Offset: 02h
Default: 8020h

3.4 Command Register

The command register provides control over the TSB12L V26 interface to the PCI bus. All bit functions adhere to the
definitions in the

PCI Local Bus Specification

, as seen in the bit descriptions of Table 3–3.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Command
Type R R R R R R R R/W R R/W R R/W R R/W R/W R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Command
Type: Read/Write, Read-only
Offset: 04h
Default: 0000h

T able 3–3. Command Register Description

BIT FIELD NAME TYPE DESCRIPTION

15–10 RSVD R Reserved. Bits 15–10 return 0s when read.

9 FBB_ENB R

Fast back-to-back enable. The TSB12LV26 does not generate fast back-to-back transactions, thus
this bit returns 0 when read.

8 SERR_ENB R/W

PCI_SERR enable. When this bit is set, the TSB12LV26 PCI_SERR driver is enabled. PCI_SERR can
be asserted after detecting an address parity error on the PCI bus.

7 STEP_ENB R

Address/data stepping control. The TSB12L V26 does not support address/data stepping, thus this bit
is hardwired to 0.

6 PERR_ENB R/W

Parity error enable. When this bit is set, the TSB12LV26 is enabled to drive PCI_PERR response to
parity errors through the PCI_PERR

signal.

5 VGA_ENB R

VGA palette snoop enable. The TSB12LV26 does not feature VGA palette snooping. This bit returns 0
when read.

4 MWI_ENB R/W

Memory write and invalidate enable. When this bit is set, the TSB12LV26 is enabled to generate MWI
PCI bus commands. If this bit is cleared, then the TSB12LV26 generates memory write commands
instead.

3 SPECIAL R

Special cycle enable. The TSB12LV26 function does not respond to special cycle transactions. This bit
returns 0 when read.

2 MASTER_ENB R/W Bus master enable. When this bit is set, the TSB12LV26 is enabled to initiate cycles on the PCI bus.
1 MEMORY_ENB R/W

Memory response enable. Setting this bit enables the TSB12LV26 to respond to memory cycles on the
PCI bus. This bit must be set to access OHCI registers.

0 IO_ENB R

I/O space enable. The TSB12LV26 does not implement any I/O mapped functionality; thus, this bit re­turns 0 when read.

3–5

3.5 Status Register

The status register provides status over the TSB12LV26 interface to the PCI bus. All bit functions adhere to the
definitions in the

PCI Local Bus Specification

. See Table 3–4 for a complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Status
Type RCU RCU RCU RCU RCU R R RCU R R R R R R R R
Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0

Register: Status
Type: Read/Clear/Update, Read-only
Offset: 06h
Default: 0210h

Table 3–4. Status Register Description

BIT FIELD NAME TYPE DESCRIPTION

15 PAR_ERR RCU Detected parity error. This bit is set when a parity error is detected, either address or data parity errors.
14 SYS_ERR RCU

Signaled system error. This bit is set when PCI_SERR is enabled and the TSB12L V26 has signaled a
system error to the host.

13 MABORT RCU

Received master abort. This bit is set when a cycle initiated by the TSB12LV26 on the PCI bus has been
terminated by a master abort.

12 TABORT_REC RCU

Received target abort. This bit is set when a cycle initiated by the TSB12LV26 on the PCI bus was
terminated by a target abort.

11 TABORT_SIG RCU

Signaled target abort. This bit is set by the TSB12L V26 when it terminates a transaction on the PCI bus
with a target abort.

10–9 PCI_SPEED R

DEVSEL timing. Bits 10–9 encode the timing of PCI_DEVSEL and are hardwired to 01b indicating that
the TSB12LV26 asserts this signal at a medium speed on nonconfiguration cycle accesses.

8 DATAPAR RCU

Data parity error detected. This bit is set when the following conditions have been met:

a. PCI_PERR

was asserted by any PCI device including the TSB12LV26.
b. The TSB12LV26 was the bus master during the data parity error.
c. The parity error response bit is set in the PCI command register (offset 04h, see Section 3.4).

7 FBB_CAP R

Fast back-to-back capable. The TSB12LV26 cannot accept fast back-to-back transactions; thus, this
bit is hardwired to 0.

6 UDF R

User definable features (UDF) supported. The TSB12L V26 does not support the UDF; thus, this bit is
hardwired to 0.

5 66MHZ R

66-MHz capable. The TSB12L V26 operates at a maximum PCI_CLK frequency of 33 MHz; therefore,
this bit is hardwired to 0.

4 CAPLIST R

Capabilities list. This bit returns 1 when read, indicating that capabilities additional to standard PCI are
implemented. The linked list of PCI power management capabilities is implemented in this function.

3–0 RSVD R Reserved. Bits 3–0 return 0s when read.

3–6

3.6 Class Code and Revision ID Register

The class code and revision ID register categorizes the TSB12L V26 as a serial bus controller (0Ch), controlling an
IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the
least significant byte. See Table 3–5 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Class code and revision ID
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Class code and revision ID
Type R R R R R R R R R R R R R R R R
Default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

Register: Class code and revision ID
Type: Read-only
Offset: 08h
Default: 0C00 1000h

Table 3–5. Class Code and Revision ID Register Description

BIT FIELD NAME TYPE DESCRIPTION

31–24 BASECLASS R

Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus
controller.

23–16 SUBCLASS R

Subclass. This field returns 00h when read, which specifically classifies the function as controlling an
IEEE 1394 serial bus.

15–8 PGMIF R

Programming interface. This field returns 10h when read, indicating that the programming model is
compliant with the

1394 Open Host Controller Interface Specification

.

7–0 CHIPREV R Silicon revision. This field returns 00h when read, indicating the silicon revision of the TSB12LV26.

3.7 Latency Timer and Class Cache Line Size Register

The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size
and the latency timer associated with the TSB12LV26. See Table 3–6 for a complete description of the register
contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Latency timer and class cache line size
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Latency timer and class cache line size
Type: Read/Write,
Offset: 0Ch
Default: 0000h

Table 3–6. Latency Timer and Class Cache Line Size Register Description

BIT FIELD NAME TYPE DESCRIPTION

15–8 LATENCY_TIMER R/W

PCI latency timer. The value in this register specifies the latency timer for the TSB12L V26, in units of
PCI clock cycles. When the TSB12LV26 is a PCI bus initiator and asserts PCI_FRAME

, the latency
timer begins counting from zero. If the latency timer expires before the TSB12LV26 transaction has
terminated, then the TSB12LV26 terminates the transaction when its PCI_GNT

is deasserted.

7–0 CACHELINE_SZ R/W

Cache line size. This value is used by the TSB12L V26 during memory write and invalidate, memory
read line, and memory read multiple transactions.

3–7

3.8 Header Type and BIST Register

The header type and BIST register indicates the TSB12L V26 PCI header type, and indicates no built-in self test. See
Table 3–7 for a complete description of the register contents.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Header type and BIST
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Header type and BIST
Type: Read-only
Offset: 0Eh
Default: 0000h

Table 3–7. Header T ype and BIST Register Description

BIT FIELD NAME TYPE DESCRIPTION

15–8 BIST R

Built-in self test. The TSB12LV26 does not include a built-in self test; thus, this field returns 00h when
read.

7–0 HEADER_TYPE R

PCI header type. The TSB12LV26 includes the standard PCI header, and this is communicated by
returning 00h when this field is read.

3.9 OHCI Base Address Register

The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI control.
When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of
memory address space are required for the OHCI registers. See T able 3–8 for a complete description of the register
contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name OHCI base address
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name OHCI address
Type R/W R/W R/W R/W R/W R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: OHCI base address
Type: Read/Write, Read-only
Offset: 10h
Default: 0000 0000h

T able 3–8. OHCI Base Address Register Description

BIT FIELD NAME TYPE DESCRIPTION

31–11 OHCIREG_PTR R/W OHCI register pointer. Specifies the upper 21 bits of the 32-bit OHCI base address register .

10–4 OHCI_SZ R

OHCI register size. This field returns 0s when read, indicating that the OHCI registers require a
2-Kbyte region of memory.

3 OHCI_PF R

OHCI register prefetch. This bit returns 0 when read, indicating that the OHCI registers are
nonprefetchable.

2–1 OHCI_MEMTYPE R

OHCI memory type. This field returns 0s when read, indicating that the OHCI base address register is
32 bits wide and mapping can be done anywhere in the 32-bit memory space.

0 OHCI_MEM R

OHCI memory indicator. This bit returns 0 when read, indicating that the OHCI registers are mapped
into system memory space.

3–8

3.10 TI Extension Base Address Register

The TI extension base address register is programmed with a base address referencing the memory-mapped TI
extension registers. See the

OHCI Base Address Register

, Section 3.9, for bit field details.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TI extension base address
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TI extension base address
Type R/W R/W R/W R/W R/W R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: TI extension base address
Type: Read/Write, Read-only
Offset: 14h
Default: 0000 0000h

3.11 Subsystem Identification Register

The subsystem identification register is used for system and option card identification purposes. This register can
be initialized from the serial ROM or programmed via the subsystem ID and subsystem vendor ID alias registers at
offset F8h. See Table 3–9 for a complete description of the register contents.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Subsystem identification
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Subsystem identification
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Subsystem identification
Type: Read/Update
Offset: 2Ch
Default: 0000 0000h

Table 3–9. Subsystem Identification Register Description

BIT FIELD NAME TYPE DESCRIPTION

31–16 OHCI_SSID RU Subsystem device ID. This field indicates the subsystem device ID.

15–0 OHCI_SSVID RU Subsystem vendor ID. This field indicates the subsystem vendor ID.