Texas Instruments TSB12LV23PZ Datasheet

TSB12LV23 OHCI-Lynx PCI-Based

IEEE 1394 Host Controller

Data Manual

Literature Number: SLLS328A

April 1999

Printed on Recycled Paper

IMPORTANT NOTICE

Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products
or to discontinue any product or service without notice, and advise customers to obtain the latest
version of relevant information to verify , before placing orders, that information being relied on
is current and complete. All products are sold subject to the terms and conditions of sale supplied
at the time of order acknowledgement, including those pertaining to warranty, patent
infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the
time of sale in accordance with TI’s standard warranty. Testing and other quality control
techniques are utilized to the extent TI deems necessary to support this warranty . Specific testing
of all parameters of each device is not necessarily performed, except those mandated by
government requirements.

CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE
POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR
ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR
PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUIT ABLE FOR
USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY
AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and
operating safeguards must be provided by the customer to minimize inherent or procedural
hazards.

TI assumes no liability for applications assistance or customer product design. TI does not
warrant or represent that any license, either express or implied, is granted under any patent right,
copyright, mask work right, or other intellectual property right of TI covering or relating to any
combination, machine, or process in which such semiconductor products or services might be
or are used. TI’s publication of information regarding any third party’s products or services does
not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1999, Texas Instruments Incorporated

Contents

Section Title Page

1 Introduction 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Related Documents 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Ordering Information 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Terminal Descriptions 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 TSB12LV23 Controller Programming Model 3–1. . . . . . . . . . . . . . . . . . . . . . . . .

3.1 PCI/CardBus Configuration Registers 3–3. . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Vendor ID Register 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 Device ID Register 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.4 PCI Command Register 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.5 PCI Status Register 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.6 Class Code and Revision ID Register 3–6. . . . . . . . . . . . . . . . . . . . . . . . . .

3.7 Latency Timer and Class Cache Line Size Register 3–6. . . . . . . . . . . . . .

3.8 Header Type and BIST Register 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.9 OHCI Base Address Register 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.10 TI Extension Base Address Register 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . .

3.11 CIS Base Address Register 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.12 CardBus CIS Pointer Register 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.13 PCI Subsystem Identification Register 3–9. . . . . . . . . . . . . . . . . . . . . . . . . .

3.14 PCI Power Management Capabilities Pointer Register 3–10. . . . . . . . . . . .

3.15 Interrupt Line and Pin Registers 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.16 MIN_GNT and MAX_LAT Register 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.17 PCI OHCI Control Register 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.18 Capability ID and Next Item Pointer Registers 3–12. . . . . . . . . . . . . . . . . . .

3.19 Power Management Capabilities Register 3–13. . . . . . . . . . . . . . . . . . . . . .

3.20 Power Management Control and Status Register 3–14. . . . . . . . . . . . . . . .

3.21 Power Management Extension Registers 3–14. . . . . . . . . . . . . . . . . . . . . . .

3.22 PCI Miscellaneous Configuration Register 3–15. . . . . . . . . . . . . . . . . . . . . .

3.23 Link Enhancement Control Register 3–16. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.24 Subsystem Access Register 3–17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.25 GPIO Control Register 3–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4 OHCI Registers 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 OHCI Version Register 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 GUID ROM Register 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Asynchronous Transmit Retries Register 4–6. . . . . . . . . . . . . . . . . . . . . . .

4.4 CSR Data Register 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

4.5 CSR Compare Register 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 CSR Control Register 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7 Configuration ROM Header Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 Bus Identification Register 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.9 Bus Options Register 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.10 GUID High Register 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.11 GUID Low Register 4–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.12 Configuration ROM Mapping Register 4–11. . . . . . . . . . . . . . . . . . . . . . . . . .

4.13 Posted Write Address Low Register 4–11. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.14 Posted Write Address High Register 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . .

4.15 Vendor ID Register 4–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.16 Host Controller Control Register 4–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.17 Self ID Buffer Pointer Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.18 Self ID Count Register 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.19 Isochronous Receive Channel Mask High Register 4–15. . . . . . . . . . . . . .

4.20 Isochronous Receive Channel Mask Low Register 4–16. . . . . . . . . . . . . . .

4.21 Interrupt Event Register 4–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.22 Interrupt Mask Register 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.23 Isochronous Transmit Interrupt Event Register 4–21. . . . . . . . . . . . . . . . . .

4.24 Isochronous Transmit Interrupt Mask Register 4–22. . . . . . . . . . . . . . . . . . .

4.25 Isochronous Receive Interrupt Event Register 4–22. . . . . . . . . . . . . . . . . . .

4.26 Isochronous Receive Interrupt Mask Register 4–23. . . . . . . . . . . . . . . . . . .

4.27 Fairness Control Register 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.28 Link Control Register 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.29 Node Identification Register 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.30 PHY Layer Control Register 4–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.31 Isochronous Cycle Timer Register 4–27. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.32 Asynchronous Request Filter High Register 4–28. . . . . . . . . . . . . . . . . . . . .

4.33 Asynchronous Request Filter Low Register 4–30. . . . . . . . . . . . . . . . . . . . .

4.34 Physical Request Filter High Register 4–32. . . . . . . . . . . . . . . . . . . . . . . . . .

4.35 Physical Request Filter Low Register 4–34. . . . . . . . . . . . . . . . . . . . . . . . . .

4.36 Physical Upper Bound Register (Optional Register) 4–36. . . . . . . . . . . . . .

4.37 Asynchronous Context Control Register 4–37. . . . . . . . . . . . . . . . . . . . . . . .

4.38 Asynchronous Context Command Pointer Register 4–38. . . . . . . . . . . . . .

4.39 Isochronous Transmit Context Control Register 4–39. . . . . . . . . . . . . . . . . .

4.40 Isochronous Transmit Context Command Pointer Register 4–40. . . . . . . .

4.41 Isochronous Receive Context Control Register 4–40. . . . . . . . . . . . . . . . . .

4.42 Isochronous Receive Context Command Pointer Register 4–41. . . . . . . .

4.43 Isochronous Receive Context Match Register 4–42. . . . . . . . . . . . . . . . . . .

5 GPIO Interface 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Serial EEPROM Interface 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 Electrical Characteristics 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Absolute Maximum Ratings Over Operating

Temperature Ranges 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

7.2 Recommended Operating Conditions 7–2. . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 Electrical Characteristics Over Recommended

Operating Conditions 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Switching Characteristics for PCI Interface 7–3. . . . . . . . . . . . . . . . . . . . . .

7.5 Switching Characteristics for PHY-Link Interface 7–3. . . . . . . . . . . . . . . . .

8 Mechanical Information 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Illustrations

Figure Title Page

2–1 Terminal Assignments 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 TSB12LV23 Block Diagram 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5–1 GPIO2 and GPIO3 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

List of Tables

Table Title Page

2–1 Signals Sorted by Pin Number 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–2 Power Supply 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–3 PCI System 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–4 PCI Address and Data 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–5 PCI Interface Control 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–6 IEEE1394 PHY/Link 2–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–7 Miscellaneous 2–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Bit Field Access Tag Descriptions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 PCI Configuration Register Map 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 PCI Command Register Description 3–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 PCI Status Register Description 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 Class Code and Revision ID Register Description 3–6. . . . . . . . . . . . . . . . . . . . .

3–6 Latency Timer and Class Cache Line Size Register Description 3–6. . . . . . . . .

3–7 Header Type and BIST Register Description 3–7. . . . . . . . . . . . . . . . . . . . . . . . . .

3–8 OHCI Base Address Register Description 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–9 CIS Base Address Register Description 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–10 CardBus CIS Pointer Register Description 3–9. . . . . . . . . . . . . . . . . . . . . . . . . .

3–11 PCI Subsystem Identification Register Description 3–9. . . . . . . . . . . . . . . . . . . .

3–12 Interrupt Line and Pin Registers Description 3–10. . . . . . . . . . . . . . . . . . . . . . . . .

3–13 MIN_GNT and MAX_LAT Register Description 3–11. . . . . . . . . . . . . . . . . . . . . . .

3–14 PCI OHCI Control Register Description 3–11. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–15 Capability ID and Next Item Pointer Registers Description 3–12. . . . . . . . . . . . .

3–16 Power Management Capabilities Register Description 3–13. . . . . . . . . . . . . . . .

3–17 Power Management Control and Status Register Description 3–14. . . . . . . . . .

3–18 Power Management Extension Registers Description 3–14. . . . . . . . . . . . . . . . .

v

3–19 PCI Miscellaneous Configuration Register 3–15. . . . . . . . . . . . . . . . . . . . . . . . . .

3–20 Link Enhancement Control Register Description 3–16. . . . . . . . . . . . . . . . . . . . .

3–21 Subsystem Access Register Description 3–17. . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–22 General-Purpose Input/Output Control Register Description 3–18. . . . . . . . . . .

4–1 OHCI Register Map 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 OHCI Version Register Description 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 GUID ROM Register Description 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Asynchronous Transmit Retries Register Description 4–6. . . . . . . . . . . . . . . . . .

4–5 CSR Control Register Description 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Configuration ROM Header Register Description 4–8. . . . . . . . . . . . . . . . . . . . . .

4–7 Bus Options Register Description 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–8 Configuration ROM Mapping Register Description 4–11. . . . . . . . . . . . . . . . . . . . .

4–9 Posted Write Address Low Register Description 4–11. . . . . . . . . . . . . . . . . . . . . . .

4–10 Posted Write Address High Register Description 4–12. . . . . . . . . . . . . . . . . . . . .

4–11 Host Controller Control Register Description 4–13. . . . . . . . . . . . . . . . . . . . . . . . .

4–12 Self ID Count Register Description 4–14. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–13 Isochronous Receive Channel Mask High Register Description 4–15. . . . . . . .

4–14 Isochronous Receive Channel Mask Low Register Description 4–16. . . . . . . . .

4–15 Interrupt Event Register Description 4–18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–16 Interrupt Mask Register Description 4–20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–17 Isochronous Transmit Interrupt Event Register Description 4–21. . . . . . . . . . . .

4–18 Isochronous Receive Interrupt Event Register Description 4–22. . . . . . . . . . . . .

4–19 Fairness Control Register Description 4–23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–20 Link Control Register Description 4–24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–21 Node Identification Register Description 4–25. . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–22 PHY Control Register Description 4–26. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–23 Isochronous Cycle Timer Register Description 4–27. . . . . . . . . . . . . . . . . . . . . . .

4–24 Asynchronous Request Filter High Register Description 4–28. . . . . . . . . . . . . . .

4–25 Asynchronous Request Filter Low Register Description 4–30. . . . . . . . . . . . . . .

4–26 Physical Request Filter High Register Description 4–32. . . . . . . . . . . . . . . . . . . .

4–27 Physical Request Filter Low Register Description 4–34. . . . . . . . . . . . . . . . . . . .

4–28 Asynchronous Context Control Register Description 4–37. . . . . . . . . . . . . . . . . .

4–29 Asynchronous Context Command Pointer Register Description 4–38. . . . . . . .

4–30 Isochronous Transmit Context Control Register Description 4–39. . . . . . . . . . .

4–31 Isochronous Receive Context Control Register Description 4–40. . . . . . . . . . . .

4–32 Isochronous Receive Context Match Register Description 4–42. . . . . . . . . . . . .

6–1 Registers and Bits Loadable through Serial EEPROM 6–1. . . . . . . . . . . . . . . . .

6–2 Serial EEPROM Map 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

1 Introduction

1.1 Description

The Texas Instruments TSB12LV23 is a PCI-to-1394 host controller compatible with the latest

Bus Power Management Interface

chip provides the IEEE 1394 link function, and is compatible with serial bus data rates of 100 Mbits/s, 200 Mbits/s,
and 400 Mbits/s.

As required by the
registers are memory mapped and non-prefetchable. The PCI configuration header is accessed through
configuration cycles specified by PCI, and provides Plug-and-Play (PnP) compatibility . Furthermore, the TSB12LV23
is compliant with the
supports the D0, D2, and D3 power states.

The TSB12L V23 design provides PCI bus master bursting, and is capable of transferring a cacheline of data at 132
Mbytes/s after connection to the memory controller. Since PCI latency can be large even on a PCI Revision 2.1
system, deep FIFOs are provided to buffer 1394 data.

The TSB12L V23 provides physical write posting buffers and a highly tuned physical data path for SBP-2 performance.
The TSB12L V23 also provides multiple isochronous contexts, multiple cacheline burst transfers, advanced internal
arbitration, and bus holding buffers on the PHY/Link interface, thus, making the TSB12L V23 the best-in-class 1394
OHCI solution.

An advanced CMOS process is used to achieve low power consumption while operating at PCI clock rates up to
33 MHz.

1394 Open Host Controller Interface

PCI Bus Power Management Interface Specification

,

IEEE 1394-1995

, and

1394 Open Host Controller Interface Specifications

(OHCI) and

IEEE 1394A

, per the

PC 98

Specifications, internal control

requirements. TSB12L V23

PCI Local Bus, PCI

. The

1.2 Features

The TSB12LV23 supports the following features:

• 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments

• Supports serial bus data rates of 100, 200, and 400 Mbits/s

• Provides bus-hold buffers on physical interface for low-cost single capacitor isolation

• Supports physical write posting of up to three outstanding transactions

• Serial ROM interface supports 2-wire devices

• Supports external cycle timer control for customized synchronization

• Implements PCI burst transfers and deep FIFOs to tolerate large host latency

• Provides two general-purpose I/Os

• Fabricated in advanced low-power CMOS process

• Packaged in 100 LQFP (PZ)

• Supports CLKRUN

• Drop-in replacement for the TSB12LV22

• Supports PCI and CardBus applications

1–1

1.3 Related Documents

• 1394 Open Host Controller Interface Specification

• IEEE 1394-1995 and Compatible with Proposal 1394A

• PC 98

• PCI Bus Power Management Interface Specification (Revision 1.1)

• PCI Local Bus Specification (Revision 2.2)

1.4 Ordering Information

ORDERING NUMBER NAME VOLTAGE PACKAGE

TSB12L V23 OHCI-Lynx PCI-Based IEEE 1394 Host Controller 3.3 V, 5-V Tolerant I/Os 100-pin LQFP

1–2

2 Terminal Descriptions

This section provides the terminal descriptions for the TSB12LV23.

PZ PACKAGE

(TOP VIEW)

GND
GPIO2
GPIO3

SCL

SDA

V

CCP

CLKRUN

PCI_INTA/CINT

3.3 V

CC

G_RST

GND

PCI_CLK

3.3 V

CC

PCI_GNT
PCI_REQ

V

CCP

PCI_PME/CSTSCHG

PCI_AD31
PCI_AD30

3.3 V

CC

PCI_AD29
PCI_AD28
PCI_AD27

GND

PCI_AD26

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

GND

PHY_LPS

PHY_LINKON

98

99

100

28

27

26

CC

PHY_SCLK

3.3 V

95

96

31

30

GND

94

32

PHY_LREQ

97

29

CC

PHY_CTL1

PHY_CTL0

93

33

92

34

PHY_DATA0

3.3 V

90

91

36

35

PHY_DATA1

89

37

PHY_DATA2

88

38

CCP

V

87

39

PHY_DATA3

86

40

CC

PHY_DATA6

44

82

PHY_DATA7

81

45

3.3 V

79

80

47

46

RST

CARDBUS/CYCLEOUT

CYCLEIN

ISOLATED

76

77

78

75

GND

74

PCI_AD0

73

PCI_AD1

72

PCI_AD2

71

PCI_AD3

70

3.3 V

69

PCI_AD4

68

PCI_AD5

67

PCI_AD6

66

PCI_AD7

65

PCI_C/BE0
PCI_AD8

64
63

V

62

PCI_AD9

61

PCI_AD10

60

GND

59

PCI_AD11

58

PCI_AD12

57

PCI_AD13

56

PCI_AD14

55

3.3 V

54

PCI_AD15

53

PCI_C/BE1

52

PCI_PAR

51

PCI_SERR

50

49

48

CC

CCP

CC

PHY_DATA5

GND

PHY_DATA4

83

84

85

43

42

41

GND

CC

3.3 V

PCI_AD25

PCI_AD24

PCI_C/BE3

PCI_IDSEL

PCI_AD23

PCI_AD20

PCI_AD21

PCI_AD18

PCI_AD19

PCI_AD22

Figure 2–1. Terminal Assignments

CCP

V

PCI_AD17

PCI_AD16

PCI_C/BE2

GND

PCI_IRDY

PCI_FRAME

CC

3.3 V

PCI_TRDY

PCI_STOP

PCI_DEVSEL

GND

PCI_PERR

2–1

Table 2–1. Signals Sorted by Pin Number

I/O

DESCRIPTION

NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME

1 GND 26 PCI_AD25 51 PCI_SERR 76 RST
2 GPIO2 27 PCI_AD24 52 PCI_PAR 77 CARDBUS/CYCLEOUT
3 GPIO3 28 PCI_C/BE3 53 PCI_C/BE1 78 CYCLEIN
4 SCL 29 PCI_IDSEL 54 PCI_AD15 79 ISOLATED
5 SDA 30 GND 55 3.3 V
6 V
7 CLKRUN 32 PCI_AD22 57 PCI_AD13 82 PHY_DATA6
8 PCI_INTA/CINT 33 PCI_AD21 58 PCI_AD12 83 GND

9 3.3 V
10 G_RST 35 3.3 V
11 GND 36 PCI_AD19 61 PCI_AD10 86 PHY_DA TA3
12 PCI_CLK 37 PCI_AD18 62 PCI_AD9 87 V
13 3.3 V
14 PCI_GNT 39 V
15 PCI_REQ 40 PCI_AD16 65 PCI_C/BE0 90 PHY_DATA0
16 V
17 PCI_PME/CSTSCHG 42 GND 67 PCI_AD6 92 PHY_CTL1
18 PCI_AD31 43 PCI_FRAME 68 PCI_AD5 93 PHY_CTL0
19 PCI_AD30 44 PCI_IRDY 69 PCI_AD4 94 GND
20 3.3 V
21 PCI_AD29 46 3.3 V
22 PCI_AD28 47 PCI_DEVSEL 72 PCI_AD2 97 PHY_LREQ
23 PCI_AD27 48 PCI_STOP 73 PCI_AD1 98 PHY_LINKON
24 GND 49 PCI_PERR 74 PCI_AD0 99 PHY_LPS
25 PCI_AD26 50 GND 75 GND 100 GND

CCP

CC

CC

CCP

CC

31 PCI_AD23 56 PCI_AD14 81 PHY_DATA7

34 PCI_AD20 59 PCI_AD11 84 PHY_DATA5

CC

38 PCI_AD17 63 V

CCP

41 PCI_C/BE2 66 PCI_AD7 91 3.3 V

45 PCI_TRDY 70 3.3 V

CC

60 GND 85 PHY_DATA4

64 PCI_AD8 89 PHY_DATA1

71 PCI_AD3 96 3.3 V

CC

CCP

CC

80 3.3 V

88 PHY_DATA2

95 PHY_SCLK

CC

CCP

CC

CC

The terminals are grouped in tables by functionality, such as PCI system function, power supply function, etc. The
terminal numbers are also listed for convenient reference.

Table 2–2. Power Supply

TERMINAL

NAME NO.

1, 11, 24, 30,

CC

42, 50, 60, 75,

83, 94, 100

9, 13, 20, 35,

46, 55, 70, 80,

91, 96

6, 16, 39, 63,

87

I Device ground terminals

I 3.3-V power supply terminals

I PCI signaling clamp voltage power input. PCI signals are clamped per the

PCI Local Bus Specification

.

GND

3.3 V

V

CCP

2–2

TERMINAL

I/O

DESCRIPTION

I/O

DESCRIPTION

NAME NO.

PCI_CLK 12 I

G_RST 10 I

PCI_INTA/CINT 8 O

RST 76 I

TERMINAL

NAME NO.

PCI_AD31
PCI_AD30
PCI_AD29
PCI_AD28
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
PCI_AD22
PCI_AD21
PCI_AD20
PCI_AD19
PCI_AD18
PCI_AD17
PCI_AD16
PCI_AD15
PCI_AD14
PCI_AD13
PCI_AD12
PCI_AD11
PCI_AD10
PCI_AD9
PCI_AD8
PCI_AD7
PCI_AD6
PCI_AD5
PCI_AD4
PCI_AD3
PCI_AD2
PCI_AD
PCI_AD0

PCI_C/BE0
PCI_C/BE1
PCI_C/BE2
PCI_C/BE3

PCI_PAR 52 I/O

18
19
21
22
23
25
26
27
31
32
33
34
36
37
38
40
54
56
57
58
59
61
62
64
66
67
68
69
71
72
73
74

65
53
41
28

I/O

I/O

Table 2–3. PCI System

PCI bus clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at rising edge
of PCLK.

Global power reset. This reset brings all of the TSB12LV23 to its default state, including those registers not
reset by RST

Interrupt signal. This output indicates interrupts from the TSB12LV23 to the host. This terminal signals an
interrupt based upon the CARDBUS

PCI or CardBus reset. When this bus reset is asserted, the TSB12LV23 places all output buffers in a high
impedance state and resets all internal registers except device power management context- and
vendor-specific bits initialized by host power on software. When asserted, the device is completely
nonfunctional.

. When asserted, the device is completely nonfunctional.

input terminal.

Table 2–4. PCI Address and Data

PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the PCI interface
during the address phase of a PCI cycle, AD31–AD0 contain a 32-bit address or other destination information.
During the data phase, AD31–AD0 contain data.

PCI bus commands and byte enables. The command and byte enable signals are multiplexed on the same PCI
terminals. During the address phase of a bus cycle C/BE3
phase, this 4-bit bus is used as byte enables.

PCI parity. In all PCI bus read and write cycles, the TSB12LV23 calculates even parity across the AD and C/BE
buses. As an initiator during PCI cycles, the TSB12LV23 outputs this parity indicator with a one PCLK delay. As
a target during PCI cycles, the calculated parity is compared to the initiator’s parity indicator; a miscompare can
result in a parity error assertion (PERR

).

–C/BE0 defines the bus command. During the data

2–3

TERMINAL

I/O

DESCRIPTION

I/O

DESCRIPTION

NAME NO.

PCI_DEVSEL 47 I/O

PCI_FRAME 43 I/O

PCI_GNT 14 I

PCI_IDSEL 29 I

PCI_IRDY 44 I/O

PCI_STOP 48 I/O

CLKRUN 7 I/O

PCI_PERR 49 I/O
PCI_PME/

CSTSCHG
PCI_REQ 15 O

PCI_SERR 51 O

PCI_TRDY 45 I/O

17 O

Table 2–5. PCI Interface Control

PCI device select. The TSB12LV23 asserts this signal to claim a PCI cycle as the target device. As a PCI
initiator, the TSB12LV23 monitors this signal until a target responds. If no target responds before time-out
occurs, then the TSB12LV23 terminates the cycle with an initiator abort.

PCI cycle frame. This signal is driven by the initiator of a PCI bus cycle. FRAME is asserted to indicate that a
bus transaction is beginning, and data transfers continue until while this signal is asserted. When FRAME
deasserted, the PCI bus transaction is in the final data phase.

PCI bus grant. This signal is driven by the PCI bus arbiter to grant the TSB12LV23 access to the PCI bus after
the current data transaction has completed. This signal may or may not follow a PCI bus request depending
upon the PCI bus parking algorithm.

Initialization device select. IDSEL selects the TSB12L V23 during configuration space accesses. IDSEL can be
connected to 1 of the upper 24 PCI address lines on the PCI bus.

PCI initiator ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase of the
transaction. A data phase is completed upon a rising edge of PCLK where both IRDY
until which wait states are inserted.

PCI cycle stop signal. This signal is driven by a PCI target to request the initiator to stop the current PCI bus
transaction. This signal is used for target disconnects, and is commonly asserted by target devices which do
not support burst data transfers.

Clock run. This terminal provides clock control through the CLKRUN protocol. An internal pulldown resistor is
implemented on this terminal for TSB12LV22 drop-in compatibility.

PCI parity error indicator. This signal is driven by a PCI device to indicate that calculated parity does not match
PAR when enabled through the command register.

PME or card status change. This terminal indicates wake events to the host. When in a CardBus configuration,
per the CARDBUS

PCI bus request. Asserted by the TSB12LV23 to request access to the bus as an initiator. The host arbiter
asserts the GNT

PCI system error. Output pulsed from the TSB12LV23 when enabled indicating an address parity error has
occurred. The TSB12LV23 needs not be the target of the PCI cycle to assert this signal.

PCI target ready. TRDY indicates the PCI bus target’s ability to complete the current data phase of the
transaction. A data phase is completed upon a rising edge of PCLK where both IRDY
until which wait states are inserted.

sample, the CSTSCHG output is an active high.

signal when the TSB12LV23 has been granted access to the bus.

and TRDY are asserted;

and TRDY are asserted;

is

Table 2–6. IEEE1394 PHY/Link

TERMINAL

NAME NO.

PHY_CTL1
PHY_CTL0

PHY_DATA7
PHY_DATA6
PHY_DATA5
PHY_DATA4
PHY_DATA3
PHY_DATA2
PHY_DATA1
PHY_DATA0

PHY_SCLK 95 I System clock. This input from the PHY provides a 49.152 MHz clock signal for data synchronization.
PHY_LREQ 97 O Link request. This signal is driven by the TSB12L V23 to initiate a request for the PHY to perform some service.
PHY_LINKON 98 I/O LinkOn wake indication. Used and defined by 1394A and 3.3-V signaling is required.
PHY_LPS 99 I/O Link power status. Used and defined by 1394A and 3.3-V signaling is required.

2–4

92
93

81
82
84
85
86
88
89
90

Phy-link interface control. These bidirectional signals control passage of information between the two devices.
The TSB12LV23 can only drive these terminals after the PHY has granted permission following a link request

I/O

(LREQ).

Phy-link interface data. These bidirectional signals pass data between the TSB12LV23 and the PHY device.
These terminals are driven by the TSB12LV23 on transmissions and are driven by the PHY on reception. Only

I/O

DATA1–DATA0 are valid for 100-Mbit speeds, DATA3–DATA0 are valid for 200-Mbit speeds, and
DATA7–DATA0 are valid for 400-Mbit speeds.

Table 2–7. Miscellaneous

I/O

DESCRIPTION

TERMINAL

NAME NO.

Serial data. The TSB12LV23 determines whether a two-wire serial ROM, or no serial ROM is implemented at

SDA 5 I/O

SCL 4 I/O

ISOLATED 79 I

CYCLEIN 78 I/O

CARDBUS/
CYCLEOUT

GPIO3 3 I/O General-purpose I/O [3]
GPIO2 2 I/O General-purpose I/O [2]

77 I/O

reset. If a two-wire serial ROM is detected, then this terminal provides the SDA serial data signaling. This
terminal must be wired low to indicate no serial ROM is present.

Serial clock. The TSB12LV23 determines whether a two-wire, or no serial ROM is implemented at reset. If a
two-wire serial ROM is implemented, then this terminal provides the SCL serial clock signaling.

Phy-link isolation barrier mode. This terminal should be asserted when the PHY device is electrically isolated
from the TSB12LV23. This input controls bus-hold I/Os.

The CYCLEIN terminal can provide an optional external 8 kHz clock set up as a cycle timer that can be used
for synchronization with other system devices.

This terminal is sampled when G_RST is asserted, and it selects between PCI buffers and CardBus buffers.
After reset, this terminal may also function as CYCLEOUT which provides an 8 kHz cycle timer synchronization
signal.

2–5

2–6

3 TSB12LV23 Controller Programming Model

This section describes the internal registers used to program the TSB12LV23, including both PCI configuration
registers and OHCI registers (see Section 4). All registers are detailed in the same format: a brief description for each
register, followed by the register offset and a bit table describing the reset state for each register.

A bit description table, typically included, indicates bit field names, a detailed field description, and field access tags.
Table 3–1 describes the field access tags.

Table 3–1. Bit Field Access Tag Descriptions

ACCESS TAG NAME MEANING

R Read Field may be read by software.

W Write Field may be written by software to any value.

S Set Field may be set by a write of 1. Writes of 0 have no effect.
C Clear Field may be cleared by a write of 1. Writes of 0 have no effect.
U Update Field may be autonomously updated by the TSB12LV23.

A simplified block diagram of the TSB12LV23 is provided in Figure 3–1.

3–1

PCI

Target

SM

Internal

Registers

OHCI PCI Power

Mgmt & CLKRUN

Serial

ROM

GPIOs

PCI

Host

Bus

Interface

Central
Arbiter

&

PCI

Initiator

SM

ISO Transmit

Contexts

Async Transmit

Contexts

Physical DMA

& Response

Resp

Timeout

PHY

Register

Access

& Status

Monitor

Request

Filters

General

Request Receive

Transmit

FIFO

Receive

Acknowledge

Cycle Start

Generator &

Cycle Monitor

Synthesized

Bus Reset

MISC

Interface

Link

Transmit

CRC

PHY /

Link

Interface

Link

Receive

Async Response

Receive

ISO Receive

Contexts

Receive

FIFO

Figure 3–1. TSB12LV23 Block Diagram

3–2

3.1 PCI/CardBus Configuration Registers

The TSB12LV23 is a single-function PCI device that can be configured as either a PCI or CardBus device. The
configuration header is compliant with the
the PCI configuration header that includes both the predefined portion of the configuration space and the user
definable registers. Most of the registers in this configuration have not changed from the TSB12LV22 design.

Table 3–2. PCI Configuration Register Map

Device ID Vendor ID 00h

Status Command 04h

BIST Header type Latency timer Cache line size 0Ch

Subsystem ID Subsystem vendor ID 2Ch

Maximum latency Minimum grant Interrupt pin Interrupt line 3Ch

Power management capabilities Next item pointer Capability ID 44h

PM data PMCSR_BSE Power management CSR 48h

PCI miscellaneous configuration register F0h

Subsystem ID alias Subsystem vendor ID alias F8h

GPIO3 GPIO2 Reserved FCh

PCI Local Bus Specification

REGISTER NAME OFFSET

Class code Revision ID 08h

OHCI registers base address 10h

TI extension registers base address 14h

CIS base address 18h

Reserved 1Ch
Reserved 20h
Reserved 24h

CardBus CIS pointer 28h

Reserved 30h

Reserved Capabilities pointer 34h

Reserved 38h

PCI OHCI control register 40h

Reserved 4C–ECh

Link_Enhancements register F4h

as a standard header. Table 3–2 illustrates

3.2 Vendor ID Register

The vendor ID register contains a value allocated by the PCI SIG and identifies the manufacturer of the PCI device.
The vendor ID assigned to Texas Instruments is 104Ch.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Vendor ID
Type R R R R R R R R R R R R R R R R
Default 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0

Register: Vendor ID
Type: Read-only
Offset: 00h
Default: 104Ch

3–3

3.3 Device ID Register

The device ID register contains a value assigned to the TSB12L V23 by Texas Instruments. The device identification
for the TSB12LV23 is 8019.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Device ID
Type R R R R R R R R R R R R R R R R
Default 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1

Register: Device ID
Type: Read-only
Offset: 02h
Default: 8019h

3.4 PCI Command Register

The command register provides control over the TSB12L V23 interface to the PCI bus. All bit functions adhere to the
definitions in the

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PCI command
Type R R R R R R R R/W R R/W R R/W R R/W R/W R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

PCI Local Bus Specification

, as seen in the following bit descriptions.

Register: PCI command
Type: Read/Write
Offset: 04h
Default: 0000h

Table 3–3. PCI Command Register Description

BIT FIELD NAME TYPE DESCRIPTION

15–10 RSVD R Reserved. Bits 15–10 return 0s when read.

9 FBB_ENB R Fast back-to-back enable. The TSB12LV23 does not generate fast back-to-back transactions, thus

8 SERR_ENB R/W SERR enable. When this bit is set, the TSB12LV23 SERR driver is enabled. SERR can be asserted

7 STEP_ENB R Address/data stepping control. The TSB12LV23 does not support address/data stepping, thus this bit

6 PERR_ENB R/W Parity error enable. When this bit is set, the TSB12LV23 is enabled to drive PERR response to parity

5 VGA_ENB R VGA palette snoop enable. The TSB12L V23 does not feature VGA palette snooping. This bit returns 0

4 MWI_ENB R/W Memory write and invalidate enable. When this bit is set, the TSB12LV23 is enabled to generate MWI

3 SPECIAL R Special cycle enable. The TSB12L V23 function does not respond to special cycle transactions. This bit

2 MASTER_ENB R/W Bus master enable. When this bit is set, the TSB12LV23 is enabled to initiate cycles on the PCI bus.

1 MEMORY_ENB R/W Memory response enable. Setting this bit enables the TSB12L V23 to respond to memory cycles on the

0 IO_ENB R I/O space enable. The TSB12L V23 does not implement any I/O mapped functionality; thus, this bit re-

this bit returns 0 when read.

after detecting an address parity error on the PCI bus.

is hardwired to 0.

errors through the PERR

when read.

PCI bus commands. If this bit is reset, then the TSB12LV23 generates memory write commands
instead.

returns 0 when read.

PCI bus. This bit must be set to access OHCI registers.

turns 0 when read.

signal.

3–4

3.5 PCI Status Register

The status register provides status over the TSB12LV23 interface to the PCI bus. All bit functions adhere to the
definitions in the

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PCI status
Type RCU RCU RCU RCU RCU R R RCU R R R R R R R R
Default 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0

Register: PCI status
Type: Read/Clear/Update
Offset: 06h
Default: 0210h

BIT FIELD NAME TYPE DESCRIPTION

15 PAR_ERR RCU Detected parity error. This bit is set when a parity error is detected, either address or data parity errors.
14 SYS_ERR RCU Signaled system error. This bit is set when SERR is enabled and the TSB12LV23 has signaled a

13 MABORT RCU Received master abort. This bit is set when a cycle initiated by the TSB12LV23 on the PCI bus has been

12 TABORT_REC RCU Received target abort. This bit is set when a cycle initiated by the TSB12LV23 on the PCI bus was

11 TABORT_SIG RCU Signaled target abort. This bit is set by the TSB12LV23 when it terminates a transaction on the PCI bus

10–9 PCI_SPEED R DEVSEL timing. Bits 10–9 encode the timing of DEVSEL and are hardwired to 01b indicating that the

8 DATAPAR RCU Data parity error detected. This bit is set when the following conditions have been met:

7 FBB_CAP R Fast back-to-back capable. The TSB12L V23 cannot accept fast back-to-back transactions; thus, this

6 UDF R User definable features (UDF) supported. The TSB12L V23 does not support the UDF; thus, this bit is

5 66MHZ R 66 MHz capable. The TSB12L V23 operates at a maximum PCLK frequency of 33 MHz; therefore, this

4 CAPLIST R Capabilities list. This bit returns 1 when read, indicating that capabilities additional to standard PCI are

3–0 RSVD R Reserved. Bits 3–0 return 0s when read.

PCI Local Bus Specification

Table 3–4. PCI Status Register Description

system error to the host.

terminated by a master abort.

terminated by a target abort.

with a target abort.

TSB12L V23 asserts this signal at a medium speed on nonconfiguration cycle accesses.

a. PERR
b. The TSB12LV23 was the bus master during the data parity error
c. The parity error response bit is set in the command register (see Section 3.4)

bit is hardwired to 0.

hardwired to 0.

bit is hardwired to 0.

implemented. The linked list of PCI power management capabilities is implemented in this function.

was asserted by any PCI device including the TSB12LV23

, as seen in the following bit descriptions.

3–5

3.6 Class Code and Revision ID Register

The class code and revision ID register categorizes the TSB12L V23 as a serial bus controller (0Ch), controlling an
IEEE1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the
lower byte.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name Class code and revision ID
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Class code and revision ID
Type R R R R R R R R R R R R R R R R
Default 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0

Register: Class code and revision ID
Type: Read-only
Offset: 08h
Default: 0C00 1000h

Table 3–5. Class Code and Revision ID Register Description

BIT FIELD NAME TYPE DESCRIPTION

31–24 BASECLASS R Base class. This field returns 0Ch when read, which broadly classifies the function as a serial bus

23–16 SUBCLASS R Subclass. This field returns 00h when read, which specifically classifies the function as controlling an

15–8 PGMIF R Programming interface. This field returns 10h when read, indicating that the programming model is

7–0 CHIPREV R Silicon revision. This field returns 00h when read, indicating the silicon revision of the TSB12LV23.

controller.

IEEE1394 serial bus.

compliant with the

1394 Open Host Controller Interface Specification

.

3.7 Latency Timer and Class Cache Line Size Register

The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size
and the latency timer associated with the TSB12LV23.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Latency timer and class cache line size
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Latency timer and class cache line size
Type: Read/Write
Offset: 0Ch
Default: 0000h

Table 3–6. Latency T imer and Class Cache Line Size Register Description

BIT FIELD NAME TYPE DESCRIPTION

15–8 LATENCY_TIMER R/W PCI latency timer. The value in this register specifies the latency timer for the TSB12LV23, in units of

7–0 CACHELINE_SZ R/W Cache line size. This value is used by the TSB12L V23 during memory write and invalidate, memory

PCI clock cycles. When the TSB12LV23 is a PCI bus initiator and asserts FRAME
begins counting from zero. If the latency timer expires before the TSB12LV23 transaction has
terminated, then the TSB12LV23 terminates the transaction when its GNT

read line, and memory read multiple transactions.

, the latency timer

is deasserted.

3–6

3.8 Header Type and BIST Register

The header type and BIST register indicates the TSB12LV23 PCI header type, and indicates no built-in self test.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Header type and BIST
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: Header type and BIST
Type: Read-only
Offset: 0Eh
Default: 0000h

Table 3–7. Header Type and BIST Register Description

BIT FIELD NAME TYPE DESCRIPTION

15–8 BIST R Built-in self test. The TSB12L V23 does not include a built-in self test; thus, this field returns 00h when

7–0 HEADER_TYPE R PCI header type. The TSB12LV23 includes the standard PCI header , and this is communicated by re-

read.

turning 00h when this field is read.

3.9 OHCI Base Address Register

The OHCI base address register is programmed with a base address referencing the memory-mapped OHCI control.
When BIOS writes all 1s to this register, the value read back is FFFF F800h, indicating that at least 2K bytes of memory
address space are required for the OHCI registers.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name OHCI base address
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name OHCI address
Type R/W R/W R/W R/W R/W R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: OHCI base address
Type: Read/Write
Offset: 10h
Default: 0000 0000h

Table 3–8. OHCI Base Address Register Description

BIT FIELD NAME TYPE DESCRIPTION

31–1 1 OHCIREG_PTR R/W OHCI register pointer. Specifies the upper 21 bits of the 32-bit OHCI base address register.

10–4 OHCI_SZ R OHCI register size. This field returns 0s when read, indicating that the OHCI registers require a

2-Kbyte region of memory.

3 OHCI_PF R OHCI register prefetch. This bit returns 0 when read, indicating that the OHCI registers are

nonprefetchable.

2–1 OHCI_MEMTYPE R OHCI memory type. This field returns 0s when read, indicating that the OHCI base address register is

32 bits wide and mapping can be done anywhere in the 32-bit memory space.

0 OHCI_MEM R OHCI memory indicator. This bit returns 0 when read, indicating that the OHCI registers are mapped

into system memory space.

3–7

3.10 TI Extension Base Address Register

The TI extension base address register is programmed with a base address referencing the memory-mapped TI
extension registers. Refer to the

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name TI extension base address
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name TI extension base address
Type R/W R/W R/W R/W R/W R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

OHCI base address register

(see Section 3.9) for bit field details.

Register: TI extension base address
Type: Read/Write
Offset: 14h
Default: 0000 0000h

3.11 CIS Base Address Register

If CARDBUS is sampled high on a PCI reset, then this 32-bit register returns 0s when read. If CARDBUS is sampled
low, then this register is to be programmed with a base address referencing the memory mapped CIS. This register
must be programmed with a nonzero value before the CIS may be accessed.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CIS base address
Type R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CIS base address
Type R/W R/W R/W R/W R/W R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: CIS base address
Type: Read/Write
Offset: 18h
Default: 0000 0000h

Table 3–9. CIS Base Address Register Description

BIT FIELD NAME TYPE DESCRIPTION

31–1 1 CIS_BASE R/W CIS base address. Specifies the upper 21 bits of the 32-bit CIS base address. If the CARDBUS input is

10–4 CIS_SZ R CIS address space size. This field returns 0s when read, indicating that the CIS space requires a

3 CIS_PF R CIS prefetch. This bit returns 0 when read, indicating that the CIS is nonprefetchable. Furthermore, the

2–1 CIS_MEMTYPE R CIS memory type. This field returns 0s when read, indicating that the CIS base address register is

0 CIS_MEM R CIS memory indicator. This bit returns 0 when read, indicating that the CIS is mapped into system

3–8

sampled high on a PCI reset, then this field is read-only , returning 0s when read.

2-Kbyte region of memory.

CIS is a byte-accessible address space, and double-word or 16-bit word access yields indeterminate
results.

32 bits wide and mapping can be done anywhere in the 32-bit memory space.

memory space.

3.12 CardBus CIS Pointer Register

The CARDBUS input to the TSB12LV23 is sampled at PCI reset to determine the TSB12LV23 application. If
CARDBUS
this register is the CardBus card information structure pointer.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name CardBus CIS pointer
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name CardBus CIS pointer
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 x 0

BIT FIELD NAME TYPE DESCRIPTION

31–28 ROM_IMAGE R Since the CIS is not implemented as a ROM image, this field returns 0s when read.

27–3 CIS_OFFSET R This field indicates the offset into the CIS address space where the CIS begins, and bits 7–3 are loaded

2–0 CIS_INDICAT OR R This field indicates the address space where the CIS resides and returns 010b if CARDBUS is

is sampled high, then this register is read-only returning 0s when read. If CARDBUS is sampled low , then

Register: CardBus CIS pointer
Type: Read-only
Offset: 28h
Default: 0000 000xh

Table 3–10. CardBus CIS Pointer Register Description

from the serial ROM field CIS_Offset (7–3). This implementation allows the TSB12LV23 to produce
serial ROM addresses equal to the lower PCI address byte to acquire data from the serial ROM.

sampled asserted during a PCI reset. If CARDBUS
returns 000b when read. Thus, bit 1 is implemented as the logical inverse of the CARDBUS

is sampled high during a PCI reset, then this field

input.

3.13 PCI Subsystem Identification Register

The PCI subsystem identification register is used for system and option card identification purposes. This register
can be initialized from the serial EEPROM or programmed via the subsystem ID and subsystem vendor ID alias
registers at offset 0XFC.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PCI subsystem identification
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PCI subsystem identification
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: PCI subsystem identification
Type: Read/Update
Offset: 2Ch
Default: 0000 0000h

Table 3–11. PCI Subsystem Identification Register Description

BIT FIELD NAME TYPE DESCRIPTION

31–16 OHCI_SSID RU Subsystem device ID. This field indicates the subsystem device ID.

15–0 OHCI_SSVID RU Subsystem vendor ID. This field indicates the subsystem vendor ID.

3–9

3.14 PCI Power Management Capabilities Pointer Register

The PCI power management capabilities pointer register provides a pointer into the PCI configuration header where
the PCI power management register block resides. The TSB12LV23 configuration header double-words at offsets
44h and 48h provide the power management registers. This register is read-only and returns 44h when read.

Bit 7 6 5 4 3 2 1 0
Name PCI power management capabilities pointer
Type R R R R R R R R
Default 0 1 0 0 0 1 0 0

Register: PCI power management capabilities pointer
Type: Read-only
Offset: 34h
Default: 44h

3.15 Interrupt Line and Pin Registers

The interrupt line and pin register is used to communicate interrupt line routing information.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Interrupt line and pin
Type R R R R R R R R R/W R/W R/W R/W R/W R/W R/W R/W
Default 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0

Register: Interrupt line and pin
Type: Read/Write
Offset: 3Ch
Default: 0100h

Table 3–12. Interrupt Line and Pin Registers Description

BIT FIELD NAME TYPE DESCRIPTION

15–8 INTR_PIN R Interrupt pin register. This register returns 01h when read, indicating that the TSB12LV23 PCI function

7–0 INTR_LINE R/W Interrupt line register. This register is programmed by the system and indicates to software to which

signals interrupts on the INTA

interrupt line the TSB12LV23 INTA

pin.

is connected.

3–10

3.16 MIN_GNT and MAX_LAT Register

The MIN_GNT and MAX_LA T register is used to communicate to the system the desired setting of the latency timer
register (see Section 3.7). If a serial ROM is detected, then the contents of this register are loaded through the serial
ROM interface after a PCI reset. If no serial ROM is detected, then this register returns a default value that
corresponds to the MIN_GNT = 2, MAX_LAT = 4.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name MIN_GNT and MAX_LAT
Type RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU RU
Default 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0

Register: MIN_GNT and MAX_LAT
Type: Read/Update
Offset: 3Eh
Default: 0202h

Table 3–13. MIN_GNT and MAX_LAT Register Description

BIT FIELD NAME TYPE DESCRIPTION

15–8 MAX_LAT RU Maximum latency. The contents of this register may be used by host BIOS to assign an arbitration

7–0 MIN_GNT RU Minimum grant. The contents of this register may be used by host BIOS to assign a latency timer register

priority-level to the TSB12LV23. The default for this register indicates that the TSB12LV23 may need to
access the PCI bus as often as every 0.25 µs; thus, an extremely high priority level is requested. The
contents of this field may also be loaded through the serial ROM.

value to the TSB12LV23. The default for this register indicates that the TSB12LV23 may need to sustain
burst transfers for nearly 64 µs; thus, requesting a large value be programmed in the TSB12LV23 latency
timer register (see Section 3.7).

3.17 PCI OHCI Control Register

The PCI OHCI control register is defined by the
bit for big endian PCI support.

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Name PCI OHCI control
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name PCI OHCI control
Type R R R R R R R R R R R R R R R R/W
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

Register: PCI OHCI control
Type: Read/Write
Offset: 40h
Default: 0000 0000h

Table 3–14. PCI OHCI Control Register Description

BIT FIELD NAME TYPE DESCRIPTION

31–1 RSVD R Reserved. Bits 31–1 return 0s when read.

0 GLOBAL_SWAP R/W When this bit is set, all quadlets read from and written to the PCI interface are byte swapped (big

endian).

1394 Open Host Controller Interface Specification

and provides a

3–11

3.18 Capability ID and Next Item Pointer Registers

The capability ID and next item pointer register identifies the linked list capability item and provides a pointer to the
next capability item.

Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Name Capability ID and next item pointer
Type R R R R R R R R R R R R R R R R
Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1

Register: Capability ID and next item pointer
Type: Read-only
Offset: 44h
Default: 0001h

Table 3–15. Capability ID and Next Item Pointer Registers Description

BIT FIELD NAME TYPE DESCRIPTION

15–8 NEXT_ITEM R Next item pointer. The TSB12LV23 supports only one additional capability that is communicated to

7–0 CAPABILITY_ID R Capability identification. This field returns 01h when read, which is the unique ID assigned by the PCI

the system through the extended capabilities list; thus, this field returns 00h when read.

SIG for PCI power management capability.

3–12