Texas Instruments TSB12LV22PZ Datasheet
TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Designed to 1394 Open Host Controller
Interface (OHCI) Specification
D
IEEE 1394-1995 Compliant and Compatible
with Proposal 1394A
D
Compliant to Latest PCI Specification,
PCI 2.2
D
PCI Power Management Compliant
D
3.3-V Core Logic with Universal PCI
Interface Compatible with 3.3-V and 5-V PCI
Signaling Environments
D
Supports Serial Bus Data Rates of 100, 200,
and 400 Mbits/s
D
Provides Bus-Hold Buffers on Physical I/F
for Low-Cost Single Capacitor Isolation
D
Supports Physical Write Posting of Up to
Three Outstanding Transactions
D
Serial ROM Interface Supports 2-Wire
Devices
D
Supports External Cycle Timer Control for
Customized Synchronization
D
Implements PCI Burst Transfers and Deep
FIFOs to Tolerate Large Host Latency
D
Provides up to Four General Purpose I/Os
D
Fabricated in Advanced Low-Power CMOS
Process
D
Packaged in 100 LQFP (PZP)
description
The T exas Instruments OHCI-Lynx is a PCI-to-1394 host controller compatible with the latest PCI, IEEE1394,
and 1394 OHCI 1.00 specifications. The chip provides the IEEE1394 link function, and is compatible with serial
bus data rates of 100 Mbits/s, 200 Mbits/s, and 400 Mbits/s.
As required by the 1394 OHCI Specification, internal control registers are memory mapped and
non-prefetchable. The PCI configuration header is accessed through configuration cycles specified by PCI, and
provides Plug-and-Play (PnP) compatibility. Furthermore, the OHCI-Lynx is compliant with the PCI Power
Management Specification, per the PC ′98 requirements.
The OHCI-Lynx design provides PCI bus master bursting, and is capable of transferring a cacheline of data at
132 Mbytes/s after connection to the memory controller. Since PCI latency can be large even on a PCI Revision
2.1 system, deep FIFOs are provided to buffer 1394 data.
Physical write posting buffers are provided to enhance serial bus performance, and multiple isochronous
channels are provided for simultaneous operation of real-time applications. The OHCI-Lynx also provides bus
holding buffers on the phy interface for simple and cost effective single capacitor isolation.
An advanced CMOS process is used to achieve low power consumption while operating at PCI clock rates up
to 33 MHz.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
OHCI-Lynx is a trademark of Texas Instruments Incorporated.
TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OHCI-Lynx block diagram
A simplified block diagram of the OHCI-Lynx is provided in Figure 1.
ISO Cycle
Timer
ISO Transmit
Contexts
Async Transmit
Context
Physical DMA
and Response
General Request
Receive
Async Response
Recieve
ISO Recieve
Contexts
PCI Pwr
Mgmt
Serial
EEPROM
PCI
Target
SM
Internal
Registers
PCI
Initiator
SM
and
Central
Arbiter
Misc
Control
PCI_INTA
PCI_PRST
PCI_PCLK
PCI_PME
PCI_AD[31:0]
PCI_C/BE
[3:0]
PCI_FRAME
PCI_IRDY
PCI_TRDY
PCI_DEVSEL
PCI_STOP
PCI_IDSEL
PCI_PAR
PCI_PERR
PCI_SERR
PCI_REQ
PCI_GNT
PCI Host Bus InterfaceMisc I/O
PHY_CTL[1:0]
PHY_DATA[7:0]
PHY_CLK50
PHY_LREQ
ISOLATED
Transmit
FIFO
Static
RAM
(Resp
Timeout)
Receive
Ack
PHY
Comm
Cycle
Monitor
Receive
FIFO
Static
RAM
(Request
Filters)
Cycle
Start
Gen
Link
Transmit
CRC
Link
Receive
Synth
Bus
Reset
PHY/Link Interface
BMC/LINKON/GPIO0
LPS/GPIO1
GPIO2–3
SCL
SDA
Figure 1. OHCI-Lynx Block Diagram
TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
terminal assignments
This section provides the terminal assignments for the OHCI-Lynx.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
GND
PHY_SCLK
GND
PHY_DATA1
PHY_DATA2
PHY_DATA5
GND
PHY_DATA6
PHY_DATA7
PCI_AD25
PCI_AD24
PCI_C/BE3
PCI_IDSEL
GND
PCI_AD18
PCI_AD17
PCI_AD16
GND
GND
PZP PACKAGE
(TOP VIEW)
PHY_DATA0
PCI_AD21
PHY_LREQ
PHY_DATA3
PHY_DATA4
CC
PCI_AD19
GPIO2
GPIO3
SCL
SDA
V
CCS
RSVD
PCI_INTA
V
CC
PCI_RST
GND
PCI_CLK
PCI_GNT
V
CCP
PCI_AD30
V
CC
PCI_AD29
PCI_AD28
PCI_AD27
GND
PCI_AD26
V
CC
PCI_REQ
PCI_PME
PCI_AD31
GND
GND
PCI_AD1
PCI_AD2
V
CC
PCI_AD5
PCI_AD7
PCI_AD8
PCI_AD9
GND
PCI_AD12
PCI_AD14
PCI_AD15
PCI_C/BE1
PCI_AD0
PCI_AD3
PCI_AD4
PCI_AD6
PCI_C/BE0
V
CCP
PCI_AD10
PCI_AD11
PCI_AD13
V
CC
PCI_PAR
PCI_SERR
TEST_EN
CC
CYCLEOUT
CYCLEIN
ISOLATED
V
CC
V
CCS
V
CC
V
PHY_CTL1
PHY_CTL0
CC
V
BMC/LINKON/GPIO0
LPS/GPIO1
PCI_AD22
PCI_AD23
PCI_AD20
V
CCP
V
PCI_C/BE2
PCI_FRAME
PCI_IRDY
PCI_TRDY
PCI_DEVSEL
PCI_STOP
PCI_PERR
Figure 2. Terminal Assignments
TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 1. Signals Sorted by Pin Number
NO TERMINAL NAME NO TERMINAL NAME NO TERMINAL NAME NO TERMINAL NAME
1 GND 26 PCI_AD25 51 PCI_SERR 76 TEST_EN
2 GPIO2 27 PCI_AD24 52 PCI_PAR 77 CYCLEOUT
3 GPIO3 28 PCI_C/BE3 53 PCI_C/BE1 78 CYCLEIN
4 SCL 29 PCI_IDSEL 54 PCI_AD15 79 ISOLATED
5 SDA 30 GND 55 V
CC
80 V
CC
6 V
CCS
31 PCI_AD23 56 PCI_AD14 81 PHY_DATA7
7 RSVD 32 PCI_AD22 57 PCI_AD13 82 PHY_DATA6
8 PCI_INT A 33 PCI_AD21 58 PCI_AD12 83 GND
9 V
CC
34 PCI_AD20 59 PCI_AD11 84 PHY_DATA5
10 PCI_RST 35 V
CC
60 GND 85 PHY_DATA4
11 GND 36 PCI_AD19 61 PCI_AD10 86 PHY_DATA3
12 PCI_CLK 37 PCI_AD18 62 PCI_AD9 87 V
CCS
13 V
CC
38 PCI_AD17 63 V
CCP
88 PHY_DATA2
14 PCI_GNT 39 V
CCP
64 PCI_AD8 89 PHY_DATA1
15 PCI_REQ 40 PCI_AD16 65 PCI_C/BE0 90 PHY_DATA0
16 V
CCP
41 PCI_C/BE2 66 PCI_AD7 91 V
CC
17 PCI_PME 42 GND 67 PCI_AD6 92 PHY_CTL1
18 PCI_AD31 43 PCI_FRAME 68 PCI_AD5 93 PHY_CTL0
19 PCI_AD30 44 PCI_IRDY 69 PCI_AD4 94 GND
20 V
CC
45 PCI_TRDY 70 V
CC
95 PHY_SCLK
21 PCI_AD29 46 V
CC
71 PCI_AD3 96 V
CC
22 PCI_AD28 47 PCI_DEVSEL 72 PCI_AD2 97 PHY_LREQ
23 PCI_AD27 48 PCI_STOP 73 PCI_AD1 98 BMC/LINKON/GPIO0
24 GND 49 PCI_PERR 74 PCI_AD0 99 LPS/GPIO1
25 PCI_AD26 50 GND 75 GND 100 GND
TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
This section describes the OHCI-Lynx terminal functions. The terminals are grouped in tables by functionality for
convenient reference.
Terminal Functions
TERMINAL
NAME NO.
I/O
DESCRIPTION
Power Supply
GND 1,11,24,30,42,50,
60,75,83,94,100
I Device ground terminals
V
CC
9,13,20,35,46,55,
70,80,91,96
I 3.3-V power supply terminals
V
CCS
6,87 I Clamp rail power input.; Provides 5 V tolerance for non PCI I/Os
V
CCP
16,39,63 I PCI signaling clamp rail power input. PCI signals clampled per PCI specification
PCI System
PCI_CLK 12 I/O PCI Bus Clock. Provides timing for all transactions on the PCI bus. All PCI signals are sampled at
rising edge of PCLK.
PCI_RST 10 I/O PCI Reset. When the PCI bus reset is asserted the OHIC1-L ynx 3-states all output buffers and resets
internal registers. When asserted, the device is completely nonfunctional. After deasserting RST
,
the OHCI-Lynx is in its default state.
PCI_INTA 8 I/O PCI Interrupt A. The OHCI-Lynx drives this shared interrupt signal low when there is a pending
internal interrupt event that has occurred.
PCI Address and Data
PCI_AD31 –
PCI_AD0
18,19,21–23,
25–27,31–34,
36–38,40,54,
56–59,61,62,64,
66–69,71–74
I/O PCI Address/Data Bus. These signals make up the multiplexed PCI address and data bus on the
PCI interface during the address phase of a PCI cycle, AD31:0 contains a 32-bit address or other
destination information. During the data phase AD31:0 contains data.
PCI_C/BE0
PCI_C/BE1
PCI_C/BE2
PCI_C/BE3
65,
53,
41,
28
I/O PCI Bus Commands and Byte Enables. The command and byte enable signals are multiplexed on
the same PCI terminals. During the address phase of a bus cycle C/BE3:0
defines the bus command.
During the data phase, this four-bit bus is used as byte enables.
PCI_PAR 52 I/O PCI Parity. In all PCI bus read and write cycles, the OHCI-L ynx calculates even parity across the AD
and C/BE
buses. As an initiator during PCI cycles, the OHCI-Lynx outputs this parity indicator with
a one PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiator’
parity indicator; a miscompare can result in a parity error assertion (PERR
).
PCI Interface Control
PCI_DEVSEL 47 I/O PCI Device Select. The OHCI-L ynx will assert this signal to claim a PCI cycle as the target device.
As a PCI initiator, the OHCI-L ynx monitors this signal until a target responds. If no target responds
before time-out occurs, then the OHCI-Lynx will terminate the cycle with an initiator abort.
PCI_FRAME 43 I/O PCI Cycle Frame. This signal is driven by the initiator of a PCI bus cycle. FRAME is asserted to
indicate that a bus transaction is beginning, and data transfers continue until while this signal is
asserted. When FRAME
is deasserted, the PCI bus transaction is in the final data phase.
PCI_GNT 14 I PCI Bus Grant. This signal is driven by the PCI bus arbiter to grant the OHCI-Lynx access to the PCI
bus after the current data transaction has completed. This signal may or may not follow a PCI bus
request depending upon the PCI bus parking algorithm.
PCI_IDSEL 29 I Initialization Device Select. IDSEL selects the OHCI-Lynx during configuration space accesses.
IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus.
PCI_IRDY 44 I/O PCI Initiator Ready. IRDY indicates the PCI bus initiator’s ability to complete the current data phase
of the transaction. A data phase is completed upon a rising edge of PCLK where both IRDY
and
TRDY
are asserted; until which wait states are inserted.
PCI_STOP 48 I/O PCI Cycle Stop Signal. This signal is driven by a PCI target to request the initiator to stop the current
PCI bus transaction. This signal is used for target disconnects, and is commonly asserted by target
devices which do not support burst data transfers.
TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions (Continued)
TERMINAL
NAME NO.
I/O
DESCRIPTION
PCI Interface Control (Continued)
PCI_PERR 49 I/O PCI Parity Error Indicator. This signal is driven by a PCI device to indicate that calculated parity does not match
PAR when enabled through the command register.
PCI_PME 17
PCI_REQ 15 O PCI Bus Request. Asserted by the OHCI-Lynx to request access to the bus as an initiator. The host arbiter
will assert the GNT# signal when the OHCI-Lynx has been granted access to the bus.
PCI_SERR 51 O PCI System Error. Output pulsed from the OHCI-Lynx when enabled indicating an address parity error has
occurred. The OHCI-Lynx needs not be the target of the PCI cycle to assert this signal.
PCI_TRDY 45 I/O PCI Target Ready. TRDY indicates the PCI bus target’s ability to complete the current data phase of the
transaction. A data phase is completed upon a rising edge of PCLK where both IRDY
and TRDY are asserted;
until which wait states are inserted.
IEEE1394 PHY/Link
PHY_CTL1
PHY_CTL0
9293I/O Phy-link Interface Control. These bidirectional signals control passage of information between the two
devices. The OHCI-Lynx can only drive these terminals after the PHY has granted permission following a link
request (LREQ).
PHY_DATA7 –
PHY_DATA0
81,82,
84–86,
88–90
I/O Phy-link Interface Data. These bidirectional signals pass data between the OHCI-L ynx and the PHY device.
These terminals are driven by the OHCI-Lynx on transmissions, and driven by the PHY on reception. Only
DAT A1:0 are valid for 100Mbit speeds, DA T A4:0 are valid for 200Mbit speeds, and DA T A7:0 are valid for 400
Mbit speeds.
PHY_SCLK 95 I System Clock. This input from the PHY provides a 49.152 MHz clock signal for data synchronization.
PHY_LREQ 97 O Link Request. This signal is driven by the OHCI-Lynx to initiate a request for the PHY to perform some service.
Miscellaneous
SDA 5 I/O Serial Data. The OHCI-Lynx determines whether a two-wire serial ROM, or no serial ROM is implemented
at reset. If a two-wire serial ROM is detected, then this terminal provides the SDA serial data signaling. This
terminal must be wired low to indicate no serial ROM is present.
SCL 4 I/O Serial Clock. The OHCI-Lynx determines whether a two-wire, or no serial ROM is implemented at reset. If a
two-wire serial ROM is implemented, then this terminal provides the SCL serial clock signaling.
ISOLATED 79 I Phy–link Isolation Barrier Mode. This terminal should be asserted when the PHY device is electrically isolated
from the OHCI-Lynx. This input controls bus-hold I/Os.
CYCLEIN 78 I Cycle Input. This optional external 8KHz clock input may be used as the cycle timer clock, and can be used
for synchronization with other system devices.
CYCLEOUT 77 O Cycle Output. This optional 8 kHz output may be used for cycle timer synchronization.
GPIO3 3 I/O General Purpose I/O [3]
GPIO2 2 I/O General Purpose I/O [2]
LPS/GPIO1 99 I/O General Purpose I/O [1]/ Link Power Status Output. Link Power status indicates that link is powered and full
functional.
BMC/LINKON/
GPIO0
98 I/O General Purpose I/O [0]/Bus Manager Contender Output/LINKON#.
LINKON. Receipt of a link-on packet. Once asserted LINKON shall remain asserted until LPS is asserted or
the PHY register L bit is set to one
TEST_EN 76 I
OHCI-Lynx controller programming model
This section describes the internal registers used to program the OHCI-Lynx, including both PCI configuration
registers and Open HCI registers. All registers are detailed in the same format. A brief description is provided
for each register, followed by the register offset and a bit–table describing the reset state for each register.
TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
OHCI-Lynx controller programming model (continued)
A bit description table is typically included that indicates bit field names, a detailed field description, and field
access tags. The field access tags are described in Table 2.
Table 2. Bit Field Access Tag Descriptions
ACCESS TAG NAME MEANING
r read Field may be read by software.
w write Field may be written by software to any value.
s set Field may be set by a write of one. Writes of zero have no effect.
c clear Field may be cleared by a write of one. Writes of zero have no effect.
u update Field may be autonomously updated by the OHCI-Lynx.
PCI configuration registers
The OHCI-Lynx configuration header is compliant with the PCI Specification as a standard header.Table 3
illustrates the PCI configuration header which includes both the predefined portion of the configuration space
and the user definable registers. The registers that are labeled Reserved are read only returning zero when
read, and are not applicable to the OHCI-Lynx design, or have been reserved by the PCI specification for future
use.
Table 3. PCI Configuration Register Map
REGISTER NAME OFFSET
Device ID Vendor ID 00h
Status Command 04h
Class Code Revision ID 08h
BIST Header Type Latency Timer Cache Line Size 0Ch
Open HCI Registers Base Address 10h
TI Extension Registers Base Address 14h
Reserved 18h
Reserved 1Ch
Reserved 20h
Reserved 24h
Reserved 28h
Subsystem ID Subsystem Vendor ID 2Ch
Reserved 30h
Reserved Capabilites Pointer 34h
Reserved 38h
Max Latency Min Grant Interrupt Pin Interrupt Line 3Ch
PCI OHCI Control Register 40h
Power Management Capabilities Next Item Pointer Capability ID 44h
PM Data PMCSR_BSE Power Management CSR 48h
Reserved 4C–F2h
Link_Enhancements Register F4h
Subsytem ID Alias Subsystem Vendor ID Alias F8h
GPIO3 GPIO2 GPIO1 GPIO0 FCh
TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
vendor ID register
This 16-bit read only register contains a value allocated by the PCI SIG and identifies the manufacturer of the
PCI device. The Vendor ID assigned to Texas Instruments is 104Ch. All bits in this register are read only.
PCI register 00h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 0 0 1 0 0 0 0 0 1 0 0 1 1 0 0
device ID register
This 16-bit read only register contains a value assigned to the OHCI-Lynx by Texas Instruments. The device
identification for the OHCI-Lynx is 8009.
PCI register 02h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1
PCI command register
The command register provides control over the OHCI-Lynx interface to the PCI bus. All bit functions adhere
to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions.
PCI register 04h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 4. Bit Descriptions – PCI Command Register
BIT FIELD NAME ACCESS DESCRIPTION
9 FBB_ENB r Fast Back-to-Back Enable. The OHCI-Lynx will not generate fast back to back transactions, thus this bit
is read only and returns zero when read.
8 SERR_ENB rw SERR# Enable. When set, the OHCI-Lynx SERR# driver is enabled. SERR# can be asserted after de-
tecting an address parity error on the PCI bus.
7 STEP_ENB r Address/Data Stepping Control. The OHCI-Lynx does not support address/data stepping, and this bit is
hardwired to zero.
6 PERR_ENB rw Parity Error Enable. When set, the OHCI-Lynx is enabled to drive PERR# response to parity errors
through the PERR# signal.
5 VGA_ENB r VGA Palette Snoop Enable. The OHCI-Lynx does not feature VGA palette snooping, and this bit is read
only returning zeros when read.
4 MWI_ENB rw Memory Write and Invalidate Enable. When set, the OHCI-Lynx is enabled to generate MWI pci bus
commands. If reset, the OHCI-Lynx will generate memory write commands instead.
3 SPECIAL r Special Cycle Enable. The OHCI-Lynx function does not respond to special cycle transactions, and this
bit is read only and returns zero when read.
2 MASTER_ENB rw Bus Master Enable. When set, the OHCI-Lynx is enabled to initiate cycles on the PCI bus.
1 MEMORY_ENB rw Memory Response Enable. Setting this bit enables the OHCI-Lynx to respond to memory cycles on the
PCI bus. This bit must be set to access OHCI registers.
0 IO_ENB r I/O Space Enable. The OHCI-Lynx does not implement any I/O mapped functionality; thus, this bit is
read only and returns zeros when read.
TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI status register
PCI Bus Specification, as seen in the bit descriptions.
PCI register 06h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0
Table 5. Bit Descriptions – PCI Status Register
BIT FIELD NAME ACCESS DESCRIPTION
15 PAR_ERR rcu Detected Parity Error. This bit is set when a parity error is detected, either address or data parity
errors.
14 SYS_ERR rcu Signaled System Error. This bit is set when SERR is enabled and the OHCI-L ynx signaled a system
error to the host.
13 MABORT rcu Received Master Abort. This bit is set when a cycle initiated by the OHCI-Lynx on the PCI bus has
been terminated by a master abort.
12 T ABORT_REC rcu Received Target Abort. This bit is set when a cycle initiated by the OHCI-Lynx on the PCI bus was
terminated by a target abort.
11 TABORT_SIG rcu Signaled Target Abort. This bit is set by the OHCI-Lynx when it terminates a transaction on the PCI
bus with a target abort.
10:9 PCI_SPEED r DEVSEL Timing. These read only bits encode the timing of DEVSEL and are hardwired 01b
indicating that the OHCI-Lynx asserts this signal at a medium speed on non-configuration cycle
accesses.
8 DATAPAR rcu Data Parity Error Detected. This bit is set when the following conditions have been met:
a. PERR# was asserted by any PCI device including the OHCI-Lynx
b. The OHCI-Lynx was the bus master during the data parity error
c. The parity error response bit is set in the command register
7 FBB_CAP r Fast Back-to-Back Capable. The OHCI-Lynx cannot accept fast back to back transactions; thus, this
bit is hardwired to zero.
6 UDF r UDF Supported. The OHCI-Lynx does not support the user definable features; thus, this bit is
hardwired to zero.
5 66MHZ r 66 MHz capable. The OHCI-Lynx operates at a maximum PCLK frequency of 33 MHz; therefore, this
bit is hardwired to zero.
4 CAPLIST r Capabilities List. This bit is read only and returns one when read, and indicates that capabilities
additional to standard PCI are implemented. The linked list of PCI Power Management capabilities is
implemented in this function.
class code and revision ID register
This read only register categorizes the OHCI-Lynx as a serial bus controller (0Ch), controlling an IEEE1394 bus
(00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the lower byte.
PCI register 08h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset State 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1
TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 6. Bit Descriptions – Class Code and Revision ID Register
BIT FIELD NAME ACCESS DESCRIPTION
31:24 BASECLASS r Base Class. This field returns 0Ch when read, which broadly classifies the function as a serial bus
controller.
23:16 SUBCLASS r Sub Class. This field returns 00h when read, which specifically classifies the function as controlling a
IEEE1394 serial bus.
15:8 PGMIF r Programming Interface. This field returns 10h when read, which indicates that the programming
model is compliant with the 1394 OHCI specification.
7:0 CHIPREV r Silicon Revision. This field returns 01h when read, indicating the silicon revision of the OHCI-Lynx.
latency timer and class cache line size register
This register is programmed by host BIOS to indicate system cache line size and the latency timer associated
with the OHCI-Lynx.
PCI register 0Ch
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 7. Bit Descriptions – Latency Timer and Class Cache Line Size Register
BIT FIELD NAME ACCESS DESCRIPTION
15:8 LATENCY_TIMER rw PCI Latency Timer. The value in this register specifies the latency timer for the OHCI-Lynx, in
units of PCI clock cycles. When the OHCI-Lynx is a PCI bus initiator and asserts FRAME
, the
latency timer will begin counting from zero. If the latency timer expires before the OHCI-Lynx
transaction has terminated, then the OHCI-Lynx will terminate the transaction when its GNT
is
deasserted.
7:0 CACHELINE_SZ rw Cache Line Size. This value is used by the OHCI-Lynx during Memory Write and Invalidate,
Memory Read Line, and Memory Read Multiple transactions.
header type and bist register
This register indicates the OHCI-Lynx PCI header type, and indicates no built-in self test.
PCI register 0Eh
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 8. Bit Descriptions – Header Type and Bist Register
BIT FIELD NAME ACCESS DESCRIPTION
15:8 BIST r Built-in Self T est. The OHCI-L ynx does not include a built-in self test, and this field returns zero
when read.
7:0 HEADER_TYPE r PCI Header Type. The OHCI-L ynx includes the standard PCI header , and this is communicated
by returning zero when this field is read.
TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
open HCI registers base address register
This register is programmed with a base address referencing the memory mapped OHCI control. When BIOS
writes all ones to this register, the value read back is FFFF F800h, indicating that at least 2 Kbytes of memory
address space are required for the OHCI registers.
PCI register 10h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 9. Bit Descriptions – Open HCI Registers Base Address Register
BIT FIELD NAME ACCESS DESCRIPTION
31:11 OHCIREG_PTR rw Open HCI Register Pointer. Specifies the upper 20 bits of the 32-bit OHCI register base
address.
10:4 OHCI_SZ r Open HCI Register Size. This read only field returns zeros when read, and indicates that the
OHCI registers require a 2Kbyte region of memory.
3 OHCI_PF r OHCI Register Prefetch. This bit returns zero, indicating the OHCI registers are
nonprefetchable.
2:1 OHCI_MEMTYPE r Open HCI Memory Type. This read only field returns zeros when read, and indicates that the
base register is 32 bits wide and mapping can be done anywhere in the 32-bit memory space.
0 OHCI_MEM r OHCI Memory Indicator. This read only bit returns zero, indicating the OHCI registers are
mapped into system memory space.
TI extension base address register
This register is programmed with a base address referencing the memory mapped TI extension registers. Refer
to the description of the OHCI Base Address Register for bit field details.
PCI register 14h
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
PCI subsystem identification register
This register is used for system and option card identification purposes. This register can be initialized from the
serial EEPROM.
PCI register 2Ch
BIT NUMBER 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 10. Bit Descriptions – Open HCI Registers Base Address Register
BIT FIELD NAME ACCESS DESCRIPTION
31:16 ru Subsystem Device ID. This field indicates the subsystem device ID.
15:0 ru Subsystem Vendor ID. This field indicates the subsystem vendor ID.
TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI power management capabilities pointer
This register provides a pointer into the PCI configuration header where the PCI power management register
block resides. OHCI-Lynx configuration header double-words at 44h and 48h provide the PM registers. This
register is read only and returns 44h when read.
PCI register 34h
BIT NUMBER 7 6 5 4 3 2 1 0
Reset State 0 1 0 0 0 1 0 0
interrupt line and pin registers
This register is used to communicate interrupt line routing information.
PCI register 3Ch
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 11. Bit Descriptions – Interrupt Line and Pin Registers
BIT FIELD NAME ACCESS DESCRIPTION
15:8 INTR_PIN r Interrupt Pin Register. This register is read only and returns 01h when read,
indicating that the OHCI-Lynx PCI function signals interrupts on INTA
pin.
7:0 INTR_LINE rw Interrupt Line Register. This register is programmed by the system and indicates
to software to which interrupt line the OHCI-Lynx INTA
is connected.
MIN_GNT and MAX_LAT registers
This register is used to communicate to the system the desired setting of the Latency Timer Register . If a serial
ROM is detected, then the contents of this register are loaded through the serial ROM interface after a PCI reset.
If no serial ROM is detected, then this register returns a default value that corresponds to the MIN_GNT = 2,
MAX_LAT = 4.
PCI register 3Eh
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0
Table 12. Bit Descriptions – MIN_GNT and MAX_LAT Registers
BIT FIELD NAME ACCESS DESCRIPTION
15:8 MAX_LAT ru Maximum Latency. The contents of this register may be used by host BIOS to
assign an arbitration priority-level to the OHCI-Lynx. The default for this register
indicates that the OHCI-Lynx may need to access the PCI bus as often as every
1/4 microsecond; thus, an extremely high priority level is requested. The
contents of this field may also be loaded through the serial ROM.
7:0 MIN_GNT ru Minimum Grant. The contents of this register may be used by host BIOS to assign
a Latency Timer Register value to the OHCI-Lynx. The default for this register
indicates that the OHCI-Lynx may need to sustain burst transfers for nearly
64 microseconds; thus, requesting a large value be programmed in the
OHCI-Lynx Latency Timer Register.
TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PCI OHCI control register
This register contains IEEE1394 Open HCI specific control bits. All bits in this register are read only and return
zeros, since no OHCI specific control bits have been implemented.
PCI register 40h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
capability ID and next item pointer registers
This read only register identifies the linked list capability item, and provides a pointer to the next capability item.
PCI register 44h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Table 13. Bit Descriptions – Capability ID and Next Item Pointer Registers
BIT FIELD NAME ACCESS DESCRIPTION
15:8 NEXT_ITEM r Next Item Pointer . The OHCI-Lynx supports only one additional capability that is communicated
to the system through the extended capabilities list; thus, this read only field returns 00h when
read.
7:0 CAPABILITY_ID r Capability Identification. This field returns 01h when read, which is the unique ID assigned by the
PCI SIG for PCI power management capability.
power management capabilities
This register indicates the capabilities of the OHCI-Lynx related to PCI power management. In summary, the
D0, D3
hot
device states are supported.
PCI register 46h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1
TSB12LV22
OHCI-Lynx PCI-BASED IEEE 1394 HOST CONTROLLER
SLLS290 – JULY 1998
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Table 14. Bit Descriptions – Capability ID and Next Item Pointer Registers
BIT FIELD NAME ACCESS DESCRIPTION
15:11 PME_SUPPORT r PME Support. This five bit field indicates the power states from which the OHCI-L ynx may assert
PME
. A zero for any bit indicates that the OHCI-Lynx cannot assert PME signal from that power
state. These five bits return a value of “01001b” when read . Each of these bits is described below:
Bit 15 – reads 0 indicating that the PME
signal cannot be asserted from D3
cold
state.
Bit 14 – reads 1 indicating that the PME
signal can be asserted from D3
hot
state.
Bit 13 – reads 0 indicating that the PME
signal cannot be asserted from D2 state.
Bit 12 – reads 0 indicating that the PME
signal cannot be asserted from D1 state.
Bit 11 – reads 0 indicating that the PME
signal cannot be asserted from D0 state.
10 D2_SUPPORT r D2 Support. This bit returns a 0 when read, indicating that the OHCI-Lynx doesnot supports the D2
power state.
9 D1_SUPPORT r D1 Support. This bit returns a 0 when read, indicating that the OHCI-Lynx doesnot support the D1
power state.
8 DYN_DA TA r Dynamic Data Support. This bit returns a zero when read, indicating that the OHCI-Lynx does not
report dynamic power consumption data.
7–6 RESERVED r Reserved. This bit is read only and returns 0 when read.
5 DSI r Device Specific Initialization. This bit is read only and returns 0 when read, indicating that the
OHCI-Lynx does not require special initialization beyond the standard PCI configuration header
before a generic class driver is able to use it.
4 AUX_PWR r Auxiliary Power Source. Since the OHCI-Lynx does not support PME generation in the D3
COLD
device state, this bit returns zero when read.
3 PME_CLK r PME Clock. This bit is read only and returns a 0 when read indicating that no host bus clock is
required for the OHCI-Lynx to generate PME
.
2:0 PM_VERSION r Power Management Version. This field returns 001b when read, indicating that the OHCI-Lynx is
compatible with the registers described in the revision 1.0 PCI Bus Power Management
Specification.
power management control and status register
This register implements the control and status of the PCI power management function. This register is not
affected by the internally generated reset caused by the transition from the D3
HOT
to D0 state.
PCI register 48h
BIT NUMBER 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reset State 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Table 15. Bit Descriptions – Power Management Control and Status Register
BIT FIELD NAME ACCESS DESCRIPTION
15 PME_STS r c This bit is set when the OHCI-Lynx would normally be asserting the PME signal, independent of the state
of the PME_ENB bit. This bit is cleared by a write back of 0, and this also clears the PME# signal driven by
the OHCI-Lynx. Writing a zero to this bit has no effect.
14:9 DYN_CTRL r Dynamic Data Control. This bit field returns zeros when read since the OHCI-Lynx does not report
dynamic data.
8 PME_ENB r w PME Enable. This bit enables the function to assert PME. If the bit is cleared assertion of PME is disabled.
4 DYN_DA TA r Dynamic Data. This bit field returns zeros when read since the OHCI-Lynx does not report dynamic data.
1:0 PWR_STA TE rw Power State. This two bit field is used to set the OHCI-Lynx device power state, and is encoded as
follows:
00 – Current power state is D0 10 – Current power state is D2
01 – Current power state is D1 11 – Current power state is D3
HOT
Loading...