TEXAS INSTRUMENTS TSB12C01A Technical data

TSB12C01A

Data Manual

IEEE 1394-1995

High-Speed Serial-Bus

Link-Layer Controller

SLLS219B

November 1998

Printed on Recycled Paper

IMPORTANT NOTICE

T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.

TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.

CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MA Y INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.

In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.

TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
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party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.

Copyright  1998, Texas Instruments Incorporated

Contents

Section Title Page

1 Overview 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.1 Description 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2 Features 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.1 Link 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.2 Physical-Link Interface 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.3 Host Bus Interface 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.2.4 General 1–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.3 Terminal Assignments 1–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

1.4 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2 Architecture 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1 Functional Block Diagram 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.1 Physical Interface 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.2 Transmitter 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.3 Receiver 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.4 Transmit and Receive FIFOs 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.5 Cycle Timer 2–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.6 Cycle Monitor 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.7 Cyclic Redundancy Check (CRC) 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.8 Internal Registers 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2.1.9 Host Bus Interface 2–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3 Internal Registers 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.1 General 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2 Internal Register Definitions 3–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.1 Version/Revision Register 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.2 Node-Address/Transmitter Acknowledge Register 3–3. . . . . . . . . . . . . . . . . . . .

3.2.3 Control Register 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.4 Interrupt and Interrupt-Mask Registers 3–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.5 Cycle-Timer Register 3–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.6 Isochronous Receive-Port Number Register 3–8. . . . . . . . . . . . . . . . . . . . . . . . .

3.2.7 Diagnostic Control and Status Register 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.8 Phy-Chip Access Register 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.9 Asynchronous Transmit-FIFO (ATF) Status Register 3–9. . . . . . . . . . . . . . . . . .

3.2.10 ITF Status Register 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.2.11 GRF Status Register 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3 FIFO Access 3–1 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.1 General 3–1 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.2 ATF Access 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.3 ITF Access 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.4 General-Receive-FIFO (GRF) 3–12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3.3.5 RAM Test Mode 3–13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iii

4 TSB12C01A Data Formats 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1 Asynchronous Transmit (Host Bus to TSB12C01A) 4–1. . . . . . . . . . . . . . . . . . . . . . . . .

4.1.1 Quadlet Transmit 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.2 Block Transmit 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.3 Quadlet Receive 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.1.4 Block Receive 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.2 Isochronous Transmit (Host Bus to TSB12C01A) 4–5. . . . . . . . . . . . . . . . . . . . . . . . . .

4.3 Isochronous Receive (TSB12C01A to Host Bus) 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . .

4.4 Snoop 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.5 CycleMark 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.6 Phy Configuration 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.7 Link-On 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4.8 Receive Self-ID 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5 Electrical Characteristics 5–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.1 Absolute Maximum Ratings Over Free-Air Temperature Range 5–1. . . . . . . . . . . . . .

5.2 Recommended Operating Conditions 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage

and Operating Free-Air Temperature 5–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.4 Host-Interface Timing Requirements 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.5 Host-Interface Switching Characteristics Over Operating Free-Air

Temperature Range 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.6 Phy-Interface Timing Requirements Over Operating Free-Air

Temperature Range 5–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.7 Phy-Interface Switching Characteristics Over Operating Free-Air

Temperature Range 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.8 Miscellaneous Timing Requirements Over Operating Free-Air

Temperature Range 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

5.9 Miscellaneous Signal Switching Characteristics Over Operating Free-Air

Temperature Range 5–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6 Parameter Measurement Information 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7 TSB12C01A to 1394 Phy Interface Specification 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.1 Introduction 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.2 Assumptions 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.3 Block Diagram 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4 Operational Overview 7–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.1 Phy Interface Has Control of the Bus 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.4.2 TSB12C01A Has Control of the Bus 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5 Request 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5.1 LREQ Transfer 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5.2 Bus Request 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.5.3 Read/Write Requests 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6 Status 7–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.1 Status Request 7–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.2 Transmit 7–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.6.3 Receive 7–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7.7 TSB12C01A to Phy Bus Timing 7–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

8 Mechanical Data 8–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

iv

List of Illustrations

Figure Title Page

1–1 TSB12C01A Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

2–1 TSB12C01A Block Diagram 2–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Internal Register Map 3–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Interrupt Logic Diagram Example 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–3 TSB12C01A Controller-FIFO-Access Address Map 3–1 1. . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Quadlet-Transmit Format 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Block-Transmit Format 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 Quadlet-Receive Format 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Block-Receive Format 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 Isochronous-Transmit Format 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Isochronous-Receive Format 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 Snoop Format 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–8 CycleMark Format 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–9 Phy Configuration Format 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–10 Link-On Format 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–11 Receive Self-ID Format 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–1 BCLK Waveform 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–2 Host-Interface Write-Cycle Waveforms 6–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–3 Host-Interface Read-Cycle Waveforms 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–4 SCLK Waveform 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–5 TSB12C01A-to-Phy-Layer Transfer Waveforms 6–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–6 Phy Layer-to-TSB12C01A Transfer Waveforms 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–7 TSB12C01A Link-Request-to-Phy-Layer Waveforms 6–3. . . . . . . . . . . . . . . . . . . . . . . . .

6–8 Interrupt Waveform 6–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–9 CYCLEIN Waveform 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

6–10 CYCLEIN and CYCLEOUT Waveforms 6–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1 Functional Block Diagram of the TSB12C01A to Phy Layer 7–1. . . . . . . . . . . . . . . . . . .

7–2 LREQ Timing 7–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3 Status-Transfer Timing 7–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4 Transmit Timing 7–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5 Receiver Timing 7–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

v

List of Tables

Table Title Page

1–1 Terminal Functions 1–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–1 Version/Revision Register Field Descriptions 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–2 Node-Address/Transmitter Acknowledge Register Field Descriptions 3–3. . . . . . . . . .

3–3 Control-Register Field Descriptions 3–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–4 Interrupt- and Mask-Register Field Descriptions 3–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–5 Cycle-Timer Register Field Descriptions 3–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–6 Isochronous Receive-Port Number Register Field Descriptions 3–8. . . . . . . . . . . . . . . .

3–7 Diagnostic Control and Status-Register Field Descriptions 3–8. . . . . . . . . . . . . . . . . . . .

3–8 Phy-Chip Access Register 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–9 ATF Status Register 3–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–10 ITF Status Register 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

3–11 GRF Status Register 3–10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–1 Quadlet-Transmit Format 4–1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–2 Block-Transmit Format Functions 4–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–3 Quadlet-Receive Format Functions 4–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–4 Block-Receive Format Functions 4–4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–5 Isochronous-Transmit Functions 4–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–6 Isochronous-Receive Functions 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–7 Snoop Functions 4–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–8 CycleMark Functions 4–7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–9 Phy Configuration Functions 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–10 Link-On Functions 4–8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

4–11 Isochronous-Receive Functions 4–9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–1 Phy Interface Control of Bus Functions 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–2 TSB12C01A Control of Bus Functions 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–3 Request Functions 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–4 Bus-Request Functions (Length of Stream: 7 Bits) 7–2. . . . . . . . . . . . . . . . . . . . . . . . . . .

7–5 Read-Register Request Functions (Length of Stream: 9 Bits) 7–3. . . . . . . . . . . . . . . . .

7–6 Write-Register Request (Length of Stream: 17 Bits) 7–3. . . . . . . . . . . . . . . . . . . . . . . . . .

7–7 TSB12C01A Request Functions 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–8 TSB12C01A Request-Speed Functions 7–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

7–9 Status-Request Functions (Length of Stream: 16 Bits) 7–5. . . . . . . . . . . . . . . . . . . . . . .

7–10 Speed Code for Receive 7–6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

vi

1 Overview

1.1 Description

The TSB12C01A is an IEEE 1394-1995 standard (from now on referred to only as 1394) high-speed
serial-bus link-layer controller that allows for easy integration into an I/O subsystem. The TSB12C01A
transmits and receives correctly formatted 1394 packets and generates and inspects the 32-bit cyclic
redundancy check (CRC). The TSB12C01A is capable of being a cycle master and supports reception of
isochronous data on two channels. It interfaces directly to the TSB11C01, TSB11LV01, and TSB21LV03
physical-layer chips and can support bus speeds of 100, 200, and 400 Mb/s. The TSB12C01A has a generic
32-bit host bus interface, which makes connection to most 32-bit host buses very simple. The TSB12C01A
has software-adjustable FIFOs for optimal FIFO size and performance characterization and allows for
variable-size asynchronous-transmit FIFO (ATF), isochronous-transmit FIFO (ITF), and general-receive
FIFO (GRF).

This document is not intended to serve as a tutorial on 1394; users should refer to the IEEE 1394-1995 serial
bus for detailed information regarding the 1394 high-speed serial bus.

1.2 Features

The following are features of the TSB12C01A.

1.2.1 Link

• Complies With IEEE-1394-1995 Standard

• Transmits and Receives Correctly Formatted 1394 Packets

• Supports Isochronous Data Transfer

• Performs Function of Cycle Master

• Generates and Checks 32-Bit CRC

• Detects Lost Cycle-Start Messages

• Contains Asynchronous, Isochronous, and General-Receive FIFOs

1.2.2 Physical-Link Interface

• Interfaces Directly to the TSB1 1C01, TSB11LV01, TSB14C01, and TSB21LV03 Phy Chips

• Supports Speeds of 100, 200, and 400 Mb/s

• Implements the Physical-Link Interface Described in Annex J of the IEEE 1394-1995 Standard

• Supports TI Bus Holder Isolation External Implementation

1.2.3 Host Bus Interface

• Provides Chip Control With Directly Addressable Registers

• Is Interrupt Driven to Minimize Host Polling

• Has a Generic 32-Bit Host Bus Interface

1.2.4 General

•

Requires a Single 5-V ±5% Power Supply

• Manufactured with Low-Power CMOS Technology

• Packaged in a 100-Pin Thin Quad Flat Package (TQFP) (PZ Package) for 0°C to 70°C and –40°C

to 85°C Operation

• Packaged in a 100-Pin Ceramic Quad Flat Package (WN Package) for –55°C to 125°C Operation

1–1

1.3 Terminal Assignments

To Phy Layer

POWERON

RAMEz

GND
GND
GND

GND
DATA0
DATA1
DATA2
DATA3

V

CC

DATA4
DATA5
DATA6
DATA7

GND
DATA8
DATA9

DATA10

DATA11

V

CC

DATA12
DATA13
DATA14
DATA15

CC

V

Reserved

NTCLK

NTOUT

NTBIHIZ

GND

ISO

GND

75747372717069686766656463626160595857565554535251
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100

12345678910111213141516171819202122232425

CC

V

LREQ

GND

SCLK

TSB12C01A

PZ PACKAGE

(TOP VIEW)

CC

CTL0

CTL1

GNDD0D1D2D3D4D5D6D7

V

GND

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

CYST
CYDNE
GRFEMP
GND
GND
GND
CYCLEOUT
V

CC

CYCLEIN
GND
GND
RESET
GND
INT
WR
CA
CS
V

CC

BCLK
GND
ADDR7
ADDR6
ADDR5
ADDR4
V

CC

GND

DATA16

DATA17

DATA18

DATA19

NOTES: A. Tie reserved terminals to GND.

B. Bit 0 is the most significant bit (MSB).

1–2

CC

V

DATA20

DATA21

DATA22

GND

DATA23

DATA24

DATA25

To Host

DATA26

DATA27

CC

V

DATA28

DATA29

DATA30

DATA31

GND

ADDR0

ADDR1

ADDR2

ADDR3

GND
DATA16
DATA17
DATA18
DATA19

V

CC

DATA20
DATA21
DATA22
DATA23

GND
DATA24
DATA25
DATA26
DATA27

V

CC

DATA28
DATA29
DATA30
DATA31

GND

ADDR0
ADDR1
ADDR2
ADDR3

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

DATA15

100

26

DATA14

99

27

DATA13

98

28

DATA12

97

29

V

96

30

CC

CC

DATA6

DATA4

DATA3

DATA2

89

37

V

DATA5

86

87

88

40

39

38

85

41

84

42

DATA0

GND

GND

GND

80

46

79

47

RAMEz

77

78

49

48

POWERON

76

75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51

50

Reserved
V

CC
NTCLK
NTOUT

NTBIHIZ
GND
ISO
GND
LREQ
GND
SCLK
V

CC
CTL0

CTL1
GND
D0
D1
D2
D3
V

CC
D4

D5
D6
D7
GND

GND

DATA1

81

82

83

45

44

43

DATA11

DATA10

DATA8

GND

DATA7

DATA9

90

91

92

93

94

95

TSB12C01AM

WN PACKAGE

(TOP VIEW)

36

35

34

33

32

31

CC

V

ADDR4

ADDR5

ADDR6

NOTES: A. Tie reserved terminals to GND.

B. Bit 0 is the most significant bit (MSB).

GND

BCLK

ADDR7

CC

V

CS

CA

WR

INT

GND

RESET

GND

GND

CC

V

GND

CYCLEIN

CYCLEOUT

GND

GND

CYST

CYDNE

GRFEMP

1–3

1.4 Terminal Functions

I/O

DESCRIPTION

Host
Bus

DATA0 – DATA31
ADDR0 – ADDR7

CS

CA
WR
INT

CYCLEIN

CYCLEOUT

BCLK
RESET
RAMEz
NTCLK
NTOUT

NTBIHIZ

TSB12C01A

10

20

D0 – D7
CTL0
CTL1
LREQ
ISO
SCLK

V

CC

GND

POWERON
CYST

CYDNE
GRFEMP

Phy Interface

Figure 1–1. TSB12C01A Terminal Functions

T able 1–1. Terminal Functions

TERMINAL

NAME NO.

Host Bus Interface

ADDR0 –
ADDR7

CA 35 O Cycle acknowledge (active low). CA is a TSB12C01A control signal to the host bus.

CS 34 I

DATA0 –
DATA31

INT 37 O

WR 36 I

22–25
27–30

2–5

7–10
12–15
17–20
82–85
87–90
92–95

97–100

I Address 0 through address 7. Host bus address bus bits 0 through 7 that address

the quadlet-aligned FIFOs and configuration registers. The two least significant
address lines, 6 and 7, must be grounded.

When asserted (low), access to the configuration registers or FIFO is complete.
Cycle start (active low). CS is a host bus control signal to enable access to the

configuration registers or FIFO.

I/O Data 0 through 31. DATA is a host bus data bus bits 0 through 31.

Interrupt (active low). When INT is asserted (low), the TSB12C01A notifies the host
bus that an interrupt has occurred.

Read/write enable. When WR is deasserted (high) in conjunction with CS, a read
from the TSB12C01A is requested. When WR
CS

, a write to the TSB12C01A is requested.

is asserted (low) in conjunction with

1–4

T able 1–1. Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NO.

Phy Interface

CTL1, CTL0 62, 63 I/O Control 1 and control 0 of the phy-link control bus. CTL1 and CTL0 indicate the four

D0 – D7 52–55

57–60

ISO 69 I

LREQ 67 O Link request. LREQ is a TSB12C01A output that makes bus requests and accesses

POWERON 76 O Power on indicator to phy interface. When active, POWERON has a clock output with

SCLK 65 I System clock. SCLK is a 49.152-MHz clock from the phy, that generates the

BCLK 32 I Bus clock. BCLK is the host bus clock used in the host-interface module of the

CYCLEIN 42 I Cycle in. CYCLEIN is an optional external 8,000-Hz clock used as the cycle clock,

CYCLEOUT 44 O Cycle out. CYCLEOUT is the TSB12C01A version of the cycle clock. It is based on

CYDNE 49 O Status of CyDne bit. When the RevAEn bit of the control register is set, CYDNE

CYST 50 O Status of CySt bit. When the RevAEn bit of the control register is set, CYST indicates

GND 1, 11,

21, 31,
38, 40,

41,
45–47,
51, 61,
66, 68,

70,
78–81,

91

GRFEMP 48 O Status of Empty bit. When the RevAEn bit of the control register is set, GRFEMP

RAMEz 77 I RAM 3-state enable. When RAMEz is deasserted (low), FIFOs are enabled. When

operations that can occur in this interface (see Section 7 of this document or Annex
J of the IEEE 1394-1995 standard for more information about the four operations).

I/O Data 0 through data 7 of the phy-link data bus. Data is expected on D0 – D1 for

100 Mb/s packets, D0 – D3 for 200 Mb/s, and D0 – D7 for 400 Mb/s.
Isolation barrier (active low). This ISO is asserted (low) when an isolation barrier is

present.

the phy layer.

1/32 of the BCLK frequency and indicates to the phy interface that the TSB12C01A
is powered. This terminal can be connected to the link power status (LPS) terminal
on the TI phy devices to provide an indication of the LLC power condition.

24.576-MHz clock.

Miscellaneous Signals

TSB12C01A. It is asynchronous to SCLK.

and it should only be used when attached to the cycle-master node. It is enabled by
the cycle source bit and should be tied high when not used.

the timer controls and received cycle-start messages.

indicates the value of the CyDne bit of the interrupt register. When RevAEn is cleared,
CYDNE is a 3-state output.

the value of the CySt bit of the interrupt register. When RevAEn is cleared, CYST is
a 3-state output.

Ground reference

indicates the value of the Empty bit of the GRF status register. When RevAEn is
cleared, GRFEMP is a 3-state output.

RAMEz is asserted, the FIFOs are 3-state outputs. (This is a manufacturing
test-mode condition and should be grounded under normal operating conditions.)

1–5

T able 1–1. Terminal Functions (Continued)

I/O

DESCRIPTION

TERMINAL

NAME NO.

NTBIHIZ 71 I NAND-tree bidirectional 3-state output. When NTBIHIZ is deasserted (low), the

NTCLK 73 I NAND clock input. The NAND-tree clock is used for VIH and VIL manufacturing

NTOUT 72 O NAND-tree output. This output should remain open under normal operating

RESET 39 I Reset (active low). RESET is the asynchronous reset to the TSB12C01A.
V

CC

6, 16, 26,

33, 43, 56,
64, 74, 86,

96

bidirectional I/Os operate in a normal state. When NTBIHZ is asserted (high), the
bidirectional I/Os are in the 3-state output mode. (This is a manufacturing
test-mode condition and should be grounded under normal operating conditions.)

tests. (This input should be grounded under normal operating conditions.)

conditions.

5-V ±5% power supplies

1–6

2 Architecture

2.1 Functional Block Diagram

The functional block architecture of the TSB12C01A is shown in Figure 2–1.

Transmitter

H

o
s

t

I

n

t

e

r

f
a
c
e

ATF

ITF

GRF

Cycle Timer

CRC

Cycle Monitor

Receiver

Configuration Registers

P
h
y
s

i
c
a

l

I
n

t

e

r

f
a
c
e

Figure 2–1. TSB12C01A Block Diagram

2.1.1 Physical Interface

The physical (phy) interface provides phy-level services to the transmitter and receiver. This includes
gaining access to the serial bus, sending packets, receiving packets, and sending and receiving
acknowledge packets.

The phy interface module also interfaces to the phy chip and conforms to the phy-link interface specification
described in Annex J of the IEEE 1394-1995 standard (refer to Section 7 of this document for more
information).

2.1.2 Transmitter

The transmitter retrieves data from either the ATF or the ITF and creates correctly formatted serial-bus
packets to be transmitted through the phy interface. When data is present at the ATF interface to the
transmitter, the TSB12C01A phy interface arbitrates for the serial bus and sends a packet. When data is
present at the ITF interface to the transmitter, the TSB12C01A arbitrates for the serial bus during the next
isochronous cycle. The transmitter autonomously sends the cycle-start packets when the chip is a cycle
master.

2–1

2.1.3 Receiver

The receiver takes incoming data from the phy interface and determines if the incoming data is addressed
to this node. If the incoming packet is addressed to this node, the CRC of the packet is checked. If the header
CRC is good, the header is confirmed in the GRF . For block and isochronous packets, the remainder of the
packet is confirmed one quadlet at a time. The receiver places a status quadlet in the GRF after the last
quadlet of the packet is confirmed in the GRF . The status quadlet contains the error code for the packet. The
error code is the acknowledge code that is sent for that packet. For broadcast packets that do not need
acknowledge packets, the error code is the acknowledge code that would have been sent. This
acknowledge code tells the transaction layer whether or not the data CRC is good or bad. When the header
CRC is bad, the header is flushed and the rest of the packet is ignored.

When a cycle-start message is received, it is detected and the cycle-start message data is sent to the cycle
timer. The cycle-start messages are not placed in the GRF like other quadlet packets. At the end of an
isochronous cycle and if the cycle mark enable (CyMrkEn) bit of the control register is set , the receiver
inserts a cycle-mark packet in the GRF to indicate the end of the isochronous cycle.

2.1.4 Transmit and Receive FIFOs

The TSB12C01A contains two transmit FIFOs (asynchronous and isochronous) and one receive FIFO
(general receive). Each of these FIFOs is one quadlet wide and their length is software adjustable. These
software-adjustable FIFOs allow customization of the size of each FIFO for individual applications. The sum
of all FIFOs cannot be larger than 509 quadlets. To understand how to set the size of the FIFOs, see
subsections 3.2.1 1 through 3.2.13. The transmit FIFOs are write only from the host bus interface, and the
receive FIFO is read only from the host bus interface.

An example of how to use software-adjustable FIFOs follows:
In applications where isochronous packets are large and asynchronous packets are small, the implementer

can set the ITF and GRF to a large size (200 quadlets each) and set the A TF to a smaller size (100 quadlets).
Notice that the sum of all FIFOs is less than or equal to 509 quadlets.

2.1.5 Cycle Timer

The cycle timer is used by nodes that support isochronous data transfer. The cycle timer is a 32-bit
cycle-timer register. Each node with isochronous data-transfer capability has a cycle-timer register as
defined in the IEEE 1394-1995 standard. In the TSB12C01A, the cycle-timer register is implemented in the
cycle timer and is located in IEEE-1212 initial register space at location 200h and can also be accessed
through the local bus at address 14h. The low-order 12 bits of the timer are a modulo 3072 counter, which
increments once every 24.576-MHz clock periods (or 40.69 ns). The next 13 higher-order bits are a count
of 8, 000-Hz (or 125 µs)cycles, and the highest 7 bits count seconds.

The cycle timer contains the cycle-timer register. The cycle-timer register consists of three fields: cycle
offset, cycle count, and seconds count. The cycle timer has two possible sources. First, if the cycle source
(CySrc) bit in the configuration register is set, then the CYCLEIN input causes the cycle count field to
increment for each positive transition of the CYCLEIN input (8 kHz) and the cycle offset resets to all zeros.
CYCLEIN should only be the source when the node is cycle master. When the cycle-count field increments,
CYCLEOUT is generated. The timer can also be disabled using the cycle-timer-enable bit in the control
register. See subsection 3.2.5 for more information.

The second cycle-source option is when the CySrc bit is cleared. In this state, the cycle-offset field of the
cycle-timer register is incremented by the internal 24.576-MHz clock. The cycle timer is updated by the
reception of the cycle-start packet for the noncycle master nodes. Each time the cycle-offset field rolls over ,
the cycle-count field is incremented and the CYCLEOUT signal is generated. The cycle-offset field in the
cycle-start packet is used by the cycle-master node to keep all nodes in phase and running with a nominal
isochronous cycle of 125 µs.

2–2

CYCLEOUT indicates to the cyclemaster node that it is time to send a cycle-start packet. And, on
noncyclemaster nodes, CYCLEOUT indicates that it is time to expect a cycle-start packet. The cycle-start
bit is set when the cycle-start packet is sent from the cyclemaster node or received by a noncyclemaster
node.

2.1.6 Cycle Monitor

The cycle monitor is only used by nodes that support isochronous data transfer. The cycle monitor observes
chip activity and handles scheduling of isochronous activity . When a cycle-start message is received or sent,
the cycle monitor sets the cycle-started interrupt bit. It also detects missing cycle-start packets and sets the
cycle-lost interrupt bit when this occurs. When the isochronous cycle is complete, the cycle monitor sets the
cycle-done-interrupt bit. The cycle monitor instructs the transmitter to send a cycle-start message when the
cycle-master bit is set in the control register.

2.1.7 Cyclic Redundancy Check (CRC)

The CRC module generates a 32-bit CRC for error detection. This is done for both the header and data. The
CRC module generates the header and data CRC for transmitting packets and checks the header and data
CRC for received packets. See the IEEE 1394-1995 standard for details on the generation of the CRC

†

2.1.8 Internal Registers

The internal registers control the operation of the TSB12C01A. The register definitions are specified in
Section 3.

2.1.9 Host Bus Interface

The host bus interface allows the TSB12C01A to be easily connected to most host processors. This host
bus interface consists of a 32-bit data bus and an 8-bit address bus. The TSB12C01A utilizes cycle-start
and cycle-acknowledge handshake signals to allow the local bus clock and the 1394 clock to be
asynchronous to one another. The TSB12C01A is interrupt driven to reduce polling.

.

†

This is the same CRC used by the IEEE802 LANs and the X3T9.5 FDDI.

2–3

2–4

3 Internal Registers

3.1 General

The host-bus processor directs the operation of the TSB12C01A through a set of registers internal to the
TSB12C01A itself. These registers are read or written by asserting CS
– ADDR7 and asserting or deasserting WR
the register addresses; subsequent sections describe the function of the various registers.

depending on whether a read or write is needed. Figure 3–1 lists

3.2 Internal Register Definitions

The TSB12C01A internal registers control the operation of the TSB12C01A. The bit definitions of the internal
registers are shown in Figure 3–1 and are described in subsections 3.2.1 through 3.2.13.

with the proper address on ADDR0

3–1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 29 30 31

00h
04h

Version

Bus Number

Node Number

Revision

ATAck

28

Version
Node

Address

08h

0Ch

10h

14h

18h

1Ch

20h

24h

28h

2Ch

30h

BsyCtrl

IntInt IdVal

PhIntPhInt RxSId

PhRstPhRst

PhRRxPhRRx

7 Bits

Seconds Count

IR Port1

FrGp

BsyFlWrPhy

ENSpRdPhy

ArbGp

regRW

PhyRgAd PhyRxAd

Full

AlF

4AV4AV

TxEn

RxEn

PSBz

RxDtaRxDta

TxRdyTxRdy

CmdRstCmdRst

Rollover @ 8000

TAGTAG

Adr_clr

Control_bit1

Control_bit_err

PSOn

RstTx

PSRO

RAM Test

PhyRgData

BlkBusDep

RstRx

ITStk

ITStk

ATStk

ATStk

SntRj

SntRj

Cycle Count

IR Port2

AIEAIEAIE

ATRC

HdrEr

TCErr

HdrEr

TCErr

13 Bits Rollover @ 3072 12 Bits

CySrc

CyMas

CySt

CySec

CySt

CySec

CyTEn

CyMrkEn

CyDne

CyPnd

CyDne

CyPnd

IRP1En

IRP2En

CyLst

CArbFl

CyLst

CArbFl

Cycle Offset

PhyRxData

EmptyEmptyEmpty

ClrClrClr

Size

Control

RevAEn

Interrupt

Interrupt
Mask

IArbFl IArbFl

Cycle
Timer

Isoch Port
Number

Reserved

Diagnostics

Phy Chip
Access

Reserved
Reserved

ATF Status

34h

38h

3Ch

40h

Full

Full

AlF

AlF

4Th

cd

Size

Size

ITF Status

Reserved

GRF Status

Reserved

NOTE A: All gray areas (bits) are reserved bits.

Figure 3–1. Internal Register Map

3.2.1 Version/Revision Register

The version/revision register allows software to be written that supports multiple versions of the high-speed
serial-bus link-layer controllers. This register is at address 00h and is read only. The initial value is
3031_3041h.

3–2

T able 3–1. Version/Revision Register Field Descriptions

BITS ACRONYM FUNCTION NAME DESCRIPTION

0–15 Version Version Version of the TSB12C01A

16–31 Revision Revision Revision of the TSB12C01A

3.2.2 Node-Address/Transmitter Acknowledge Register

The node-address/transmitter acknowledge register controls which packets are accepted/rejected, and it
presents the last acknowledge received for packets sent from the ATF. This register is at offset 04h. The
bus number and node number fields are read/write. The A T acknowledge (AT Ack) received is normally read
only. Setting the regRW bit in the diagnostic register makes these fields read/write. The initial value is
FFFF_0000h.

T able 3–2. Node-Address/Transmitter Acknowledge Register Field Descriptions

BITS ACRONYM FUNCTION NAME DESCRIPTION

0–9 BusNumber Bus number BusNumber is the 10-bit IEEE 1212 bus number that the

10–15 NodeNumber Node number NodeNumber is the 6-bit node number that the TSB12C01A uses

16–23 Reserved Reserved Reserved
24–27 ATAck Address transmitter

28–31 Reserved Reserved Reserved

acknowledge
received

TSB12C01A uses with the node number in the SOURCE address
for outgoing packets and to accept or reject incoming packets. The
TSB12C01A always accepts packets with a bus number equal to
3FFh.

with the bus number in the source address for outgoing packets and
to accept or reject incoming packets. The TSB12C01A always
accepts packets with the node address equal to 3Fh. See
BlkBusDep bits in Table 3–3 for exceptions.

AT Ack is the last acknowledge received by the transmitting node in
response to a packet sent from the asynchronous transmit-FIFO.
When an acknowledge time out occurs, the value written to ATAck
is 0h. See T able 6–13 in IEEE 1394-1995 standard for acknowledge
codes.

3.2.3 Control Register

The control register dictates the basic operation of the TSB12C01A. This register is at address 08h and is
read/write. The initial value is 0000_0000h.

T able 3–3. Control-Register Field Descriptions

BITS ACRONYM FUNCTION NAME DESCRIPTION

0 IdVal ID Valid When IdVal is set, the TSB12C01A accepts packets addressed to

1 RxSId Received self-ID

packets

the IEEE 1212 address set (Node Number) in the node-address
register. When IdVal is cleared, the TSB12C01A accepts only
broadcast packets.

When RxSId is set, the self-identification packets generated by phy
chips during bus initialization are received and placed into the GRF
as a single packet. Each self-identification packet is composed of
two quadlets, where the second quadlet is the logical inverse of the
first. If ACK (4 bits) equals 1h, then the data is good. If ACK equals
Dh, then the data is wrong.

3–3

T able 3–3. Control-Register Field Descriptions (Continued)

BITS ACRONYM FUNCTION NAME DESCRIPTION

2–4 BsyCtrl Busy control These bits control which busy status (as described in IEEE 1394-1995

5 TxEn Transmitter enable When TxEn is cleared, the transmitter does not arbitrate or send

6 RxEn Receiver enable When RXEn is cleared, the receiver does not receive any packets.
7 PSBz Physical DMA

busy

8 PSOn Physical DMA on When PSOn is set, the TSB12C01A uses PSRO and PSBz to determine

9 PSRO Physical DMA read

only

10 RstTx Reset transmitter When RstTx is set, the entire transmitter resets synchronously. This bit

11 RstRx Reset receiver When RstRx is set, the entire receiver resets synchronously. This bit

12–15 BlkBusDep Block bus-

dependent
address

16–17 ATRC AT retry code This field contains the last retry code received. This code is logically

standard, the chip returns to incoming packets. The field is defined as
follows:

000 = follow normal busy/retry protocol, only send busy when

necessary.
001 = send busyA when it is necessary to send a busy acknowledge.
010 = send busyB when it is necessary to send a busy

acknowledge.
011 = reserved
100 = send a busy acknowledge to all incoming packets following the

normal busy/retry protocol.
101 = send a busy acknowledge to all incoming packets by sending

a busyA acknowledge.
110 = send a busy acknowledge to all incoming packets by sending

a busyB acknowledge.
111 = reserved

When retry_X is received and the receiving node needs to send a busy
acknowledge signal, it sends an ack_busy_X signal.

packets.

When:

1) PSOn is set,

2) PSRO is cleared or the incoming packet is a read,

3) destination offset is in the lower 4 Gbytes, and

4) PSBz is set,

the TSB12C01A sends a busy acknowledge to the incoming packet.

acceptance of incoming request packets addressed to the lower
4 Gbytes of initial memory space.

When PSOn is set, the TSB12C01A uses PSRO to determine the
acceptance of incoming write request packets addressed to the lower
4 Gbytes of initial memory space.

clears itself.

clears itself.
This field is used by the receiver to filter out broadcast packets to the

bus-dependent area of CSR space. Setting the LSB of this field disables
the reception of broadcast packets to the lowest 128 bytes of
bus-dependent CSR space. Setting the MSB of this field disables the
reception of broadcast packets to the highest 128 bytes of
bus-dependent CSR space.

ORed with the retry code field (00) in the transmit packet, and the packet
is resent. This alleviates the need to change the retry code in the transmit
packet. The retry encoding follows the IEEE 1394-1995 standard. The
retry code is as follows:
00 retry_o (new) 01 retry_X
10 retry_A 11 retry_B

3–4

T able 3–3. Control-Register Field Descriptions (Continued)

BITS ACRONYM FUNCTION NAME DESCRIPTION

18–19 Reserved Reserved Reserved

20 CyMas Cycle master When CyMas is set and the TSB12C01A is attached to the root phy, the

21 CySrc Cycle source When CySrc is set, the cycle_count field increments and the

22 CyTEn Cycle-timer enable When CyTEn is set, the cycle_offset field increments.
23 CyMrkEn Cycle mark enable When CyMrkEn is set, cycle marks are inserted into GRF at the end of

24 IRP1En IR port 1 enable When IRP1En is set, the receiver accepts isochronous packets when

25 IRP2En IR port 2 enable When IRP2En is set, the receiver accepts isochronous packets when

26–30 Reserved Reserved Reserved

31 RevAEn Rev A enable When set, RevAEn enables the output of GRFEMP, CYDNE, and CYST .

cyclemaster function is enabled. When the cycle_count field of the cycle
timer register increments, the transmitter sends a cycle-start packet.
This bit is not cleared upon bus reset. When another node is selected as
root during a bus reset, the transaction layer in the now nonroot
TSB12C01A node must clear this bit and the transaction layer in the
TSB12C01a node selected as root must set this bit.

cycle_offset field resets for each positive transition of CYCLEIN. When
CySrc is cleared, the cycle_count field increments when the cycle_offset
field rolls over.

each isochronous cycle (TSB12C01A compatible). When CyMrkEn is
cleared, no cycle marks are generated.

the channel number matches the value in the IR Port1 field.

the channel number matches the value in the IR Port2 field.

When not set, these outputs are in a high-impedance state, which makes
TSB12C01A pin-compatible with the TSB12C01. This bit is 0 on power
up.

3.2.4 Interrupt and Interrupt-Mask Registers

The interrupt and interrupt-mask registers work in tandem to inform the host bus interface when the state
of the TSB12C01A changes. The interrupt register is at address 0Ch. The interrupt mask register is at
address 10h. The interrupt mask register is read/write. Its initial value is 0000_0000h. When regRW is
cleared to 0, the interrupt register (except for the Int bit) is write to clear. When regR W (in diagonstics register
at 20h) is set to 1, the interrupt register (including the Int bit) is read/write. Its initial value is 1000_0000h.

The interrupt bits all work the same. For example, when a phy interrupt occurs, the PhInt bit is set. When
the PhIntMask bit is set, the Int bit is set. When the IntMask is set, the INT
the interrupt bits is shown in Figure 3–2. Table 3–4 defines the interrupt and interrupt-mask register field
descriptions. As shown in Figure 3–2, the INT bit is the OR of interrupt bits 1 – 31. When all the interrupt
bits are cleared, INT equals 0. When any of the interrupt bits are set, INT equals 1, even when the INT bit
was just cleared.

signal is asserted. The logic for

3–5

PhInt Source

DATA (01)

WR

CS

SCLK

PhInt Bit

Set

Clear

Clk

Q

PhInt Bit

PhIntMask Bit

Interrupt Bit

IntMask Bit

Other

Interrupts

INT

Interrupt Bit (INT)

Figure 3–2. Interrupt Logic Diagram Example

T able 3–4. Interrupt- and Mask-Register Field Descriptions

BITS ACRONYM FUNCTION NAME DESCRIPTION

0 Int Interrupt Int contains the value of all interrupt and interrupt mask bits ORed

1 PhInt Phy chip interrupt When PhInt is set, the phy chip has signaled an interrupt through the

2 PhyRRx Phy register

information received

3 PhRst Phy reset started When PhRst is set, a phy-layer reconfiguration has started (1394 bus

4 Reserved Reserved Reserved
5 TxRdy T ransmitter ready When TxRdy is set, the transmitter is idle and ready.
6 RxDta Receiver has data In normal mode and when set, RxDta indicates that the receiver has

7 CmdRst Command reset

received

8–10 Reserved Reserved Reserved

11 ITStk Transmitter is stuck

(IT)

12 ATStk Transmitter is stuck

(AT)

together.

Phy interface.
When PhyRRx is set, a register value has been transferred to the phy

chip access register (offset 24h) from the phy interface.

reset).

accepted a quadlet of data into the GRF interface. This bit is set each
time a quadlet of data is accepted. However, during the self-ID portion
of a bus reset, this bit is set after each complete self-ID packet is
received into the GRF.

When CmdRst is set, the receiver has been sent a quadlet write
request addressed to the RESET_START CSR register.

When ITStk is set, the transmitter has detected invalid data at the
isochronous transmit-FIFO interface.

When ATStk is set, the transmitter has detected invalid data at the
asynchronous transmit-FIFO interface. If the first quadlet of a packet
is not written to the ATF_First or ATF_First&Update, the transmitter
enters a state denoted by an ATStuck interrupt. An underflow of the
ATF also causes an ATStuck interrupt. If this state is entered, no
asynchronous packets can be sent until the ATF is cleared by way of
the CLR ATF control bit. Isochronous packets can be sent while in this
state.

3–6

T able 3–4. Interrupt- and Mask-Register Field Descriptions (Continued)

BITS ACRONYM FUNCTION NAME DESCRIPTION

13 Reserved Reserved Reserved
14 SntRj Busy acknowledge

sent by receiver

15 HdrEr Header error When HdrEr is set, the receiver detected a header CRC error on an

16 TCErr Transaction code

error

17–19 Reserved Reserved Reserved

20 CySec Cycle second

incremented

21 CySt Cycle started When CySt is set, the transmitter has sent or the receiver has received

22 CyDne Cycle done When CyDne is set, an arbitration gap has been detected on the bus

23 CyPnd Cycle pending When CyPnd is set, the cycle-timer offset is set to 0 (rolled over or

24 CyLst Cycle lost When CyLst is set, the cycle timer has rolled over twice without the

25 CArbFI Cycle arbitration

failed

26–30 Reserved Reserved Reserved

31 IArbFI Isochronous

arbitration failed

When SntRj is set, the receiver is forced to send a busy acknowledge
to a packet addressed to this node because the GRF overflowed.

incoming packet that may have been addressed to this node.
When TCErr is set, the transmitter detected an invalid transaction code

in the data at the transmit FIFO interface.

When CySec is set, the cycle-second field in the cycle-timer register
is incremented. This occurs approximately every second when the
cycle timer is enabled.

a cycle-start packet.

after the transmission or reception of a cycle-start packet. This
indicates that the isochronous cycle is over.

reset) and remains set until the isochronous cycle ends.

reception of a cycle-start packet. This occurs only when this node is not
the cycle master.

When CArbFI is set, the arbitration to send the cycle-start packet failed.

When IArbFI is set, the arbitration to send an isochronous packet failed.

3.2.5 Cycle-Timer Register

The cycle-timer register contains the seconds_count, cycle_count and cycle_offset fields of the cycle timer .
The register is at address 14h and is read/write. This field is controlled by the cycle master, cycle source,
and cycle timer enable bits of the control register. Its initial value is 0000_0000h.

T able 3–5. Cycle-Timer Register Field Descriptions

BITS ACRONYM FUNCTION NAME DESCRIPTION

0–6 seconds_count Seconds count 1-Hz cycle-timer counter

7–19 cycle_count Cycle count 8,000-Hz cycle-timer counter

20–31 cycle_offset Cycle offset 24.576-MHz cycle-timer counter

3–7

3.2.6 Isochronous Receive-Port Number Register

The isochronous receive-port number register controls which isochronous channels are received by this
node. This register is at address 18h. The register is read/write, and its initial value is 0000_0000h.

T able 3–6. Isochronous Receive-Port Number Register Field Descriptions

BITS ACRONYM FUNCTION NAME DESCRIPTION

0–7 IRPort1 Isochronous receive

TAG bits and port 1
channel number

8–15 IRPort2 Isochronous receive

TAG bits and port 2
channel number

16–31 Reserved Reserved Reserved

IRPort1 contains the channel number of the isochronous packets the
receiver accepts when IRP1En is set (bits 0 and 1 are reserved as
TAG bits). See Table 4–5 and Table 4–6 for more information.

IRPort2 contains the channel number of the isochronous packets the
receiver accepts when IRP2En is set (bits 8 and 9 are reserved as
TAG bits). See Table 4–5 and Table 4–6 for more information.

3.2.7 Diagnostic Control and Status Register

The diagnostic control and status register allows for the monitoring and control of the diagnostic features
of the TSB12C01A. The register is at address 20h. The regRW and enable snoop bits are read/write. When
regRW is cleared, all other bits are read only. When regRW is set, all bits are read/write. Its initial value is
0000_0000h. For a RAM test read/write, enable RAM test mode and set Adr_clr to clear the RAM internal
address counter. Do the host bus read/write to location 80h; this accesses RAM starting at location 00h.
With each read/write the RAM internal address counter increments by one.

T able 3–7. Diagnostic Control and Status-Register Field Descriptions

BITS ACRONYM FUNCTION NAME DESCRIPTION

0 ENSp Enable Snoop When ENSp is set, the receiver accepts all packets on the bus

1 BsyFl Busy flag When BsyFl is set, the receiver sends an ack_busyB the next time the

2 ArbGp Arbitration reset

gap

3 FrGp Fair gap When FrGp is set, the serial bus has been idle for a fair-gap time

4 regR/W Register read/write

access

5 Adr_clr Address clear When Adr_clr is set, the internal RAM address counter and the

6 Control_bit1 Control bit for RAM

test write

7 Control_bit_err Control bit error

flag

8 RAMTest RAM test mode When RAMTest and regRW are set, RAM test mode is enabled.

9–31 Reserved Reserved Reserved

regardless of address or format. The receiver uses the snoop data
format defined in Section 4.4.

receiver must busy a packet. When cleared, the receiver sends an
ack_busyA the next time the receiver must busy a packet.

When ArbGp is set, the serial bus has been idle for an arbitration reset
gap.

(Sub-Action Gap).
When regR/W is set, most registers are fully read/write.

Control_bit_err flag are cleared.
During RAM test mode, Control_bit1 is written into the control bit of

RAM (bit 33) for RAM write transaction.
When Control_bit_err is set, the control bit of the RAM does not

match Control_bit1 during RAM test mode.

3.2.8 Phy-Chip Access Register

The phy-chip access register allows access to the registers in the attached phy chip. The most significant
16 bits send read and write requests to the phy-chip registers. The least significant 16 bits are for the phy
chip to respond to a read request sent by the TSB12C01A. The phy-chip access register also allows the
phy interface to send important information back to the TSB12C01A. When the phy interface sends new

3–8

information to the TSB12C01A, the phy register-information-receive (PhyRRx) interrupt is set. The register
is at address 24h and is read/write. Its initial value is 0000_0000h. All gap counts (set in the phy device
registers) on all nodes of a 1394 bus must be identical. This can be accomplished by using the phy
configuration packets to set a specific gap count or by using two bus resets, which resets the gap counts
to the default 3Fh. See Section 4.6 for the format of the phy configuration packets.

T able 3–8. Phy-Chip Access Register

BITS ACRONYM FUNCTION NAME DESCRIPTION

0 RdPhy Read phy-chip

register

1 WrPhy Write phy-chip

register

2–3 Reserved Reserved Reserved
4–7 PhyRgAd Phy-chip-register

address

8–15 PhyRgData Phy-chip-register

data
16–19 Reserved Reserved Reserved
20–23 PhyRxAd Phy-chip-register-

received address
24–31 PhyRxData Phy-chip-register-

received data

When RdPhy is set, the TSB12C01A sends a read register request with
address equal to phyRgAd to the phy interface. This bit is cleared when
the request is sent.

When WrPhy is set, the TSB12C01A sends a write register request
with an address equal to phyRgAd on to the phy interface. This bit is
cleared when the request is sent.

PhyRgAd is the address of the phy-chip register that is to be accessed.

PhyRgData is the data to be written to the phy-chip register indicated
in PhyRgAd.

PhyRxAd is the address of the register from which PhyRxData came.

PhyRxData contains the data from register addressed by PhyRxAd.

3.2.9 Asynchronous Transmit-FIFO (ATF) Status Register

The ATF status register allows access to the registers that control or monitor the ATF. The register is at
address 30h. All the FIFO flag bits are read only, and the FIFO control bits are read/write. Its initial value
is 0000_0000h.

T able 3–9. ATF Status Register

BITS ACRONYM FUNCTION NAME DESCRIPTION

0 Full ATF full flag When Full is set, the FIFO is full. Write operations are ignored.
1 AlF ATF almost-full flag When AlF is set, the FIFO can accept one more write.

2–3 Reserved Reserved Reserved

4 4AV A TF-4-available flag When 4AV is set, the FIFO has space available for at least four

5–13 Reserved Reserved Reserved

14 AlE ATF-almost-empty flag When AlE is set, the FIFO has only one quadlet in it.
15 Empty ATF-empty flag When Empty is set, the FIFO is empty.

16–18 Reserved Reserved Reserved

19 Clr ATF-clear control bit When Clr is set by software/firmware, the FIFO is cleared of all

20 – 22 Reserved Reserved Reserved
23 – 31 Size ATF-size control bits Size is equal to the ATF size number in quadlets.

quadlets.

entries.

3–9

3.2.10 ITF Status Register

The ITF status register allows access to the registers that control or monitor the ITF. The register is at
address 34h. All the FIFO flag bits are read only, and the FIFO control bits are read/write. Its initial value
is 0000_0000h.

T able 3–10. ITF Status Register

BITS ACRONYM FUNCTION NAME DESCRIPTION

0 Full ITF full flag When Full is set, the FIFO is full and all writes are ignored.
1 AlF ITF almost-full flag When AlF is set, the FIFO can accept only one more write.

2–3 Reserved Reserved Reserved

4 4AV ITF-4-available flag When 4AV is set, the FIFO has space for at least four more quadlets.

5–13 Reserved Reserved Reserved

14 AlE ITF-almost-empty flag When AlE is set, the FIFO has only one quadlet in it.
15 Empty ITF-empty flag When Empty is set, the FIFO is empty.

16–18 Reserved Reserved Reserved

19 Clr ITF-clear control bit When Clr is set by software/firmware, the FIFO is cleared of all

20 – 22 Reserved Reserved Reserved
23 – 31 Size ITF-size control bits The size is equal to the ITF size number in quadlets.

entries.

3.2.11 GRF Status Register

The GRF status register allows access to the registers that control or monitor the GRF. The register is at
address 3Ch. All the FIFO flag bits are read only, and the FIFO control bits are read/write. Its initial value
is 0000_0000h.

Table 3–11. GRF Status Register

BITS ACRONYM FUNCTION NAME DESCRIPTION

0 Full GRF full flag When Full is set, the FIFO is full.
1 AlF GRF-almost-full flag When AlF is set, the FIFO can accept only one more write.

2–11 Reserved Reserved Reserved

12 4Th GRF four there When 4Th is set, the FIFO has at least four quadlets in it.
13 Reserved Reserved Reserved
14 AlE GRF-almost-empty

flag

15 Empty GRF-empty flag When Empty is set, the FIFO is empty and reads are ignored.
16 cd GRF control bit This is the control bit for the GRF. When cd is set, either the first

17 – 18 Reserved Reserved Reserved

19 Clr GRF-clear control bit When Clr is set by software/firmware, the FIFO is cleared of all

20 – 22 Reserved Reserved Reserved
23 – 31 Size GRF-size control bits The size is equal to the GRF size number in quadlets.

3–10

When AlE is set, the FIFO has one quadlet in it.

quadlet of a packet is being read from the GRF_Data address, or the
final quadlet (trailer quadlet) of a packet is being read from the GRF
data address. See Section 4 for descriptions of received packet
formats.

entries.

3.3 FIFO Access

Access to all the transmit FIFOs is fundamentally the same; only the address to where the write is made
changes.

3.3.1 General

The TSB12C01A controller FIFO-access address map shown in Figure 3–3 illustrates how the FIFOs are
mapped. The suffix _First denotes a write to the FIFO location where the first quadlet of a packet should
be written when the writer wants the packet to be held in the FIFO until a quadlet is written to an update
location.

The suffix _Continue denotes a write to the FIFO location where the second through n–1 quadlets of a packet
could be written.

The suffix _First&Update denotes a write to the FIFO location where the first quadlet of a packet should be
written when the writer wants the packet to be transmitted as soon as possible.

The suffix _Continue&Update denotes a write to the FIFO location where the second through n quadlets
of a packet could be written when the writer wants the packet to be transmitted as soon as possible. The
last quadlet of a multiple quadlet packet should be written to the FIFO location with the notation
_Continue&Update.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

80h
84h
88h

8Ch

90h
94h

98h
9Ch
A0h
A4h
A8h

ACh

B0h
B4h
B8h

BCh

C0h
C4h
C8h

CCh

ATF_First

ATF_Continue

Reserved

ATF_Continue & Update

ITF_First

ITF_Continue

Reserved

ITF_Continue & Update

Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved

GRF Data

Reserved
Reserved
Reserved

Figure 3–3. TSB12C01A Controller-FIFO-Access Address Map

3–11

3.3.2 ATF Access

The procedure to access to the ATF is as follows:

1. Write the first quadlet of the packet to ATF location 80h: the data is not confirmed for transmission.

2. Write the second n–1 quadlets of the packet to ATF location 84h: the data is not confirmed for
transmission.

3. Write the final quadlet of the packet to ATF location 8Ch: the data is confirmed for transmission.
If the first quadlet of a packet is not written to the A TF_First address, the transmitter enters a state

denoted by an ATStuck interrupt. An underflow of the ATF also causes an ATStuck interrupt.
When this state is entered, no asynchronous packets can be sent until the A TF is cleared via the
CLR ATF control bit. Isochronous packets can be sent while in this state.

Ack code = 0000b is reserved, however, the TSB12C01A uses ATAck code = 0000b to indicate
that no acknowledgement was received. For example, if an asynchronous write is addressed to a
nonexistent address, the TSB12C01 waits until a time out occurs and then sets ATAck (in the
node address register) to 0000b. After the asychonous command is sent, the sender reads
ATAck. If ATAck = 0000b, then a time out has occurred (i.e., no response from any node was
received).

ATF access example:

The first quadlet of n quadlets is written to A TF location 80h. Quadlets (2 to n-1) are written to ATF
location 84h. The last quadlet (nth) is written to A TF location 8Ch. If the A TFEmpty bit is true, it is
set to false and the TSB12C01A requests the phy layer to arbitrate for the bus. T o ensure that an
A TF underflow condition does not occur, loading of the ATF in this manner is suggested.

After loading the ATF with an asychronous packet and sending it, the software driver needs to
wait until the TxRdy bit (bit 5) of the Interrupt register is set to 1 before reading ATAck. When
TxRdy is set to 1, this indicates that the transmitter has received an ACK or time out. So the
correct ATAck can then be read from the node address register. In order to receive the next Ack
code, the TxRdy bit needs to be cleared to 0.

3.3.3 ITF Access

The procedure to access to the ITF is as follows:

1. Write to ITF location 90h: the data is not confirmed for transmission (first quadlet of the packet).

2. Write to ITF location 94h: the data is not confirmed for transmission (second n–1 quadlets of the
packet).

3. Write to ITF location 98h: the data is confirmed for transmission (first quadlet of the packet). The
read logic sees all data written to the FIFO since the last confirm (update).

4. Write to ITF location 9Ch: the data is confirmed for transmission (second n quadlet of the packet).
If the first quadlet of a packet is not written to the ITF_First or ITF_First&Update, the transmitter

enters a state denoted by an ITStuck interrupt. An underflow of the ITF also causes an ITStuck
interrupt. When this state is entered, no isochronous packets can be sent until the ITF is cleared
by the CLR ITF control bit. Asynchronous packets can be sent while in this state.

ITF access example:

The first quadlet of n quadlets is written to ITF location 90h. Quadlets (2 to n-1) are written to ITF
location 94h. The last quadlet (nth) is written to ITF location 9Ch. If the ITFEmpty is true, it is set to
false and the TSB12C01A requests the phy layer to arbitrate for the bus. To ensure that an ITF
underflow condition does not occur, loading of the ITF in this manner is suggested.

3.3.4 General-Receive-FIFO (GRF)

Access to the GRF is done with a read from the GRF, which requires a read from address C0h.

3–12

3.3.5 RAM Test Mode

The purpose of RAM test mode is to test the RAM with writes and reads. During RAM test mode, RAM, which
makes up the A TF , ITF , and GRF, is accessed directly from the host bus. Different data is written to and read
back from the RAM and compared with what was expected to be read back. A TF status, ITF status, and GRF
status are not changed during RAM test mode, but the stored data in RAM is changed by any write
transaction. To enable RAM test mode, set regRW bit and RAMTest bit of the diagnostics register. Before
beginning any read or write to the RAM, the Adr_clr bit of the diagnostics register should be set to clear the
internal RAM address counter. This action also clears the Adr_clr bit.

During RAM test mode, the host bus address should be 80h. The first host bus transaction (either read or
write) accesses location 0 of the RAM. The second host bus transaction accesses location 1 of the RAM.
The nth host bus transaction accesses location n–1 of the RAM. After each transaction, the internal RAM
address counter is incremented by one.

The RAM has 512 locations with each location containing 33 bits. The most significant bit is the control bit.
When the control bit is set, that indicates the quadlet is the start of the packet. In order to set the control bit,
Control-bit1 of the diagnostics register has to be set. In order to clear the control bit, Control_bit1 of the
diagnostics register has to be cleared. When a write occurs, the 32 bits of data from the host bus is written
to the low order 32 bits of the RAM and the value in Control-bit1 is written to the control bit. When a read
occurs, the low order 32 bits of RAM are sent to the host data bus and the control bit is compared to
Control_bit1. If the control bit and Control_bit1 do not match, Control_bit_err of the diagnostics register is
set. This does not stop operation and another read or write can immediately be transmitted. To clear
Control_bit_err, set Adr_clr of the diagnostics register, or transact another write.

3–13

3–14

4 TSB12C01A Data Formats

The data formats for transmission and reception of data are shown in the following sections. The transmit
format describes the expected organization of data presented to the TSB12C01A at the host-bus interface.
The receive formats describe the data format that the TSB12C01A presents to the host-bus interface.

4.1 Asynchronous Transmit (Host Bus to TSB12C01A)

Asynchronous transmit refers to the use of the asynchronous-transmit FIFO (ATF) interface. The
general-receive FIFO (GRF) is shared by asynchronous data and isochronous data. There are two basic
formats for data to be transmitted and received. The first is for quadlet packets, and the second is for block
packets. For transmits, the FIFO address indicates the beginning, middle, and end of a packet. For receives,
the data length, which is found in the header of the packet, determines the number of bytes in a block packet.

4.1.1 Quadlet Transmit

The quadlet-transmit format is shown in Figure 4–1. The first quadlet contains packet control information.
The second and third quadlets contain the 64-bit, quadlet-aligned address. The fourth quadlet is data used
only for write requests and read responses. For read requests and write responses, the quadlet data field
is omitted.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

spd tLabel rt tCode priority

destinationID destinationOffsetHigh

destinationOffsetLow

quadlet data (for write request and read response)

Figure 4–1. Quadlet-Transmit Format

T able 4–1. Quadlet-Transmit Format

FIELD NAME DESCRIPTION

spd This field indicates the speed at which this packet is to be sent. 00 = 100 Mb/s, 01 = 200 Mb/s,

tLabel This field is the transaction label, which is a unique tag for each outstanding transaction

rt The retry code for this packet is: 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB.
tCode tCode is the transaction code for this packet (see Table 6–10 of IEEE 1394-1995 standard).
priority The priority level for this packet. For cable implementation, the value of the bits must be 0.

destinationID This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the

destination OffsetHigh,
destination OffsetLow

quadlet data For write requests and read responses, this field holds the data to be transferred. For write

and 10 = 400 Mb/s, and 11 is undefined for this implementation.

between two nodes. This is used to pair up a response packet with its corresponding request
packet.

For backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE 1394-1995
standard.

destination node address of this packet.
The concatenation of these two fields addresses a quadlet in the destination nodes address

space. This address must be quadlet aligned (modulo 4).

responses and read requests, this field is not used and should not be written into the FIFO.

4–1

4.1.2 Block Transmit

The block-transmit format is shown in Figure 4–2. The first quadlet contains packet-control information. The
second and third quadlets contain the 64-bit address. The first 16 bits of the fourth quadlet contains the
dataLength field. This is the number of bytes of data in the packet. The remaining 16 bits represent the
extended_tCode field. (See Table 6–11 of the IEEE 1394-1995 standard for more information on
extended_tCodes.) The block data, if any , follows the extended_tCode. Block write responses are identical
to the quadlet write response and use the format described in subsection 4.1.3.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

spd tLabel rt tCode priority

destinationID destinationOffsetHigh

destinationOffsetLow

dataLength extended_tCode

block data

Figure 4–2. Block-Transmit Format

T able 4–2. Block-Transmit Format Functions

FIELD NAME DESCRIPTION

spd This field indicates the speed at which this packet is to be sent. 00 = 100 Mb/s, 01 = 200 Mb/s,

tLabel This field is the transaction label, which is a unique tag for each outstanding transaction

rt The retry code for this packet is 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB.
tCode tCode is the transaction code for this packet (see Table 6–10 of IEEE 1394-1995 standard).
priority The priority level for this packet. For cable implementation, the value of the bits must be 0.

destinationID This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the

destination OffsetHigh,
destination OffsetLow

dataLength The number of bytes of data to be transmitted in the packet.
extended_tCode This field is the block extended_tCode to be performed on the data in this packet. See Table

block data The data to be sent. If dataLength is 0, no data should be written into the FIFO for this field.

and 10 = 400 Mb/s, and 11 is undefined for this implementation.

between two nodes. This is used to pair up a response packet with its corresponding request
packet.

For backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE 1394-1995
standard.

node address to which this packet is being sent.
The concatenation of these two fields addresses a quadlet in the destination node’s address

space. This address must be quadlet aligned (modulo 4). The upper four bits of the
destination OffsetHigh field are used as the response code for lock-response packets and
the remaining bits are reserved.

6–11 of the IEEE 1394-1995 standard.

Regardless of the destination or source alignment of the data, the first byte of the block must
appear in byte 0 of the first quadlet.

4.1.3 Quadlet Receive

The quadlet-receive format is shown in Figure 4–3. The first 16 bits of the first quadlet contain the destination
node and bus id, and the remaining 16 bits contain packet-control information. The first 16 bits of the second

4–2

quadlet contain the node and bus ID of the source, and the remaining 16 bits of the second and third quadlets
contain the 48-bit, quadlet-aligned destination offset address. The fourth quadlet contains data that was
used by write requests and read responses. For read requests and write responses, the quadlet data field
is omitted. The last quadlet contains packet-reception status, added by the TSB12C01A.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

destinationID

sourceID destinationOffsetHigh

destinationOffsetLow

quadlet data (for write request and read response)

spd

tLabel rt tCode priority

ackSent

Figure 4–3. Quadlet-Receive Format

T able 4–3. Quadlet-Receive Format Functions

FIELD NAME DESCRIPTION

destinationID This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the

tLabel This field is the transaction label, which is a unique tag for each outstanding transaction

rt The retry code for this packet is 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB.
tCode tCode is the transaction code for this packet. (See Table 6–10 of the IEEE 1394-1995

priority The priority level for this packet. For cable implementation, the value of the bits must be zero.

sourceID This is the node ID of the sender of this packet.
destination OffsetHigh,

destination OffsetLow

quadlet data For write requests and read responses, this field holds the transferred data. For write

spd This field indicates the speed at which this packet was sent. 00 = 100 Mb/s, 01 = 200 Mb/s,

ackSent This field holds the acknowledge sent by the receiver for this packet. (See T able 6–13 in the

node address to which this packet is being sent.

between two nodes. This is used to pair up a response packet with its corresponding request
packet.

standard).

For backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the IEEE 1394-1995
standard.

The concatenation of these two fields addresses a quadlet in the destination node’s address
space. This address must be quadlet aligned (modulo 4). (The upper four bits of the
destination OffsetHigh field are used as the response code for lock-response packets, and
the remaining bits are reserved.)

responses and read requests, this field is not present.

10 = 400 Mb/s, and 11 is undefined for this implementation.

draft standard.)

4.1.4 Block Receive

The block-receive format is shown in Figure 4–4. The first 16 bits of the first quadlet contain the node and
bus ID of the destination node, and the last 16 bits contain packet-control information. The first 16 bits of
the second quadlet contain the node and bus ID of the source node, and the last 16 bits of the second
quadlet and all of the third quadlet contain the 48-bit, quadlet-aligned destination offset address. All
remaining quadlets, except for the last one, contain data that is used only for write requests and read

4–3

responses. For block read requests and block write responses, the data field is omitted. The last quadlet
contains packet-reception status.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

destinationID

sourceID destinationOffsetHigh

destinationOffsetLow

dataLength extended_tCode

block data (if any)

spd

tLabel rt tCode priority

ackSent

Figure 4–4. Block-Receive Format

T able 4–4. Block-Receive Format Functions

FIELD NAME DESCRIPTION

destinationID This is the concatenation of the 10-bit bus number and the 6-bit node number that forms the

tLabel This field is the transaction label, which is a unique tag for each outstanding transaction

rt The retry code for this packet is 00 = new, 01 = retry_X, 10 = retryA, and 11 = retryB.
tCode tCode is the transaction code for this packet. (See Table 6–10 of the IEEE 1394-1995

priority This field contains the priority level for this packet. For cable implementation, the value of the

sourceID This is the node ID of the sender of this packet.
destination OffsetHigh,

destination OffsetLow

dataLength For write request, read responses, and locks, this field indicates the number of bytes being

extended_tCode The block extended_tCode to be performed on the data in this packet. See Table 6–1 1 of the

block data This field contains any data being transferred for this packet. Regardless of the destination

spd This field indicates the speed at which this packet was sent. 00 = 100 Mb/s, 01 = 200 Mb/s,

ackSent This field holds the acknowledge sent by the receiver for this packet.

node address to which this packet is being sent.

between two nodes. This is used to pair up a response packet with its corresponding request
packet.

standard).

bits must be zero. For backplane implementation, see clause 5.4.1.3 and 5.4.2.1 of the
IEEE 1394-1995 standard.

The concatenation of these two fields addresses a quadlet in the destination node’s address
space. This address must be quadlet aligned (modulo 4). The upper four bits of the
destination OffsetHigh field are used as the response code for lock-response packets and
the remaining bits are reserved.

transferred. For read requests, this field indicates the number of bytes of data to be read. A
write-response packet does not use this field. Note that the number of bytes does not include
the head, only the bytes of block data.

IEEE 1394-1995 standard.

address or memory alignment, the first byte of the data appears in byte 0 of the first quadlet
of this field. The last quadlet of this field is padded with zeros out to four bytes, if necessary.

10 = 400 Mb/s, and 11 is undefined for this implementation.

4–4

4.2 Isochronous Transmit (Host Bus to TSB12C01A)

The format of the isochronous-transmit packet is shown in Figure 4–5. The data for each channel must be
presented to the isochronous-transmit FIFO interface in this format in the order that packets are to be sent.
The transmitter sends any packets available at the isochronous-transmit interface immediately following
reception or transmission of the cycle-start message.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

dataLength

TAG

isochronous data

chanNum spd sy

Figure 4–5. Isochronous-Transmit Format

T able 4–5. Isochronous-Transmit Functions

FIELD NAME DESCRIPTION

dataLength This field indicates the number of bytes in this packet
TAG This field indicates the format of data carried by the isochronous packet (00 = formatted, 01 – 11

chanNum This field carries the channel number with which this data is associated.
spd This field contains the speed at which to send this packet.
sy This field carries the transaction layer-specific synchronization bits.
isochronous data This field contains the data to be sent with this packet. The first byte of data must appear in byte

are reserved).

0 of the first quadlet of this field. If the last quadlet does not contain four bytes of data, the unused
bytes should be padded with zeros.

4.3 Isochronous Receive (TSB12C01A to Host Bus)

The format of the isochronous-receive data is shown in Figure 4–6. The data length, which is found in the
header of the packet, determines the number of bytes in an isochronous packet.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

dataLength

isochronous data

TAG

spd

Figure 4–6. Isochronous-Receive Format

chanNum tCode sy

errCode

4–5

T able 4–6. Isochronous-Receive Functions

FIELD NAME DESCRIPTION

dataLength This field indicates the number of bytes in this packet
TAG This field indicates the format of data carried by isochronous packet (00 = formatted, 01 – 11 are

chanNum This field contains the channel number with which this data is associated
tCode This field carries the transaction code for this packet (tCode = Ah).
sy This field carries the transaction layer-specific synchronization bits.
isochronous data This field has the data to be sent with this packet. The first byte of data must appear in byte 0 of

spd This field indicates the speed at which this packet was sent.
errCode This field indicates whether this packet was received correctly. The possibilities are Complete,

reserved).

the first quadlet of this field. The last quadlet should be padded with zeros.

DataErr, or CRCErr and have the same encoding as the corresponding acknowledge codes.

4.4 Snoop

The format of the snoop data is shown in Figure 4–7. The receiver module can be directed to receive any
and all packets that pass by on the serial bus. In this mode, the receiver presents the data received to the
receive-FIFO interface.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

snooped_data

spd ackSnpdsnpStat

Figure 4–7. Snoop Format

T able 4–7. Snoop Functions

FIELD NAME DESCRIPTION

snooped_data This field contains the entire packet received or as much as could be received.
spd This field carries the speed at which this packet was sent.
snpStat This field indicates whether the entire packet snooped was received correctly . A value equal to the

ackSnpd This field indicates the acknowledge seen on the bus after the packet is received.

4–6

complete acknowledge code indicates complete reception. A busyA or busyB acknowledge code
indicates incomplete reception.

4.5 CycleMark

The format of the CycleMark data is shown in Figure 4–8. The receiver module inserts a single quadlet to
mark the end of an isochronous cycle. The quadlet is inserted into the receive-FIFO.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

CyDne

Figure 4–8. CycleMark Format

T able 4–8. CycleMark Functions

FIELD NAME DESCRIPTION

CyDne This field indicates the end of an isochronous cycle.

4.6 Phy Configuration

The format of the phy configuration packet is shown in Figure 4–9. The phy configuration packet transmit
contains two quadlets, which are loaded into the A TF . The first quadlet is written to address 80h. The second
quadlet is written to address 8Ch. The 00E0h in the first quadlet tells the TSB12C01A that this is the phy
configuration packet. The Eh is then replaced with 0h before the packet is transmitted to the phy interface.

There is a possibility of a false header error on receipt of a phy configuration packet. If the first 16 bits of
a phy configuration packet (see Figure 4–9) happen to match the destination identifier of a node (bus
number and node number), the TSB12C01A on that node issues a header error since the node misinterprets
the phy configuration packet as a data packet addressed to the node. The suggested solution to this
potential problem is to assign bus numbers that all have the MS bit set to 1. Since the all-ones case is
reserved for addressing the local bus, this leaves only 51 1 available unique bus identifiers. This is an artifact
of the IEEE 1394-1995 standard.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

00

logical inverse of first 16 bits of first quadlet

root_ID gap_cnt

RT

1110000000000000

1111111111111111

Figure 4–9. Phy Configuration Format

4–7

Table 4–9. Phy Configuration Functions

FIELD NAME DESCRIPTION

00 This field is the phy configuration packet identifier.
root_ID This field is the physical_ID of the node to have its force_root bit set (only meaningful when

†

R

†

T

gap_cnt This field contains the new value for PHY_CONFIGURATION.gap_count for all nodes. This

†

A phy configuration packet with R = 0, and T = 0 is reserved and is ignored when received.

R is set).
When R is set, the force-root bit of the node identified in root_ID is set and the force_root bit

of all other nodes are cleared. When R is cleared, root_ID is ignored.
When T is set, the PHY_CONFIGURATION.gap_count field of all the nodes is set to the value

in the gap_cnt field.

value goes into effect immediately upon receipt and remains valid after the next bus reset.
After the second reset, gap_cnt is set to 63h unless a new phy configuration packet is
received.

4.7 Link-On

The format of the link-on packet is shown in Figure 4–10. The link-on packet transmit contains two quadlets,
which are loaded into the A TF. The first quadlet is written to address 80h. The second quadlet is written to
address 8Ch. The 00E0h in the first quadlet tells the TSB12C01A that this is the link-on packet. The Eh is
then replaced with 0h before the packet is transmitted to the phy interface.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

01 1110000000000000

logical inverse of first 16 bits of first quadlet

root_ID

00000000

1111111111111111

Figure 4–10. Link-On Format

T able 4–10. Link-On Functions

FIELD NAME DESCRIPTION

01 This field is the link-on packet identifier.
root_ID This field is the physical_ID of the node to have its force_root bit set.

4–8

4.8 Receive Self-ID

The format of the receive self-ID packet is shown in Figure 4–1 1. The first quadlet is the packet header with
the special tCode of Eh. The quadlets that follow are a concatenation of all received self-ID packets. The
last quadlet contains the final packet status. See IEEE 1394-1995 standard, paragraph 4.3.4.1, for
additional information about self-ID packets.

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

tCode priority

Self-ID Packet Data

spd

ackSent

Figure 4–11. Receive Self-ID Format

T able 4–11. Isochronous-Receive Functions

FIELD NAME DESCRIPTION

tCode This field carries the transaction code for this packet (tCode = Eh).
priority This field carries the priority level for this packet.
Self-ID packet data This field contains a concatenation of all the Self-ID packets received.
spd This field indicates the speed at which this packet was sent (00 = 100 Mbits/s, 01 = 200 Mbits/s,

ackSent This field holds the acknowledge sent by the receiver for this packet.

10 = 400 Mbits/s, and 11 is undefined).

4–9

4–10

5 Electrical Characteristics

PACKAGE

A

FACTOR

A

PARAMETER

TEST

UNIT

5.1 Absolute Maximum Ratings Over Free-Air Temperature Range (Unless
Otherwise Noted)

Supply voltage range, V
Input voltage range, at any input, V
Output voltage range, V
Input clamp current, I

Continuous total power dissipation See Maximum Dissipation Rating Table. . . . . . . . . .

Output clamp current, I
Operating free-air temperature range, T

Storage temperature range, T
Case temperature for 10 seconds, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These
are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated
under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for
extended periods may affect device reliability.

NOTES: 1. All voltage values are with respect to GND.

‡

Power dissipation of package based on an absolute maximum junction temperature of 150°C.

2. This applies to all inputs.

3. This applies to all outputs.

T

≤ 25°C

POWER RATING

PZ

WN

2119 mW

2404 mW

†

(see Note 1) –0.5 V to 6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . .

CC

–0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

(VI < 0 or VI > VCC) (see Note 2) ±20 mA. . . . . . . . . . . . . . . . . .

IK

(VO < 0 or VO > VCC) (see Note 3) ±20 mA. . . . . . . . . . . . . .

OK

–0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . .

I

: A suffix 0°C to 70°C. . . . . . . . . . . . . . . . . . . . .

A

AI suffix –40°C to 85°C. . . . . . . . . . . . . . . . . .

AM suffix –55°C to 125°C. . . . . . . . . . . . . . . .

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

MAXIMUM DISSIPATION RATING T ABLE

DERATING

ABOVE TA = 25°C

16.9 mW/°C

19.2 mW/°C

260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

C

‡

T

= 70°C T

POWER RATINGAPOWER RATINGAPOWER RATING

1356 mW
1538 mW

= 85°C T

1102 mW
1250 mW

= 125°C

—

481 mW

PACKAGE THERMAL CHARACTERISTICS

TEST

CONDITIONS

Junction-to-ambient thermal

R

θJA

impedance
Junction-to-case thermal

R

θJC

impedance

§

Thermal characteristics very depending on die and leadframe pad size as well as mold compound. These values
represent typical die and pad sizes for the respective packages. The R value decreases as the die or pad sizes
increases. Thermal values represent PWB bands with minimal amounts of metal.

Board mounted,
No air flow

PZ PACKAGE WN PACKAGE

MIN NOM MAX MIN NOM MAX

§

59 52 °C/W

13 8 °C/W

5–1

5.2 Recommended Operating Conditions

Clock frequenc

MH

†

A

CoOut ut ca acitance

F

MIN NOM MAX UNIT

Supply voltage, V
Input voltage, V
High-level input voltage, V
Low-level input voltage, V

Virtual junction temperature, T

Operating free-air temperature, T

†

Actual junction temperature is a function of ambient temperature, package selection, power dissipation, and air flow.
Customer is responsible for maintaining the junction temperature within the recommended operating conditions.
Operating device at junction temperatures higher than what is recommended will cause device to operate outside the
characterization models established during device simulation and may affect the reliability performance.

CC

I

IH

IL

y

J

BCLK 25
SCLK 49.152
TSB12C01A 115
TSB12C01AI 125
TSB12C01AM 150
TSB12C01A 0 70
TSB12C01AI –40 85

A

TSB12C01AM –55 125

4.75 5 5.25 V
0 V
2 V
0 0.8 V

CC
CC

V
V

°C

°C

5.3 Electrical Characteristics Over Recommended Ranges of Supply Voltage
and Operating Free-Air Temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT

V

High-level output voltage IOH = –4 mA VCC– 0.8 V

OH

V

Low-level output voltage IOL = 4 mA 0.5 V

OL

V

Positive-going input threshold voltage 2 V

IT+

V

Negative-going input threshold voltage 0.8 V

IT–

I

Low-level input current VI = GND –1 µA

IL

I

High-level input current VI = V

IH

I

High-impedance-state output current

OZ

I

Supply current

CC

PZ package
input terminals

WN package
input terminals

C

Input capacitance

i

p

p

†

All typical values are at VCC = 5 V and TA = 25°C.

NOTE 4: All outputs are in the high-impedance state.

PZ package
bidirectional
terminals

WN package
bidirectional
terminals

PZ package 8
WN package 7

CC

VO = VCC or GND,
See Note 4

No load on outputs,
SCLK = 49.152 MHz
BCLK = 25 MHz

VCC = 5 V,
TA = 25°C

150 mA

13

1 µA

±10 µA

5

6

pF

7

p

z

5–2

5.4 Host-Interface Timing Requirements, TA = 25°C (see Note 5)

PARAMETER MIN MAX UNIT

t

c1

t

w1(H)

t

w1(L)

t

su1

t

h1

t

su2

t

h2

t

su3

t

h3

t

su4

t

h4

NOTE 5: These parameters are not production tested.

Cycle time, BCLK (see Figure 6–1) 30 111 ns
Pulse duration, BCLK high (see Figure 6–1) 10 ns
Pulse duration, BCLK low (see Figure 6–1) 10 ns
Setup time, DATA0 – DATA31 valid before BCLK↑ (see Figure 6–2) 4 ns
Hold time, DATA0 – DATA31 invalid after BCLK↑ (see Figure 6–2) 2 ns
Setup time, ADDR0 – ADDR7 valid before BCLK↑ (see Figures 6–2 and 6–3) 12 ns
Hold time, ADDR0 – ADDR7 invalid after BCLK↑ (see Figures 6–2 and 6–3) 2 ns
Setup time, CS↓ before BCLK↑ (see Figures 6–2 and 6–3) 12 ns
Hold time, CS↑ after BCLK↑ (see Figures 6–2 and 6–3) 2 ns
Setup time, WR valid before BCLK↑ (see Figures 6–2 and 6–3) 12 ns
Hold time, WR invalid after BCLK↑ (see Figures 6–2 and 6–3) 2 ns

5.5 Host-Interface Switching Characteristics Over Operating Free-Air

Temperature Range of 0°C to 70°C, C

PARAMETER MIN MAX UNIT

t

Delay time, BCLK↑ to CA↓ (see Figure 6–2) 4 16 ns

d1

t

Delay time, BCLK↑ to CA↑ (see Figure 6–2) 4 16 ns

d2

t

Delay time, BCLK↑ to DATA0 – DATA31 valid (see Figure 6–3 and Note 5) 4 24 ns

d3

t

Delay time, BCLK↑ to DATA0 – DATA31 invalid (see Figure 6–3 and Note 5) 4 24 ns

d4

NOTE 5: These parameters are not production tested.

= 45 pF (unless otherwise noted)

L

5.6 Phy-Interface Timing Requirements Over Operating Free-Air

Temperature Range of 0°C to 70°C (see Note 5)

PARAMETER MIN MAX UNIT

t

c2

t

w2(H)

t

w2(L)

t

su5

t

h5

t

su6

t

h6

NOTE 5: These parameters are not production tested.

Cycle time, SCLK (see Figure 6–4) 20.24 20.45 ns
Pulse duration, SCLK high (see Figure 6–4) 9 ns
Pulse duration, SCLK low (see Figure 6–4) 9 ns
Setup time, D0 – D7 valid before SCLK↑ (see Figure 6–6) 6 ns
Hold time, D0 – D7 invalid after SCLK↑ (see Figure 6–6) 1 ns
Setup time, CTL0 – CTL1 valid before SCLK↑ (see Figure 6–6) 6 ns
Hold time, CTL0 – CTL1 invalid after SCLK↑ (see Figure 6–6) 1 ns

5–3

5.7 Phy-Interface Switching Characteristics Over Operating Free-Air

Temperature Range of 0°C to 70°C, C

= 45 pF (unless otherwise noted)

L

(see Note 5)

PARAMETER MIN MAX UNIT

t

Delay time, SCLK↑ to D0 – D7 valid (see Figure 6–5) 3 14 ns

d5

t

Delay time, SCLK↑ to D0 – D7↑↓ (see Figure 6–5) 3 14 ns

d6

t

Delay time, SCLK↑ to D0 – D7 invalid (see Figure 6–5) 3 14 ns

d7

t

Delay time, SCLK↑ to CTL0 – CTL1 valid (see Figure 6–5) 3 14 ns

d8

t

Delay time, SCLK↑ to CTL0 – CTL1↑↓ (see Figure 6–5) 3 14 ns

d9

t

Delay time, SCLK↑ to CTL0 – CTL1 invalid (see Figure 6–5) 3 14 ns

d10

t

Delay time, SCLK↑ to LREQ↑↓ (see Figure 6–7) 3 14 ns

d11

NOTE 5: These parameters are not production tested.

5.8 Miscellaneous Timing Requirements Over Operating Free-Air

Temperature Range of 0°C to 70°C (see Figure 6–9 and Note 5)

PARAMETER MIN MAX UNIT

t

c3

t

w3(H)

t

w3(L)

NOTE 5: These parameters are not production tested.

Cycle time, CYCLEIN 124.99 125.01 µs
Pulse duration, CYCLEIN↑ 62 µs
Pulse duration, CYCLEIN↓ 62 µs

5.9 Miscellaneous Signal Switching Characteristics Over Operating Free-Air

Temperature Range of 0°C to 70°C (see Note 5)

PARAMETER MIN MAX UNIT

t

Delay time, SCLK↑ to INT↓ (see Figure 6–8) 4 18 ns

d12

t

Delay time, SCLK↑ to INT↑ (see Figure 6–8) 4 18 ns

d13

t

Delay time, SCLK↑ to CYCLEOUT↑ (see Figure 6–10) 4 16 ns

d14

t

Delay time, SCLK↑ to CYCLEOUT↓ (see Figure 6–10) 4 16 ns

d15

NOTE 5: These parameters are not production tested.

5–4

6 Parameter Measurement Information

BCLK

BCLK

DATA0 – DATA31

ADDR0 – ADDR7

CS

50% 50%

t

w1(H)

50% 50%

t

su3

50% 50%

50%

t

w1(L)

t

c1

Figure 6–1. BCLK Waveform

50%

t

su1

t

su2

t

h3

t

su4

t

h1

t

h2

t

h4

WR

t

d1

(see Note A)

NOTE A: When back-to-back write cycles are done, a maximum of 9 BCLK cycles may be required after the falling edge

CA

of CS

before CA is asserted (low). DATA0 – DATA31, ADDR0 – ADDR7, and WR need to remain valid until

CA

is asserted (low). These cycles are to synchronize data passing between the BCLK and SCLK clock

domains.

50% 50%

t

d2

Figure 6–2. Host-Interface Write-Cycle Waveforms

6–1

ÎÎÎÎ

ООООО

BCLK

DATA0 –

DATA31

50%

50%

t

d3

50%

t

d4

t

su2

t

h2

ADDR0 –

ADDR7

t

CS

su3

50% 50%

t

su4

t

h3

t

h4

WR

t

(see Note A)

CA

d1

50% 50%

t

d2

NOTE A: When back-to-back read cycles are done, a maximum of 9 BCLK cycles may be required after the falling edge

of CS

and before CA is asserted (low). ADDR0 – ADDR7 and WR need to remain valid until CA is asserted

(low).

Figure 6–3. Host-Interface Read-Cycle Waveforms

SCLK

50% 50%

t

w2(H)

50%

t

w2(L)

CTL0 – CTL1

6–2

SCLK

D0 – D7

t

c2

Figure 6–4. SCLK Waveform

50% 50% 50%

t

d5

t

d8

t

d6

t

d9

Figure 6–5. TSB12C01A-to-Phy-Layer Transfer Waveforms

t

t

d7

d10

SCLK

D0 – D7

CTL0 – CTL1

50%

t

t

su6

su5

t

h5

t

h6

Figure 6–6. Phy Layer-to-TSB12C01A Transfer Waveforms

SCLK

LREQ

t

50%

d11

Figure 6–7. TSB12C01A Link-Request-to-Phy-Layer Waveforms

SCLK

t

d12

50%

50%INT 50%

Figure 6–8. Interrupt Waveform

50%

t

d13

6–3

CYCLEIN

50% 50%

t

w3(H)

50%

t

w3(L)

t

c3

Figure 6–9. CYCLEIN Waveform

SCLK

CYCLEIN

CYCLEOUT

t

d14

50% 50%

Figure 6–10. CYCLEIN and CYCLEOUT Waveforms

t

d15

50%50%

6–4

7 TSB12C01A to 1394 Phy Interface Specification

7.1 Introduction

This chapter provides an overview of a TSB12C01A to the phy interface. The information that follows can
be used as a guide through the process of connecting the TSB12C01A to a 1394 physical-layer device. The
part numbers referenced, the TSB11C01 and the TSB12C01A, represent the Texas Instruments
implementation of the phy (TSB11C01) and link (TSB12C01A) layers of the IEEE 1394-1995 standard.

The specific details of how the TSB11C01 device operates is not discussed in this document. Only those
parts that relate to the TSB12C01A phy-link interface are mentioned.

7.2 Assumptions

The TSB12C01A is capable of supporting 100 Mb/s, 200 Mb/s and 400 Mb/s phy-layer devices. For that
reason, this document describes an interface to a 400-Mb/s (actually 393.216-Mb/s) device. To support
lower-speed phy layers, adjust the width of the data bus by two terminals per 100 Mb/s. For example, for
100-, 200- and 400-Mb/s devices, the data bus is 2, 4, and 8 bits wide respectively . The width of the CTL
bus and the clock rate between the devices, however, does not change regardless of the transmission speed
that is used.

Finally, the 1394 phy layer has control of all bidirectional terminals that run between the phy layer and
TSB12C01A. The TSB12C01A can drive these terminals only after it has been given permission by the phy
layer. A dedicated request terminal (LREQ) is used by the TSB12C01A for any activity that the designer
wishes to initiate.

7.3 Block Diagram

The functional block diagram of the TSB12C01A to phy layer is shown in Figure 7–1.

1394
Link

Layer

TSB12C01A

NOTE A: See T able 2–2 for signal definition.

D0 – D7

CTL0 – CTL1

LREQ

SCLK

ISO ISO

1394

Phy-Layer

Device

Figure 7–1. Functional Block Diagram of the TSB12C01A to Phy Layer

7.4 Operational Overview

The four operations that can occur in the phy-link interface are request, status, transmit, and receive. With
the exception of the request operation, all actions are initiated by the phy layer.

The CTL0 – CTL1 bus is encoded as shown in the following sections.

7–1

7.4.1 Phy Interface Has Control of the Bus

Table 7–1. Phy Interface Control of Bus Functions

CTL0,CTL1 NAME DESCRIPTION OF ACTIVITY

00 Idle No activity is occurring (this is the default mode).
01 Status Status information is being sent from the phy layer to the TSB12C01A.
10 Receive An incoming packet is being sent from the phy layer to the TSB12C01A.
11 Transmit The TSB12C01A has been given control of the bus to send an outgoing packet.

7.4.2 TSB12C01A Has Control of the Bus

The TSB12C01A has control of the bus after receiving permission from the phy layer.

Table 7–2. TSB12C01A Control of Bus Functions

CTL0, CTL1 NAME DESCRIPTION OF ACTIVITY

00 Idle The TSB12C01A releases the bus (transmission has been completed).
01 Hold The TSB12C01A is holding the bus while data is being prepared for transmission, or the

10 Transmit An outgoing packet is being sent from the TSB12C01A to phy layer.
11 Reserved None

TSB12C01A wants to send another packet without arbitration.

7.5 Request

A serial stream of information is sent across the LREQ terminal whenever the TSB12C01A needs to request
the bus or access a register that is located in the phy layer. The size of the stream varies depending on
whether the transfer is a bus request, a read command, or a write command. Regardless of the type of
transfer, a start bit of 1 is required at the beginning of the stream and a stop bit of 0 is required at the end
of the stream.

T able 7–3. Request Functions

NUMBER

of BITS

7 Bus Request
9 Read Register Request

17 Write Register Request

NAME

7.5.1 LREQ Transfer

The definition of the bits in the three different types of transfers are shown in Table 7–4.

7.5.1.1 TSB12C01A Bus Request

Table 7–4. Bus-Request Functions (Length of Stream: 7 Bits)

BIT(S) NAME DESCRIPTION

0 Start Bit Start bit indicates the beginning of the transfer (always set).

1–3 Request Type Request type indicates the type of bus request (see T able 7–7 for the encoding of this

4–5 Request Speed Request speed indicates the speed at which the phy interface sends the packet for this

6 Stop Bit Stop bit indicates the end of the transfer (always cleared).

7–2

field).

particular request (see Table 7–8 for the encoding of this field).

7.5.1.2 TSB12C01A Read-Register Request

Table 7–5. Read-Register Request Functions (Length of Stream: 9 Bits)

BIT(S) NAME DESCRIPTION

0 Start Bit Start bit indicates the beginning of the transfer (always set).

1–3 Request Type Request type indicates the type of request function (see Table 7–7 for the encoding of this

4–7 Address These bits contain the address of the phy register to be read.

8 Stop Bit Stop bit indicates the end of the transfer (always cleared).

field).

7.5.1.3 TSB12C01A Write-Register Request

Table 7–6. Write-Register Request (Length of Stream: 17 Bits)

BIT(S) NAME DESCRIPTION

0 Start Bit Start bit indicates the beginning of the transfer (always set).
1–3 Request Type Request type indicates the type of request (see Table 7–7 for the encoding of this field).
4–7 Address These bits contain the address of the phy register to be written to.

8–15 Data These bits contain the data that is to be written to the specified register address.

16 Stop Bit Stop bit indicates the end of the transfer (always cleared).

7.5.1.4 Request-Type Field for TSB12C01A Request

T able 7–7. TSB12C01A Request Functions

LREQ1 –

LREQ3

000 TakeBus Immediate request. Upon detection of an idle, take control of the bus immediately (no

001 IsoReq Isochronous request. IsoReq arbitrates for control of the bus after an isochronous gap.
010 PriReq Priority request. PriReq arbitrates for control of the bus after a fair gap and ignores fair

011 FairReq Fair request. FairReq arbitrates for control of the bus after a fair gap and uses fair protocol.
100 RdReg Read request. RdReg returns the specified register contents through a status transfer.
101 WrReg Write request. WrReg writes to the specified register.

110, 111 Reserved Reserved

NAME DESCRIPTION

arbitration) for asynchronous packet ACK response.

protocol.

7.5.1.5 Request-Speed Field for TSB12C01A Request

T able 7–8. TSB12C01A Request-Speed Functions

LREQ4, LREQ5 DATA RATE

00 100 Mb/s
01 200 Mb/s
10 400 Mb/s
11 Reserved

7–3

7.5.2 Bus Request

For fair or priority access, the TSB12C01A requests control of the bus at least one clock after the
TSB12C01A phy interface becomes idle CTL0 – CTL1 = 00, which indicates the physical layer is in an idle
state. If the TSB12C01A senses that CTL0 – CTL1 = 10, then it knows that its request has been lost. This
is true any time during or after the TSB12C01A sends the bus request transfer. Additionally , the phy interface
ignores any fair or priority requests when it asserts the receive state while the TSB12C01A is requesting
the bus. The link then reissues the request one clock after the next interface idle.

The cycle master uses a normal priority request to send a cycle-start message. After receiving a cycle start,
the TSB12C01A can issue an isochronous bus request. When arbitration is won, the TSB12C01A proceeds
with the isochronous transfer of data. The isochronous request is cleared in the phy interface once the
TSB12C01A sends another type of request or when the isochronous transfer has been completed.

The TakeBus request is issued when the TSB12C01A needs to send an acknowledgment after reception
of a packet addressed to it. This request must be issued during packet reception. This is done to minimize
the delay times that a phy interface would have to wait between the end of a packet reception and the
transmittal of an acknowledgment. As soon as the packet ends, the phy interface immediately grants access
of the bus to the TSB12C01A. The TSB12C01A sends an acknowledgment to the sender unless the header
CRC of the packet turns out to be invalid. In this case, the TSB12C01A releases the bus immediately; it is
not allowed to send another type of packet on this grant. To ensure this, the TSB12C01A is forced to wait
160 ns after the end of the packet is received. The phy interface then gains control of the bus and the
acknowledge with the CRC error sent. The bus is then released and allowed to proceed with another
request.

Although highly improbable, it is conceivable that two separate nodes believe that an incoming packet is
intended for them. The nodes then issue a TakeBus request before checking the CRC of the packet. Since
both phys seize control of the bus at the same time, a temporary, localized collision of the bus occurs
somewhere between the competing nodes. This collision would be interpreted by the other nodes on the
network as being a ZZ line state, not a bus reset. As soon as the two nodes check the CRC, the mistaken
node drops its request and the false line state is removed. The only side effect is the loss of the intended
acknowledgment packet (this is handled by the higher layer protocol).

7.5.3 Read/Write Requests

When the TSB12C01A requests to read the specified register contents, the phy interface sends the contents
of the register to the TSB12C01A through a status transfer. When an incoming packet is received while the
phy interface is transferring status information to the TSB12C01A, the phy interface continues to attempt
to transfer the contents of the register until it is successful.

For write requests, the phy interface loads the data field into the appropriately addressed register as soon
as the transfer has been completed. The TSB12C01A is allowed to request read or write operations at any
time.

See Section 7.6, for a more detailed description of the status transfer.

7.6 Status

A status transfer is initiated by the phy interface when it has some status information to transfer to the
TSB12C01A. The transfer is initiated by asserting the following: CTL0 – CTL1 = 01 and D0 – D1 are used
to transmit the status data; see Table 7–9 for status-request functions. D2 – D7 are not used for status
transfers.

The status transfer can be interrupted by an incoming packet from another node. When this occurs, the phy
interface attempts to resend the status information after the packet has been acted upon. The phy interface
continues to attempt to complete the transfer until the information has been successfully transmitted.

NOTE:

There must be at least one idle cycle between consecutive status transfers.

7–4

7.6.1 Status Request

The definition of the bits in the status transfer is shown in Table 7–9.

T able 7–9. Status-Request Functions (Length of Stream: 16 Bits)

BIT(s) NAME DESCRIPTION

0 Arbitration Reset

Gap

1 Fair Gap The fair-gap bit indicates that the phy interface has detected that the bus has been idle

2 Bus Reset The bus reset bit indicates that the phy interface has entered the bus reset state.
3 phy Interrupt The phy interrupt bit indicates that the phy interface is requesting an interrupt to the host.

4–7 Address The address bits hold the address of the phy register whose contents are transferred

8–15 Data The data bits hold the data that is to be sent to the TSB12C01A.

The arbitration-reset gap bit indicates that the phy interface has detected that the bus
has been idle for an arbitration reset gap time (this time is defined in the IEEE 1394-1995
standard). This bit is used by the TSB12C01A in its busy/retry state machine.

for a fair-gap time (this time is defined in the IEEE 1394-1995 standard). This bit is used
by the TSB12C01A to detect the completion of an isochronous cycle.

to the TSB12C01A.

Normally , the phy interface sends just the first four bits of data to the TSB12C01A. These bits are used by
the TSB12C01A state machine. However, if the TSB12C01A initiates a read request (through a request
transfer), then the phy interface sends the entire status packet to the TSB12C01A. Additionally, the phy
interface sends the contents of the register to the TSB12C01A when it has some important information to
pass on. Currently , the only condition where this occurs is after the self-identification process when the phy
interface needs to inform the TSB12C01A of its new node address (physical ID register).

There may be times when the phy interface wants to start a second status transfer. The phy interface first
has to wait at least one clock cycle with the CTL lines idle before it can begin a second transfer.

7.6.2 Transmit

When the TSB12C01A wants to transmit information, it first requests access to the bus through an LREQ
signal. Once the phy interface receives this request, it arbitrates to gain control of the bus. When the phy
interface wins ownership of the serial bus, it grants the bus to the TSB12C01A by asserting the transmit state
on the CTL terminals for at least one SCLK cycle. The TSB12C01A takes control of the bus by asserting
either hold or transmit on the CTL lines. Hold is used by the TSB12C01A to keep control of the bus when
it needs some time to prepare the data for transmission. The phy interface keeps control of the bus for the
TSB12C01A by asserting a data-on state on the bus. It is not necessary for the TSB12C01A to use hold
when it is ready to transmit as soon as bus ownership is granted.

When the TSB12C01A is prepared to send data, it asserts transmit on the CTL lines as well as sends the
first bits of the packet on the D0 – D7 lines (assuming 400 Mb/s). The transmit state is held on the CTL
terminals until the last bits of data have been sent. The TSB12C01A then asserts idle on the CTL lines for
one clock cycle after which it releases control of the interface.

However, there are times when the TSB12C01A needs to send another packet without releasing the bus.
For example, the TSB12C01A may want to send consecutive isochronous packets or it may want to attach
a response to an acknowledgment. To do this, the TSB12C01A asserts hold instead of idle when the first
packet of data has been completely transmitted. Hold, in this case, informs the phy interface that the
TSB12C01A needs to send another packet without releasing control of the bus. The phy interface then waits
a set amount of time before asserting transmit. The TSB12C01A can then proceed with the transmittal of
the second packet. After all data has been transmitted and the TSB12C01A has asserted idle on the CTL
terminals, the phy interface asserts its own idle state on the CTL lines. When sending multiple packets in
this fashion, it is required that all data be transmitted at the same speed. This is required because the
transmission speed is set during arbitration, and since the arbitration step is skipped, there is no way of
informing the network of a change in speed.

7–5

7.6.3 Receive

When data is received by the phy interface from the serial bus, it transfers the data to the TSB12C01A for
further processing. The phy interface asserts receive on the CTL lines and is set to 1 on each D terminal.
The phy interface indicates the start of the packet by placing the speed code on the data bus (see the
following note). The phy interface then proceeds with the transmittal of the packet to the TSB12C01A on
the D lines while still keeping the receive status on the CTL terminals. Once the packet has been completely
transferred, the phy interface asserts idle on the CTL terminals that completes the receive operation.

NOTE:

The speed code sent is a phy-TSB12C01A protocol and not included in the packets
CRC calculation.

SPD = Speed code
D0 => Dn = Packet data

T able 7–10. Speed Code for Receive

D0 – D7 DATA RATE

00xxxxxx
0100xxxx
01010000 400 Mb/s
111111111 Data-on indication

†

The x means transmitted as 0 and ignored by
phy layer.

†

†

100 Mb/s
200 Mb/s

7.7 TSB12C01A to Phy Bus Timing

LREQ2 LREQ3LREQ1LREQ0 LREQn

Figure 7–2. LREQ Timing

Phy

CTL0 – CTL1

Phy

D0 – D7

S(0,1)

NOTE A: Each cell represents one SCLK sample time.

Figure 7–3. Status-Transfer Timing

7–6

S(2,3)

S(4,5)

01 00 0000 01 01 01

S(14,15)

LREQ

00 0000

n–1

CTL0 – CTL1

Phy

00 11 00 ZZ ZZ ZZ ZZ ZZ ZZ ZZ

ZZ

00

Phy

D0 – D7

CTL0 – CTL1

Link

D0 – D7

CTL0 – CTL1

Phy

D0 – D7

CTL0 – CTL1

Link

D0 – D7

NOTE A:

Link

Phy

Link

00 00 00 ZZ ZZ ZZ ZZ ZZ ZZ ZZ

ZZ ZZ ZZ 01 10 10 10 10 00 00

ZZ ZZ ZZ 00 D0 D1 D2 Dn 00 00

ZZ

01

00

SINGLE PACKET

00

00

ZZ

ZZ

CONTINUED PACKET

00 11 00ZZ ZZ ZZ ZZ ZZ ZZ ZZ

00 00 00ZZ ZZ ZZ ZZ ZZ ZZ ZZ

ZZ ZZ ZZ10 10 01 00 01 10 10

ZZ ZZ ZZDn-1 Dn 00 00 00 D0 D1

ZZ = high-impedance state, D0 – Dn = packet data

Figure 7–4. Transmit T iming

00

ZZ

ZZ

ZZ

ZZ

01

00

CTL0 – CTL1

Phy

Phy

D0 – D7

00 10 10 10 10 10 10 00 00

00 FF FF SPD D0 D1 Dn 00 00

Figure 7–5. Receiver Timing

7–7

7–8

8 Mechanical Data

PZ (S-PQFP-G100) PLASTIC QUAD FLATPACK

76

100

0,50

75

0,27
0,17

51

50

26

1

12,00 TYP

14,20

SQ

13,80
16,20

SQ

15,80

25

0,08

M

0,13 NOM

Gage Plane

1,45
1,35

1,60 MAX

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-026

0,05 MIN

0,25

0,75
0,45

Seating Plane

0,08

0°–7°

4040149/B 11/96

8–1

WN (R-GQFP-G100) CERAMIC QUAD FLATPACK

76

100

75

51

50

26

1

0.600 (15,25) TYP

0.755 (19,18)

0.745 (18,92)

0.885 (22,48)

0.875 (22,22)

SQ

SQ

25

0.010 (0,25) TYP

0.025 (0,65)

0.006 (0,16)
NOM

0.140 (3,56)

0.010 (0,25) MIN

0.160 (4,07) MAX

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

8–2

NOM

0°–8°

0.020 (0,51) MIN

Seating Plane

0.004 (0,10)

4081535/A 09/95