Texas Instruments TRF7960A Datasheet

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TRF7960A Multiprotocol Fully Integrated 13.56-MHz RFID Reader/Writer IC

1 Device Overview

1.1 Features

• Completely Integrated Protocol Handling for ISO/IEC 15693, ISO/IEC 18000-3, ISO/IEC 14443A, ISO/IEC 14443B, NFC Forum Device Types 2 to 5, and FeliCa™

• Input Voltage Range: 2.7 VDC to 5.5 VDC

• Programmable Output Power: +20 dBm (100 mW) or +23 dBm (200 mW)

• Programmable I/O Voltage Levels:

1.8 VDC to 5.5 VDC

• Programmable System Clock Frequency Output (RF, RF/2, RF/4)

1.2 Applications

• Secure Access Control

• Product Authentication

• Digital Door Locks

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SLOS732G –JUNE 2011–REVISED MARCH 2020

• Programmable Modulation Depth

• Dual Receiver Architecture With RSSI for Elimination of "Read Holes" and Adjacent Reader System or Ambient In-Band Noise Detection

• Programmable Power Modes for Ultra-Low-Power System Design (Power Down <0.5 µA)

• Parallel or SPI Interface

• Integrated Voltage Regulator for Microcontroller Supply

• Temperature Range: –40°C to 110°C

• 32-Pin QFN Package (5 mm × 5 mm) (RHB)

• Public Transport or Event Ticketing

• Medical Systems

• Remote Sensor Applications

1.3 Description

The TRF7960A device is an integrated analog front-end (AFE) and multiprotocol data-framing device for a

13.56-MHz RFID reader/writer system that supports ISO/IEC 14443 A and B, Sony FeliCa, and ISO/IEC 15693. Built-in programming options make it suitable for a wide range of applications for proximity and vicinity identification systems.

The reader is configured by selecting the desired protocol in the control registers. Direct access to all control registers allows fine tuning of various reader parameters as needed.

The TRF7960A device supports data rates up to 848 kbps with all framing and synchronization tasks for the ISO protocols onboard. The device also supports reader/writer mode for NFC Forum tag types 1, 2, 3, 4, and 5. NFC Forum tag types 2, 3, 4, and 5 are supported with the built-in protocol decoders used in Direct Mode 2. NFC Forum tag type 1 requires the use of Direct Mode 0. Other standards and custom protocols can also be implemented by using Direct Mode 0. Direct Mode 0 lets the user fully control the AFE and also gain access to the raw subcarrier data or the unframed, but already ISO-formatted, data and the associated (extracted) clock signal.

The receiver system has a dual-input receiver architecture to maximize communication robustness. The receivers also include various automatic and manual gain control options. The received signal strength from transponders, ambient sources, or internal levels is available in the RSSI register.

A SPI or parallel interface can be used for the communication between the MCU and the TRF7960A reader. When the built-in hardware encoders and decoders are used, transmit and receive functions use a 12-byte FIFO register. For direct transmit or receive functions, the encoders or decoders can be bypassed so the MCU can process the data in real time.

The TRF7960A device supports a wide supply voltage range of 2.7 V to 5.5 V and data communication levels from 1.8 V to 5.5 V for the MCU I/O interface.

The transmitter has selectable output power levels of 100 mW (+20 dBm) or 200 mW (+23 dBm) equivalent into a 50-Ω load when using a 5-V supply and supports OOK and ASK modulation with selectable modulation depth.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

TRF796xA

MCU

(MSP430 or ARM)

Matching

VDD_X VDD_I/O

TX_OUT

RX_IN 1

RX_IN 2

VSS

VIN

Parallel

or SPI

Supply

2.7 V to 5.5 V

VDD

Crystal

13.56 MHz

XIN

TRF7960A

SLOS732G –JUNE 2011–REVISED MARCH 2020

The built-in programmable auxiliary voltage regulator delivers up to 20 mA to supply an MCU and additional external circuits within the reader system.

To evaluate the latest products in the TRF79xx product family – TRF7970A and TRF7964A – see the NFC

Transceiver Booster Pack. Documentation, Tools, Reference Designs, and Software, Samples

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PART NUMBER PACKAGE BODY SIZE

TRF7960ARHB VQFN (32) 5 mm × 5 mm

(1) For more information, see Section 9, Mechanical Packaging and Orderable Information.

1.4 Application Block Diagram

Figure 1-1 shows a typical application block diagram.

Figure 1-1. Application Block Diagram

Device Information

(1)

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1 Device Overview ......................................... 1

1.1 Features .............................................. 1

1.2 Applications........................................... 1

1.3 Description............................................ 1

1.4 Application Block Diagram ........................... 2

2 Revision History ......................................... 4

3 Device Characteristics.................................. 5

3.1 Related Products ..................................... 5

4 Terminal Configuration and Functions.............. 6

4.1 Pin Diagrams ......................................... 6

4.2 Signal Descriptions ................................... 6

5 Specifications ............................................ 8

5.1 Absolute Maximum Ratings .......................... 8

5.2 ESD Ratings.......................................... 8

5.3 Recommended Operating Conditions ................ 8

5.4 Electrical Characteristics ............................. 9

5.5 Thermal Resistance Characteristics ................ 10

5.6 Switching Characteristics ........................... 10

6 Detailed Description ................................... 11

6.1 Functional Block Diagram........................... 11

6.2 Power Supplies ..................................... 11

6.3 Supply Arrangements ............................... 12

6.4 Supply Regulator Settings .......................... 13

6.5 Power Modes ....................................... 14

6.6 Receiver – Analog Section .......................... 17

6.7 Receiver – Digital Section........................... 18

6.8 Oscillator Section ................................... 21

6.9 Transmitter - Analog Section........................ 22

6.10 Transmitter - Digital Section ........................ 22

6.11 Transmitter – External Power Amplifier or

Subcarrier Detector ................................. 23

6.12 Communication Interface............................ 23

6.13 Direct Commands from MCU to Reader ............ 42

6.14 Register Description................................. 45

7 Applications, Implementation, and Layout........ 62

7.1 TRF7960A Reader System Using SPI With SS

Mode ................................................ 62

7.2 System Design ...................................... 63

8 Device and Documentation Support ............... 65

8.1 Getting Started and Next Steps..................... 65

8.2 Device Nomenclature ............................... 65

8.3 Tools and Software ................................. 66

8.4 Documentation Support ............................. 66

8.5 Support Resources.................................. 66

8.6 Trademarks.......................................... 66

8.7 Electrostatic Discharge Caution..................... 67

8.8 Export Control Notice ............................... 67

8.9 Glossary............................................. 67

9 Mechanical, Packaging, and Orderable

Information .............................................. 68

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2 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from May 18, 2017 to March 11, 2020 Page

• Removed references to obsolete EVMs .......................................................................................... 2

• Corrected typo (changed "...and 3.4 V for VDD_A and VDD_A" to "...and 3.4 V for VDD_A and VDD_X") in

Section 6.3, Supply Arrangements................................................................................................ 13

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3 Device Characteristics

Table 3-1 lists the supported protocols.

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Table 3-1. Supported Protocols

DEVICE

TRF7960A ✓ ✓ ✓ ✓ ✓ ✓ ✓

106 kbps 212 kbps 424 kbps 848 kbps

ISO/IEC 14443 A AND B

ISO/IEC 15693

ISO/IEC 18000-3

MODE 1

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

Products for TI Wireless Connectivity Connect more with the industry’s broadest wireless connectivity

portfolio.

Products for NFC / RFID TI provides one of the industry’s most differentiated NFC and RFID product

portfolios and is your solution to meet a broad range of NFC connectivity and RFID identification needs.

Companion Products for TRF7960A Review products that are frequently purchased or used with this

product.

Reference Designs for TRF7960A The TI Designs Reference Design Library is a robust reference

design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at ti.com/tidesigns.

NFC Forum

TYPES 1 TO 5

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2 3

I/O_6

I/O_5

I/O_4

I/O_3

I/O_2

I/O_1

I/O_0

I/O_7

VIN

VDD_RF

VDD_PA

TX_OUT

VSS_PA

VSS_RX

RX_IN1

VDD_A

OSC_IN

OSC_OUT

VSS_D

SYS_CLK

DATA_CLK

EN2

VDD_X

VSS

ASK/OOK

IRQ

MOD

VSS_A

VDD_I/O

RX_IN2

23 22

9 10 11 13 1412 15 16

32 31 30 28 2729 26 25

Thermal Pad

(connect to ground)

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4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pinout for the 32-pin RHB package.

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Figure 4-1. 32-Pin RHB Package (Top View)

4.2 Signal Descriptions

Table 4-1 describes the signals.

Table 4-1. Signal Descriptions

TERMINAL

NO. NAME

1 VDD_A OUT Internal regulated supply (2.7 V to 3.4 V) for analog circuitry 2 VIN SUP External supply input to chip (2.7 V to 5.5 V) 3 VDD_RF OUT Internal regulated supply (2.7 V to 5 V); normally connected to VDD_PA (pin 4) 4 VDD_PA INP Supply for PA; normally connected externally to VDD_RF (pin 3) 5 TX_OUT OUT RF output (selectable output power: 100 mW or 200 mW, with VDD= 5 V) 6 VSS_PA SUP Negative supply for PA; normally connected to circuit ground 7 VSS_RX SUP Negative supply for receive inputs; normally connected to circuit ground 8 RX_IN1 INP Main receive input

9 RX_IN2 INP Auxiliary receive input 10 VSS SUP Chip substrate ground 11 BAND_GAP OUT Bandgap voltage (VBG= 1.6 V); internal analog voltage reference

12 ASK/OOK BID

13 IRQ OUT Interrupt request

14 MOD

15 VSS_A SUP Negative supply for internal analog circuits. Connected to GND. 16 VDD_I/O INP Supply for I/O communications (1.8 V to VIN) level shifter. VIN should be never exceeded. 17 I/O_0 BID I/O pin for parallel communication 18 I/O_1 BID I/O pin for parallel communication 19 I/O_2 BID I/O pin for parallel communication

(1) SUP = Supply, INP = Input, BID = Bidirectional, OUT = Output 6

(1)

TYPE

DESCRIPTION

Selection between ASK and OOK modulation (0 = ASK, 1 = OOK) for direct mode 0 and 1. It can be configured as an output to provide the received analog signal output.

INP External data modulation input for direct mode 0 or 1

OUT Subcarrier digital data output (see register 0x1A and 0x1B definitions)

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Table 4-1. Signal Descriptions (continued)

TERMINAL

NO. NAME

20 I/O_3 BID I/O pin for parallel communication

21 I/O_4 BID

22 I/O_5 BID

23 I/O_6 BID

24 I/O_7 BID

25 EN2 INP 26 DATA_CLK INP Data clock input for MCU communication (parallel and serial)

27 SYS_CLK OUT

28 EN INP Chip enable input (if EN = 0, then the chip is in sleep or power-down mode) 29 VSS_D SUP Negative supply for internal digital circuits 30 OSC_OUT OUT Crystal or oscillator output 31 OSC_IN INP Crystal or oscillator input

32 VDD_X OUT

PAD PAD SUP Chip substrate ground

TYPE

(1)

I/O pin for parallel communication Slave select signal in SPI mode

I/O pin for parallel communication Data clock output in direct mode 1

I/O pin for parallel communication MISO for serial communication (SPI) Serial bit data output in direct mode 1 or subcarrier signal in direct mode 0

I/O pin for parallel communication. MOSI for serial communication (SPI)

Selection of power down mode. If EN2 is connected to VIN, then VDD_X is active during power down mode 2 (for example, to supply the MCU).

If EN = 1 (EN2 = don't care) the system clock for the MCU is configured with register 0x09 (off,

3.39 MHz, 6.78 MHz, or 13.56 MHz). If EN = 0 and EN2 = 1, the system clock is set to 60 kHz.

Internally regulated supply (2.7 V to 3.4 V) for digital circuit and external devices (for example, an MCU)

DESCRIPTION

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5 Specifications

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5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)

(1)

(2)

MIN MAX UNIT

Input voltage range, V Maximum current, I

Maximum operating virtual junction temperature, T

Storage temperature, T

STG

(3)

Any condition 140 Continuous operation, long-term reliability 125

–0.3 6 V

150 mA

°C

–55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating

Conditions are not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to substrate ground terminal VSS. (3) The maximum junction temperature for continuous operation is limited by package constraints. Operation above this temperature may

result in reduced reliability or lifetime of the device.

5.2 ESD Ratings

VALUE UNIT

(1)

(2)

±2000

±500

VCharged-device model (CDM), per JEDEC specification JESD22‑C101

Electrostatic discharge

(ESD)

Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001

Machine model (MM) ±200

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. (2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

V T T

Operating input voltage 2.7 5 5.5 V

Operating ambient temperature –40 25 110 °C

Operating virtual junction temperature –40 25 125 °C

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5.4 Electrical Characteristics

TYP operating conditions are TA= 25°C, VIN= 5 V, full-power mode (unless otherwise noted) MIN and MAX operating conditions are over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

PD1

PD2

STBY

ON1

ON2

ON3

POR

DD_A

DD_X

VDD_Xmax

RFOUT

RFIN

RF_INmax

RF_INmin

SYS_CLK

CRYSTAL

D_CLKmax

OUT

SYS_CLK

Supply current in power down mode 1

Supply current in power down mode 2 (sleep mode)

Supply current in standby mode Supply current without antenna driver

current Supply current in TX (half power)

Supply current in TX (full power) Power-on reset voltage Input voltage at VIN 1.4 2 2.6 V

Bandgap voltage (pin 11) Internal analog reference voltage 1.5 1.6 1.7 V Regulated output voltage for analog

circuitry (pin 1) Regulated supply for external circuitry Output voltage pin 32, VIN= 5 V 3.1 3.4 3.8 V Maximum output current of VDD_X Output current pin 32, VIN= 5 V 20 mA

Antenna driver output resistance

(1)

RX_IN1 and RX_IN2 input resistance 4 10 20 kΩ Maximum RF input voltage at RX_IN1

or RX_IN2 Minimum RF input voltage at RX_IN1

or RX_IN2 (input sensitivity)

(2)

SYS_CLK frequency In power mode 2, EN = 0, EN2 = 1 25 60 120 kHz Carrier frequency Defined by external crystal 13.56 MHz

Crystal run-in time

Maximum DATA_CLK frequency

(4)

Input voltage, logic low

Input voltage threshold, logic high Output resistance, I/O_0 to I/O_7 500 800 Ω

Output resistance R

SYS_CLK

(1) Antenna driver output resistance (2) Measured with subcarrier signal at RX_IN1 or RX_IN2 and measured the digital output at MOD pin with register 0x1A bit 6 = 1 (3) Depending on the crystal parameters and components (4) Recommended DATA_CLK speed is 2 MHz; higher data clock depends on the capacitive load. Maximum SPI clock speed should not

exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output

resistance of 400 Ω (12-ns time constant when 30-pF load is used).

All building blocks disabled, including supplyvoltage regulators; measured after 500-ms

<0.5 5 µA

settling time (EN = 0, EN2 = 0) The SYS_CLK generator and VDD_X remain

active to support external circuitry, measured

120 200 µA

after 100-ms settling time (EN = 0, EN2 = 1) Oscillator running, supply-voltage regulators in

low-consumption mode (EN = 1, EN2 = x) Oscillator, regulators, RX, and AGC are active,

TX is off Oscillator, regulators, RX, AGC, and TX

active, P

OUT

= 100 mW

Oscillator, regulators, RX, AGC, and TX active, P

OUT

= 200 mW

1.9 3.5 mA

10.5 14 mA

70 78 mA

130 170 mA

VIN= 5 V 3.1 3.5 3.8 V

Half-power mode, VIN= 2.7 V to 5.5 V 8 12 Full-power mode, VIN= 2.7 V to 5.5 V 4 6

RF_INmax

SUBCARRIER

Time until oscillator stable bit is set (register 0x0F)

Depends on capacitive load on the I/O lines, recommendation is 2 MHz

I/O lines, IRQ, SYS_CLK, DATA_CLK, EN, EN2

should not exceed VIN 3.5 V

= 424 kHz 1.4 2.5 = 848 kHz 2.1 3

(3)

(4)

2 4 10 MHz

5 ms

0.2 ×

DD_I/O

0.8 ×

DD_I/O

200 400 Ω

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5.5 Thermal Resistance Characteristics

PACKAGE Rθ

(1)

Rθ

TA≤ 25°C TA≤ 85°C

POWER RATING

RHB (32) 31°C/W 36.4°C/W 2.7 W 1.1 W

(1) This data was taken using the JEDEC standard high-K test PCB. (2) Power rating is determined with a junction temperature of 125°C. This is the point where distortion starts to increase substantially.

Thermal management of the final PCB should strive to keep the junction temperature at or below 125°C for best performance and long-

term reliability.

(2)

5.6 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

LO/HI

STE,LEAD

STE,LAG

SU,SI

HD,SI

SU,SO

HD,SO

VALID,SO

DATA_CLK time, high or low (one half of DATA_CLK at 50% duty cycle)

Depends on capacitive load on the I/O lines

Slave select lead time, slave select low to clock

Slave select lag time, last clock to slave select high

MOSI input data setup time 15 ns MOSI input data hold time 15 ns MISO input data setup time 15 ns MISO input data hold time 15 ns MISO output data valid time DATA_CLK edge to MISO valid, CL= <30 pF 30 50 75 ns

(1)

50 62.5 250 ns

200 ns

(1) Recommended DATA_CLK speed is 2 MHz; higher data clock depends on the capacitive load. Maximum SPI clock speed should not

exceed 10 MHz. This clock speed is acceptable only when external capacitive load is less than 30 pF. MISO driver has a typical output

resistance of 400 Ω (12-ns time constant when 30-pF load is used).

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MUX

RX_IN1

RX_IN2

Phase and

Amplitude

Detector

Gain

RSSI

(AUX)

Logic

Level Shifter

State

Control

Logic

(Control

Registers and

Command

Logic)

12-Byte

FIFO

MCU

Interface

VDD_I/O

I/O_0

I/O_1

I/O_2

I/O_3

I/O_4

I/O_5

I/O_6

I/O_7

IRQ

SYS_CLK

DATA_CLK

ISO Protocol Handling

Decoder

RSSI

(External)

Gain

RSSI

(Main)

Filter

and AGC

Digitizer

Bit

Framing

Serial

Conversion

CRC and Parity

Transmitter

Analog Front End

TX_OUT

VDD_PA

VSS_PA

Digital Control State Machine

Crystal or Oscillator

Timing System

EN2

ASK/OOK

MOD

OSC_IN

OSC_OUT

Voltage Supply Regulator Systems

(Supply Regulators and Reference Voltages)

VSS_A

VSS_RF

VDD_RF

VDD_X

VSS_D

VSS

VIN

VDD_A

BAND_GAP

Phase and

Amplitude

Detector

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6 Detailed Description

6.1 Functional Block Diagram

Figure 6-1 shows the functional block diagram.

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6.2 Power Supplies

The TRF7960A positive supply input VIN (pin 2) sources three internal regulators with output voltages VDD_RF, VDD_A, and VDD_X. All regulators require external bypass capacitors for supply noise filtering and must be connected as indicated in reference schematics. These regulators provide a high power supply reject ratio (PSRR) as required for RFID reader systems. All regulators are supplied by VIN (pin 2).

The regulators are not independent and have common control bits in register 0x0B for output voltage setting. The regulators can be configured to operate in either automatic or manual mode (register 0x0B, bit

7). The automatic regulator setting mode ensures an optimal compromise between PSRR and the highest possible supply voltage for RF output (to ensure maximum RF power output). The manual mode lets the user manually configure the regulator settings.

Figure 6-1. Functional Block Diagram

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6.3 Supply Arrangements

Regulator Supply Input: VIN

The positive supply at VIN (pin 2) has an input voltage range of 2.7 V to 5.5 V. VIN provides the supply input sources for three internal regulators with the output voltages VDD_RF, VDD_A, and VDD_X. External bypass capacitors for supply noise filtering must be used (per reference schematics).

VIN must be the highest voltage supplied to the TRF7960A.

RF Power Amplifier Regulator: VDD_RF

The VDD_RF (pin 3) regulator is supplying the RF power amplifier. The voltage regulator can be set for either 5-V or 3-V operation. External bypass capacitors for supply noise filtering must be used (per reference schematics). When configured for 5-V manual operation, the VDD_RF output voltage can be set from 4.3 V to 5 V in 100-mV steps. In 3-V manual operation, the output can be programmed from 2.7 V to

3.4 V in 100-mV steps (see Table 6-2). The maximum output current capability for 5-V operation is 150 mA and for 3-V operation is 100 mA.

Analog Supply Regulator: VDD_A

Regulator VDD_A (pin 1) supplies the analog circuits of the device. The output voltage setting depends on the input voltage and can be set for 5-V and 3-V operation. When configured for 5-V manual operation, the output voltage is fixed at 3.4 V. External bypass capacitors for supply noise filtering must be used (per reference schematics). When configured for 3-V manual operation, the VDD_A output can be set from 2.7 V to 3.4 V in 100-mV steps (see Table 6-2).

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NOTE

The configuration of VDD_A and VDD_X regulators are not independent from each other. The VDD_A output current should not exceed 20 mA.

Digital Supply Regulator: VDD_X

The digital supply regulator VDD_X (pin 32) provides the power for the internal digital building blocks and can also be used to supply external electronics within the reader system. When configured for 3-V operation, the output voltage can be set from 2.7 to 3.4 V in 100-mV steps. External bypass capacitors for supply noise filtering must be used (refer to the reference schematics).

NOTE

The configuration of the VDD_A and VDD_X regulators are not independent from each other. The VDD_X output current should not exceed 20 mA.

The RF power amplifier regulator (VDD_RF), analog supply regulator (VDD_A), and digital supply regulator (VDD_X) can be configured to operate in either automatic or manual mode described in Table 6-

1. The automatic regulator setting mode ensures an optimal compromise between PSRR and the highest

possible supply voltage to ensure maximum RF power output. By default, the regulators are set in automatic regulator setting mode. In this mode, the regulators are

automatically set every time the system is activated by setting EN input High or each time the automatic regulator setting bit, B7 in register 0x0B is set to a 1. The action is started on the 0 to 1 transition. This means that, if the user wants to rerun the automatic setting from a state in which the automatic setting bit is already high, the automatic setting bit (B7 in register 0x0B) should be changed: 1-0-1.

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By default, the regulator setting algorithm sets the regulator outputs to a "Delta Voltage" of 250 mV below VIN, but not higher than 5 V for VDD_RF and 3.4 V for VDD_A and VDD_X. The "Delta Voltage" in automatic regulator mode can be increased up to 400 mV (for more details, see bits B0 to B2 in register 0x0B).

Power Amplifier Supply: VDD_PA

The power amplifier of the TRF7960A is supplied through VDD_PA (pin 4). The positive supply pin for the RF power amplifier is externally connected to the regulator output VDD_RF (pin 3).

I/O Level Shifter Supply: VDD_I/O

The TRF7960A has a separate supply input VDD_I/O (pin 16) for the build in I/O level shifter. The supported input voltage ranges from 1.8 V to VIN, however not exceeding 5.5 V. Pin 16 is used to supply the I/O interface pins (I/O_0 to I/O_7), IRQ, SYS_CLK, and DATA_CLK pins of the reader. In typical applications, VDD_I/O is directly connected to VDD_X while VDD_X also supplies the MCU. This ensures that the I/O signal levels of the MCU match with the logic levels of the TRF7960A.

Negative Supply Connections: VSS, VSS_RX, VSS_A, VSS_PA

The negative supply connections VSS_X of each functional block are all externally connected to GND. The substrate connection is VSS (pin 10), the analog negative supply is VSS_A (pin 15), the logic

negative supply is VSS_D (pin 29), the RF output stage negative supply is VSS_PA (pin 6), and the negative supply for the RF receiver VSS_RX (pin 7).

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6.4 Supply Regulator Settings

The input supply voltage mode of the reader must be selected. This is done in the Chip Status Control register (0x00). Bit 0 in register 0x00 selects either 5-V or 3-V input supply voltage. The default configuration is 5 V, which reflects an operating supply voltage range of 4.3 V to 5.5 V. If the supply voltage is below 4.3 V, the 3-V configuration should be used.

The various regulators can be configured to operate in automatic or manual mode. This is done in the Regulator and I/O Control register (0x0B) (see Table 6-1 and Table 6-2).

Table 6-1. Supply Regulator Setting: 5-V System

ADDRESS

Automatic Mode (default)

0B 1 x x x x x 1 1 Automatic regulator setting with 250-mV difference 0B 1 x x x x x 1 0 Automatic regulator setting with 350-mV difference 0B 1 x x x x x 0 0 Automatic regulator setting with 400-mV difference

Manual Mode

0B 0 x x x x 1 1 1 VDD_RF = 5 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 1 1 0 VDD_RF = 4.9 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 1 0 1 VDD_RF = 4.8 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 1 0 0 VDD_RF = 4.7 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 0 1 1 VDD_RF = 4.6 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 0 1 0 VDD_RF = 4.5 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 0 0 1 VDD_RF = 4.4 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 0 0 0 VDD_RF = 4.3 V, VDD_A = 3.4 V, VDD_X = 3.4 V

(1) x = don't care

OPTION BITS SETTING IN REGULATOR CONTROL

B7 B6 B5 B4 B3 B2 B1 B0

(1)

COMMENTS

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Table 6-2. Supply Regulator Setting: 3-V System

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ADDRESS

Automatic Mode (default)

Manual Mode

0B 0 x x x x 1 1 1 VDD_RF = 3.4 V, VDD_A = 3.4 V, VDD_X = 3.4 V 0B 0 x x x x 1 1 0 VDD_RF = 3.3 V, VDD_A = 3.3 V, VDD_X = 3.3 V 0B 0 x x x x 1 0 1 VDD_RF = 3.2 V, VDD_A = 3.2 V, VDD_X = 3.2 V 0B 0 x x x x 1 0 0 VDD_RF = 3.1 V, VDD_A = 3.1 V, VDD_X = 3.1 V 0B 0 x x x x 0 1 1 VDD_RF = 3.0 V, VDD_A = 3.0 V, VDD_X = 3.0 V 0B 0 x x x x 0 1 0 VDD_RF = 2.9 V, VDD_A = 2.9 V, VDD_X = 2.9 V 0B 0 x x x x 0 0 1 VDD_RF = 2.8 V, VDD_A = 2.8 V, VDD_X = 2.8 V 0B 0 x x x x 0 0 0 VDD_RF = 2.7 V, VDD_A = 2.7 V, VDD_X = 2.7 V

(1) x = don't care

OPTION BITS SETTING IN REGULATOR CONTROL

B7 B6 B5 B4 B3 B2 B1 B0

(1)

COMMENTS

The regulator configuration function adjusts the regulator outputs by default to 250 mV below VIN level, but not higher than 5 V for VDD_RF, 3.4 V for VDD_A and VDD_X. This ensures the highest possible supply voltage for the RF output stage while maintaining an adequate PSRR (power supply rejection ratio).

To further improve the PSRR, it is possible to increase the target voltage difference across VDD_X and VDD_A from its default to 350 mV or even 400 mV (for details, see Regulator and I/O Control register 0x0B definition and Table 6-2.)

6.5 Power Modes

The chip has several power states, which are controlled by two input pins (EN and EN2) and several bits in the Chip Status Control register (0x00).

Table 6-3 lists the configuration for the different power modes when using a 5-V or 3-V system supply.

The main reader enable signal is pin EN. When EN is set high, all of the reader regulators are enabled, the 13.56-MHz oscillator is running, and the SYS_CLK (output clock for external microcontroller) is also available.

The Regulator Control register settings shown are for optimized power out. The automatic setting (normally 0x87) is optimized for best PSRR and noise reduction.

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Table 6-3. Power Modes

CHIP STATUS

MODE EN2 EN

Mode 4

(full power)

5 VDC

Mode 4

(full power)

3.3 VDC Mode 3

(half power)

5 VDC

Mode 3

(half power)

3.3 VDC Mode 2

5 VDC

Mode 2

3.3 VDC Mode 1

5 VDC

Mode 1

3.3 VDC

Standby mode

5 VDC

Standby mode

3.3 VDC

Sleep mode 1 0 x x Off Off Off On On 0.120 — 1.5 ms Power down 0 0 x x Off Off Off Off Off <0.001 — Start

(1) x = don't care

x 1 21 07 On On On x On 130 23 20 to 25 µs

x 1 20 07 On On On x On 67 18

x 1 31 07 On On On x On 70 20 20 to 25 µs

x 1 30 07 On On On x On 53 15

x 1 03 07 Off On On x On 10.5 — 20 to 25 µs

x 1 02 00 Off On On x On 9 —

x 1 01 07 Off Off On x On 5 — 20 to 25 µs

x 1 00 00 Off Off On x On 3

x 1 81 07 Off Off On x On 3 — 4.8 ms

x 1 80 00 Off Off On x On 2 —

CONTROL

(0X00)

REGULATOR

CONTROL

(0X0B)

TRANSMITTER

RECEIVER

(1)

SYS_CLK

(13.56 MHz)

SYS_CLK

(60 kHz)

VDD_X

TYPICAL

CURRENT

(mA)

TYPICAL

POWER

OUT (dBm)

TIME

(FROM

STATE)

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The input pin EN2 has two functions:

• A direct connection from EN2 to VIN to ensure the availability of the regulated supply VDD_X and an auxiliary clock signal (60 kHz, SYS_CLK) for an external MCU. This mode (EN = 0, EN2 = 1) is intended for systems in which the MCU is also being supplied by the reader supply regulator (VDD_X) and the MCU clock is supplied by the SYS_CLK output of the reader. This lets the MCU supply and clock be available during sleep mode.

• EN2 enables the start-up of the reader system from complete power down (EN = 0, EN2 = 0). In this case, the EN input is being controlled by the MCU (or other system device) that is without supply voltage during complete power down (thus unable to control the EN input). A rising edge applied to the EN2 input (which has an approximately 1-V threshold level) starts the reader supply system and

13.56‑MHz oscillator (identical to condition EN = 1).

When the user MCU controls EN and EN2, use a delay of 5 ms between EN and EN2. When the MCU controls only EN, TI recommends connecting EN2 to either VIN or GND, depending on the application MCU requirements for VDD_X and SYS_CLK.

Using EN = 1 and EN2 = 1 in parallel at start-up should not be done as it may cause incorrect operation.

This start-up mode lasts until all of the regulators have settled and the 13.56-MHz oscillator has stabilized. If the EN input is set high (EN = 1) by the MCU (or other system device), the reader stays active. If the EN input is not set high (EN = 0) within 100 µs after the SYS_CLK output is switched from auxiliary clock (60 kHz) to high-frequency clock (derived from the crystal oscillator), the reader system returns to complete Power-Down Mode 1. This option can be used to wake the reader system from complete power down (PD Mode 1) by using a push-button switch or by sending a single pulse.

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NOTE

After the reader EN line is high, the other power modes are selected by control bits within the Chip Status Control register (0x00). The power mode options and states are listed in Table 6-3.

When EN is set high (or on rising edge of EN2 and then confirmed by EN = 1) the supply regulators are activated and the 13.56-MHz oscillator started. When the supplies are settled and the oscillator frequency is stable, the SYS_CLK output is switched from the auxiliary frequency of 60 kHz to the 13.56-MHz frequency derived from the crystal oscillator. At this time, the reader is ready to communicate and perform the required tasks. The MCU can then program the Chip Status Control register 0x00 and select the operation mode by programming the additional registers.

• Standby mode (bit 7 = 1 of register 0x00), the reader is capable of recovering to full operation in 100 µs.

• Mode 1 (active mode with RF output disabled, bit 5 = 0 and bit 1 = 0 of register 0x00) is a low-power mode that lets the reader recover to full operation within 25 µs.

• Mode 2 (active mode with only the RF receiver active, bit 1 = 1 of register 0x00) can be used to measure the external RF field (as described in RSSI measurements paragraph) if reader-to-reader anticollision is implemented.

• Mode 3 and Mode 4 (active modes with the entire RF section active, bit 5 = 1 of register 0x00) are the modes used for typical transmit and receive operations.

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6.6 Receiver – Analog Section

6.6.1 Main and Auxiliary Receiver

The TRF7960A has two receiver inputs: RX_IN1 (pin 8) and RX_IN2 (pin 9). Each of the inputs is connected to an external capacitive voltage divider to ensure that the modulated signal from the tag is available on at least one of the two inputs. This architecture eliminates any possible communication holes that may occur from the tag to the reader.

The two RX inputs (RX_IN1 and RX_IN2) are multiplexed into two receivers–the main receiver and the auxiliary receiver. Only the main receiver is used for reception; the auxiliary receiver is used for signal quality monitoring. Receiver input multiplexing is controlled by bit B3 in the Chip Status Control register (address 0x00).

After start-up, RX_IN1 is multiplexed to the main receiver which is composed of an RF envelope detection, first gain and band-pass filtering stage, second gain and filtering stage with AGC. Only the main receiver is connected to the digitizing stage which output is connected to the digital processing block. The main receiver also has an RSSI measuring stage, which measures the strength of the demodulated signal (subcarrier signal).

The primary function of the auxiliary receiver is to monitor the RX signal quality by measuring the RSSI of the demodulated subcarrier signal (internal RSSI). After start-up, RX_IN2 is multiplexed to the auxiliary receiver. The auxiliary receiver has an RF envelope detection stage, first gain and filtering with AGC stage and finally the auxiliary RSSI block.

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The default MUX setting is RX_IN1 connected to the main receiver and RX_IN2 connected to the auxiliary receiver. To determine the signal quality, the response from the tag is detected by the "main" (pin RX_IN1) and "auxiliary" (pin RX_IN2) RSSI. Both values measured and stored in the RSSI level register (address 0x0F). The MCU can read the RSSI values from the TRF7960A RSSI register and decide if swapping the input signals is preferable or not. Setting B3 in the Chip Status Control register (address 0x00) to 1 connects RX_IN1 (pin 8) to the auxiliary receiver and RX_IN2 (pin 9) to the main receiver.

The main and auxiliary receiver input stages are RF envelope detectors. The RF amplitude at RX_IN1 and RX_IN2 should be approximately 3 VPPfor a VIN supply level greater than 3.3 V. If the VIN level is lower, the RF input peak-to-peak voltage level should not exceed the VIN level.

6.6.2 Receiver Gain and Filter Stages

The first gain and filtering stage has a nominal gain of 15 dB with an adjustable band-pass filter. The band-pass filter has programmable 3-dB corner frequencies from 110 kHz to 450 kHz for the high-pass filter and from 570 kHz to 1500 kHz for the low-pass filter. After the band-pass filter, there is another gainand-filtering stage with a nominal gain of 8 dB and with frequency characteristics identical to the first bandpass stage.

The internal filters are configured automatically depending on the selected ISO communication standard in the ISO Control register (address 0x01). If required, additional fine tuning can be done by writing directly to the RX special setting registers (address 0x0A).

Table 6-4 shows the various settings for the receiver analog section. Setting B4, B5, B6, and B7 to 0

results in a band-pass characteristic of 240 kHz to 1.4 MHz, which is appropriate for ISO/IEC 14443 B data rate of 106 kbps, ISO/IEC 14443 A or B data rates of 212 kbps and 424 kbps, and FeliCa data rate of 424 kbps.

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Table 6-4. RX Special Setting Register (0x0A)

BIT FUNCTION COMMENTS

B7 Band-pass filter from 110 kHz to 570 kHz Appropriate for any 212-kHz subcarrier systems like FeliCa B6 Band-pass filter from 200 kHz to 900 kHz Appropriate for 424-kHz subcarrier systems (for example, used in ISO/IEC 15693).

B5 Band-pass filter from 450 kHz to 1.5 MHz

B4 Band-pass filter from 100 kHz to 1.5 MHz B3 00 = No gain reduction

01 = Gain reduction for 5 dB 10 = Gain reduction for 10 dB

11 = Gain reduction for 15 dB B1 Reserved B0 Reserved

Appropriate for Manchester-coded 106-kbps 848-kHz subcarrier systems (for example, used in ISO/IEC 14443 A).

Appropriate for highest bit rate (848 kbps) used in high-bit-rate ISO/IEC 14443 B. Gain is reduced by 7 dB.

Sets the RX digital gain reduction (changing the window of the digitizing comparator).

6.7 Receiver – Digital Section

The output of the TRF7960A analog receiver block is a digitized subcarrier signal and is the input to the digital receiver block, which consists of two sections that partly overlap. The digitized subcarrier signal is a digital representation of the modulation signal on the RF envelope. The two sections of the digital receiver block are the protocol bit decoder section and the framing logic section.

The protocol bit decoder section converts the subcarrier coded signal into a serial bit stream and a data clock. The decoder logic is designed for maximum error tolerance. This tolerance lets the decoder section successfully decode even partly corrupted subcarrier signals that would otherwise be lost due to noise or interference.

The framing logic section formats the serial bit stream data from the protocol bit decoder stage into data bytes. During the formatting process, special signals such as the start of frame (SOF), end of frame (EOF), start of communication, and end of communication are automatically removed. The parity bits and CRC bytes are also checked and removed. The end result is "clean" or "raw" data that is then sent to the 12-byte FIFO register where it can be read by the external microcontroller system. Providing the data this way, in conjunction with the timing register settings of the TRF7960A, means the firmware developer must know about much less of the finer details of the ISO protocols to create a very robust application, especially in low-cost platforms where code space is at a premium and high performance is still required.

The start of the receive operation (successfully received SOF) sets the IRQ flags in the IRQ Status register (0x0C). The end of the receive operation is signaled to the external system MCU by setting pin 13 (IRQ) to high. When data is received in the FIFO, an interrupt is sent to the MCU to signal that there is data to be read from the FIFO. The FIFO Status register (0x1C) should be used to provide the number of bytes that should be clocked out during the actual FIFO read. Additionally, an interrupt is sent to the MCU when the received data occupies 75% of the FIFO capacity to signal that the data should be removed from the FIFO. That interrupt is triggered when the received data packet is longer than 9 bytes.

Any error in the data format, parity, or CRC is detected and notified to the external system by an interrupt request pulse. The source condition of the interrupt request pulse is available in the IRQ Status register (0x0C). The main register controlling the digital part of the receiver is the ISO Control register (0x01). By writing to this register, the user selects the protocol to be used. With each new write in this register, the default presets are reloaded in all related registers, so no further adjustments in other registers are needed for proper operation.

NOTE

If additional register setting changes are needed to fine-tune the system, set the ISO Control register (0x01) before making the additional changes.

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The framing section also supports the bit-collision detection as specified in ISO/IEC 14443 A and ISO/IEC 15693. When a bit collision is detected, an interrupt request is sent and a flag is set in the IRQ Status register (0x0C). For ISO/IEC 14443 A specifically, the position of the bit collision is written in two registers: partly in the Collision Position register (0x0E) and partly in the Collision Position and Interrupt Mask register (0x0D) (bits B6 and B7).

The collision position is presented as sequential bit number, where the count starts immediately after the start bit. This means a collision in the first bit of a UID would give the value 00 0001 0000 in these registers when their contents are combined after being read. (the count starts with 0 and the first 16 bits are the command code and the number of valid bits [NVB] byte).

The receive section also includes two timers. The RX wait time timer is controlled by the value in the RX Wait Time register (0x08). This timer defines the time interval after the end of the transmit operation in which the receive decoders are not active (held in reset state). This prevents false detections resulting from transients following the transmit operation. The value of the RX Wait Time register (0x08) defines the time in increments of 9.44 µs. This register is preset at every write to ISO Control register (0x01) according to the minimum tag response time defined by each standard.

The RX no response timer is controlled by the RX No Response Wait Time register (0x07). This timer measures the time from the start of slot in the anticollision sequence until the start of tag response. If there is no tag response in the defined time, an interrupt request is sent and a flag is set in the IRQ Status register (0x0C). This enables the external controller to be relieved of the task of detecting empty slots. The wait time is stored in the register in increments of 37.76 µs. This register is also automatically preset for every new protocol selection.

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6.7.1 Received Signal Strength Indicator (RSSI)

The TRF7960A incorporates three independent RSSI building blocks: Internal Main RSSI, Internal Auxiliary RSSI, and External RSSI. The internal RSSI blocks are measuring the amplitude of the subcarrier signal, and the external RSSI block measures the amplitude of the RF carrier signal at the receiver input.

6.7.1.1 Internal RSSI – Main and Auxiliary Receivers

Each receiver path has its own RSSI block to measure the envelope of the demodulated RF signal (subcarrier). Internal Main RSSI and Internal Auxiliary RSSI are identical except that they are connected to different RF input pins. The Internal RSSI is intended for diagnostic purposes to set the correct RX path conditions.

The Internal RSSI values can be used to adjust the RX gain settings or decide which RX path (main or auxiliary) provides the greater amplitude and, hence, to decide if the MUX may need to be reprogrammed to swap the RX input signal. The measuring system latches the peak value, so the RSSI level can be read after the end of each receive packet. The RSSI register values are reset with every transmission (TX) by the reader. This guarantees an updated RSSI measurement for each new tag response.

The Internal RSSI has 7 steps (3 bit) with a typical increment of approximately 4 dB. The operating range is 600 mVpp to 4.2 Vpp with a typical step size of approximately 600 mV. Both RSSI values "Internal Main" and "Internal Aux" RSSI are stored in the RSSI Levels and Oscillator Status register (0x0F).

Figure 6-2 shows the nominal relationship between the input RF peak level and the RSSI value.

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0 25 50 75 100 125 150 175 200 225 250 275 300 325

RF Input Voltage Level at Pin RF_IN1 (mV )

RSSI Levels and Oscillator Status Register Value (0x0F)

0 0.25 0.5 0.75 1 1.25 1.5 1.75 2 2.25 2.5 2.75 3 3.25 3.5 3.75 4 4.25

Input RF Carrier Level (V )

RSSI Levels and Oscillator Status Register Value (0x0F)

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Figure 6-2. Digital Internal RSSI (Main and Auxiliary) Value vs RF Input Level

This RSSI measurement is done during the communication to the Tag; this means the TX must be on. Bit 1 in the Chip Status Control register (0x00) defines if internal RSSI or the external RSSI value is stored in the RSSI Levels and Oscillator Status register 0x0F. Direct command 0x18 is used to trigger an internal RSSI measurement.

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6.7.1.2 External RSSI

The external RSSI is mainly used for test and diagnostic to sense the amplitude of any 13.56-MHz signal at the receiver's RX_IN1 input. The external RSSI measurement is typically done in active mode when the receiver is on but transmitter output is off. The level of the RF signal received at the antenna is measured and stored in the RSSI Levels and Oscillator Status register (0x0F).

Figure 6-3 shows the relationship between the voltage at the RX_IN1 input and the 3-bit code.

Figure 6-3. Digital External RSSI Value vs RF Input Level

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Crystal

TRF796xA

Pin 31

Pin 30

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The relation between the 3-bit code and the external RF field strength (A/m) sensed by the antenna must be determined by calculation or by experiments for each antenna design. The antenna Q-factor and connection to the RF input influence the result. Direct command 0x19 is used to trigger an internal RSSI measurement.

To check the internal or external RSSI value independent of any other operation:

1. Set transmitter to desired state (on or off) using Bit 5 of the Chip Status Control register (0x00) and enable receiver using Bit 1.

2. Check internal or external RSSI using direct commands 0x18 or 0x19, respectively. This action places the RSSI value in the RSSI register.

3. Delay at least 50 µs.

4. Read the RSSI register using direct command 0x0F. Values can range from 0x40 to 0x7F.

5. Repeat steps 1 to 4 as desired; the register is reset after read.

6.8 Oscillator Section

The 13.56-MHz oscillator is controlled by the Chip Status Control register (0x00) and the EN and EN2 signals. The oscillator generates the RF frequency for the RF output stage and the clock source for the digital section. The buffered clock signal is available at pin 27 (SYS_CLK) for external circuits. B4 and B5 inside the Modulation and SYS_CLK register (0x09) can be used to divide the external SYS_CLK signal at pin 27 by 1, 2, or 4.

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Typical start-up time from complete power down is in the range of 3.5 ms. During Power Down Mode 2 (EN = 0, EN2 = 1) the frequency of SYS_CLK is switched to 60 kHz (typical). The 13.56-MHz crystal must be connected between pin 30 and pin 31. The external shunt capacitors

values for C1and C2must be calculated based on the specified load capacitance of the crystal being used. The external shunt capacitors are calculated as two identical capacitors in series plus the stray capacitance of the TRF7960A and parasitic PCB capacitance in parallel to the crystal.

The parasitic capacitance (CS, stray and parasitic PCB capacitance) can be estimated at 4 to 5 pF (typical).

As an example, using a crystal with a required load capacitance (CL) of 18 pF, the calculation is as follows (see Figure 6-4):

C1= C2= 2 × (CL– CS) = 2 × (18 pF – 4.5 pF) = 27 pF

Place a 27-pF capacitor on pins 30 and 31 to ensure proper crystal oscillator operation.

Figure 6-4. Crystal Block Diagram

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Table 6-5 shows the minimum characteristics recommended for any crystal used with TRF7960A.

Table 6-5. Minimum Crystal Recommendations

PARAMETER SPECIFICATION

Mode of operation Fundamental Type of resonance Parallel

Frequency tolerance ±20 ppm

Operation temperature range –40°C to 85°C

As an alternative, an external clock oscillator source can be connected to pin 31 to provide the system clock, and pin 30 can be left open.

6.9 Transmitter - Analog Section

The 13.56-MHz oscillator generates the RF signal for the PA stage. The power amplifier consists of a driver with selectable output resistance of 4 Ω or 8 Ω (typical). The transmit power levels are selectable between 100 mW (half power) or 200 mW (full power) when configured for 5-V automatic operation. Selection of the transmit power level is set by bit B4 in the Chip Status Control register (0x00). When configured for 3-V automatic operation, the transmit power level is typically in the range of 33 mW (half power) or 70 mW (full power).

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Frequency 13.56 MHz

Aging <5 ppm/year

The ASK modulation depth is controlled by bits B0, B1, and B2 in the Modulator and SYS_CLK Control register (0x09). The ASK modulation depth range can be adjusted from 7% to 30% or 100% (OOK).

External control of the transmit modulation depth is possible by setting the ISO Control register (0x01) to direct mode. While operating the TRF7960A in direct mode, the transmit modulation is made possible by selecting the modulation type ASK or OOK at pin 12. External control of the modulation type is made possible only if enabled by setting B6 in the Modulator and SYS_CLK Control register (0x09) to 1.

In normal operation mode, the length of the modulation pulse is defined by the protocol selected in the ISO Control register (0x01). In case of a high-Q antenna, the modulation pulse is typically prolonged, and the tag detects a longer pulse than intended. For such cases, the modulation pulse length must be corrected by using the TX Pulse Length register (0x06).

If the register contains all zeros, then the pulse length is governed by the protocol selection. If the register contains a value other than 0x00, the pulse length is equal to the value of the register multiplied by

73.7 ns. This means the pulse length can be adjusted from 73.7 ns to 18.8 µs in 73.7-ns increments.

6.10 Transmitter - Digital Section

The digital part of the transmitter is a mirror of the receiver. The settings controlled the ISO Control register (0x01) are applied to the transmitter just like the receiver. In the TRF7960A default mode (ISO Mode), the TRF7960A automatically adds all the special signals like start of communication, end of communication, SOF, EOF, parity bits and CRC bytes.

The data is then coded to modulation pulse levels and sent to the RF output stage modulation control unit. Just like with the receiver, this means that the external system MCU only must load the FIFO with data and all the microcoding is done automatically, again saving the firmware developer code space and time. Additionally, all the registers used for transmit parameter control are automatically preset to optimum values when a new selection is entered into the ISO Control register (0x01).

NOTE

The FIFO must be reset before starting any transmission with direct command 0x0F.

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There are two ways to start the transmit operation:

• Send the transmit command and the number of bytes to be transmitted first, and then start to send the

• Load the number of bytes to be sent into registers 0x1D and 0x1E and load the data to be sent into the

At the end of a transmit operation, the external system MCU is notified by interrupt request (IRQ) with a flag in the IRQ register (0x0C) indicating TX is complete (example value = 0x80).

The TX Length registers also support incomplete byte transmission. The high two nibbles in register 0x1D and the nibble composed of bits B4 to B7 in register 0x1E store the number of complete bytes to be transmitted. Bit B0 in register 0x1E is a flag indicating that there are also additional bits to be transmitted which do not form a complete byte. The number of bits is stored in bits B1 to B3 of the same register (0x1E).

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data to the FIFO. The transmission starts when first data byte is written into the FIFO.

FIFO (address 0x1F), followed by sending a transmit command (see Direct Commands section). The transmission then starts when the transmit command is received.

NOTE

If the data length is longer than the FIFO, the external system MCU is warned when the majority of data from the FIFO was already transmitted by sending and interrupt request with flag in IRQ register to indicate a FIFO low or high status. The external system should respond by loading next data packet into the FIFO.

Some protocols have options so there are two sublevel configuration registers to select the TX protocol options.

• ISO14443B TX Options register (0x02). It controls the SOF and EOF selection and EGT selection for the ISO/IEC 14443 B protocol.

• ISO14443A High-Bit-Rate and Parity Options register (0x03). This register enables the use of different bit rates for RX and TX operations in ISO/IEC 14443 high-bit-rate protocol. Besides that, it also selects the parity method in case of ISO/IEC 14443 A high bit rate.

The digital section also has a timer. The timer can be used to start the transmit operation at a precise time in accordance with a selected event. This is necessary if the tag expects a replay in exact time window following the tag response. This is normally not the case with existing protocols but is needed in protocols when using 'fixed slot' command.

The TX timer uses two registers (register addresses 0x04 and 0x05). Register 0x04 uses 2 bits (B7 and B6) to define the trigger conditions. The remaining 6 bits of register 0x04 are the upper bits, and the 8 bits in register address 0x05 are the lower bits that preset the counter. The range of this counter is from 590 ns to 9.7 ms, in 590-ns increments.

6.11 Transmitter – External Power Amplifier or Subcarrier Detector

The TRF7960A can be used in conjunction with an external TX power amplifier or external subcarrier detector for the receiver path. If this is the case, Bit B6 of the Regulator and I/O Control register (0x0B) must be set to 1. This setting has two functions: First, to provide a modulated signal for the transmitter, if needed. Second, to configure the TRF7960A receiver inputs for an external demodulated subcarrier input. The design of an external power amplifier requires detailed RF knowledge. There are also readily designed and certified high-power HF reader modules on the market.

6.12 Communication Interface

6.12.1 General Introduction

The communication interface to the reader can be configured in two ways: with a eight line parallel interface (D0:D7) plus DATA_CLK, or with a 3- or 4-wire Serial Peripheral Interface (SPI). The SPI interface uses traditional master out/slave in (MOSI), master in/slave out (MISO), IRQ, and DATA_CLK lines. The SPI can be operated with or without using the slave select line.

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TRF7960A

SLOS732G –JUNE 2011–REVISED MARCH 2020

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These communication modes are mutually exclusive, which means that only one mode can be used at a time in the application.

When the SPI interface is selected, the unused I/O_2, I/O_1, and I/O_0 pins must be hard-wired according to Table 6-6. At power up, the TRF7960A IC samples the status of these three pins and then enters one of the possible SPI modes in Table 6-6.

samples the status of these three pins. If they are not the same (all high or all low), the IC enters one of the possible SPI modes.

The TRF7960A always behaves as the slave, while the microcontroller (MCU) behaves as the master device. The MCU initiates all communications with the TRF7960A. The TRF7960A makes use of the Interrupt Request (IRQ) pin in both parallel and SPI modes to prompt the MCU for servicing attention.

Table 6-6. Pin Assignment in Parallel and Serial Interface Connection or Direct Mode

PIN PARALLEL PARALLEL DIRECT SPI WITH SS SPI WITHOUT SS

DATA_CLK DATA_CLK DATA_CLK DATA_CLK from master DATA_CLK from master

MISO

(1)

= data in (reader in) MOSI

(2)

= data out (MCU out) MISO

(3)

(4)

I/O_7 A/D[7] MOSI I/O_6 A/D[6]

I/O_5 (3) A/D[5] Direct mode, strobe (bit clock out) See

I/O_4 A/D[4] SS (slave select) I/O_3 A/D[3] – – – I/O_2 A/D[2] – At VDD At VDD I/O_1 A/D[1] – At VDD At VSS I/O_0 A/D[0] – At VSS At VSS

IRQ IRQ interrupt IRQ interrupt IRQ interrupt IRQ interrupt

(1) MOSI = Master out, slave in (2) MISO = Master in, slave out (3) The I/O_5 pin is used only for information when data is put out of the chip (for example, reading 1 byte from the chip). It is necessary

first to write in the address of the register (8 clocks) and then to generate another 8 clocks for reading out the data. The I/O_5 pin goes high during the second 8 clocks. But for normal SPI operations I/O_5 pin is not used.

(4) The slave select pin is active low.

Direct mode, data out (subcarrier or bit stream)

See –

(1)

= data in (reader in)

(2)

= data out (MCU out)

(3)

Communication is initialized by a start condition, which is expected to be followed by an Address/Command word (Adr/Cmd). The Adr/Cmd word is 8 bits long, and Table 6-7 describes its format.

Table 6-7. Address/Command Word Bit Distribution

BIT DESCRIPTION BIT FUNCTION ADDRESS COMMAND

B7 Command control bit

B6 Read/Write B5 Continuous address mode 1 = Continuous mode R/W 0

B4 Address/command bit 4 Adr 4 Cmd 4 B3 Address/command bit 3 Adr 3 Cmd 3 B2 Address/command bit 2 Adr 2 Cmd 2 B1 Address/command bit 1 Adr 1 Cmd 1 B0 Address/command bit 0 Adr 0 Cmd 0

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0 = Address

1 = Command

1 = Read 0 = Write

0 1

R/W 0

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Texas Instruments TRF7960A Datasheet

1 Device Overview

1.1 Features

1.2 Applications

1.3 Description

1.4 Application Block Diagram

Table of Contents

2 Revision History

3 Device Characteristics

3.1 Related Products

4 Terminal Configuration and Functions

4.1 Pin Diagrams

4.2 Signal Descriptions

5 Specifications

5.1 Absolute Maximum Ratings

5.2 ESD Ratings

5.3 Recommended Operating Conditions

5.4 Electrical Characteristics

5.5 Thermal Resistance Characteristics

5.6 Switching Characteristics

6 Detailed Description

6.1 Functional Block Diagram

6.2 Power Supplies

6.3 Supply Arrangements

6.4 Supply Regulator Settings

6.5 Power Modes

6.6 Receiver – Analog Section

6.6.1 Main and Auxiliary Receiver

6.6.2 Receiver Gain and Filter Stages

6.7 Receiver – Digital Section

6.7.1 Received Signal Strength Indicator (RSSI)

6.7.1.1 Internal RSSI – Main and Auxiliary Receivers

6.7.1.2 External RSSI

6.8 Oscillator Section

6.9 Transmitter - Analog Section

6.10 Transmitter - Digital Section

6.11 Transmitter – External Power Amplifier or Subcarrier Detector

6.12 Communication Interface

6.12.1 General Introduction