TRF3765 Integer/Fractional-N PLL With Integrated VCO
Evaluation Module
This document describes usage and features of the TRF3765 evaluation module (EVM) for wideband
frequency synthesis applications. The synthesizer uses an integer/fractional-N PLL with integrated VCOs
to generate local oscillator signals from 300 MHz to 4800 MHz. This document describes rapid-start setup
procedures, detailed descriptions of circuit blocks and available options, schematics and printed-circuit
board layout, and a common start-up problem troubleshooting guide.
The TRF3765 evaluation module (EVM) is preconfigured to use a 3.3-Vdc power supply on TP2. The
supply must be capable of supplying 250 mA.
SPI communication is required for configuring the TRF3765 device. J7 accepts a mini-USB connector that
can be driven through the device graphical user interface (GUI).
Local oscillator (LO) outputs are available in four differential pairs on SMA coaxial connectors J1, J3-J6,
and J9-J11.
The following steps describe the EVM setup for basic operation with the default hardware configuration.
1. Connect the mini-USB connector. LED D1 draws power through the mini-USB connector and
illuminates immediately.
2. Power the device by supplying TP2 with 3.3 V. Use TP3 for the ground connection. Board revisions
prior to Revision D may require additional power supply connections.
3. Connect the LO output to measurement equipment.
4. Install and start the GUI software.
5. Initiate a communication link with the device by using the GUI Connect button. Follow on-screen
instructions to load a register configuration file. Select file TRF3765.FracMode.3p3Vtank.2600MHz.txt
for a fractional mode board and TRF3765.IntMode.3p3Vtank.2600MHz.txt for an integer mode board.
6. Verify lock-detect on LED D2 and the signal on measurement equipment. If D2 is not illuminated, no
signal is present or the signal is at the incorrect frequency. Check GUI settings on any of the High
Level tabs and recalibrate.
7. Using default hardware and configuration settings, fractional mode integrate phase noise is –47 dBc to
–48 dBc/Hz, whereas integer mode integrated phase is –44 dBc/Hz.
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2Circuit Block Descriptions
This section describes each of the major circuit blocks and their configuration options.
2.1Test Points
Test points are used throughout the board for control and monitoring. These test points are color-coded
for quick reference. The color codes are described in Table 1.
The TRF3765 uses three primary power supplies: VCC1, VCC2, and VCC3. In the default configuration,
VCC1 and VCC2 are connected onboard by R41 and VCC3 is unused. The entire board can be supplied
through 3.3 V on TP2 or Revision D boards. Earlier board revisions require multiple power connections.
A clean power supply is critical to optimal phase noise performance of the synthesizer. The impact of the
power supply is discussed in detail in the application report Supply Noise Effect on Oscillator Phase Noise
(SLWA066). Linear power supplies are the best sources available. Switching power supplies degrade inband phase noise by 10 dB compared to linear laboratory supplies. Onboard regulators U3 and U4 are
ultra-clean TPS74201 linear regulators that also provide excellent performance when they are driven by
most laboratory power supply equipment. These regulators provide performance comparable to a clean
linear supply. To use these regulated 3.3-V supplies, disconnect power from TP2 and remove R41.
Connect 5 V to TP26, using TP27 for ground. Place jumpers on JP4 and JP5 to shunt jumper pins 1 and
2.
VCC3 can be used to drive VCC_TK, a 3.3-V/5-V tolerant supply on the TRF3765. VCC_TK is normally
driven by the 3.3-V VCC2 supply, but some applications perform better with a 5-V supply on VCC_TK. To
use VCC3 to drive VCC_TK at 5 V, move FB2 onto FB11. Populate R12 with a short. Then drive VCC3
through TP5 with a clean linear laboratory supply at 5 V.
VCC3 can also be driven at 5 V by onboard regulator U5. However, this regulator is not as clean as a
linear laboratory supply, and some phase noise performance loss occurs. To use the VCC3 onboard 5-V
regulator, drive TP25 with 6 V using TP28 for ground and place a jumper on JP1 to shunt jumper pins 1
and 2.
The TRF3765EVM includes a power supply filter. This filter can be used to reduce in-band frequency
noise from a switching power supply so that an external supply can drive 5 V on VCC_TK. Phase noise
performance using a high-quality laboratory switching power supply to drive VCC3 through TP5 is similar
to performance measured using a linear supply. The filter is integrated on Rev. E and later boards. Rev. D
and earlier boards include an external filter that is equipped with BNC connectors for a convenient
connection with power supply banana jacks.
Each VCC pin on the TRF3765 connects to an individual test point. The test point may be used for
monitoring. Because each supply pin is isolated through a ferrite bead, by lifting the ferrite bead these test
points may also be used to drive single-device supply pins.
Spurs occurring in the LO signal at 60 kHz and 100 kHz offset from the carrier are usually the result of
ground loops in power supply cabling.
Circuit Block Descriptions
2.3Loop Filter
Loop-filter components are also critical to optimal phase noise performance. The loop filter must be
matched to the selected phase frequency detector (PFD) frequency. TRF3765 boards are shipped with
components matched to the onboard reference clock and configuration file. However, to use a different
PFD frequency, the loop-filter components must be updated. The Loop Filter Design Tool available at
ti.com in the TRF3765EVM product folder is an intuitive software package that identifies proper
component values.
Loop filter reference designators are shown in Figure 1. The assembly layout of these components is
shown in a silkscreen blow-up on the EVM.
SLWU076A–November 2011–Revised July 2012TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation Module
VTune may be monitored on TP12 without disrupting circuit operation, because R20 is a high-value
resistance. TP12 can also be used to drive VTune for open-loop VCO measurements when the TRF3765
charge pump is in 3-state logic. A 1-µF capacitor on C4 is also recommended for open-loop
measurements to help stabilize the applied voltage.
By default, reference is tied to ground through shorts on R13, R15, and R45, with R46 open.
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Figure 1. Loop Filter Reference Designators
2.4SPI Communication
SPI communication from the TRF3765 GUI passes through mini-USB connector J7. The USB interface is
decoded and encoded by U2 into SPI lines DATA, STROBE, CLK, and RDBK. U2 is powered through the
USB connection instead of the board supply, and LED D1 indicates USB power is applied. Test points
TP6–TP10 can be used to monitor SPI communication with laboratory equipment. The laboratory
equipment must be set to high impedance so that it does not load the communication lines.
When the USB cable is disconnected, U2 I/Os are high impedance. In this case, TP6–TP10 can be used
to directly drive the SPI lines.
The power-on reset default register settings in the TRF3765 do not correspond to a valid operational state.
SPI initialization is required to operate the device. Once the registers have been initialized, the mini-USB
cable may be disconnected without disrupting device operation. However, once the mini-USB has been
reconnected, the link must be reestablished through the GUI Connect button on the Start Up tab. The link
exists between the GUI computer and U2, so loss of power to the TRF3765 device does not require
reestablishing the link. Loss of device power, however, does require re-initialization of the registers.
2.5Reference Clock
An oscillator is installed on the TRF3765EVM to provide a reference clock to the device. JP2 installed
provides supply voltage to the oscillator, whereas JP3 installed connects the oscillator output to the
TRF3765. The oscillator frequency drifts over temperature and is not rated for the full TRF3765
temperature operating range, so temperature testing must use an external reference clock.
An external reference clock can be supplied through the SMA connector J8. When using an external
reference clock, remove jumpers on JP2 and JP3. The external reference is ac-coupled to the TRF3765
input pin. An external reference can also be used to frequency-lock the device to laboratory equipment.
Verify that any supplied reference clock has low phase noise.
3Configuration Options
The TRF3765 evaluation module ships configured for either integer mode or fractional mode. Each
configuration is designed to use different reference and PFD frequencies and also has the corresponding
loop-filter components. Differences in integer mode and fractional mode boards are listed in Table 2.
4
TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation ModuleSLWU076A–November 2011–Revised July 2012
The TRF3765EVM is designed to be a high-performance platform for the TRF3765 device. This section
describes the schematic, layout and stackup, and bill of materials corresponding to Revision D boards.
4.1Schematic
Physical Description
Table 2. Integer and Fractional Mode Configurations
C20 = 2200 pFC20 = 47 pF
C19 = 22000 pFC19 = 560 pF
R6 = 475 ΩR6 = 10 kΩ
C14 = 220 pFC14 = 4.7 pF
R4 = 475 ΩR4 = 0 Ω
C15 = 220 pFC15 = open
SLWU076A–November 2011–Revised July 2012TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation Module
71J7USB_SUPER-MINI_ABCON_SMRT_USBMNE20_FACONMNE20-5G5P10
285JP1-JP5JUMPER_1X2_100HDR_THVT_1X2_100_MSAMTECTSW-102-07-L-S
294MT1-MT4STANDOFF4-40 X 0.500"mfg125_platedKEYSTONE3480
This section provides troubleshooting sequences in Table 5 to resolve several of the most frequently
asked questions.
ProblemResponse
LD diode D2 won't light up
No readback from registersPrerelease device revisions may not support readback. Verify the device markings do not include a
No LO output
Spurs or unstable output
frequency
Poor phase noise
Troubleshooting FAQs
Table 5. Troubleshooting Sequences
Verify that the loop filter components correspond to the programmed PFD frequency.
Check power on device pin test points: TP12. TP13.TP19-TP23
Verify that one refclk is applied, generated either onboard or offboard.
Registers 1 to 6 must be initialized. Reload the start-up macro. Execute VCO calibration after
initialization is complete.
Fractional mode operation must set LD_ANA_PREC* at low precision (1).
Verify GUI communication with the device. Readback value fields display nonzero hexadecimal
values after a register is written. The GUI Low Level display allows direct register readback.
Using the GUI Low Level tab, read registers. Verify that read ADDR bits are correct and that no N.U.
bits have been initialized. Reset the device by removing power if a faulty address has been sent to
the device or if any N.U. bits have been set.
Measure voltage on TP8. Multimeter measurements below 2 V but above 0.5 V indicate toggling LD.
Verify Cal_Clk frequency.
High Level tab readback is supported on GUI revision 6 or later. Low Level readback is supported on
all GUI releases.
P prefix on the first line.
On the GUI Start Up tab, Disconnect, verify that Simulate Connection is not selected, then Connect.
Verify that the buffer is configured to be powered on by reading back register 4 on the GUI Low
Level tab. 0 = on, and 1 = off.
Verify that registers are successfully reading back from the device to confirm communication.
Check power on device pin test points: TP12, TP13, TP19-TP23
Verify that one refclk is applied, generated either onboard or offboard.
Remove any monitoring equipment from the VTune tap on TP12.
Verify that EN_DITH, EN_ISOURCE are set properly for integer or fractional mode. Verify
VCO_BIAS is set properly for the applied VCC_TK voltage level. In fractional mode, verify that
MOD_ORD is third (2) and DITH_SEL is Random (0).
Eliminate ground loops in power supplies.
Verify that the installed loop filter corresponds to the applied refclk and PFD frequency.
Verify that the power supply is clean and is not an unfiltered switching power supply.
Revert the board to shipping hardware configuration, load a factory-supplied, start-up file, and verify
phase noise against data sheet measurements.
SLWU076A–November 2011–Revised July 2012TRF3765 Integer/Fractional-N PLL With Integrated VCO Evaluation Module
Texas Instruments (TI) provides the enclosed Evaluation Board/Kit/Module (EVM) under the following conditions:
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arising from the handling or use of the goods.
Should this evaluation board/kit not meet the specifications indicated in the User’s Guide, the board/kit may be returned within 30 days from
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For EVMs annotated as FCC – FEDERAL COMMUNICATIONS COMMISSION Part 15 Compliant
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FCC Interference Statement for Class A EVM devices
This equipment has been tested and found to comply with the limits for a Class A digital device, pursuant to part 15 of the FCC Rules.
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FCC Interference Statement for Class B EVM devices
This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to part 15 of the FCC Rules.
These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment
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this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and
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• Reorient or relocate the receiving antenna.
• Increase the separation between the equipment and receiver.
• Connect the equipment into an outlet on a circuit different from that to which the receiver is connected.
• Consult the dealer or an experienced radio/TV technician for help.
For EVMs annotated as IC – INDUSTRY CANADA Compliant
This Class A or B digital apparatus complies with Canadian ICES-003.
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Cet appareil numérique de la classe A ou B est conforme à la norme NMB-003 du Canada.
Les changements ou les modifications pas expressément approuvés par la partie responsable de la conformité ont pu vider l’autorité de
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(p.i.r.e.) ne dépasse pas l'intensité nécessaire à l'établissement d'une communication satisfaisante.
Le présent émetteur radio a été approuvé par Industrie Canada pour fonctionner avec les types d'antenne énumérés dans le manuel
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【【Important Notice for Users of this Product in Japan】】
This development kit is NOT certified as Confirming to Technical Regulations of Radio Law of Japan
If you use this product in Japan, you are required by Radio Law of Japan to follow the instructions below with respect to this product:
1. Use this product in a shielded room or any other test facility as defined in the notification #173 issued by Ministry of Internal Affairs and
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