TEXAS INSTRUMENTS TPS68000 Technical data

(6,4 mm x 7,8 mm)

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GA

GB

GC

GD

SA

PGND

SC

V5A

V5C

V5

CA−

CSEN

VA−

OCP

PH

SET

EN

VCC

VREF

GND

STC

ABR

BF

FAULT

VSEN

BBR

BC

C

1

Q

A

TPS68000

2 V

3.3 V

R

1

C

5

C

7

VLOGIC

Supply Voltage

8V .. 30V

Error Output

Operating Frequency

Device Enable

Lamp current

(Analog Dimming Input)

Burst Duty Cycle

(Burst Dimming Input)

Direct Burst Dimming Input

(Frequency + Duty Cycle)

C

10

C

3

C

4

C

2

C

12

C

13

R

4

R

3

C

8

C

9

SYNC

R

2

2.0 V

0 V

CAO

VAO

C

14

Q

C

Q

B

Q

D

T

1

C

6

0 V

0 V

Burst Frequency

Synchronization

Synchronization Phase Shift

SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006

HIGHLY EFFICIENT PHASE SHIFT FULL BRIDGE CCFL CONTROLLER

FEATURES DESCRIPTION

• 8-V to 30-V Input Voltage Range

• Full Bridge Topology With Integrated Gate

Drives for 4 NMOS Switches

• Synchronizable Constant Frequency

Operation

• Programmable Phase Delays of Operating

Frequency for Master-Slave Operation

• Lamp Voltage and Lamp Current Regulation

• Analog and Burst Dimming

• Configurable Distributed Burst Dimming in

Multiple Controller Applications

• Programmable Voltage Regulation Timeout

for Startup and Fault Conditions

• Open-Lamp and Short-Circuit Protection

• Internal Over-Temperature Protection converter circuits driving multi-lamp applications,

• Undervoltage Lockout

• 30-pin TSSOP Package

APPLICATIONS

• CCFL Backlight Power Supplies for Desktop

Monitors and LCD TVs

• CCFL Backlight Power Supplies for Notebook

Computers

The TPS68000 device provides a power supply
controller solution for CCFL backlight applications in a
large variety of applications. The wide input voltage
range of 8 V to 30 V makes it suitable to be powered
directly from regulated 12-V or 24-V rails, or any
other source with output voltages in this range. When
using a 10% accurate regulated 5-V rail, it also can
be used in notebook computers or other portable
battery-powered equipment having lower minimum
supply voltages. The controller is capable of driving
the gates of all 4 NMOS switches directly without the
need for any additional circuitry, like dedicated gate
drivers or gate-drive transformers. The wide input
voltage range also makes it easy to design CCFL
converters with higher input voltages like 120 V or
400 V available at the output of a power factor
correction unit. The TPS68000 also supports CCFL

either by using higher power-rated switches and
transformers, or using several TPS68000s
synchronized. When synchronized, they can be
operated either at the same frequency and phase, or
phase shifted to minimize RMS input current. Already
implemented smart dimming features, such as
support of distributed dimming, also help to optimize
the performance of multi-controller applications.

(Continued on next page)

TPS68000

Distributed Dimming is a registered trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Copyright © 2005–2006, Texas Instruments Incorporated

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TPS68000

SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

DESCRIPTION (CONTINUED)

To start the lamp, an automatic strike control is implemented. It smoothly increases the lamp voltage by
sweeping the operating frequency across the self resonance frequency of the transformer-series capacitor
resonant circuit. During this time the maximum lamp voltage is limited and regulated by a voltage control loop
until the lamp current increases to a value allowing the current control loop to take over control. The lamp current
is regulated over a wide current range. To set the lamp brightness, analog and PWM dimming circuits are
implemented. Analog and PWM dimming can be used independent of each other to control lamp brightness over
a wide range.

To protect the circuit during fault conditions, for example broken, disconnected, or shorted lamps, overvoltage
protection and overcurrent protection circuits are implemented. To protect the TPS68000 from overheating, an
internal temperature sensor is implemented that triggers controller turn-off at an excessive device temperature.

The device is packaged in a 30-pin TSSOP package measuring 6,4 mm x 7,8 mm (DBT).

AVAILABLE DEVICE OPTIONS

T

A

–40 ° C to 85 ° C 30-Pin TSSOP TPS68000DBT

(1) The DBT package is available taped and reeled. Add R suffix to device type (e.g., TPS68000DBTR) to order quantities of 2000 devices

per reel.

PACKAGE PART NUMBER

(1)

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

Input voltage range on VCC, EN, FAULT –0.3 V to 33 V
Input voltage range on SYNC, SET, PH, STC, ABR, BBR, BF, BC, VREF, VA-, VAO, CA-, CAO –0.3 V to 6 V
Input voltage range on VSEN, CSEN, OCP –6 V to 6 V
Input voltage range on GD, GB, V5 –0.3 V to 6 V
maximum differential voltage between GA, V5A and SA 6 V
maximum differential voltage between GC, V5C and SC 6 V
maximum differential voltage between SA and PGND 35 V
maximum differential voltage between SC and PGND 35 V
Operating virtual junction temperature range, T
Storage temperature range T

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated uner "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

stg

J

(1)

TPS68000

–40 ° C to 150 ° C
–65 ° C to 150 ° C

DISSIPATION RATINGS

PACKAGE

DBT 63.9 ° C/W 1565 mW 16 mW/ ° C 860 mW 626 mW

THERMAL RESISTANCE POWER RATING DERATING FACTOR POWER RATING POWER RATING

θ

JA

TA≤ 25 ° C ABOVE TA= 25 ° C TA≤ 70 ° C TA≤ 85 ° C

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

V
T
T

Supply voltage at VCC 8.0 30 V

I

Operating free air temperature range –40 85 ° C

A

Operating virtual junction temperature range –40 125 ° C

J

2

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SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006

ELECTRICAL CHARACTERISTICS

over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25 ° C) (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

MAIN CONTROL

V

5

I

OUT-V5

V

UVLO

V

OL

V

lkg

V

IL

V

IH

I

STC

I

STC

I

STC

V

REF

I

OUT-VREF

GATE DRIVE

MAIN OSCILLATOR

f 30 100 kHz

f

SYNC

V

IL

V

IH

I

SYNC

I

SYNC

Internal control supply regulator I
Control supply output current 25 mA

< 25 mA 4.5 5 5.5 V

OUT-V5

including internal current

consumption
Under voltage lockout threshold at V5 Voltage at V5 decreasing 4.0 4.1 4.3 V
FAULT output low voltage I
FAULT output leakage current V

= 500 µA 0.2 0.4 V

FAULT

= 5 V 0.1 1 µA

FAULT

EN input low voltage 0.4 V
EN input high voltage 1.4 V
EN input current V

= 24 V 0.05 0.1 µA

CC

STC source current during strike 6 µA
STC source current during wait 2 µA

STC source and sink current 10 µA

normal operation, V

1.25 V

=

STC

Overtemperature protection 140 ° C
Overtemperature hysteresis 20 ° C
Quiescent current into VCC VCC = 12 V, V5 = 5.5 V 30 50 µA
Quiescent current into VCC VCC = V5 = 5.5 V 25 40 µA
Quiescent current into V5 VCC = V5 = 5.5 V 1000 1500 µA
Shutdown current into VCC VCC = V5 = 5.5 V, EN = 0V 1 2 µA
Shutdown current into V5 VCC = V5 = 5.5 V, EN = 0V 1 2 µA
Shutdown current into VCC VCC = 12 V, EN = 0V 2.5 5 µA
Reference Voltage I

OUT-VREF

< 5 mA 3.27 3.3 3.33 V

Reference output current 5 mA

High side drive sink resistance ID= 0.05 A 1.2 2.0 Ω
High side drive source resistance ID= 0.05 A 1.5 2.5 Ω
High side drive rise time CG= 4.7 nF, SA= SC= 0 V, 35 50 ns

V

= V

5A

= 5 V

5C

High side drive fall time CG= 4.7 nF 15 25 ns
Time delay between high side off and CG= 4.7 nF 100 ns

low side on
Time delay between low side off and CG= 4.7 nF 100 ns

high side on
Low side drive sink resistance ID= 0.05 A 1.2 2.0 Ω
Low side drive source resistance ID= 0.05 A 1.5 2.5 Ω
Low side drive rise time CG= 4.7 nF, V5= 5 V 35 50 ns
Low side drive fall time CG= 4.7 nF 15 25 ns

Oscillator frequency programming
range

Frequency capture range for
synchronization

0.5 x f 2 x f

SYNC low voltage 0.4 V
SYNC high voltage 1.4 V

SYNC input current 0.5 1.5 µA
SYNC drive current V

VPH≤ V5- 1.3 V, V

V

≥ 1.4 V, V

SYNC

= 3.3

SYNC

= 5 V 1000 1250 1500 µA

PH

TPS68000

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TPS68000

SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006

ELECTRICAL CHARACTERISTICS (continued)

over recommended free-air temperature range and over recommended input voltage range (typical at an ambient temperature
range of 25 ° C) (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

I

SYNC

V

SET

I

PH

V

PH

VOLTAGE AND CURRENT CONTROL

R

CSEN

R

CSEN

R

VSEN

R

VSEN

I

, I

CAO

I

, I

CAO

VREF
VREF
VREF
I

OCP

I

OCP

VREF

DIMMING

I

ABR

V

ABR

I

BBR

V

BBR

I

BF

f

Burst

f

BC

t

r

I

BC

V

IL

V

IH

SYNC sink current V
Minimum pulse width for

synchronization

SYNC

≤ 0.4 V, V

= 5 V 1000 1250 1500 µA

PH

100 ns

SET output voltage 1.25 V
Phase shift of the main oscillator clock V
PH input current V
Threshold for programming device as

main oscillator frequency master

Current sense input impedance V
Current sense input impedance V
Voltage sense input impedance V
Voltage sense input impedance V
Voltage and current amplifier output

VAO

source current
Voltage and current amplifier output

VAO

sink current
Voltage regulator reference voltage (0.8 × V

VREG

Overvoltage comparator threshold V

OVP

Current regulator reference voltage V

CREG

Overcurrent comparator input current V
Overcurrent comparator input current V
Overcurrent comparator threshold V

OCP

ABR input current V
ABR input voltage range for lamp

current programming
BBR input current V
Burst duty cycle V
BBR input voltage threshold for

selecting synchronized burst dimming

= 0.1 V .. 1.9 V 90 ° / V

PH

= 2.0 V 0.1 1 µA

PH

V5– 1.3 V V5– 0.7 V V

= 3.3 V 35 k Ω

CSEN

= –3.3 V 25 k Ω

CSEN

= 3.3 V 25 k Ω

VSEN

= –3.3 V 30 k Ω

VSEN

V

, V

CAO

V

CAO

OCP
OCP

ABR

BC = V

BBR
BBR

= 2.5 V 55 µA

VAO

, V

= 2.5 V 200 µA

VAO

) / π V

REF

REF

ABR

= 3.3V 0.1 1 µA
= –3.3V 50 µA

REF

= 3.3 V 0.01 0.1 µA

5

0 3.3 V

= 2.0 V 0.1 1 µA
= 0 V .. 2 V 50 % / V

V5– 1.3 V V5– 0.7 V V

BF source current 10 µA
Internal burst frequency range 20 1000 Hz
Frequency lock / capture range for 0.5 x

synchronized burst dimming f

Burst

Burst current pulse rise time 400 µs
BC input current V

= 3.3V 0.1 1 µA

BC

BC input low voltage 0.4 V
BC input high voltage 1.4 V
minimum pulse width at BC 100 ns
Phase shift of the dimming burst V

compared to BC clock dimming selected

= 0 V .. 2 V, distributed

PH

180 ° / V

/ π V

1.5 x f

Burst

PH

V

V

BBR

PH

4

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1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

30
29
28
27
26
25
24
23
22
21
20
19
18
17
16

SYNC

SET
STC

PH

BBR

BC

BF
ABR
VAO

VA−

VSEN

CA−

CAO

CSEN

OCP

VREF
GND
SA
GA
V5A
GB
VCC
V5
PGND
GD
V5C
GC
SC
EN
FAULT

TPS68000

SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006

PIN ASSIGNMENTS

DBT PACKAGE

(TOP VIEW)

Terminal Functions

TERMINAL

NAME NO.

ABR 8 I Analog brightness programming input. A DC voltage applied at that pin programs the lamp current

BBR 5 I Burst brightness programming input. A DC voltage applied at that pin programs the duty cycle of the

BC 6 I Burst control. A PWM signal applied at that pin is directly used for burst dimming. Frequency and

BF 7 I Burst frequency programming. A capacitor at that pin programs the burst frequency.
CA- 12 I Current amplifier negative input. This input is used to connect the compensation capacitor for

CAO 13 O Current amplifier output. This is the output for the current amplifier. It is used to connect the

CSEN 14 I Current sense. Measuring input for the lamp current. The applied voltage (coming from a shunt

EN 17 I Enable input. Logic high enables the device.
FAULT 16 O Error output, any detected malfunctioning of the application will be reported as error on this pin.

GA 27 O Gate drive output of switch A
GB 25 O Gate drive output of switch B
GC 19 O Gate drive output of switch C
GD 21 O Gate drive output of switch D
GND 29 Analog ground pin. Reference ground for all control signals.
OCP 15 I Over current protection. This input is used to monitor a voltage derived from a current sensor in any

PGND 22 Reference ground for the gate drivers and the gate drive supply.

I/O DESCRIPTION

the current regulator regulates. 0 V means no current and 3.3 V means maximum current.

burst pulses generated to dimm the brightness. 0 V means zero duty cycle and 2 V means
maximum duty cycle. Applying V5 (5 V) programs the device to operate in synchronized burst
dimming mode.

duty cycle are used directly. This input has priority against the burst frequency programming with
BBR and BF

compensating the current loop.

compensation capacitor for the current loop.

resistor) will be used for lamp current regulation. Sensed AC voltages can be applied directly. They
will be rectified internally.

Error means the output is pulled low. The output is open drain to allow connecting multiple error
outputs of similar devices together.

part of the converter. This voltage is compared to an internal reference voltage. Exceeding the
internal reference voltage causes the device logic to turn the device off and report an error signal at
the fault pin.

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TPS68000

SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006

PIN ASSIGNMENTS (continued)

Terminal Functions (continued)

TERMINAL

NAME NO.

PH 4 I Phase delay programming input. A voltage between 0 V and 2 V applied to that pin programs the

SA 28 Source connection of switch A
SC 18 Source connection of switch C
SET 2 I Operating frequency programming input. A resistor connected to this pin programs the internal

STC 3 I Startup capacitor. A capacitor connected to that pin determines the the time the device waits in

SYNC 1 I/O Synchronization input or operating frequency output. If the device is configured as master (see PH)

V5 23 I/O Input/Output of the internal 5 V regulator for gate drive supply and control supply. A capacitor must

V5A 26 O Supply input for the gate driver of the high-side switch A. A capacitor must be connected to that pin

V5C 20 O Supply input for the gate driver of the high side switch C. A capacitor must be connected to that pin

VA- 10 I Voltage amplifier negative input. This input is used to connect the compensation capacitor for

VAO 9 O Voltage amplifier output. This is the output for the voltage amplifier. It is used to connect the

VCC 24 I Device supply voltage input. VCC must be connected to V5 in case the device is powered directly

VREF 30 O Voltage reference. Output of the internal 3.3 V reference for use with all the analog control inputs.
VSEN 11 I Voltage sense. Measuring input for the lamp voltage. This voltage is used for lamp voltage

I/O DESCRIPTION

phase delay of the operating frequency compared to the synchronizing frequency. Applying V5 (5.0
V) programs the device as a master regarding the main oscillator frequency (see SYNC). The
voltage applied to that pin is also used to determine the phase delay in a distributed dimming
configuration

operating frequency.

voltage regulation for the lamp to strike.

the pin is used to provide the synchronization frequency for the slaves. Otherwise the device works
as slave and uses the applied frequency at that pin for synchronizing the operating frequency.

be connected to that pin to decouple switching noise caused by the gate drivers.

to supply the gate driver during switching (bootstrap).

to supply the gate driver during switching (bootstrap).

compensating the voltage loop.

compensation capacitor for the voltage loop.

from a regulated 5 V rail.

regulation (open lamp regulation) and overvoltage protection. Sensed AC voltages can be applied
directly. They are rectified internally.

6

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GA

GB

GC

GD

SA

PGND

SC

V5A

V5C

V5

Gate

Control

CA−

CAO

VA−

Main Control

VREF_OCP

OCP

Oscillator

Phase Shift

Control

SET

PH

EN

VCC

VREF

GND

Startup

and Strike

Control

STC

Analog

and

Burst

Dimming

ABR

BF

V5

VREF

VREF_VREG

VREF_OVP

OVP

V5

OVP

Control Supply

OCP

FAULT

OCP

VAO

OVP

BBR

BC

V5

VREF

Rectifier

CSEN

Rectifier

VSEN

SYNC

GA

GB

GC

GD

SA

PGND

SC

V5A

V5C

V5

CA−

CSEN

VA−

OCP

PH

SET

EN

VCC

VREF

GND

STC

ABR

BF

FAULT

VSEN

BBR

BC

C

1

Q

A

TPS68000

2 V

3.3 V

R

1

C

5

C

7

VLOGIC

Supply Voltage

8V .. 30V

Error Output

Operating Frequency

Device Enable

Lamp current

(Analog Dimming Input)

Burst Duty Cycle

(Burst Dimming Input)

Direct Burst Dimming Input

(Frequency + Duty Cycle)

C

10

C

3

C

4

C

2

C

12

C

13

R

4

R

3

C

8

C

9

SYNC

R

2

2.0 V

0 V

CAO

VAO

C

14

Q

C

Q

B

Q

D

T

1

C

6

0 V

0 V

Burst Frequency

Synchronization

Synchronization Phase Shift

FUNCTIONAL BLOCK DIAGRAM (TPS68000)

TPS68000

SLVS524A – OCTOBER 2005 – REVISED FEBRUARY 2006

PARAMETER MEASUREMENT INFORMATION

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