TEXAS INSTRUMENTS TPS62110, TPS62111, TPS62112 Technical data
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SYNC
GND PGND
SW
V
O
= 3.3 V
6.8 Hm
C = 22 F
6.3 V
O
m
VIN
LBI
C = 10 F
25 V
I
m
1 Fm
V = 3.8 V to 17 V
I
VIN
EN
VINA
PGNDGND PwPD
AGND
TPS62111
SW
LBO
PG
1 M
FB
TPS62111
Efficiency vs Output Current
100
0
90
70
40
20
80
50
60
30
10
0.0001 0.001 0.01 0.1 10
1
I - Output Current- A
O
Efficiency - %
5 V
4.2 V
12 V
8.4 V
V = 3.3 V
T
PFM Mode
O
A
= 25 C
o
17-V, 1.5-A, SYNCHRONOUS STEP-DOWN CONVERTER
FEATURES DESCRIPTION
• High-Efficiency Synchronous Step-Down
Converter With up to 95% Efficiency
• 3.1-V to 17-V Operating Input Voltage Range
• Adjustable Output Voltage Range From
1.2 V to 16 V
• Fixed Output Voltage Options Available in
3.3 V and 5 V
• Synchronizable to External Clock Signal up to
1.4 MHz
• Up to 1.5-A Output Current
• High Efficiency Over a Wide Load Current
Range Due to PFM/PWM Operation Mode
• 100% Maximum Duty Cycle for Lowest
Dropout
• 20-µA Quiescent Current (Typical)
• Overtemperature and Overcurrent Protected
• Available in 16-Pin QFN Package
APPLICATIONS
• Point-of-Load Regulation From 12-V Bus
• Organizers, PDAs, and Handheld PCs
• Handheld Scanners
TPS62110
TPS62111
TPS62112
SLVS585 – JULY 2005
The TPS6211x devices are a family of low-noise
synchronous step-down dc-dc converters that are
ideally suited for systems powered from a 2-cell Li-ion
battery or from a 12-V or 15-V rail.
The TPS6211x is a synchronous PWM converter with
integrated – and P-channel power MOSFET switches.
Synchronous rectification is used to increase efficiency and to reduce external component count. To
achieve highest efficiency over a wide load current
range, the converter enters a power-saving,
pulse-frequency modulation (PFM) mode at light load
currents. Operating frequency is typically 1 MHz,
allowing the use of small inductor and capacitor
values. The device can be synchronized to an external clock signal in the range of 0.8 MHz to 1.4 MHz.
For low noise operation, the converter can be
operated in PWM-only mode. In the shutdown mode,
the current consumption is reduced to less than 2 µA.
The TPS6211x is available in the 16-pin (RSA) QFN
package, and operates over a free-air temperature
range of –40 ° C to 85 ° C.
TYPICAL APPLICATION
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2005, Texas Instruments Incorporated
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TPS62110
TPS62111
TPS62112
SLVS585 – JULY 2005
This device contains circuits to protect its inputs and outputs against damage due to high static voltages
or electrostatic fields. These circuits have been qualified to protect this device against electrostatic
discharges; HBM according to EIA/JESD22-A114-B, MM according EIA/JESD22-A115-A, and CDM
according EIA/JESD22C101C; however, it is advised that precautions be taken to avoid application of
any voltage higher than maximum-rated voltages to these high-impedance circuits. During storage or
handling the device leads should be shorted together or the device should be placed in conductive foam.
In a circuit, unused inputs should always be connected to an appropriate logic voltage level, preferably
either VCC or ground. Specific guidelines for handling devices of this type are contained in the
publication Guidelines for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices and Assemblies
available from Texas Instruments.
ORDERING INFORMATION
PLASTIC QFN 16 PIN
(RSA) FUNCTIONALITY
TPS62110 Adjustable 1.2 V to 16 V Standard TPS62110
TPS62111 3.3 V Standard TPS62111
TPS62112 5 V Standard TPS62112
(1) The RSA package is available in tape and reel. Add R suffix (TPS62110RSAR) to order quantities of
3000 parts per reel. Add T suffix (TPS62110RSAT) to order quantities of 250 parts per reel.
(1)
OUTPUT VOLTAGE MARKING
LBI/LBO
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
UNIT
V
CC
V
I
I
O
T
J
T
A
T
stg
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
DISSIPATION RATINGS
PACKAGE
RSA 2.5 W 25 mW/ ° C 1.375 W 1 W
(1) Based on a thermal resistance of 40 K/W soldered onto a high K board.
Supply voltage at VIN, VINA –0.3 V to 20 V
Voltage at SW –0.3 V to V
Voltage at EN, SYNC, LBO, PG –0.3 V to 20 V
Voltage at LBI, FB –0.3 V to 7 V
Output current at SW 2400 mA
Maximum junction temperature 150 ° C
Operating free-air temperature –40 ° C to 85 ° C
Storage temperature –65 ° C to 150 ° C
Lead temperature 1,6 mm (1/16-inch) from case for 10 seconds 300 ° C
(1)
TA≤ 25 ° C DERATING FACTOR TA= 70 ° C TA= 85 ° C
POWER RATING ABOVE TA= 25 ° C POWER RATING POWER RATING
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
V
T
Supply voltage at VIN , VINA 3.1 17 V
CC
Maximum voltage at power-good, LBO, EN, SYNC 17 V
Operating junction temperature –40 125 ° C
J
I
2
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TPS62110
TPS62111
TPS62112
SLVS585 – JULY 2005
ELECTRICAL CHARACTERISTICS
VI= 12 V, VO= 3.3 V, IO= 600 mA, EN = VI, TA= –40 ° C to 85 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT
V
I
(Q)
I
(SD)
ENABLE
V
V
I
IKG
I
(EN)
V
POWER SWITCH
r
DS(ON)
r
DS(ON)
POWER GOOD OUTPUT , LBI, LBO
V
V
I
OL
V
ILBI LBI input leakage current 10 100 nA
V
OSCILLATOR
f
S
f
(SYNC)
V
V
Input voltage range 3.1 17 V
I
IO= 0 mA, SYNC = GND, VI= 7.2 V, 20
Operating quiescent current µA
TA= 25 ° C
IO= 0 mA, SYNC = GND, VI= 17 V
Shutdown current µA
EN high-level input voltage 1.3 V
IH
EN low-level input voltage 0.3 V
IL
EN = GND 1.5 5
EN = GND, TA= 25 ° C, VI= 7.2 V 1.5 3
(1)
(1)
EN trip-point hysteresis 170 mV
EN input leakage current EN = GND or VI, VI= 12 V 0.01 0.2 µA
EN input current 0.6 V ≤ V
Undervoltage lockout threshold Input voltage falling 2.8 3 3.1 V
(UVLO)
≤ 4 V 10 20 µA
(EN)
Undervoltage lockout hysteresis 250 300 mV
VI≥ 5.4 V; IO= 350 mA 165 250
P-channel MOSFET on-resistance VI= 3.5 V; IO= 200 mA 340 m Ω
VI= 3 V; IO= 100 mA 490
P-channel MOSFET leakage
current
V
= 17 V 0.1 1 µA
DS
P-channel MOSFET current limit VI= 7.2 V, VO= 3.3 V 2400 mA
VI≥ 5.4 V; IO= 350 mA 145 200
N-channel MOSFET on-resistance VI= 3.5 V; IO= 200 mA 170 m Ω
VI= 3 V; IO= 100 mA 200
N-channel MOSFET leakage
current
Power good trip voltage VO- V
(PG)
Power good delay time µs
PG, LBO output low voltage V
OL
V
= 17 V 0.1 2 µA
DS
1.6%
VOramping positive 50
VOramping negative 200
= 0.8 × VOnominal, IOL= 1 mA 0.3 V
(FB)
PG, LBO sink current 1 mA
PG, LBO output leakage current V
= VOnominal, V
(FB)
= V
(LBI)
I
0.01 0.25 µA
Minimum supply voltage for valid power 3 V
good, LBI, LBO signal
Low battery input trip voltage Input voltage falling 1.256 V
LBI
Low battery input trip-point
accuracy
Low battery input hysteresis 25 mV
LBI,HYS
Oscillator frequency 900 1000 1100 kHz
Synchronization range CMOS-logic clock signal on SYNC pin 800 1400 kHz
SYNC high-level input voltage 1.5 V
IH
SYNC low-level input voltage 0.3 V
IL
23 26
1.5%
(1) Device is not switching.
3
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TPS62110
TPS62111
TPS62112
SLVS585 – JULY 2005
ELECTRICAL CHARACTERISTICS (continued)
VI= 12 V, VO= 3.3 V, IO= 600 mA, EN = VI, TA= –40 ° C to 85 ° C (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
I
lkg
OUTPUT
V
V
I
O
η Efficiency 92%
SYNC input leakage current SYNC = GND or VIN 0.01 0.2 µA
SYNC trip-point hysteresis 170 mV
SYNC input current 0.6 V ≤ V
Duty cycle of external clock signal 30% 90%
Adjustable output voltage range TPS62110 1.153 16 V
O
Feedback voltage TPS62110 1.153 V
FB
FB leakage current TPS62110 10 100 nA
Feedback voltage tolerance TPS62110 –2% 2%
Fixed output voltage tolerance
Maximum output current mA
Current into internal voltage divider for
fixed voltage versions
Duty cycle range for main switches at 1 MHz 10% 100%
Minimum tontime for main switch 100 ns
Shutdown temperature 145 ° C
Start-up time IO= 800 mA, VI= 12 V, Vo= 3.3 V 1 ms
(3)
TPS62111 –3% 3%
TPS62112 –3% 3%
VI≥ 3 V (once undervoltage lockout
voltage exceeded)
VI≥ 3.5 V 500
VI≥ 4.3 V 1200
VI≥ 6 V 1500
VI= 7.2 V; VO= 3.3 V; IO= 600 mA
VI= 12 V, Vo= 5 V, Io= 600 mA
≤ 4 V 10 20 µA
(SYNC)
VI= 3.1 V to 17 V;
0 mA < IO< 1500 mA
VI= 3.8 V to 17 V;
0 mA < IO< 1500 mA
VI= 5.5 V to 17 V;
0 mA < IO< 1500 mA
(2)
(2)
(2)
100
5 µA
(2) The maximum output current depends on the input voltage. See the maximum output current for further restrictions on the minimum
input voltage.
(3) The output voltage accuracy includes line and load regulation over the full temperature range TA= -40 ° C to 85 ° C. See the section for
no-load operation in this data sheet.
4
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16 15 14 13
5 6 7 8
1
2
3
4 9
GND
GND
FB
AGND
PGND
Exposed
Thermal
Pad
VIN
VIN
EN
PGND
SW
LBI
VINA
SW
PG
SYNC
LBO
12
11
10
TPS62110
TPS62111
TPS62112
SLVS585 – JULY 2005
DEVICE INFORMATION
PIN ASSIGNMENT TOP VIEW
TERMINAL FUNCTIONS
TERMINAL
NAME NO.
EN 4 I
FB 10 I
LBO 6 O Open-drain, low-battery output. This pin is pulled low if LBI is below its threshold.
GND 11, 12 I Ground
LBI 7 I Low-battery input
SW 14, 15 O
PG 13 O between PG and VOUT. The output goes active high when the output voltage is greater than 98.4% of
PGND 1, 16 I Power ground. Connect all power grounds to this pin.
AGND 9 I Analog ground, connect to GND and PGND
SYNC 5 I Input for synchronization to external clock signal. Synchronizes the converter switching frequency to an
VIN 2, 3 I Supply voltage input (power stage)
VINA 8 I Supply voltage input (support circuits)
PowerPAD™ Connect to AGND
I/O DESCRIPTION
Enable. A logic high enables the converter; logic low forces the device into shutdown mode reducing the
supply current to less than 2 µA.
Feedback pin for the fixed output voltage option. For the adjustable version, an external resistive divider
is connected to this pin. The internal voltage divider is disabled for the adjustable version.
Connect the inductor to this pin. This pin is the switch pin and connected to the drain of the internal
power MOSFETS.
Power good comparator output. This is an open-drain output. A pullup resistor should be connected
the nominal value.
external clock signal with CMOS level:
SYNC = HIGH: Low-noise mode enabled, fixed frequency PWM operation is forced
SYNC = LOW (GND): Power save mode enabled, PFM/PWM Mode enabled
5
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_
+
_
+
_
+
_
+
_
+
REF
REF
Load Comparator
I
AVG
Comparator
Current Limit Comparator
P-Channel
Power MOSFET
Driver
Shoot-Through
Logic
Control
Logic
Soft Start
1-MHz
Oscillator
Comparator
S
R
N-Channel
Power MOSFET
Comparator High
Comparator Low
Comparator High 2
V
(COMP)
Sawtooth
Generator
V
I
Undervoltage
Lockout
Bias Supply
_
+
Comparator High
Comparator Low
Compensation
V = 1.153 V
REF
R2
(See Note A)
R1
V
I
EN
SW
FB PGND
Gm
Thermal
Shutdown
Vina
_
+
_
+
SKIP Comparator
_
+
_
+
PG
LBO
LBI
GND
1.256 V
TPS62110
TPS62111
TPS62112
SLVS585 – JULY 2005
FUNCTIONAL BLOCK DIAGRAM
A. For the adjustable version (TPS62110), the internal feedback divider is disabled and the FB pin is directly connected
to the internal GM amplifier.
6
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100
0
90
70
40
20
80
50
60
30
10
0.0001 0.001 0.01 0.1 10
1
I - Output Current- A
O
Efficiency - %
15 V
12 V
8.4 V
V = 5 V
T
PWM Mode
O
A
= 25 C
o
100
0
90
70
40
20
80
50
60
30
10
0.0001 0.001 0.01 0.1 10
1
I - Output Current- A
O
Efficiency - %
15 V
12 V
8.4 V
V = 5 V
T
PFM Mode
O
A
= 25 C
o
TPS62110
TPS62111
TPS62112
SLVS585 – JULY 2005
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
Efficiency vs Output current (5 V) 1, 2
Efficiency vs Output current (3.3 V) 3, 4, 5
Maximum output current vs Input voltage 6
Efficiency vs Output current (1.8 V) 7, 8
Efficiency vs Output current (1.5 V) 9, 10
Line transient response 11
Load transient response 12
Output ripple 13
Start-up timing 14
Switching frequency vs Input voltage 15
Quiescent current vs Input voltage 16
Graphs with V
= 1.8 V were taken using the circuit according to Figure 20 .
O
TPS62112 TPS62112
EFFICIENCY EFFICIENCY
OUTPUT CURRENT OUTPUT CURRENT
vs vs
Figure 1. Figure 2.
7
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