TEXAS INSTRUMENTS TPS5430, TPS5431 Technical data

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VIN

ENA

GND

VSENSE

BOOT

TPS5430/31

VIN VOUT

100

0 0.5 1 1.5 2.5 3 3.5

Efficiency − %

I OutputCurrent AO--

EfficiencyvsOutputCurrent

SimplifiedSchematic

VI=12V V =5V f =500kHz T =25 C

3-A, WIDE INPUT RANGE, STEP-DOWN SWIFT™ CONVERTER

FEATURES APPLICATIONS

• Wide Input Voltage Range:

– TPS5430: 5.5 V to 36 V – TPS5431: 5.5 V to 23 V

• Up to 3-A Continuous (4-A Peak) Output

Current

• High Efficiency up to 95% Enabled by 110-m Ω

Integrated MOSFET Switch

• Wide Output Voltage Range: Adjustable Down

to 1.22 V with 1.5% Initial Accuracy

• Internal Compensation Minimizes External

Parts Count

• Fixed 500 kHz Switching Frequency for Small

Filter Size

• Improved Line Regulation and Transient

Response by Input Voltage Feed Forward

• System Protected by Overcurrent Limiting,

Overvoltage Protection and Thermal Shutdown

• –40 ° C to 125 ° C Operating Junction

Temperature Range

• Available in Small Thermally Enhanced 8-Pin

SOIC PowerPAD™ Package

• For SWIFT™ Documentation, Application

Notes and Design Software, See the TI Website at www.ti.com/swift

TPS5430 TPS5431

SLVS632C – JANUARY 2006 – REVISED NOVEMBER 2006

• Consumer: Set-top Box, DVD, LCD Displays

• Industrial and Car Audio Power Supplies

• Battery Chargers, High Power LED Supply

• 12-V/24-V Distributed Power Systems

DESCRIPTION

As a member of the SWIFT™ family of DC/DC regulators, the TPS5430/TPS5431 is a high-output-current PWM converter that integrates a low resistance high side N-channel MOSFET. Included on the substrate with the listed features are a high performance voltage error amplifier that provides tight voltage regulation accuracy under transient conditions; an undervoltage-lockout circuit to prevent start-up until the input voltage reaches

5.5 V; an internally set slow-start circuit to limit inrush currents; and a voltage feed-forward circuit to improve the transient response. Using the ENA pin, shutdown supply current is reduced to 18 µ A typically. Other features include an active-high enable, overcurrent limiting, overvoltage protection and thermal shutdown. To reduce design complexity and external component count, the TPS5430/TPS5431 feedback loop is internally compensated. The TPS5431 is intended to operate from power rails up to 23 V. The TPS5430 regulates a wide variety of power sources including 24-V bus.

The TPS5430/TPS5431 device is available in a thermally enhanced, easy to use 8-pin SOIC PowerPAD™ package. TI provides evaluation modules and the SWIFT™ Designer software tool to aid in quickly achieving high-performance power supply designs to meet aggressive equipment development cycles.

SWIFT, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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TPS5430 TPS5431

SLVS632C – JANUARY 2006 – REVISED NOVEMBER 2006

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

ORDERING INFORMATION

INPUT VOLTAGE OUTPUT VOLTAGE PACKAGE

–40 ° C to 125 ° C 5.5 V to 36 V Adjustable to 1.22 V Thermally Enhanced SOIC (DDA) –40 ° C to 125 ° C 5.5 V to 23 V Adjustable to 1.22 V Thermally Enhanced SOIC (DDA)

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) The DDA package is also available taped and reeled. Add an R suffix to the device type (i.e., TPS5430DDAR). See applications section

of data sheet for PowerPAD™ drawing and layout information.

ABSOLUTE MAXIMUM RATINGS

over operating free-air temperature range (unless otherwise noted)

VIN –0.3 to 40

TPS5430 BOOT –0.3 to 50

Input voltage range

TPS5431 BOOT –0.3 to 35

lkg

T T

Source current PH Internally Limited Leakage current PH 10 µ A Operating virtual junction temperature range –40 to 150 ° C

Storage temperature –65 to 150 ° C

stg

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. (3) Approaching the absolute maximum rating for the VIN pin may cause the voltage on the PH pin to exceed the absolute maximum rating.

PH (steady-state) –0.6 to 40 VIN –0.3 to 25

PH (steady-state) –0.6 to 25 ENA –0.3 to 7 BOOT-PH 10 VSENSE –0.3 to 3 PH (transient < 10 ns) –1.2

(1) (2)

(1)

VALUE UNIT

PART NUMBER

(2) (2)

TPS5430DDA TPS5431DDA

(3)

DISSIPATION RATINGS

8 Pin DDA (2-layer board with solder) 8 Pin DDA (4-layer board with solder)

(1) (2)

PACKAGE

(3) (4)

THERMAL IMPEDANCE

JUNCTION-TO-AMBIENT

33 ° C/W 26 ° C/W

(1) Maximum power dissipation may be limited by overcurrent protection. (2) Power rating at a specific ambient temperature TAshould be determined with a junction temperature of 125 ° C. This is the point where

distortion starts to substantially increase. Thermal management of the final PCB should strive to keep the junction temperature at or

below 125 ° C for best performance and long-term reliability. See Thermal Calculations in applications section of this data sheet for more

information. (3) Test board conditions:

a. 3 in x 3 in, 2 layers, thickness: 0.062 inch.

b. 2 oz. copper traces located on the top and bottom of the PCB.

c. 6 thermal vias in the PowerPAD area under the device package. (4) Test board conditions:

a. 3 in x 3 in, 4 layers, thickness: 0.062 inch.

b. 2 oz. copper traces located on the top and bottom of the PCB.

c. 2 oz. copper ground planes on the 2 internal layers.

d. 6 thermal vias in the PowerPAD area under the device package.

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TPS5430 TPS5431

SLVS632C – JANUARY 2006 – REVISED NOVEMBER 2006

RECOMMENDED OPERATING CONDITIONS

MIN NOM MAX UNIT

VIN Input voltage range V

Operating junction temperature –40 125 ° C

ELECTRICAL CHARACTERISTICS

TJ= –40 ° C to 125 ° C, VIN = 12.0 V (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY VOLTAGE (VIN PIN)

VSENSE = 2 V, Not switching,

UNDERVOLTAGE LOCK OUT (UVLO)

VOLTAGE REFERENCE

OSCILLATOR

ENABLE (ENA PIN)

CURRENT LIMIT

THERMAL SHUTDOWN

OUTPUT MOSFET

DS(on)

Quiescent current

Start threshold voltage, UVLO 5.3 5.5 V Hysteresis voltage, UVLO 330 mV

Voltage reference accuracy V

Internally set free-running frequency 400 500 600 kHz Minimum controllable on time 150 200 ns Maximum duty cycle 87 89 %

Start threshold voltage, ENA 1.3 V Stop threshold voltage, ENA 0.5 V Hysteresis voltage, ENA 450 mV Internal slow-start time (0~100%) 6.6 8 10 ms

Current limit 4 5 6 A Current limit hiccup time 13 16 20 ms

Thermal shutdown trip point 135 162 ° C Thermal shutdown hysteresis 14 ° C

High-side power MOSFET switch m Ω

PH pin open Shutdown, ENA = 0 V 18 50 µ A

TJ= 25 ° C 1.202 1.221 1.239 IO= 0 A – 3 A 1.196 1.221 1.245

VIN = 5.5 V 150

TPS5430 5.5 36 TPS5431 5.5 23

3 4.4 mA

110 230

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PowerPAD

(Pin9)

BOOT

VSENSE

VIN

GND

ENA

DDAPACKAGE

(TOPVIEW)

TPS5430 TPS5431

SLVS632C – JANUARY 2006 – REVISED NOVEMBER 2006

PIN ASSIGNMENTS

TERMINAL FUNCTIONS

TERMINAL

NAME NO.

BOOT 1 Boost capacitor for the high-side FET gate driver. Connect 0.01 µ F low ESR capacitor from BOOT pin to PH pin. NC 2, 3 Not connected internally. VSENSE 4 Feedback voltage for the regulator. Connect to output voltage divider. ENA 5 On/off control. Below 0.5 V, the device stops switching. Float the pin to enable. GND 6 Ground. Connect to PowerPAD.

VIN 7 PH 8 Source of the high side power MOSFET. Connected to external inductor and diode.

PowerPAD 9 GND pin must be connected to the exposed pad for proper operation.

Input supply voltage. Bypass VIN pin to GND pin close to device package with a high quality, low ESR ceramic capacitor.

DESCRIPTION

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2.5

2.75

3.25

3.5

−50 −25 0 25 50 75 100 125

−JunctionT emperature − °C

−QuiescentCurrent

−mA

V =12V

460

470

480

490

500

510

520

530

−50 −25 0 25 50 75 100 125

f − OscillatorFrequency − kHz

T − JunctionTemperature − °C

1.210

1.215

1.220

1.225

1.230

-50 -25 0 25 50 75 100 125

T -JunctionTemperature-°C

V -VoltageReference-V

REF

0 5 10 15 20 25 30 35 40

=125

°C

=27°C

TJ=

– °40 C

ENA=0V

VI−InputV oltage −V

−ShutdownCurrent

−

Aµ

7.5

8.5

−50 −25 0 25 50 75 100 125 T

− JunctionTemperature − °C

− InternalSlowStartT

ime − ms

100

110

120

130

140

150

160

170

180

−50 −25 0 25 50 75 100 125

mΩ

−OnResistance

−

DS(on)

TJ−JunctionTemperature − °C

VI=12V

TPS5430 TPS5431

SLVS632C – JANUARY 2006 – REVISED NOVEMBER 2006

TYPICAL CHARACTERISTICS

OSCILLATOR FREQUENCY NON-SWITCHING QUIESCENT CURRENT

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 1. Figure 2.

SHUTDOWN QUIESCENT CURRENT VOLTAGE REFERENCE

vs vs

INPUT VOLTAGE JUNCTION TEMPERATURE

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 3. Figure 4.

ON RESISTANCE INTERNAL SLOW START TIME

vs vs

Figure 5. Figure 6.

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7.25

7.50

7.75

-50 -25 0 25

75 100 125

T -JunctionTemperature-°C

MinimumDutyRatio-%

120

130

140

150

160

170

180

−50 −25 0 25 50 75 100 125 T

− JunctionTemperature − °C

MinimumControllableOnT

ime

− ns

TPS5430 TPS5431

SLVS632C – JANUARY 2006 – REVISED NOVEMBER 2006

TYPICAL CHARACTERISTICS (continued)

MINIMUM CONTROLLABLE ON TIME MINIMUM CONTROLLABLE DUTY RATIO

vs vs

JUNCTION TEMPERATURE JUNCTION TEMPERATURE

Figure 7. Figure 8.

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FUNCTIONAL BLOCK DIAGRAM

VIN

UVLO

ENABLE

Thermal

Protection

Reference

Overcurrent

GateDrive

Oscillator

Ramp

Generator

VREF

ENA

GND

BOOT

SHDN

VIN

112.5%VREF

VSENSE

OVP

HICCUP

SHDN

FeedForward

BOOT

POWERPAD

VIN

VOUT

5 µA

1.221VBandgap SlowStart

Boot

Regulator

Error

Amplifier

Gain=25

PWM

Comparator

Protection

Gate Driver

Control

VSENSE

TPS5430 TPS5431

SLVS632C – JANUARY 2006 – REVISED NOVEMBER 2006

APPLICATION INFORMATION

DETAILED DESCRIPTION

Oscillator Frequency

The internal free running oscillator sets the PWM switching frequency at 500 kHz. The 500 kHz switching frequency allows less output inductance for the same output ripple requirement resulting in a smaller output inductor.

Voltage Reference

The voltage reference system produces a precision reference signal by scaling the output of a temperature stable bandgap circuit. The bandgap and scaling circuits are trimmed during production testing to an output of

1.221 V at room temperature.

Enable (ENA) and Internal Slow Start

The ENA pin provides electrical on/off control of the regulator. Once the ENA pin voltage exceeds the threshold voltage, the regulator starts operation and the internal slow start begins to ramp. If the ENA pin voltage is pulled below the threshold voltage, the regulator stops switching and the internal slow start resets. Connecting the pin to ground or to any voltage less than 0.5 V will disable the regulator and activate the shutdown mode. The quiescent current of the TPS5430/TPS5431 in shutdown mode is typically 18 µ A.

The ENA pin has an internal pullup current source, allowing the user to float the ENA pin. If an application requires controlling the ENA pin, use open drain or open collector output logic to interface with the pin. To limit the start-up inrush current, an internal slow-start circuit is used to ramp up the reference voltage from 0 V to its final value, linearly. The internal slow start time is 8 ms typically.

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Feed Forward Gain +

VIN

Ramp

pk*pk

TPS5430 TPS5431

SLVS632C – JANUARY 2006 – REVISED NOVEMBER 2006

APPLICATION INFORMATION (continued)

Undervoltage Lockout (UVLO)

The TPS5430/TPS5431 incorporates an undervoltage lockout circuit to keep the device disabled when VIN (the input voltage) is below the UVLO start voltage threshold. During power up, internal circuits are held inactive and the internal slow start is grouded until VIN exceeds the UVLO start threshold voltage. Once the UVLO start threshold voltage is reached, the internal slow start is released and device start-up begins. The device operates until VIN falls below the UVLO stop threshold voltage. The typical hysteresis in the UVLO comparator is 330 mV.

Boost Capacitor (BOOT)

Connect a 0.01 µ F low-ESR ceramic capacitor between the BOOT pin and PH pin. This capacitor provides the gate drive voltage for the high-side MOSFET. X7R or X5R grade dielectrics are recommended due to their stable values over temperature.

Output Feedback (VSENSE) and Internal Compensation

The output voltage of the regulator is set by feeding back the center point voltage of an external resistor divider network to the VSENSE pin. In steady-state operation, the VSENSE pin voltage should be equal to the voltage reference 1.221 V.

The TPS5430/TPS5431 implements internal compensation to simplify the regulator design. Since the TPS5430/TPS5431 uses voltage mode control, a type 3 compensation network has been designed on chip to provide a high crossover frequency and a high phase margin for good stability. See the Internal Compensation Network in the applications section for more details.

Voltage Feed Forward

The internal voltage feed forward provides a constant dc power stage gain despite any variations with the input voltage. This greatly simplifies the stability analysis and improves the transient response. Voltage feed forward varies the peak ramp voltage inversely with the input voltage so that the modulator and power stage gain are constant at the feed forward gain, i.e.

The typical feed forward gain of TPS5430/TPS5431 is 25.

Pulse-Width-Modulation (PWM) Control

The regulator employs a fixed frequency pulse-width-modulator (PWM) control method. First, the feedback voltage (VSENSE pin voltage) is compared to the constant voltage reference by the high gain error amplifier and compensation network to produce a error voltage. Then, the error voltage is compared to the ramp voltage by the PWM comparator. In this way, the error voltage magnitude is converted to a pulse width which is the duty cycle. Finally, the PWM output is fed into the gate drive circuit to control the on-time of the high-side MOSFET.

Overcurrent Limiting

Overcurrent limiting is implemented by sensing the drain-to-source voltage across the high-side MOSFET. The drain to source voltage is then compared to a voltage level representing the overcurrent threshold limit. If the drain-to-source voltage exceeds the overcurrent threshold limit, the overcurrent indicator is set true. The system will ignore the overcurrent indicator for the leading edge blanking time at the beginning of each cycle to avoid any turn-on noise glitches.

Once overcurrent indicator is set true, overcurrent limiting is triggered. The high-side MOSFET is turned off for the rest of the cycle after a propagation delay. The overcurrent limiting mode is called cycle-by-cycle current limiting.

(1)

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TPS5430 TPS5431

SLVS632C – JANUARY 2006 – REVISED NOVEMBER 2006

APPLICATION INFORMATION (continued)

Sometimes under serious overload conditions such as short-circuit, the overcurrent runaway may still happen when using cycle-by-cycle current limiting. A second mode of current limiting is used, i.e. hiccup mode overcurrent limiting. During hiccup mode overcurrent limiting, the voltage reference is grounded and the high-side MOSFET is turned off for the hiccup time. Once the hiccup time duration is complete, the regulator restarts under control of the slow start circuit.

Overvoltage Protection

The TPS5430/TPS5431 has an overvoltage protection (OVP) circuit to minimize voltage overshoot when recovering from output fault conditions. The OVP circuit includes an overvoltage comparator to compare the VSENSE pin voltage and a threshold of 112.5% x VREF. Once the VSENSE pin voltage is higher than the threshold, the high-side MOSFET will be forced off. When the VSENSE pin voltage drops lower than the threshold, the high-side MOSFET will be enabled again.

Thermal Shutdown

The TPS5430/TPS5431 protects itself from overheating with an internal thermal shutdown circuit. If the junction temperature exceeds the thermal shutdown trip point, the voltage reference is grounded and the high-side MOSFET is turned off. The part is restarted under control of the slow start circuit automatically when the junction temperature drops 14 ° C below the thermal shutdown trip point.

PCB Layout

Connect a low ESR ceramic bypass capacitor to the VIN pin. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the VIN pin, and the TPS5430/TPS5431 ground pin. The best way to do this is to extend the top side ground area from under the device adjacent to the VIN trace, and place the bypass capacitor as close as possible to the VIN pin. The minimum recommended bypass capacitance is 4.7 µ F ceramic with a X5R or X7R dielectric.

There should be a ground area on the top layer directly underneath the IC, with an exposed area for connection to the PowerPAD. Use vias to connect this ground area to any internal ground planes. Use additional vias at the ground side of the input and output filter capacitors as well. The GND pin should be tied to the PCB ground by connecting it to the ground area under the device as shown below.

The PH pin should be routed to the output inductor, catch diode and boot capacitor. Since the PH connection is the switching node, the inductor should be located very close to the PH pin and the area of the PCB conductor minimized to prevent excessive capacitive coupling. The catch diode should also be placed close to the device to minimize the output current loop area. Connect the boot capacitor between the phase node and the BOOT pin as shown. Keep the boot capacitor close to the IC and minimize the conductor trace lengths. The component placements and connections shown work well, but other connection routings may also be effective.

Connect the output filter capacitor(s) as shown between the VOUT trace and GND. It is important to keep the loop formed by the PH pin, Lout, Cout and GND as small as is practical.

Connect the VOUT trace to the VSENSE pin using the resistor divider network to set the output voltage. Do not route this trace too close to the PH trace. Due to the size of the IC package and the device pin-out, the trace may need to be routed under the output capacitor. Alternately, the routing may be done on an alternate layer if a trace under the output capacitor is not desired.

If using the grounding scheme shown in Figure 9 , use a via connection to a different layer to route to the ENA pin.

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+ 18 hidden pages

TEXAS INSTRUMENTS TPS5430, TPS5431 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual

FEATURES APPLICATIONS

DESCRIPTION

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

ABSOLUTE MAXIMUM RATINGS

DISSIPATION RATINGS

RECOMMENDED OPERATING CONDITIONS

ELECTRICAL CHARACTERISTICS

PIN ASSIGNMENTS

TYPICAL CHARACTERISTICS

FUNCTIONAL BLOCK DIAGRAM

APPLICATION INFORMATION

DETAILED DESCRIPTION

Oscillator Frequency

Voltage Reference

Enable (ENA) and Internal Slow Start

Undervoltage Lockout (UVLO)

Boost Capacitor (BOOT)

Output Feedback (VSENSE) and Internal Compensation

Voltage Feed Forward

Pulse-Width-Modulation (PWM) Control

Overcurrent Limiting

Overvoltage Protection

Thermal Shutdown

PCB Layout